JP6319668B2 - Voltage detection circuit - Google Patents

Description

  The present invention relates to a voltage detection circuit that detects a predetermined voltage with low power consumption.

  For example, in the field of energy harvesting that harvests minute energy from the surrounding environment (harvest) and converts it into electric power, when receiving power from solar cells, thermoelectric elements, etc., whether or not those power generation elements are generating electricity It is necessary to find out. In order to detect the presence or absence of power generation, a voltage detection circuit is used.

  For example, in a thermoelectric element using the Seebeck effect, the output voltage obtained with a temperature difference of 2 ° C. is about 100 mV. The output power is very small. Therefore, the power consumption of the voltage detection circuit that detects the presence or absence of power generation is desired to be as low as possible.

  As a low power consumption voltage detection circuit, for example, one disclosed in Non-Patent Document 1 is known. The voltage detection circuit includes a voltage divider using a diode chain, a current detection circuit having a latch portion that operates at 1 nA or less, and a hysteresis comparator.

T. Shimamura, M. Ugajin, K Suzuki, K. Ono, N. Sato, K. Kuwabara, H. Morimura, and S. Mutoh, “Nano-watt power management and vibration sensing on a dust-size batteryless sensor node for ambient intelligence application, ”IEEE International Solid-State Circuits Conference Dig. Tech. Papers, pp. 501-505, Feb. 2010.

  However, the conventional voltage detection circuit has a problem that the temperature change of the detection voltage increases because the temperature dependency of the latch portion of the current detection circuit is large.

  The present invention has been made in view of this problem, and an object of the present invention is to provide a voltage detection circuit with low power consumption and small temperature change of the detection voltage.

  The voltage detection circuit of the present invention includes a first PMOS transistor having a source electrode, a gate electrode, and a back gate electrode connected to an output terminal, and a drain electrode connected to a ground electrode, and a source electrode and a back gate electrode connected to a voltage input terminal. A second PMOS transistor having a drain electrode connected to the output terminal and a gate electrode connected to a ground electrode, wherein the threshold voltage of the second PMOS transistor is greater than the threshold voltage of the first PMOS transistor This is the gist.

  According to the voltage detection circuit of the present invention, current consumption required for voltage detection can be reduced. Further, since a difference in threshold voltage is detected without including a latch portion having a large temperature dependence, a voltage detection circuit with low power consumption and small temperature change of the detection voltage can be provided.

It is a figure which shows the function structural example of the voltage detection circuit 1 of 1st Embodiment of this invention. 3 is a graph showing temperature characteristics of a detection voltage (inversion threshold voltage) of the voltage detection circuit 1; 3 is a graph showing an example of power consumption characteristics of the voltage detection circuit 1; It is a figure which shows the function structural example of the voltage detection circuit 2 of 2nd Embodiment of this invention. 4 is a graph showing the relationship between the output of the first multistage diode of the voltage detection circuit 2 and the detection voltage. Is a graph showing the relationship between split (dX) and inversion threshold voltage V _S. It is a diagram illustrating another configuration example of the transfer gate 40 _X. It is a figure which shows the function structural example of the voltage detection circuit 3 of 3rd Embodiment of this invention. 5 is a graph showing an example of V _DETECT output from the voltage detection circuit 3. 6 is a diagram illustrating a functional configuration example of a voltage detection circuit 4 of a modification of the voltage detection circuit 3. FIG. It is a figure which shows the function structural example of the voltage detection circuit 5 of 4th Embodiment of this invention. 5 is a diagram illustrating a specific example of a reference voltage unit 90. FIG. 2 is a diagram illustrating a configuration example of a comparator 100. FIG. It is a figure which shows the function structural example of the voltage detection circuit 6 of 5th Embodiment of this invention.

Embodiments of the present invention will be described below with reference to the drawings. The same reference numerals are given to the same components in a plurality of drawings, and the description will not be repeated.

[First Embodiment]
FIG. 1 shows a functional configuration example of the voltage detection circuit 1 of the first embodiment. The voltage detection circuit 1 of the present embodiment includes a first PMOS transistor 10 and a second PMOS transistor 20.

The first PMOS transistor 10 has a source electrode, a gate electrode, and a back gate electrode connected to the output terminal β, and a drain electrode connected to the ground electrode γ. The second PMOS transistor 20 has a source electrode and a back gate electrode connected to the voltage input terminal α, a drain electrode connected to the output terminal β, and a gate electrode connected to the ground electrode γ. The voltage input terminal α is a terminal that receives power from an external energy harvesting device such as a thermoelectric element. The threshold voltage V _TH2 of the second PMOS transistor 20 is larger than the threshold voltage V _TH1 of the first PMOS transistor 10.

When the voltage V _{α at the} voltage input terminal α is low, the leakage current of the first PMOS transistor 10 is larger than the leakage current of the second PMOS transistor 20. Therefore, the voltage V _β of the output terminal β is the same potential as the voltage of the ground electrode γ. Hereinafter, the voltage at each terminal may be simply expressed as V _α , V _β , V _γ or the like. The same applies to other voltage notations.

The gate of the high becomes the first 2PMOS transistor 20 to a voltage is V _alpha - consuming sufficient voltage between the source, the magnitude of the leakage current of the 2PMOS transistor 20, exceeds the leakage current of the 1PMOS transistor 10. As a result, V _α = V _β is obtained. That is, it can be detected that the output signal voltage detection circuit 1 is inverted, V _alpha is inputted to the voltage input terminal alpha becomes greater than a predetermined voltage.

The leakage current I ₁ of the first PMOS transistor 10 is expressed by the equation (1), and the leakage current I ₂ of the second PMOS transistor 20 is expressed by the equation (2). Here, the subscript 1 means a parameter of the first PMOS transistor. The subscript 2 means a parameter of the second PMOS transistor 20.

また、μはキャリアの移動度、Ｃはゲート容量、Ｗはゲート幅、Ｌはゲート長である。ｍはＭＯＳトランジスタのサブスレッショルド係数、及びＶ_Ｔは熱電圧（ｋＴ/ｑ）である。ｋはボルツマン定数、Ｔは絶対温度、ｑは素電荷である。

Further, μ is the carrier mobility, C is the gate capacitance, W is the gate width, and L is the gate length. m is a sub-threshold coefficient of the MOS transistors, and _{V T} is the thermal voltage (kT / q). k is the Boltzmann constant, T is the absolute temperature, and q is the elementary charge.

V _{α at} which the leakage current I ₂ of the second PMOS transistor 20 becomes larger than the leakage current I ₁ of the first PMOS transistor 10 is defined as an inversion threshold voltage V _S. V _S can be expressed by the following equation when Equation (1) and Equation (2) are obtained simultaneously.

Ｖ_Ｓは、トランジスタの閾値電圧で定まる第１項と第２項と、温度依存性のある第３項とで表される。温度依存性のある第３項は、対数項に第１ＰＭＯＳトランジスタ１０のゲート幅Ｗ_１とゲート長Ｌ_１と、第２ＰＭＯＳトランジスタ２０のゲート幅Ｗ_２とゲート長Ｌ_２との積の比を含む。よって、温度依存性（第３項）は、それぞれのトランジスタのサイズを適切なサイズ比にすることで消去できる（式４）。

V _S is expressed by a first term and a second term determined by a threshold voltage of the transistor, and a third term having temperature dependency. The third term having temperature dependence includes a ratio of the product of the gate width W ₁ and the gate length L ₁ of the first PMOS transistor 10 and the gate width W ₂ and the gate length L _{2 of} the second PMOS transistor 20 in the logarithmic term. . Therefore, the temperature dependence (third term) can be eliminated by setting the size of each transistor to an appropriate size ratio (Equation 4).

式（４）に示すようにＶ_Ｓは、おおよそ第２ＰＭＯＳトランジスタ２０の閾値電圧Ｖ_ＴＨ２と、第１ＰＭＯＳトランジスタ１０の閾値電圧Ｖ_ＴＨ１の大きさの差に等しい電圧である。

As shown in Expression (4), V _S is a voltage approximately equal to the difference in magnitude between the threshold voltage V _TH2 of the second PMOS transistor 20 and the threshold voltage V _TH1 of the first PMOS transistor 10.

FIG. 2 shows an example of the temperature characteristic of the inversion threshold voltage V _S. The horizontal axis in FIG. 2 is temperature [° C.], and the vertical axis is the inversion threshold voltage V _S [mV].

Since the inversion threshold voltage V _{S at} −20 ° C. is 522 mV and the inversion threshold voltage V _{S at} 80 ° C. is 524.7 mV, the temperature coefficient is approximately 27 μV / ° C. This value is about one-hundred of that of a conventional voltage detection circuit (2.19 mV / ° C.).

Figure 3 shows the power consumption characteristics to changes in the V _alpha voltage detecting circuit 1. The horizontal axis represents the voltage V _α [V] of the voltage input terminal α, and the vertical axis represents the power consumption [pW]. V _alpha is increased, the gate of the second 2PMOS transistor 20 - the power consumption of the consuming sufficient voltage between the source voltage detecting circuit 1 is increased stepwise, linearly power consumption with the increase after V _alpha Shows increasing characteristics. The power consumption of the voltage detection circuit 1 when V _α = 1V is about 18 pW.

Thus, the voltage detection circuit 1 has low power consumption, and the temperature dependency of the inversion threshold voltage V _S is small. Therefore, the voltage detection circuit 1 is suitable as a voltage detection circuit that detects the voltage of a power source having a small power, such as an energy harvesting device.

[Second Embodiment]
FIG. 4 shows a functional configuration example of the voltage detection circuit 2 of the second embodiment. In the voltage detection circuit 2 of the present embodiment, the configuration of the first multistage diode 30, the first multiplexer 40, and the inverter 50 is added to the configuration of the voltage detection circuit 1. The voltage detection circuit 2 can adjust the variation of the inversion threshold voltage V _S.

  The first multistage diode 30 includes a plurality of diode-connected PMOS transistors connected in series between the voltage input terminal α and the ground electrode γ. Here, the diode connection means that the back gate electrode of the PMOS transistor is connected to the source electrode, and the gate electrode is connected to the drain electrode.

If all the diode-connected PMOS transistors have the same size, the voltage V _α between the voltage input terminal α and the ground electrode γ can be equally divided without being affected by the temperature. FIG. 4 is an example in which _Vα is equally divided by 16 diode-connected PMOS transistors.

The closest drain electrode of the PMOS transistor 30 ₁ to the voltage input terminal alpha, highest divided voltage V _d1, the drain electrode of the PMOS transistor 30 ₂ the second closest to the voltage input terminal alpha is next highest partial pressure The voltage V _d2 is output.

The drain electrode of the fifteenth PMOS transistor _{30 15} counted from the closest PMOS transistor 30 ₁ to the voltage input terminal alpha, the lowest divided voltage _{V d15} obtained by dividing the V _alpha is outputted. In this way, the divided voltages V _{d1 to} V _d15 obtained by equally dividing V _α can be obtained from each node (drain electrode) of the first multistage diode 30. Since the divided voltages V _{d1 to} V _d15 are divided by diode-connected PMOS transistors of the same size, they are not easily affected by temperature.

The divided voltages V _{d1 to} V _d15 of the first multistage diode 30 are input to a first multiplexer (hereinafter referred to as a first MUX) 40. The first MUX 40 selects one divided voltage corresponding to the selection signal S from the divided voltages V _{d1 to} V _d15 .

The selection signal S is, for example, a 4-bit signal. The first MUX 40 selects the division d1 by, for example, 1 (0001) of the selection signal S and the division d15 by, for example, 15 (1111) of the selection signal S. The divided voltage V _dX of the selected divided dX is input to the source electrode of the second PMOS transistor 20 of the voltage detection circuit 1 (FIG. 1). Hereinafter, the voltage detection circuit 1 is referred to as a core portion 7.

The voltage output circuit 2 detects the inversion threshold voltage V _S from the divided voltage V _dX obtained by dividing Vα input to the voltage input terminal α by the first multistage diode 30. That is, the voltage output circuit 2 can adjust the inversion threshold voltage V _S by changing the _divided voltage V _dX selected by the first multiplexer 40.

The _divided voltage V _dX input to the core portion 7 is a voltage obtained by dividing the voltage V _α of the voltage input terminal α. Therefore, it is possible to variably by a 1MUX40 the slope of V _alpha. For example, when the selection signal S is set to 5 (0101) so that the first MUX 40 selects the division d5, the inversion threshold voltage V _S can be increased.

FIG. 5 shows an example in which the inversion threshold voltage V _S is changed. The horizontal axis of FIG. 5 is the voltage V _α [V] of the voltage input terminal α, and the vertical axis is the voltage [V]. The notation of V _S on the vertical axis indicates the inversion threshold voltage V _S of the voltage detection circuit 1. The notation of V _S on the vertical axis indicates that the voltage of the voltage detection circuit 1 corresponds to the fact that V _S at 25 ° C. in FIG.

Selecting a split d5 at the 1MUX40, voltage between the drain electrode of the source electrode and the 1PMOS transistor 10 of the first 2PMOS transistor 20 of the core portion 7 will divided voltage _{V d5.} Divided voltage V _d5 are the voltage obtained by dividing the voltage V _alpha inputted to the voltage input terminal alpha min, voltage smaller than V _alpha.

Therefore, the inversion threshold voltage V _S of the core portion 7 of the voltage detecting circuit 2 is higher than the inversion threshold voltage V _{S =} 524.3mV of the voltage detection circuit 1. That is, the voltage V _α of the voltage input terminal α at which the inversion threshold voltage V _S of the core portion 7 becomes 524.3 mV is about 0.77 V (V _{S on} the horizontal axis in FIG. 5).

The voltage V _beta of the output terminals of the core portion 7 beta in V.alpha ≒ 0.77 V, inverted from 0V to the divided voltage V _d5. Then, V _DETECT that is an output signal of the inverter 50 connected to the output terminal β is inverted from V _α to 0V. Thus, the value of the inversion threshold voltage V _S of the voltage detection circuit 2 can be adjusted by changing the divided voltage selected by the first MUX 40.

FIG. 6 shows the relationship between the division and the inversion threshold voltage V _S. The horizontal axis in FIG. 6 is the division number selected by the first MUX 40, and the vertical axis is the inversion threshold voltage V _S [V].

_{V S} is increased and a larger division number dX. This is because when the division number dX is increased, the gradient of the divided voltage V _dX with respect to the change in _VIN is reduced.

Division number d6 and d7 in _{V S} changes 92mV. By operating the selection signal S of the first MUX 40, the value of the inversion threshold voltage V _S of the voltage detection circuit 2 can be adjusted to fall within the target value range. That is, according to the voltage detection circuit 2, it is possible to absorb the variation in the threshold voltage _{V TH1, V TH2} obtain the desired _{V S.}

The first MUX 40 is configured by a transfer gate that selects the divided voltage V _dX corresponding to the selection signal S. The transfer gate is generally one in which the source electrodes and the drain electrodes of the PMOS transistor and the NMOS transistor are connected to each other, and a current is conducted between the source and drain electrodes.

An increase or decrease in leakage current due to global variation including manufacturing variations of transistors having different polarities constituting the transfer gate may affect the temperature characteristics of the _divided voltage V _dX extracted from the first multistage diode 30. That is, variations between the PMOS transistor and the NMOS transistor occur independently. Therefore, the leakage current of the PMOS transistor of the first multistage diode 30 and the leakage current of the NMOS transistor of the transfer gate of the first MUX 40 do not change in the same direction.

FIG. 7 shows a configuration diagram of a transfer gate composed of only PMOS transistors. FIG. 7 shows one transfer gate 40 _X of the first MUX 30 that transmits one divided voltage V _dX in the first multistage diode 30.

The transfer gate 40 _X is composed of three PMOS transistors 41 _X , 42 _X , 43 _X (hereinafter, transistor notation is omitted). The source electrode of the PMOS 41 _X is connected to the _divided voltage V _dX , and the drain electrode thereof is connected to the voltage input terminal α of the core portion 7. Between the source and drain of the PMOS 41 _X , the PMOSs 42 _X and 43 _X are connected in series so that the direction of the electrodes is the same as that of the PMOS 41 _X. That is, the source electrode of the PMOS 42 _X is connected to the source electrode of the PMOS 41 _X. PMOS 42 _X and the source electrode of the drain electrode and the PMOS 43 _X of the connection.

Then, PMOS 41 is the gate electrode of the _X selection signal S (actually signal obtained by decoding a selection signal S) is connected, PMOS 42 gate electrode of the _X is connected to the drain electrode of the PMOS 43 _X, the gate electrode of the PMOS 43 _X of PMOS 42 _X Connected to source electrode.

  In this way, the transfer gate can be configured by all PMOS. In the above example, the first multi-stage diode 30 is also configured by diode-connecting PMOS, so that all transistors can be configured by PMOS. Then, even if the leakage current of the first MUX 40 increases or decreases, the leakage current of the first multistage diode 30 also increases or decreases in the same direction. Therefore, the leakage current is adjusted in a self-aligning manner.

As described above, the voltage detection circuit 2 has an effect of enabling adjustment of the inversion threshold voltage V _S. The first multi-stage diode 30 of the voltage detection circuit 2 has been described as an example configured with a PMOS transistor, but may be configured with a series connection of a plurality of NMOS transistors.

[Third Embodiment]
FIG. 8 shows a functional configuration example of the voltage detection circuit 3 of the third embodiment. The voltage detection circuit 3 of the present embodiment is obtained by replacing the inverter 50 of the voltage detection circuit 2 with a two-input NAND gate (hereinafter referred to as NAND) 70 and a second core portion 60, and outputs the voltage detection circuit. The signal is prevented from becoming indefinite.

The output signal of the voltage detection circuit 2 (FIG. 4) is the output of the inverter 50. Power of the inverter 50 also, since it is V _alpha supplied from outside, for example, energy harvesting devices, if V _alpha is low, the inverter 50 does not act as an inverter. Therefore, the output signal of the inverter 50, it may not be determined to vary between 0V and V _alpha (undefined). This variation means a false detection and needs to be prevented.

  The second core portion 60 includes two PMOS transistors 61 and 62, and is the same as the voltage detection circuit 1 (FIG. 1). The output terminal of the second core portion 60 is connected to the input B which is one input terminal of the NAND 70. The output terminal of the core portion 7 is connected to the input A which is the other input terminal of the NAND 70.

  As is well known, the NAND 70 is composed of the same number of PMOSs 71 and 72 connected in parallel as the number of inputs and the same number of NMOSs 73 and 74 connected in series as the PMOS. Here, the threshold voltage of the PMOS 72 constituting one input B of the NAND 70 is set lower than the threshold voltage of the PMOS 71.

The second core portion 60 has the same configuration as that of the voltage detection circuit 1 (FIG. 1) as described above. Therefore, the output of the second core portion 60 is inverted from 0 V to V _α at V _α lower than that of the core portion 7. That is, the input B of the NAND70 is inverted V _alpha from earlier 0V than the input A.

During the input B of the NAND70 is 0V, depending PMOS72 which is set to a low threshold voltage, the output of the voltage detection circuit 3 is pulled up to V _alpha. In short, in the voltage range where V _α becomes unstable when an inverter is used, the output V _DETECT is pulled up to V _α by one PMOS 72. Then, NAND70 become high enough to V _alpha there voltage to function as NAND after becoming voltage that can operate as logic gates.

Thus, by configuring the output of the voltage detection circuit with NAND, it is possible to prevent the output signal of the voltage detection circuit from becoming unstable in a voltage range where V _α is a low voltage. FIG. 9 shows V _DETECT output from the voltage detection circuit 3. The horizontal axis in FIG. 9 is Vα, and the vertical axis is V _DETECT .

In the low voltage range of V _α = 0 to 0.5 V, the state of V _DETECT = Vα is maintained. Then, the output is inverted when V _α ≈0.84V. Thus, in the voltage detection circuit 3, V _DETECT does not become unstable.

  Note that the output of the voltage detection circuit may be configured by a gate other than NAND. As shown in FIG. 10, even if it is constituted by a two-input AND gate (AND) 80, the same effect can be obtained. The description of the operation in FIG. 10 is omitted because it is clear from the above description.

[Fourth Embodiment]
FIG. 11 shows a functional configuration example of the voltage detection circuit 5 of the fourth embodiment. The voltage detection circuit 5 according to the present embodiment is obtained by reducing the power consumption of the voltage detection circuit 3 (FIG. 8).

The voltage detection circuit 4 is obtained by replacing the core portion 7 of the voltage detection circuit 3 with a reference voltage unit 90 and a comparator 100. The core portion 7 of the voltage detection circuit 3 operates using the divided voltage V _dX supplied from the first MUX 40 as a power source. Since the input impedance of the core portion 7 is not sufficiently high, the current flowing through the first multistage diode 30 that supplies current to the core portion 7 must be increased to some extent.

  In order for the first multistage diode 30 and the core portion 7 to operate correctly, it is necessary to pass a current about 10 times the current flowing through the core portion 7 to the first multistage diode 30. Therefore, the power consumption of the voltage detection circuit 3 is increased. Therefore, the voltage detection circuit 4 includes a reference voltage unit 90 and a comparator 100 in place of the core part 7 in order to reduce the current flowing from the first multistage diode 30 to the core part 7.

  Since the input impedance of the comparator 100 is infinite, the impedance when the comparator 100 is viewed from the first multistage diode 30 can be regarded as an open state. Therefore, the current flowing through the first multistage diode 30 can be reduced (minimized).

The comparator 100 compares the reference voltage V _REF generated by the reference voltage unit 90 with the _divided voltage V _dX of the first multi-stage diode 30, and outputs the output voltage when the _divided voltage V _dX becomes larger than the reference voltage V _REF. It is inverted V _α. The output terminal of the comparator 100 corresponds to the output terminal β of the core portion 7 (FIG. 4).

  FIG. 12 shows a configuration example of the reference voltage unit 90. The reference voltage unit 90 is composed of two PMOS transistors 91 and 92.

Threshold voltage _{V TH91} of the PMOS transistor 91 is higher than the threshold voltage _{V TH92} of the PMOS transistor 92. By appropriately designing the sizes of the PMOS transistor 91 and the PMOS transistor 92, the temperature dependence of the reference voltage _VREF can be canceled. The reference voltage V _{REF in} that case can be approximated by the following equation.

図１３に、コンパレータ１００の具体的な構成例を示す。コンパレータ１００は、電圧入力端子αと接地電極との間に接続され、３個のＰＭＯＳトランジスタ１０１，１０２，１０３と、２個のＮＭＯＳトランジスタ１０４，１０５とで構成される。これらのトランジスタが構成する回路は、一般的なものである。

FIG. 13 shows a specific configuration example of the comparator 100. The comparator 100 is connected between the voltage input terminal α and the ground electrode, and includes three PMOS transistors 101, 102, and 103 and two NMOS transistors 104 and 105. A circuit formed by these transistors is a general one.

  However, it differs from a general comparator in that the gate electrode of the PMOS transistor 101 that determines the constant current value is connected to the source electrode of the transistor. The constant current can be reduced by connecting the gate electrode of the constant current transistor to the source electrode. The comparator 100 configured in this manner is suitable for low power consumption applications.

  According to the voltage detection circuit 5 described above, since the current flowing through the first multistage diode 30 of the voltage detection circuit 3 (FIG. 8) can be reduced, the power consumption of the voltage detection circuit can be reduced. The configuration for reducing the power consumption of the voltage detection circuit 5 may be combined with the voltage detection circuit 2 (FIG. 4).

[Fifth Embodiment]
FIG. 14 shows a functional configuration example of the voltage detection circuit 6 of the fifth embodiment. The voltage detection circuit 5 of the present embodiment is one in which the adjustment accuracy of the inversion threshold voltage V _S is improved.

  The voltage detection circuit 6 is obtained by adding a second multistage diode 110 and a second multiplexer 120 to the voltage detection circuit 5 (FIG. 11). The second multi-stage diode 110 includes a plurality of diode-connected PMOS transistors connected in series between the output terminal of the reference voltage unit 90 and the ground electrode.

  The second multiplexer 120 selects the divided voltage of each of the second multistage diodes 110. The divided voltage selected by the second multiplexer 120 is connected to the non-inverting input terminal (−) of the comparator 100.

The configuration of the second multistage diode 110 and the second multiplexer 120 here is the same as that of the first multistage diode 30 and the first multiplexer 40 described above. In contrast to the voltage detection circuit 5 in which the reference voltage V _REF input to the comparator 100 is fixed, the voltage detection circuit 6 _supplies a divided voltage obtained by dividing the reference voltage V _REF to the non-inverting input terminal (−) of the comparator 100. To enter. Therefore, the adjustment accuracy of the inversion threshold voltage V _S can be improved.

  As described above, according to the embodiment, the following operational effects can be obtained.

According to the voltage detection circuit 1 (FIG. 1) of the first embodiment, it is possible to provide a voltage detection circuit with low power consumption and low temperature dependence of the inversion threshold voltage V _S. This voltage detection circuit 1 is suitable as a voltage detection circuit for detecting the voltage of a power source having a small power, such as an energy harvesting device.

Further, according to the voltage detection circuit 2 of the second embodiment (FIG. 4), operational effects that allows adjustment of the inversion threshold voltage V _S in addition to the effect of the voltage detection circuit 1. Moreover, according to the voltage detection circuit 3 (FIG. 8) of 3rd Embodiment, in addition to the effect of the voltage detection circuit 2, there exists an effect which stabilizes the output of a voltage detection circuit.

In addition, according to the voltage detection circuit 5 of the fourth embodiment, there is an effect of reducing the power consumption while enabling the inversion threshold voltage V _S to be adjusted. Further, according to the voltage detection circuit 6 of the fifth embodiment, the effect of enhancing the adjustment accuracy of the inversion threshold voltage V _S.

  Although the contents of the present invention have been described according to the embodiments, the present invention is not limited to these descriptions, and it is obvious to those skilled in the art that various modifications and improvements can be made. For example, the number of divisions of the first multistage diode 30 and the second multistage diode 110 has been described in the same example, but different division numbers may be used. Further, the core portion 7 of the voltage detection circuit 2 (FIG. 4) may be replaced with the reference voltage unit 90 and the comparator 100 of the voltage detection circuit 5.

  The embodiment of the present invention described above can be widely used as a voltage detection circuit that detects the voltage of a power source having a small power, such as an energy harvesting device.

1, 2, 3, 4, 5, 6: voltage detection circuit 7: core portion 10: first PMOS transistor 20: second PMOS transistor 30: first multistage diode 40: first multiplexer 50: inverter 60: second core portion 70 : NAND
80: AND
90: Reference voltage unit 100: Comparator 110: Second multistage diode 120: Second multiplexer

Claims (5)

A first PMOS transistor having a source electrode, a gate electrode, and a back gate electrode connected to the output terminal, and a drain electrode connected to the ground electrode;
A second PMOS transistor having a source electrode and a back gate electrode connected to a voltage input terminal, a drain electrode connected to the output terminal, and a gate electrode connected to a ground electrode;
The voltage detection circuit according to claim 1, wherein a threshold voltage of the second PMOS transistor is larger than a threshold voltage of the first PMOS transistor. The voltage detection circuit according to claim 1,
A first multi-stage diode composed of a plurality of diode-connected MOS transistors connected in series between the voltage input terminal and the ground electrode;
A first multiplexer for selecting a divided voltage of each of the first multistage diodes;
The voltage detection circuit, wherein a voltage input terminal to which a source electrode of the second MOS transistor is connected is an output terminal of the first multiplexer. The voltage detection circuit according to claim 2,
AND gate,
A third PMOS transistor having a source electrode, a gate electrode, and a back gate electrode connected to one input terminal of the AND gate, and a drain electrode connected to a ground electrode;
A fourth PMOS transistor having a source electrode and a back gate electrode connected to the voltage input terminal, a drain electrode connected to one gate of the AND gate, and a gate electrode connected to a ground electrode;
A drain electrode of the first PMOS transistor and a source electrode of the second PMOS transistor are connected to the other gate of the AND gate, and the threshold voltage of the PMOS transistors connected in parallel constituting one gate of the AND gate Is lower than the threshold voltage of another PMOS transistor connected in parallel with the AND gate. The voltage detection circuit according to claim 1,
A first multi-stage diode composed of a plurality of diode-connected PMOS transistors connected in series between the voltage input terminal and the ground electrode;
A first multiplexer for selecting a divided voltage of each of the first multistage diodes;
A reference voltage unit for generating a reference voltage from a voltage between the voltage input terminal and the ground electrode;
A comparator for comparing the divided voltage output from the first multiplexer with the reference voltage;
AND gate,
A third PMOS transistor having a source electrode, a gate electrode, and a back gate electrode connected to one input terminal of the AND gate, and a drain electrode connected to a ground electrode;
A fourth PMOS transistor having a source electrode and a back gate electrode connected to the voltage input terminal, a drain electrode connected to one gate of the AND gate, and a gate electrode connected to the ground electrode;
The output of the comparator is connected to one gate of the AND gate, the source electrode of the third PMOS transistor is connected to the other gate, and the PMOS transistors connected in parallel constituting the other gate of the AND gate The voltage detection circuit is characterized in that the threshold voltage is lower than the threshold voltage of another PMOS transistor connected in parallel with the AND gate. The voltage detection circuit according to claim 4,
A second multi-stage diode composed of a plurality of diode-connected PMOS transistors connected in series between the output of the reference voltage unit and the ground electrode;
A second multiplexer for selecting a divided voltage of each of the second multistage diodes;
An output of the second multiplexer is connected to the comparator.

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