JP6314620B2 - Arithmetic processing device and control method of arithmetic processing device - Google Patents

Description

  The present invention relates to an arithmetic processing unit and a control method for the arithmetic processing unit.

  An arithmetic processing unit such as a processor includes, for example, an instruction decoder, an arithmetic unit that executes an operation, a commit stack entry (CSE), and a reservation station (RS) (for example, Patent Documents). 1). For example, the instruction decoder decodes an instruction received from the instruction cache memory in order.

  The commit stack entry is, for example, a buffer used for instruction completion processing for completing an instruction. The instruction completion process is, for example, control that reflects the execution result of the instruction in a register or the like. The reservation station is provided for each instruction type, such as a fixed-point arithmetic instruction and a floating-point arithmetic instruction, and controls out-of-order execution. For example, in out-of-order execution, execution is performed from an executable instruction regardless of the program order.

  For example, the arithmetic processing unit registers all instructions decoded by the instruction decoder in the commit stack entry in the order of instructions and registers them in each reservation station. Each reservation station selects an executable instruction out of order. Then, for example, the computing unit executes the instruction selected by the reservation station.

  Here, in arithmetic processing such as floating point arithmetic, exceptions such as overflow may occur. For this reason, a floating-point arithmetic device has been proposed that determines whether or not exception processing is necessary by inspecting a flag that displays an overflow or the like detected based on the operation result (see, for example, Patent Document 2). Hereinafter, an exception generated by the calculation process is also referred to as a calculation exception.

  For example, when the detection of an operation exception is suppressed, when the commit stack entry receives operation completion information indicating completion of an operation by the operation unit, information regarding an instruction corresponding to the operation completion information is displayed as information indicating the completion of the operation. Update to For example, when the arithmetic processing unit is operating in a cycle of a predetermined clock, the information of the instruction updated to the information indicating the completion of the operation is the commit stack entry in-order after the cycle after the information is updated. Read from. For example, the instruction completion process is executed in order based on the information of the instruction read from the commit stack entry.

  Note that, in a pipelined information processing apparatus that processes an instruction having a delay slot, an interrupt processing method has been proposed in which an interrupt immediately after a delay instruction is enabled or disabled depending on the state of a flag register (for example, Patent Documents). 3). The state of the flag register can be set by software, for example.

JP 2011-8732 A JP-A-5-143320 JP 2007-188527 A

  If the instruction information registered in the commit stack entry is read in the cycle in which the arithmetic unit outputs the operation completion information, the read instruction information includes the content of the operation completion information (completion of operation). Is not reflected. For this reason, the execution of the instruction completion process is waited until the information of the instruction registered in the commit stack entry is updated to information indicating the completion of the operation even when the detection of the operation exception is suppressed.

  In one aspect, the arithmetic processing device and the control method for the arithmetic processing device disclosed in the present disclosure are from when the arithmetic unit outputs the operation completion information to when executing the instruction completion processing when detection of the operation exception is suppressed. It is to shorten the time.

  According to one aspect, the arithmetic processing device includes a decoding unit that decodes an instruction, an arithmetic unit that executes an operation based on the decoded instruction, and a completion control unit that executes instruction completion processing for completing the instruction in the order of decoding The completion control unit is registered in the order in which the decoded instructions are decoded, holds state information indicating whether the calculation based on the registered instruction is completed, and indicates completion of the calculation by the calculation unit When the operation completion information is received, a holding unit that updates the state information of the instruction indicated by the operation completion information to information indicating the completion of the operation, and instructions that are the target of the instruction completion processing are read from the holding unit in the order of decoding. When the selection unit and detection of exceptions generated by the arithmetic processing are suppressed, and the instruction indicated by the operation completion information output from the arithmetic unit matches the instruction that is the target of the instruction completion processing A bypass unit that generates bypass information indicating the completion of the operation, and bypass information that indicates completion of the operation by executing an instruction completion process based on the bypass information for the instruction for which the bypass information indicating the completion of the operation is generated For a command that has not been generated, a completion processing unit that executes a command completion process based on the status information of the command read from the holding unit.

  According to another aspect, an operation based on an instruction is performed in a decoding unit that decodes an instruction, an operation unit that performs an operation based on the decoded instruction, and a holding unit that registers the decoded instruction in the order of decoding. In the control method of the arithmetic processing unit having a completion control unit that stores state information indicating whether or not completed in correspondence with an instruction and executes instruction completion processing for completing the instruction in the order of decoding, the completion control unit includes: Instructions subject to instruction completion processing are read from the holding unit in the decoded order, and when the completion control unit receives calculation completion information indicating completion of the calculation by the calculation unit, the completion control unit includes state information held in the holding unit. The status information of the instruction indicated by the operation completion information is updated to information indicating the completion of the operation, and the completion control unit suppresses detection of an exception generated by the operation process and is output from the operation unit. If the instruction indicated by the operation completion information matches the instruction that is the target of the instruction completion processing, bypass information indicating completion of the operation is generated, and the completion control unit generates bypass information indicating completion of the operation. Instruction completion processing is executed based on the bypass information for the received instruction, and instruction completion processing is executed based on the status information of the instruction read from the holding unit for the instruction for which bypass information indicating completion of the operation is not generated Execute.

  The arithmetic processing device and the control method of the arithmetic processing device disclosed in the present disclosure can shorten the time from when the arithmetic unit outputs the operation completion information until the execution of the instruction completion processing when the detection of the arithmetic exception is suppressed. .

It is a figure which shows one Embodiment of the arithmetic processing apparatus and the control method of an arithmetic processing apparatus. It is a figure which shows an example of the operation | movement flow of the arithmetic processing unit shown in FIG. It is a figure which shows another example of the operation | movement flow of the arithmetic processing unit shown in FIG. It is a figure which shows another embodiment of the arithmetic processing apparatus and the control method of an arithmetic processing apparatus. It is a figure which shows an example of the command completion control part shown in FIG. It is a figure which shows an example of the pipeline process of the arithmetic processing unit shown in FIG. It is a figure which shows an example of the out-of-order execution by a superscalar system. It is a figure which shows an example of operation | movement of the instruction completion control part shown in FIG. It is a figure which shows another example of operation | movement of the instruction completion control part shown in FIG. It is a figure which shows another example of operation | movement of the instruction completion control part shown in FIG. It is a figure which shows another example of operation | movement of the instruction completion control part shown in FIG. It is a figure which shows the comparative example of operation | movement of the instruction completion control part shown in FIG. It is a figure which shows another example of the instruction completion control part shown in FIG. It is a figure which shows an example of the operation | movement flow of the instruction completion control part shown in FIG. It is a figure which shows an example of operation | movement of the instruction completion control part shown in FIG.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an embodiment of an arithmetic processing unit and a control method for the arithmetic processing unit. The arithmetic processing unit PU of this embodiment is, for example, a processor such as a CPU (Central Processing Unit) that operates at a predetermined clock cycle. The arithmetic processing unit PU may be a superscalar processor having a plurality of circuits for executing instructions, or may be a processor other than the superscalar processor.

  The arithmetic processing unit PU decodes an instruction decoder DEC that decodes an instruction, an operation unit OP that executes an operation based on the decoded instruction, and an instruction completion process that completes the instruction (hereinafter also referred to as a commit process) in the order of decoding. And an instruction completion control unit CCTL to be executed. The commit process is, for example, control for reflecting an instruction execution result in a register or the like.

  The instruction decoder DEC is an example of a decoding unit that decodes an instruction. For example, the instruction decoder DEC reads an instruction from the instruction cache and decodes the read instruction. Then, the instruction decoder DEC outputs the decoded instruction to the reservation station RS and the instruction completion control unit CCTL. Then, a command is output from the reservation station RS to the operation unit OP.

  The operation unit OP is an example of an operation unit that performs an operation based on a decoded instruction. For example, the operation unit OP includes an arithmetic unit that performs floating-point arithmetic, an arithmetic unit that performs fixed-point arithmetic, and the like. The operation unit OP receives an instruction from the reservation station RS in which the instruction decoded by the instruction decoder DEC is set. Then, the arithmetic unit OP performs floating point arithmetic, fixed point arithmetic, and the like out of order based on the decoded result of the received instruction. For example, in out-of-order execution, execution is performed from an instruction that can be executed by an instruction registered in the reservation station RS regardless of the program order.

  Further, when the operation based on the instruction is completed, the operation unit OP outputs operation completion information indicating the completion of the operation to the instruction completion control unit CCTL. Further, for example, when an exception such as overflow, underflow, or division by zero occurs in the arithmetic processing, the arithmetic unit OP may output exception information indicating that the exception has occurred to the instruction completion control unit CCTL. Hereinafter, an exception generated by the calculation process is also referred to as a calculation exception.

  The instruction completion control unit CCTL is an example of a completion control unit that executes instruction completion processing for completing an instruction in the order of decoding. For example, the instruction completion control unit CCTL executes the instruction completion process for up to four instructions in one cycle. In this case, among the instructions for which the instruction completion processing is not executed, four instructions from the oldest instruction (first instruction) to the fourth instruction correspond to the instruction completion target instructions.

  Note that the maximum number of instructions executed in the instruction completion process in one cycle is not limited to four. The instruction completion control unit CCTL, for example, when an instruction that has not been calculated is included in the four instructions that are the target of instruction completion processing, Command completion processing is executed up to the previous command.

  The instruction completion control unit CCTL includes, for example, a commit stack entry CSE, a selection unit SEL10, a bypass unit BYP, and a completion processing unit COMPU.

  The commit stack entry CSE is an example of a holding unit in which decoded instructions are registered in the order of decoding. The commit stack entry CSE is a buffer used for instruction completion processing, for example. For example, the commit stack entry CSE includes entry information including an instruction identifier for identifying an instruction (hereinafter also referred to as IID (Instruction IDentification)), an instruction type, status information, a register number in which an instruction result is stored, and the like. Registered every time. The state information is information indicating the state of the instruction, such as waiting for execution of the instruction, executing the instruction, or ending the instruction. Therefore, the state information corresponds to information indicating whether or not the calculation based on the registered instruction is completed.

  For example, the commit stack entry CSE receives an instruction decoded by the instruction decoder DEC, and holds entry information related to the received instruction so that they are arranged in the order of decoding. As a result, the instructions decoded by the instruction decoder DEC are registered in the commit stack entry CSE in the order of decoding.

  When the commit stack entry CSE receives operation completion information indicating completion of the operation by the operation unit OP, the commit stack entry CSE updates the status information of the instruction indicated by the operation completion information to information indicating the completion of the operation.

  The selection unit SEL10 is an example of a selection unit that reads instructions to be subjected to instruction completion processing from a holding unit (for example, commit stack entry CSE) in the order of decoding. For example, the selection unit SEL10 reads from the commit stack entry CSE in order from the oldest instruction among the valid instructions registered in the commit stack entry CSE (instructions for which instruction completion processing has not been executed). Since the instruction completion processing is executed in the order of decoding, the oldest instruction among the valid instructions registered in the commit stack entry CSE corresponds to the first instruction that is the target of the instruction completion processing.

  The instruction read from the commit stack entry CSE by the selection unit SEL10 is transferred to, for example, the completion processing unit COMPU and the bypass unit BYP. For example, the selection unit SEL10 outputs the state information of the instruction read from the commit stack entry CSE to the bypass unit BYP, and completes information (IID, instruction type, etc.) other than the state information of the instruction read from the commit stack entry CSE Output to the unit COMPU.

  The bypass unit BYP is an example of a bypass unit that generates bypass information indicating completion of calculation. For example, when the detection of an exception caused by the arithmetic processing is suppressed, the bypass unit BYP generates bypass information indicating the completion of the calculation based on the calculation completion information indicating the completion of the calculation by the calculation unit OP.

  Here, for example, the arithmetic processing unit PU has a FED (Floating-point Exception Disable mode) flag indicating that detection of an exception caused by arithmetic processing such as floating point arithmetic is suppressed. For example, when the FED flag is set to “1”, detection of an operation exception is suppressed. For example, when the FED flag is set to “0”, the detection of the calculation exception is not suppressed. For example, the FED flag can be arbitrarily rewritten by an instruction during the operation of the program. Note that an operation exception whose detection is suppressed by the FED flag is not limited to an exception generated by a floating-point operation. For example, detection of an exception that occurs due to fixed-point arithmetic may be suppressed by the FED flag.

  For example, the bypass unit BYP receives calculation completion information indicating completion of calculation by the calculation unit OP. Then, the bypass unit BYP suppresses detection of an exception generated by the arithmetic processing, and the instruction indicated by the operation completion information output from the arithmetic unit OP matches the instruction that is the target of the instruction completion processing. The bypass information indicating the completion of the calculation is generated. That is, the bypass unit BYP generates bypass information that reflects the content of the operation completion information (completion of operation) when the operation completion information of the instruction that is the target of the instruction completion process is output from the operation unit OP.

  Further, for example, the bypass unit BYP transfers the status information of the command received from the selection unit SEL10 to the completion processing unit COMPU. When the bypass unit BYP generates bypass information indicating the completion of the calculation, the bypass unit BYP outputs the bypass information indicating the completion of the calculation to the completion processing unit COMPU instead of the state information of the instruction corresponding to the bypass information. In this case, instead of the state information of the instruction read from the commit stack entry CSE before the content of the operation completion information is reflected, bypass information reflecting the content of the operation completion information (completion of operation) is received as a completion processing unit. Forwarded to COMPU.

  In this way, when the detection of the calculation exception is suppressed, the bypass unit BYP determines the time from when the calculation unit OP outputs the calculation completion information until the completion processing unit COMPU is notified of the content of the calculation completion information. Can be shortened. As a result, the arithmetic processing unit PU can shorten the time from when the arithmetic unit OP outputs the operation completion information to when the instruction completion processing is executed when detection of the arithmetic exception is suppressed.

  The completion processing unit COMPU executes instruction completion processing based on the bypass information for an instruction for which bypass information has been generated, and based on state information read from the holding unit for an instruction for which bypass information has not been generated. 3 is an example of a completion processing unit that executes instruction completion processing. For example, the completion processing unit COMPU determines, for each instruction, whether or not the calculation is completed based on information (bypass information or instruction state information) received from the bypass unit BYP.

  For example, the completion processing unit COMPU determines that the calculation has been completed for an instruction for which bypass information indicating the completion of the calculation is generated. In addition, for example, the completion processing unit COMPU, for an instruction for which bypass information indicating completion of the operation is not generated, has the operation been completed based on the state information of the instruction read from the commit stack entry CSE. Determine whether or not.

  Then, the completion processing unit COMPU executes the instruction completion processing for the instruction targeted for the instruction completion processing in the order of decoding based on the determination result of whether or not the calculation is completed. For example, the completion processing unit COMPU processes instruction completion processing from the first instruction to the instruction before the instruction that has not been completed among the instructions read from the commit stack entry CSE as the target of instruction completion processing. Are executed in the order of decoding. The completion processing unit COMPU, for example, for all instructions read from the commit stack entry CSE as the target of instruction completion processing, for all instructions targeted for instruction completion processing, Instruction completion processing is executed in the order of decoding.

  Note that the configuration of the arithmetic processing unit PU is not limited to this example. For example, the instruction completion control unit CCTL receives completion information other than the operation completion information (for example, branch determination completion information indicating a branch prediction determination result for the branch instruction), and performs instruction completion processing based on the received completion information. May be executed.

  Further, for example, the selection unit SEL10 may output the status information of the instruction read from the commit stack entry CSE to the completion processing unit COMPU without outputting to the bypass unit BYP. In this case, the completion processing unit COMPU determines whether or not to execute the instruction completion processing based on the bypass information and the state information of the instruction read from the commit stack entry CSE by the selection unit SEL10. For example, the completion processing unit COMPU determines, based on the bypass information, whether or not to execute the instruction completion processing for an instruction for which bypass information indicating completion of the operation is generated. Further, the completion processing unit COMPU determines whether or not to execute the instruction completion processing for an instruction for which bypass information indicating the completion of the operation is not generated, from the status information of the instruction read from the commit stack entry CSE Determine based on.

  FIG. 2 shows an example of an operation flow of the arithmetic processing unit PU shown in FIG. That is, FIG. 2 shows one form of the control method of the arithmetic processing unit. FIG. 2 shows an example of the operation of the instruction completion control unit CCTL when detection of an operation exception is suppressed. The operation of FIG. 2 may be realized only by hardware, or may be realized by controlling the hardware by software.

  Although not shown in FIG. 2, instructions decoded by the instruction decoder DEC are registered in the commit stack entry CSE in the order of decoding. For example, the instruction completion control unit CCTL stores state information indicating whether or not the operation based on the instruction is completed in a commit stack entry CSE registered in the order in which the decoded instruction is decoded in association with the instruction.

  For example, step S120 is executed in parallel with steps S130-S140. In this case, steps S120 to S140 are executed in the same cycle, for example. Further, for example, step S150 is executed in a cycle after the cycle in which steps S120 to S140 are executed.

  In step S100, the selection unit SEL10 reads instructions to be subjected to instruction completion processing from the commit stack entry CSE in the order of decoding. For example, when the maximum number of instructions executed in the instruction completion process is four in one cycle, the selection unit SEL10 selects four effective instructions registered in the commit stack entry CSE in order from the oldest instruction. Are read from the commit stack entry CSE.

  In step S110, the instruction completion control unit CCTL determines whether or not calculation completion information indicating completion of calculation by the calculation unit OP has been received. When the calculation completion information is received (Yes in step S110), the operation of the instruction completion control unit CCTL proceeds to step S120. On the other hand, when the operation completion information has not been received (No in step S110), the operation of the instruction completion control unit CCTL proceeds to step S150.

  In step S120, the instruction completion control unit CCTL updates the state information of the instruction indicated by the operation completion information among the state information held in the commit stack entry CSE to information indicating the completion of the operation. That is, when the commit stack entry CSE receives the operation completion information indicating the completion of the operation by the operation unit OP, the commit stack entry CSE updates the status information of the instruction indicated by the operation completion information to the information indicating the completion of the operation.

  In step S130, the instruction completion control unit CCTL determines whether or not the instruction of the operation completion information received in step S110 is a target of the instruction completion process read in step S100. The operation completion information instruction is an instruction indicated by the operation completion information (an instruction for which the operation has been completed). When the instruction of the operation completion information is a target of instruction completion processing (Yes in step S130), the operation of the instruction completion control unit CCTL proceeds to step S140. On the other hand, when the instruction of the operation completion information is not the target of the instruction completion process (No in Step S130), the operation of the instruction completion control unit CCTL proceeds to Step S150.

  In step S140, the bypass unit BYP generates bypass information indicating the completion of the calculation (the calculation of the instruction indicated by the calculation completion information) based on the calculation completion information. For example, the bypass unit BYP generates bypass information indicating completion of the operation in response to an instruction indicated by the operation completion information. In this way, the bypass unit BYP suppresses detection of exceptions generated by the arithmetic processing, and the instruction indicated by the arithmetic completion information output from the arithmetic unit OP matches the instruction that is the target of the instruction completion processing. If so, bypass information indicating completion of the calculation is generated.

  In step S150, the instruction completion control unit CCTL executes instruction completion processing based on the bypass information and the state information of the instruction read from the commit stack entry CSE. For example, the completion processing unit COMPU executes instruction completion processing based on the bypass information generated in step S140 and the state information of the instruction read from the commit stack entry CSE in step S100.

  For example, the completion processing unit COMPU determines that the operation is completed when either the bypass information generated in step S140 or the status information of the instruction read from the commit stack entry CSE in step S100 indicates the completion of the operation. judge. Then, for example, the completion processing unit COMPU performs instruction completion processing from the first instruction read from the commit stack entry CSE to the instruction before the instruction that has not been completed. Run in decoded order.

  For example, when the operation is completed for all the instructions read from the commit stack entry CSE in step S100, the completion processing unit COMPU performs the instruction completion process for all the instructions that are the target of the instruction completion process. Are executed in the order of decoding. By executing the instruction completion process, the target of the instruction completion process is updated.

  Further, for example, when the operation is not completed for all the instructions read from the commit stack entry CSE in step S100, the completion processing unit COMPU performs the processing for all the instructions read from the commit stack entry CSE. Does not execute instruction completion processing. In this case, the target of the instruction completion process is not updated.

  Thus, for example, the content of the operation completion information is set in the commit stack entry CSE during the cycle in which the commit stack entry CSE receives the operation completion information, and is held as instruction status information indicated by the operation completion information. For this reason, the content of the calculation completion information received at step S110 is not reflected in the state information referred to at step S150. For example, the content of the operation completion information is reflected in the state information of the instruction read from the commit stack entry CSE in a cycle after the cycle in which the commit stack entry CSE receives the operation completion information.

  On the other hand, for example, when the instruction of the operation completion information received in step S110 is an instruction completion processing target, the content of the operation completion information is the same as that in step S150 during the cycle in which the commit stack entry CSE receives the operation completion information. It is reflected in the bypass information referenced in. That is, the arithmetic processing unit PU can shorten the time from when the calculation unit OP outputs the calculation completion information to when the completion processing unit COMPU receives the information reflecting the contents of the calculation completion information.

  As a result, the arithmetic processing unit PU can shorten the time from when the arithmetic unit OP outputs the operation completion information to when the instruction completion processing is executed when detection of the arithmetic exception is suppressed. For example, when the number of cycles required for step S120 is one cycle, the arithmetic processing unit PU omits the bypass unit BYP from the time when the arithmetic unit OP outputs the operation completion information to the time when the instruction completion processing is executed. Compared to the configuration, one cycle can be shortened. Note that the operation of the arithmetic processing unit PU is not limited to this example.

  FIG. 3 shows another example of the operation flow of the arithmetic processing unit PU shown in FIG. FIG. 3 shows an example of the operation of the instruction completion control unit CCTL when the detection of the operation exception is not suppressed. The operation of FIG. 3 may be realized only by hardware, or may be realized by controlling the hardware by software. Although not shown in FIG. 3, instructions decoded by the instruction decoder DEC are registered in the commit stack entry CSE in the order of decoding. Detailed description of the same or similar operations as those in FIG. 2 will be omitted.

  In step S200, the selection unit SEL10 reads instructions to be subjected to instruction completion processing from the commit stack entry CSE in the order of decoding.

  In step S210, the instruction completion control unit CCTL determines whether or not calculation completion information indicating completion of calculation by the calculation unit OP has been received. When the operation completion information is received (Yes in step S210), the operation of the instruction completion control unit CCTL proceeds to step S220. On the other hand, when the operation completion information has not been received (No in step S210), the operation of the instruction completion control unit CCTL proceeds to step S250.

  In step S220, the instruction completion control unit CCTL updates the state information of the instruction indicated by the operation completion information among the state information held in the commit stack entry CSE to information indicating the completion of the operation.

  In step S230, the instruction completion control unit CCTL determines whether an exception is detected. For example, the instruction completion control unit CCTL determines whether exception information indicating that an exception such as overflow, underflow, or division by zero has occurred is received from the arithmetic unit OP. If an exception is detected (Yes in step S230), the operation of the instruction completion control unit CCTL proceeds to step S240. On the other hand, when no exception is detected (No in step S230), the operation of the instruction completion control unit CCTL proceeds to step S250.

  In step S240, the instruction completion control unit CCTL updates the state information of the instruction indicated by the operation completion information among the state information held in the commit stack entry CSE to information indicating the occurrence of an exception.

  In step S250, the instruction completion control unit CCTL executes instruction completion processing based on the instruction status information read from the commit stack entry CSE. For example, the completion processing unit COMPU executes exception processing when the status information of the instruction read from the commit stack entry CSE in step S100 indicates the occurrence of an exception. In exception processing, for example, an instruction subsequent to an instruction in which an exception has occurred is canceled.

  Note that the operation of the arithmetic processing unit PU is not limited to this example. For example, as shown in FIG. 14, in the bypass unit BYP, no exception is detected, and the instruction indicated by the operation completion information output from the operation unit OP matches the instruction that is the target of the instruction completion process. In this case, bypass information indicating completion of the calculation may be generated. In this case, for example, the instruction completion control unit CCTL executes an instruction completion process based on the bypass information and the instruction status information read from the commit stack entry CSE in step S250.

  As described above, in the arithmetic processing device and the control method of the arithmetic processing device of the embodiment shown in FIGS. 1 to 3, the instruction completion control unit CCTL is based on the bypass information and the status information of the instruction read from the commit stack entry CSE. Instruction completion processing is executed. For example, the instruction completion control unit CCTL suppresses detection of exceptions generated by the arithmetic processing, and the instruction indicated by the operation completion information output from the arithmetic unit OP matches the instruction that is the target of the instruction completion processing. If so, bypass information indicating completion of the calculation is generated.

  That is, the bypass unit BYP generates bypass information that reflects the content of the operation completion information (completion of operation) when the operation completion information of the instruction that is the target of the instruction completion process is output from the operation unit OP. For example, when the bypass unit BYP generates bypass information indicating the completion of the calculation, the bypass unit BYP outputs the bypass information indicating the completion of the calculation to the completion processing unit COMPU instead of the state information of the instruction corresponding to the bypass information.

  Thereby, in this embodiment, when the detection of the calculation exception is suppressed, the time from the calculation unit OP outputting the calculation completion information to notifying the completion processing unit COMPU of the content of the calculation completion information is shortened. it can. As a result, in this embodiment, when the detection of the operation exception is suppressed, the time from when the operation unit OP outputs the operation completion information to when the instruction completion processing is executed can be shortened.

  FIG. 4 shows another embodiment of the arithmetic processing device and the control method of the arithmetic processing device. Elements that are the same as or similar to those described in FIGS. 1 to 3 are given the same or similar reference numerals, and detailed descriptions thereof are omitted. In the instruction completion control unit CCTL shown in FIG. 4, descriptions other than the commit stack entry CSE are omitted for easy understanding of the drawing.

  The arithmetic processing unit PU is a processor such as a CPU that operates in a predetermined clock cycle, for example. For example, the arithmetic processing unit PU is a superscalar processor having a plurality of circuits (operating units EXU, FPU, etc.) that execute instructions. The arithmetic processing unit PU includes, for example, a state control unit MCTL, a branch prediction mechanism BRPRE, an instruction fetch address generator FAGEN, an instruction cache CCM, an instruction decoder DEC, an operation unit OP, a data cache DCM, a branch control unit BCTL, and an instruction completion control unit. Have CCTL.

  The state control unit MCTL includes, for example, a program counter PC and a next program counter NPC. For example, the program counter PC outputs a value indicating an address of an instruction executed by the arithmetic processing unit PU (hereinafter also referred to as a PC value) to the instruction fetch address generator FAGEN. The next program counter NPC holds the next PC value. For example, the value of the program counter PC (PC value) and the value of the next program counter NPC (next PC value) increase every time the instruction completion process is executed.

  Further, the state control unit MCTL has an FED flag indicating that detection of an operation exception is suppressed. For example, the FED flag can be arbitrarily rewritten by an instruction for setting the operation mode of the arithmetic processing unit PU. For example, the state control unit MCTL sets the FED flag to “1” when the detection of the calculation exception is suppressed, and sets the FED flag to “0” when the detection of the calculation exception is not suppressed. Then, the state control unit MCTL outputs the set value of the FED flag to the instruction completion control unit CCTL.

  The branch prediction mechanism BRPRE predicts the result of the branch instruction. The instruction fetch address generator FAGEN receives the value of the program counter PC (PC value), the result of branch prediction by the branch prediction mechanism BRPRE, and information from the branch control unit BCTL (for example, information indicating whether or not branch prediction is successful). Based on the above, an instruction fetch address is generated. The instruction cache CCM stores, for example, a plurality of instructions for executing a program. For example, the instruction cache CCM outputs an instruction indicated by the instruction fetch address generated by the instruction fetch address generator FAGEN to the instruction decoder DEC.

  The instruction decoder DEC is the same as or similar to the instruction decoder DEC shown in FIG. That is, the instruction decoder DEC is an example of a decoding unit that decodes an instruction. For example, the instruction decoder DEC reads an instruction indicated by the instruction fetch address generated by the instruction fetch address generator FAGEN from the instruction cache CCM. Then, the instruction decoder DEC decodes the instruction read from the instruction cache CCM, and outputs the decoded instruction to the instruction completion control unit CCTL. As a result, the instruction decoded by the instruction decoder DEC is registered in order in the instruction order in the commit stack entry CSE of the instruction completion control unit CCTL.

  The instruction decoder DEC outputs the decoded instruction to the reservation stations RSA, RSE, RSF of the operation unit OP and the reservation station RSBR of the branch control unit BCTL. As a result, the instruction decoded by the instruction decoder DEC is registered in one of the reservation stations RSA, RSE, RSF, and RSBR. The reservation stations RSA, RSE, RSF, and RSBR are provided for each instruction type such as a load / store instruction, a fixed-point arithmetic instruction, a floating-point arithmetic instruction, a branch instruction, and the like, and control out-of-order execution.

  The calculation unit OP is the same as or similar to the calculation unit OP shown in FIG. That is, the operation unit OP is an example of an operation unit that executes an operation based on the decoded instruction. For example, the arithmetic unit OP includes reservation stations RSA, RSE, RSF, operand address generators OAGEN, arithmetic units EXU, FPU, fixed point update buffer EXBUF, floating point update buffer FPBUF, fixed point register EXREG, and floating point register FPREG. .

  Hereinafter, the fixed-point update buffer EXBUF and the fixed-point register EXREG are also referred to as an update buffer EXBUF and a register EXREG, respectively. The floating point update buffer FPBUF and the floating point register FPREG are also referred to as an update buffer FPBUF and a register FPREG, respectively.

  The reservation station RSA is a reservation station (RSA) for load / store instructions. For example, the reservation station RSA receives the load / store instruction decoded by the instruction decoder DEC. Thereby, a load / store instruction is registered in the reservation station RSA. Then, the reservation station RSA selects an executable load / store instruction out of order. The operand address generator OAGEN generates the address of the operand of the instruction selected by the reservation station RSA.

  For example, in the case of a load instruction, the data cache DCM transfers the data at the address generated by the operand address generator OAGEN to the update buffers EXBUF, FPBUF, and the like. Further, for example, in the case of a store instruction, the data cache DCM writes the data received from the register or the like to the address generated by the operand address generator OAGEN. Further, when the data transfer to the update buffer EXBUF, FPBUF, or the like is completed, the data cache DCM outputs data transfer completion information indicating that the data transfer is completed to the instruction completion control unit CCTL.

  The reservation station RSE is a reservation station (RSE) for fixed point arithmetic instructions. For example, the reservation station RSE receives a fixed point arithmetic instruction decoded by the instruction decoder DEC. As a result, a fixed-point arithmetic instruction is registered in the reservation station RSE. Then, the reservation station RSE selects an executable fixed-point operation instruction out-of-order.

  The arithmetic unit EXU is an arithmetic unit that performs fixed-point arithmetic. For example, the arithmetic unit EXU receives data from the update buffer EXBUF, the register EXREG, etc. based on the fixed-point arithmetic instruction selected by the reservation station RSE, and executes the fixed-point arithmetic. The calculation result is transferred to, for example, the update buffer EXBUF. For example, when the operation unit EXU transfers the operation result to the update buffer EXBUF, the operation unit EXU outputs operation completion information indicating the completion of the operation to the instruction completion control unit CCTL. Further, for example, when an arithmetic exception occurs, the arithmetic unit EXU outputs exception information indicating that the arithmetic exception has occurred to the instruction completion control unit CCTL.

  The fixed-point update buffer EXBUF stores the calculation result received from the calculator EXU. Then, the fixed-point update buffer EXBUF outputs the stored calculation result to the fixed-point register EXREG in accordance with control from the instruction completion control unit CCTL. As a result, the result of the calculation by the calculator EXU is stored in the fixed point register EXREG.

  The reservation station RSF is a reservation station (RSF) for a floating point arithmetic instruction. For example, the reservation station RSF receives a floating point arithmetic instruction decoded by the instruction decoder DEC. As a result, a floating point arithmetic instruction is registered in the reservation station RSF. Then, the reservation station RSF selects an executable floating-point arithmetic instruction out-of-order.

  The arithmetic unit FPU is an arithmetic unit that performs floating-point arithmetic. For example, the arithmetic unit FPU receives data from the update buffer FPBUF, the register FPREG, and the like based on the floating point arithmetic instruction selected by the reservation station RSF, and executes the floating point arithmetic. The calculation result is transferred to the update buffer FPBUF, for example. For example, when the operation unit FPU transfers the operation result to the update buffer FPBUF, the operation unit FPU outputs operation completion information indicating the completion of the operation to the instruction completion control unit CCTL. Further, for example, when an arithmetic exception occurs, the arithmetic unit FPU outputs exception information indicating that the arithmetic exception has occurred to the instruction completion control unit CCTL.

  The floating point update buffer FPBUF stores the calculation result received from the calculator FPU. Then, the floating-point update buffer FPBUF outputs the stored calculation result to the floating-point register FPREG in accordance with control from the instruction completion control unit CCTL. As a result, the result of the calculation by the calculator FPU is stored in the floating point register FPREG.

  The branch control unit BCTL has, for example, a reservation station RSBR. The reservation station RSBR is a reservation station for branch instructions (RSBR). For example, the reservation station RSBR receives the branch instruction decoded by the instruction decoder DEC. As a result, a branch instruction is registered in the reservation station RSBR. Then, the reservation station RSBR selects an executable branch instruction out-of-order.

  For example, the branch control unit BCTL determines whether the branch prediction of the branch prediction mechanism BRPRE for the branch instruction selected by the reservation station RSBR is successful. Then, the branch control unit BCTL updates the value of the next program counter NPC (next PC value) and the like based on the determination result of whether the branch prediction of the branch prediction mechanism BRPRE is successful. In addition, for example, when the determination of whether or not the branch prediction of the branch prediction mechanism BRPRE is successful, the branch control unit BCTL receives the branch determination completion information indicating that the determination of the branch prediction of the branch prediction mechanism BRPRE is completed. Output to the instruction completion control unit CCTL.

  As described above, the operation unit OP and the branch control unit BCTL perform data transfer, floating point operation, fixed point operation, branch processing, and the like out of order.

  The instruction completion control unit CCTL is the same as or similar to the instruction completion control unit CCTL shown in FIG. That is, the instruction completion control unit CCTL is an example of a completion control unit that executes instruction completion processing for completing an instruction in the order of decoding. For example, the instruction completion control unit CCTL has a commit stack entry CSE as shown in FIG.

  The commit stack entry CSE is the same as or similar to the commit stack entry CSE shown in FIG. That is, the commit stack entry CSE is an example of a holding unit in which decoded instructions are registered in the order of decoding. The commit stack entry CSE includes, for example, the instruction type of the instruction decoded by the instruction decoder DEC, state information indicating the state of the instruction (execution waiting, executing, execution end, etc.), a register number in which the instruction result is stored, and the like. Entry information is held for each instruction identifier. For example, the commit stack entry CSE has a plurality of (for example, 64) latches that hold instruction entry information, and holds entry information for each instruction identifier. Details of the instruction completion control unit CCTL will be described with reference to FIG.

  Note that the configuration of the arithmetic processing unit PU is not limited to this example. For example, the operation unit OP may include a plurality of operand address generators OAGEN, a plurality of operation units EXU, and a plurality of operation units FPU. The operation of the arithmetic processing unit PU is the same as or similar to the operation shown in FIGS. 2 and 3, for example.

  FIG. 5 shows an example of the instruction completion control unit CCTL shown in FIG. In FIG. 5, a module for receiving data transfer completion information from the data cache DCM, branch determination completion information from the branch control unit BCTL, operation completion information from the arithmetic unit EXU, exception information, etc. Is omitted. For example, the comparison unit CMP20 and the logical product unit AND3 of the bypass unit BYP are provided corresponding to each module (data cache DCM, branch control unit BCTL, arithmetic unit EXU, FPU, etc.) that outputs completion information. In this case, the logical sum unit OR1 outputs a logical sum result of the output of the logical product unit AND3 provided corresponding to each module and the output of the selection unit SEL10. Further, for example, the selection unit SEL20, the latches LAT10, LAT12, LAT20, LAT40, the inverter INV1, the logical product units AND1, AND2, and the comparison unit CMP10 correspond to the respective arithmetic units EXU, FPU that output the completion information and the exception information. Provided.

  In the example of FIG. 5, the instruction completion control unit CCTL executes the instruction completion process for a maximum of four instructions in one cycle. Note that the maximum number of instructions executed in the instruction completion process in one cycle is not limited to four.

  The instruction completion control unit CCTL includes a pointer unit PT, an addition unit ADD, latches LAT10, LAT12, LAT20, LAT30, LAT40, an inverter INV1, an AND unit AND1, AND2, a selection unit SEL10, SEL20, a commit stack entry CSE, and a bypass unit BYP. , A comparison unit CMP10, an instruction completion processing unit COMPU1, and an instruction completion unit COMPU2. The bypass unit BYP includes a comparison unit CMP20, a logical product unit AND3, and a logical sum unit OR1.

  The instruction completion control unit CCTL receives a signal FED indicating the set value of the FED flag from the state control unit MCTL. The instruction completion control unit CCTL receives an operation completion signal ECOMP indicating the completion of the operation and an instruction identifier EIID for identifying the instruction from the arithmetic unit FPU as operation completion information. For example, when the number of instructions that can be registered in the commit stack entry CSE is 64, the instruction identifier EIID is a 6-bit signal.

  Further, the instruction completion control unit CCTL, when an exception such as an overflow occurs due to the arithmetic processing of the arithmetic unit FPU, the exception information EXSIG indicating that the arithmetic exception has occurred is displayed in the next cycle when the arithmetic completion signal ECOMP is received. Received from the arithmetic unit FPU. Hereinafter, the operation completion signal ECOMP, the instruction identifier EIID, and the exception information EXIGG are also referred to as signals ECOMP, EID, and EXIGG.

  The latches LAT10, LAT12, LAT20, LAT30, and LAT40 hold the received data. Then, the latches LAT10, LAT12, LAT20, LAT30, and LAT40 output the held data in the next cycle when the data is received.

  For example, the latch LAT10 receives the operation completion signal ECOMP and the instruction identifier EIID from the arithmetic unit FPU, and holds the operation completion signal ECOMP and the instruction identifier EIID. Then, the latch LAT10 outputs the signals ECOMP and EIID to the latch LAT12 and the selection unit SEL20 as the operation completion signal ECOMP_LCH and the instruction identifier EIID_LCH in the next cycle after receiving the signals ECOMP and EIID. Hereinafter, the operation completion signal ECOMP_LCH and the instruction identifier EIID_LCH are also referred to as signals ECOMP_LCH and EID_LCH.

  In addition, for example, the latch LAT12 outputs the signals ECOMP_LCH and EIID_LCH received from the latch LAT10 as the operation completion signal ECOMP_LL and the instruction identifier EIID_LL in the next cycle after receiving the signals ECOMP_LCH and EIID_LCH. For example, the latch LAT12 outputs the operation completion signal ECOMP_LL to the logical product unit AND2, and outputs the instruction identifier EIID_LL to the comparison unit CMP10 and the commit stack entry CSE.

  The selection unit SEL20 receives the operation completion signal ECOMP and the instruction identifier EIID from the arithmetic unit FPU, and receives the operation completion signal ECOMP_LCH and the instruction identifier EIID_LCH from the latch LAT10. Further, the selection unit SEL20 receives the signal FED from the state control unit MCTL. Then, the selection unit SEL20 selects one of the signal ECOMP and EIID and the signal ECOMMP_LCH and EIID_LCH based on the signal FED, and outputs the selected signal to the commit stack entry CSE as the signals ECOMPa and EIIDa. .

  For example, when the signal FED has a logical value “1”, the selection unit SEL20 outputs the operation completion signal ECOMP and the instruction identifier EIID received from the arithmetic unit FPU to the commit stack entry CSE as signals ECOMPa and EIIDa. For example, when the signal FED has a logical value “0”, the selection unit SEL20 outputs the operation completion signal ECOMP_LCH and the instruction identifier EIID_LCH received from the latch LAT10 to the commit stack entry CSE as signals ECOMPa and EIIDa. Hereinafter, the signal ECOMPa is also referred to as an operation completion signal ECOMPa, and the signal EIIDa is also referred to as an instruction identifier EIIDa.

  The commit stack entry CSE updates entry information of an instruction corresponding to the instruction identifier EIIDa based on the calculation completion signal ECOMPa and the instruction identifier EIIDa received from the selection unit SEL20. For example, the commit stack entry CSE sets the status information in the entry information of the instruction corresponding to the instruction identifier EIIDa to the information of the operation completion signal ECOMPa (completion of operation).

  In addition, when the commit stack entry CSE receives the exception information EXSIG_LCH and the instruction identifier EIID_LL from the latches LAT20 and LAT12, the commit stack entry CSE updates the entry information of the instruction corresponding to the instruction identifier EIID_LL. For example, the commit stack entry CSE sets the state information in the entry information of the instruction corresponding to the instruction identifier EIID_LL to the content of the exception information EXIG_LCH (occurrence of operation exception).

  The exception information EXSIG_LCH corresponds to the exception information EXSIG transferred from the computing unit FPU to the commit stack entry CSE via the logical product unit AND1 and the latch LAT20. When the signal FED has a logical value “1”, the exception information EXSIG_LCH has a logical value “0” regardless of whether or not the AND unit AND1 receives the exception information EXSIG.

  For example, the inverter INV1 receives the signal FED from the state control unit MCTL, and outputs an inverted signal of the signal FED to the AND unit AND1. The AND unit AND1 receives the exception information EXSIG from the arithmetic unit FPU and receives the inverted signal of the signal FED from the inverter INV1. The logical product unit AND1 outputs a logical product result of the exception information EXSIG and the inverted signal of the signal FED to the latch LAT20.

  The latch LAT20 outputs the logical product result (logical product result of the exception information EXSIG and the inverted signal of the signal FED) received from the logical product unit AND1 as exception information EXSIG_LCH in the next cycle in which the logical product result is received. For example, the latch LAT20 outputs the exception information EXSIG_LCH to the commit stack entry CSE and the AND unit AND2.

  Here, for example, when an operation exception occurs, the arithmetic unit FPU sends the exception information EXSIG indicating that the operation exception has occurred in the next cycle after outputting the operation completion signal ECOMP and the instruction identifier EIID to the instruction completion control unit CCTL. Output to. For this reason, when an operation exception occurs, the commit stack entry CSE receives the exception information EXSIG_LCH in the same cycle as the cycle in which the instruction identifier EIID_LL is received.

  The entry information of the instruction registered in the commit stack entry CSE is read based on the pointers PTR1, PTR2, PTR3, and PTR4. Note that the pointers PTR1, PTR2, PTR3, and PTR4 are generated based on the pointers PTRm1, PTRm2, PTRm3, and PTRm4.

  The pointer PTRm1 is a pointer signal indicating the number of the oldest instruction identifier among valid instructions registered in the commit stack entry CSE (instructions for which instruction completion processing has not been executed). That is, the pointer PTRm1 is a pointer signal indicating the top of the queue (TOQ: Top Of Queue). The pointers PTRm2, PTRm3, and PTRm4 are pointer signals indicating the numbers of the second, third, and fourth oldest instruction identifiers among the valid instructions registered in the commit stack entry CSE.

  For example, when the number of instructions that can be registered in the commit stack entry CSE is 64, the pointers PTRm (PTRm1-PTRm4) and PTR (PTR1-PTR4) are 6-bit signals. Each pointer PTRm is counted up, for example, every time an instruction completion process is executed.

  For example, the pointer unit PT holds the pointers PTRm1 to PTRm4, and outputs the held pointers PTRm1 to PTRm4 to the adding unit ADD.

  The adding unit ADD receives the pointers PTRm1 to PTRm4 from the pointer unit PT, and receives the signals COMMIT1, COMMIT2, COMMIT3, and COMMIT4 from the instruction completion processing unit COMPU1. Then, the adding unit ADD counts up the pointers PTRm1 to PTRm4 received from the pointer unit PT according to the signals COMMIT1 to COMMIT4 received from the instruction completion processing unit COMPU1. The signals COMMIT1 to COMMIT4 are signals for causing the instruction completion unit COMPU2 to execute instruction completion processing, for example.

  For example, when only the signal COMMIT1 has the logical value “1”, the adder ADD adds 1 to the values of the pointers PTRm1 to PTRm4 received from the pointer unit PT because one instruction is completed. Further, for example, when all of the signals COMMIT1 to COMMIT4 have the logical value “1”, the adder ADD adds 4 to the values of the pointers PTRm1 to PTRm4 received from the pointer unit PT because four instructions are completed. To do.

  Then, the addition unit ADD outputs the pointers PTRm1 to PTRm4 counted up according to the signals COMMIT1 to COMMIT4 as the pointers PTR1 to PTR4 to the pointer unit PT, the selection unit SEL10, the comparison units CMP10 and CMP20. For example, the pointer unit PT holds the pointers PTR1 to PTR4 received from the adding unit ADD as pointers PTRm1 to PTRm4.

  When the number of instructions that can be registered in the commit stack entry CSE is 64, for example, the upper limit of the numerical values set in the pointers PTRm1-PTRm4 and PTR1-PTR4 is 63. For this reason, when the value of the pointers PTR1 to PTR4 after the addition exceeds 63, the addition unit ADD returns to 0 and performs calculation. For example, when the value of the pointer PTRm1 is 62 and only the signal COMMIT1 is the logical value “1”, the values of the pointers PTR1, PTR2, PTR3, and PTR4 are 63, 0, 1, and 2, respectively.

  The selection unit SEL10 is the same as or similar to the selection unit SEL10 illustrated in FIG. That is, the selection unit SEL10 is an example of a selection unit that reads instructions to be subjected to instruction completion processing from a holding unit (for example, commit stack entry CSE) in the order of decoding. For example, the selection unit SEL10 receives the pointers PTR1 to PTR4 from the addition unit ADD as read pointers when reading entry information from the commit stack entry CSE. Then, the selection unit SEL10 reads the entry information of the instruction identifier having the number indicated by the pointers PTR1 to PTR4 from the entry information registered for each instruction identifier in the commit stack entry CSE.

  For example, the selection unit SEL10 outputs signals ECOMPc1, ECOMPc2, ECOMPc3, and ECOMPc4 in the entry information read from the commit stack entry CSE to the logical sum unit OR1 of the bypass unit BYP. Signals ECOMPc1-ECOMPc4 are signals indicating information on the operation completion signal ECOMP set in the state information in the entry information of the instruction indicated by the pointers PTR1-PTR4.

  For example, the selection unit SEL10 outputs signals TRAPs1, TRAPs2, TRAPs3, and TRAPs4 in the entry information read from the commit stack entry CSE to the latch LAT30. Signals TRAPs1-TRAPs4 are signals indicating the contents of the exception information EXSIG_LCH set in the state information in the entry information of the instruction indicated by the pointers PTR1-PTR4. Thereby, the contents (signals TRAPs1-TRAPs4) of the exception information EXSIG_LCH of the instruction indicated by the pointers PTR1-PTR4 are set in the latch LAT30.

  Here, the bypass unit BYP will be described. The bypass unit BYP is the same as or similar to the bypass unit BYP shown in FIG. That is, the bypass unit BYP is an example of a bypass unit that generates bypass information indicating completion of calculation. For example, the comparison unit CMP20 of the bypass unit BYP receives the instruction identifier EIID from the arithmetic unit FPU and receives the pointers PTR1 to PTR4 from the addition unit ADD. Then, the comparison unit CMP20 compares the instruction identifier EIID with the pointers PTR1 to PTR4 and outputs the comparison result to the AND unit AND3.

  For example, when the instruction identifier EIID matches the pointer PTR1, the comparison unit CMP20 performs a logical AND operation on a comparison result (a signal having a logical value “1”) indicating that the instruction identifier EIID matches the pointer PTR1. Output to the part AND3. Further, the comparison unit CMP20 outputs a comparison result (a signal having a logical value “0”) indicating that the instruction identifier EIID and the pointers PTR2 to PTR3 do not match to the logical product unit AND3.

  The AND unit AND3 receives the comparison result between the instruction identifier EIID and each of the pointers PTR1 to PTR4, the operation completion signal ECOMP, and the signal FED from the comparison unit CMP20, the arithmetic unit FPU, and the state control unit MCTL, respectively. Then, the logical product unit AND3 outputs the logical product result of the received signal to the logical sum unit OR1 as bypass information ECOMPw1, ECOMPw2, ECOMPw3, and ECOMPw4.

  For example, the logical product unit AND3 outputs the logical product result of the three signals of the comparison result between the instruction identifier EIID and the pointer PTR1 and the operation completion signal ECOMP and the signal FED as the bypass information ECOMPw1 to the logical sum unit OR1. Further, for example, the logical product unit AND3 outputs the logical product result of the three signals of the comparison result between the instruction identifier EIID and the pointer PTR2 and the operation completion signal ECOMP and the signal FED as the bypass information ECOMPw2 to the logical sum unit OR1.

  Further, for example, the AND unit AND3 outputs the comparison result between the instruction identifier EIID and the pointer PTR3 and the logical product result of three signals of the operation completion signal ECOMP and the signal FED to the OR unit OR1 as bypass information ECOMPw3. Further, for example, the AND unit AND3 outputs a comparison result between the instruction identifier EIID and the pointer PTR4 and a logical product result of three signals of the operation completion signal ECOMP and the signal FED to the OR unit OR1 as bypass information ECOMPw4.

  As described above, the bypass information ECOMPw (for example, a signal having the logical value “1”) indicating the completion of the operation matches the instruction identifier EIID corresponding to the operation completion signal ECOMP and the pointer PTR, and the signal FED has the logical value. If “1”, it is generated. In other words, the bypass unit BYP suppresses detection of an exception generated by the arithmetic processing, and the instruction indicated by the arithmetic completion information output from the arithmetic unit FPU matches the instruction that is the target of the instruction completion processing. Bypass information ECOMPw indicating completion of the calculation is generated. Hereinafter, the bypass information ECOMPw1-ECOMPw4 is also referred to as signals ECOMPw1-ECOMPw4.

  The OR unit OR1 receives the signals ECOMPw1-ECOMPw4 from the logical product unit AND3, and receives the signals ECOMPc1-ECOMPc4 from the selection unit SEL10. Then, the OR unit OR1 outputs the logical OR results of the signals ECOMPw1-ECOMPw4 and the signals ECOMPc1-ECOMPc4 to the latch LAT30 as signals ECOMPs1, ECOMPs2, ECOMPS3, ECOMPs4.

  Thereby, information (signals ECOMPs1-ECOMPs4) related to the state of the instruction indicated by the pointers PTR1-PTR4 is set in the latch LAT30. Hereinafter, the signals ECOMPs1-ECOMPs4 are also referred to as operation completion signals ECOMPs1-ECOMPs4.

  For example, the signal ECOMPs1 is a logical sum result of the signals ECOMPw1 and ECOMPc1, and the signal ECOMPs2 is a logical sum result of the signals ECOMPw2 and ECOMPc2. For example, the signal ECOMPs3 is a logical sum result of the signals ECOMPw3 and ECOMPc3, and the signal ECOMPs4 is a logical sum result of the signals ECOMPw4 and ECOMPc4.

  As described above, when the detection of the operation exception is suppressed and the instruction identifier EIID matches any of the pointers PTR1 to PTR4, the operation completion signal ECOMP is used as the operation completion signal ECOMPs of the instruction indicated by the instruction identifier EIID. It is transferred to the latch LAT30. That is, the operation completion signal ECOMP relating to the instruction to be processed is transferred to the latch LAT 30 without going through the commit stack entry CSE. For this reason, the instruction completion control unit CCTL can shorten the time from the reception of the operation completion signal ECOMP related to the instruction to be subjected to instruction completion processing until the information of the operation completion signal ECOMP is set in the latch LAT30.

  For example, the latch LAT30 holds the signals ECOMPs1-ECOMPs4 received from the logical sum unit OR1 of the bypass unit BYP. The latch LAT 30 outputs the held signals ECOMPs 1 to ECOMPs 4 to the instruction completion unit COMPU 1 as signals ECOMPsl 1, ECOMPsl 2, ECOMPsl 3, and ECOMPsl 4 in the next cycle when the signals ECOMPs 1 to ECOMPs 4 are received.

  Further, for example, the latch LAT30 holds the signals TRAPs1-TRAPs4 received from the selection unit SEL10. Then, the latch LAT30 outputs the held signals TRAPs1-TRAPs4 to the instruction completion unit COMPU2 as signals TRAPsl1, TRAPsl2, TRAPsl3, TRAPsl4 in the next cycle when the signals TRAPs1-TRAPs4 are received.

  The instruction completion unit COMPU1 receives from the latch LAT40 a signal INH that inhibits execution of the instruction completion processing in addition to the signals ECOMPsl1-ECOMPsl4 output from the latch LAT30. The signal INH is generated, for example, when detection of an operation exception is not suppressed and an operation exception occurs in one of the instructions that are the target of instruction completion processing.

  For example, the comparison unit CMP10 receives the instruction identifier EIID_LL and the pointers PTR1-PTR4 from the latch LAT12 and the addition unit ADD, and compares the instruction identifier EIID_LL with each pointer PTR1-PTR4. For example, when the instruction identifier EIID_LL matches any of the pointers PTR1 to PTR4, the comparison unit CMP10 outputs a signal having a logical value “1” to the logical product unit AND2 as a comparison result. Further, for example, when the instruction identifier EIID_LL does not match any of the pointers PTR1 to PTR4, the comparison unit CMP10 outputs a signal having a logical value “0” to the logical product unit AND2 as a comparison result.

  The AND unit AND2 receives, for example, the comparison result by the comparison unit CMP10, the operation completion signal ECOMP_LL held in the latch LAT12, and the exception information EXSIG_LCH held in the latch LAT20. Then, the AND unit AND2 outputs the logical product result of the three signals of the comparison result by the comparison unit CMP10, the operation completion signal ECOMP_LL, and the exception information EXSIG_LCH to the latch LAT40. The latch LAT40 outputs the logical product result of the logical product unit AND2 to the instruction completion processing unit COMPU1 as a signal INH in the next cycle after receiving the logical product result.

  The instruction completion processing unit COMPU1 and the instruction completion unit COMPU2 are examples of a completion processing unit. For example, the instruction completion processing unit COMPU1 receives the signals ECOMPsl1-ECOMPsl4 from the latch LAT30, and receives the signal INH for inhibiting the execution of the instruction completion processing from the latch LAT40.

  Then, the instruction completion processing unit COMPU1 generates signals COMMIT1-COMMIT4 based on the signals ECOMPsl1-ECOMPsl4, INH. For example, the instruction completion processing unit COMPU1 suppresses generation of the signals COMMIT1 to COMMIT4 for executing the instruction completion processing when the signal INH for suppressing the execution of the instruction completion processing is received or when the pipeline flush is executed. .

  For example, in a cycle in which the signal INH is a logical value “0”, the instruction completion processing unit COMPU1 sends signals COMMIT1 to COMMIT4 (for example, a signal having a logical value “1”) for executing the instruction completion processing to the instruction completion unit COMPU2. Suppresses output.

  For example, when the signal COMMIT having the logical value “1” instructs execution of the instruction completion process, the instruction completion processing unit COMPU1 sets the signals COMMIT1 to COMMIT4 to the logical value in the cycle in which the signal INH has the logical value “1”. Set to 0 ”. Further, for example, in a cycle in which the signal INH has a logical value “0”, the instruction completion processing unit COMPU1 receives the signals COMMIT1 to COMMIT4 having the logical value “1” and the signals ECOMPsl1 to ECOMPsl4 having the logical value “1”. , Output to the instruction completion unit COMPU2.

  For example, the condition that the signal COMMIT1 is set to the logic value “1” in the cycle in which the signal INH is the logic value “0” is the case where the signal ECOMPsl1 is the logic value “1”. The condition for setting the signal COMMIT2 to the logical value “1” is when the signal COMMIT1 and the signal ECOMPsl2 are the logical value “1”. The condition for setting the signal COMMIT3 to the logical value “1” is when the signal COMMIT2 and the signal ECOMPsl3 are the logical value “1”. The condition for setting the signal COMMIT4 to the logical value “1” is when the signal COMMIT3 and the signal ECOMPsl4 are the logical value “1”. Hereinafter, a condition in which each of the signals COMMIT1 to COMMIT4 is set to the logical value “1” is also referred to as a completion condition.

  The instruction completion unit COMPU2 receives the signals COMMIT1-COMMIT4 from the instruction completion processing unit COMPU1, and receives the signals TRAPsl1-TRAPsl4 from the latch LAT30. Then, the instruction completion unit COMPU2 executes instruction completion processing and exception processing based on the signals COMMIT1-COMMIT4 and the signals TRAPsl1-TRAPsl4.

  For example, when the instruction completion unit COMPU2 receives the signals COMMIT1 to COMMIT4 having the logical value “1”, the instruction completion unit COMPU2 outputs a control signal for writing the operation result to the floating point register FPREG to the floating point update buffer FPBUF and the like. Further, for example, when the instruction completion unit COMPU2 receives the signal COMMIT1 to COMMIT4 having the logical value “1”, the instruction completion unit COMPU2 outputs a control signal for updating the PC value and the next PC value to the state control unit MCTL.

  In this way, the instruction completion unit COMPU2 executes instruction completion processing based on the signals COMMIT1-COMMIT4 generated based on the bypass information ECOMPw1-ECOMPw4, the signals ECOMPc1-ECOMPc4, and the like. That is, the instruction completion unit COMPU2 executes instruction completion processing based on the bypass information ECOMPw and the state information (signal ECOMPc) of the instruction read from the commit stack entry CSE by the selection unit SEL10.

  For example, when the bypass information ECOMPw1 indicating the completion of the operation is generated, the signal COMMIT1 is a signal corresponding to the bypass information ECOMPw1 indicating the completion of the operation. For example, when the bypass information ECOMPw1 indicating completion of the calculation is not generated, the signal COMMIT1 is a signal corresponding to the signal ECOMPc1.

  Therefore, for example, the instruction completion unit COMPU2 executes instruction completion processing based on the bypass information ECOMPw1 for the instruction for which the bypass information ECOMPw1 indicating the completion of the operation is generated. Further, for example, the instruction completion unit COMPU2 executes instruction completion processing based on the signal ECOMPc1 read from the commit stack entry CSE for an instruction for which bypass information ECOMPw1 indicating completion of the operation has not been generated.

  For example, the completion processing unit COMPU illustrated in FIG. 1 corresponds to a module including the latch LAT 30, the instruction completion processing unit COMPU1, the instruction completion unit COMPU2, and the like. Further, the configuration of the instruction completion control unit CCTL is not limited to this example.

  FIG. 6 shows an example of pipeline processing of the arithmetic processing unit PU shown in FIG. For example, the arithmetic processing unit PU executes pipeline processing including a decode stage D, a priority stage P, a buffer stage B, an arithmetic execution stage X, a register update stage U, and a register write stage W.

  In the decode stage D, the instruction decoder DEC decodes the instruction received from the instruction cache CCM in order. Then, the instruction decoder DEC registers the decoded instruction together with the instruction identifier in the order of instructions in the commit stack entry CSE of the instruction completion control unit CCTL in order. Further, the instruction decoder DEC registers the decoded instruction in the reservation stations RSA, RSE, RSF, and RSBR based on the instruction type.

  In the priority stage P, each reservation station RSA, RSE, RSF, RSBR selects an instruction in an executable state. In the buffer stage B, modules such as the arithmetic units EXU and FPU read data and the like used by the instruction selected in the priority stage P from a register (for example, registers EXREG and FPREG).

  In the operation execution stage X, modules such as the operation units EXU and FPU execute the instruction selected in the priority stage P using the data read from the register in the buffer stage B and the like.

  In the register update stage U, modules such as the calculators EXU and FPU store the calculation results in an update buffer (for example, update buffer EXBUF, FPBUF, etc.). Further, the arithmetic units EXU and FPU output calculation completion information (for example, a calculation completion signal ECOMP and an instruction identifier EIID) indicating the completion of the calculation to the instruction completion control unit CCTL. For example, when an arithmetic exception occurs, the arithmetic units EXU and FPU output exception information EXSIG indicating that the arithmetic exception has occurred to the instruction completion control unit CCTL.

  Further, for example, the data cache DCM outputs data transfer completion information indicating that the data transfer is completed to the instruction completion control unit CCTL. Further, for example, the branch control unit BCTL outputs branch determination completion information indicating that the determination on the branch prediction of the branch prediction mechanism BRPRE is completed to the instruction completion control unit CCTL. Then, the instruction completion control unit CCTL executes instruction completion processing in-order based on each completion information such as the operation completion signal ECOMP.

  In the register write stage W, the update buffer (for example, the update buffer EXBUF, FPBUF, etc.) writes the operation result or the like to the register (for example, the register EXREG, FPREG, etc.). Further, the state control unit MCTL updates the PC value, the next PC value, and the like. Note that the pipeline processing of the arithmetic processing unit PU is not limited to this example.

  FIG. 7 shows an example of out-of-order execution by the superscalar method. In the example of FIG. 7, the arithmetic processing unit PU executes a maximum of four instructions in parallel. For example, the instruction decoder DEC acquires (fetches) a plurality of instructions from the instruction cache CCM in order, and decodes the acquired plurality of instructions in order. Then, the operation unit OP and the branch control unit BCTL execute a plurality of instructions decoded by the instruction decoder DEC out of order. Finally, the instruction completion control unit CCTL or the like executes a commit process (instruction completion process) for an instruction for which an operation has been completed in order. Since the commit process is executed in order, an instruction executed out of order may be waited until the commit process is executed (commit wait in FIG. 7). As described above, the arithmetic processing unit PU executes the commit process in order even when a plurality of instructions are executed out of order.

  FIG. 8 shows an example of the operation of the instruction completion control unit CCTL shown in FIG. FIG. 8 shows an example of the operation of the instruction completion control unit CCTL when detection of an operation exception is suppressed (FED = 1) and an operation exception occurs. In the operation of FIG. 8, since the signal FED has the logical value “1”, even when the instruction completion control unit CCTL receives the exception information EXSIG having the logical value “1” in the cycle 5, the exception information EXSIG_LCH is The value is maintained at “0”. For this reason, the signal INH is maintained at the logical value “0”.

  FADD (IID = 12) in the figure indicates a pipeline stage of floating point addition based on an instruction corresponding to an instruction identifier (IID = 12) having a value “12”. For example, cycle 4 corresponds to the last operation execution stage X of the floating point addition.

  In cycle 4, the instruction completion control unit CCTL receives the operation completion signal ECOMP having the logical value “1” and the instruction identifier EIID having the value “12” from the arithmetic unit FPU. The instruction identifier EIID having the value “12” is an identifier of an instruction corresponding to the operation completion signal ECOMP. Since the signal FED is a logical value “1” and the value of the pointer PTR1 and the value of the instruction identifier EIID are both 12, the signal ECOMPw1 is the same logical value “1” as the logical value “1” of the operation completion signal ECOMP. To change. Then, since the signal ECOMPw1 changes to the logical value “1”, the signal ECOMPs1 changes to the logical value “1”.

  As a result, the signal ECOMPs1 having the logical value “1” is held in the latch LAT30. In cycle 4, the operation completion signal ECOMP information (computation completion) is set in the status information of the instruction corresponding to the instruction identifier EIID having the value “12” among the instructions registered in the commit stack entry CSE. The

  In cycle 5, since the signal ECOMPs1 having the logical value “1” is held in the latch LAT30 in cycle 4, the signal ECOMPsl1 that is the output signal of the latch LAT30 changes to the logical value “1”. Since the signal ECOMPsl1 is the logical value “1” and the signal INH is the logical value “0”, the signal COMMIT1 changes to the logical value “1”.

  Further, for example, the signals COMMIT 2 -COMIT 4 change to the logical value “1” when the completion conditions described in FIG. 5 are satisfied. For example, when the signal ECOMPc2-ECOMPc4 having the logical value “1” is read from the commit stack entry CSE in the cycle 4, the signal COMMIT2-COMIT4 also changes to the logical value “1” in the cycle 5. Since the signal COMMIT1-COMIT4 changes to the logical value “1”, the value of the pointer PTR1 changes to 16 (= 12 + 4). As a result, the pointer PTR1 having the value “16” is held in the pointer portion PT.

  In cycle 6, the value of pointer PTR1m changes to 16, which is the value of pointer PTR1 held in pointer unit PT in cycle 5.

  In this way, the instruction completion control unit CCTL can execute the register update stage U in one cycle when the signal FED has a logical value “1” and the value of the instruction identifier EIID is the same as the value of the pointer PTR1, for example. On the other hand, for example, in a configuration in which bypass information ECOMPw1-ECOMPw4 is not generated, the register update stage U is executed in two cycles as shown in FIG.

  That is, in the operation of FIG. 8, the instruction completion process can be started one cycle earlier than the operation of the configuration in which the bypass information ECOMPw1-ECOMPw4 is not generated (for example, the operation of FIG. 12). For this reason, the performance of the arithmetic processing unit PU is improved. For example, when the completion condition of the signal COMMIT2-COMIT4 is satisfied, the arithmetic processing unit PU also causes the instruction indicated by the pointer PTR2-PTR4 (the instruction subsequent to the instruction indicated by the pointer PTR1) to be in the same cycle as the instruction indicated by the pointer PTR1. The instruction completion process can be started. That is, the arithmetic processing unit PU can also start the instruction completion process for the subsequent instruction one cycle earlier than the operation (for example, the operation of FIG. 12) in which the bypass information ECOMPw1-ECOMPw4 is not generated.

  FIG. 9 shows another example of the operation of the instruction completion control unit CCTL shown in FIG. FIG. 9 shows an example of the operation of the instruction completion control unit CCTL when detection of an operation exception is suppressed (FED = 1) and no operation exception occurs. Detailed descriptions of the same or similar operations as those described in FIG. 8 are omitted. FADD (IID = 12) in the figure indicates a pipeline stage of floating point addition based on an instruction corresponding to an instruction identifier (IID = 12) having a value “12”.

  The operation of FIG. 9 is the same as or similar to the operation of FIG. 8 except that the exception information EXSIG from the arithmetic unit FPU is maintained at the logical value “0”. Therefore, also in the operation of FIG. 9, the instruction completion process can be started one cycle earlier than the operation (for example, FIG. 12) in which the bypass information ECOMPw1-ECOMPw4 is not generated.

  FIG. 10 shows another example of the operation of the instruction completion control unit CCTL shown in FIG. FIG. 10 shows an example of the operation of the instruction completion control unit CCTL when an operation exception occurs in a state where detection of an operation exception is not suppressed (FED = 0). Detailed description of the same or similar operations as those described with reference to FIGS. 8 to 9 will be omitted. FADD (IID = 12) in the figure indicates a pipeline stage of floating point addition based on an instruction corresponding to an instruction identifier (IID = 12) having a value “12”. For example, cycle 4 corresponds to the last operation execution stage X of the floating point addition.

  In cycle 4, the instruction completion control unit CCTL receives the operation completion signal ECOMP having the logical value “1” and the instruction identifier EIID having the value “12” from the arithmetic unit FPU. As a result, the operation completion signal ECOMP having the logical value “1” and the instruction identifier EIID having the value “12” are held in the latch LAT10. Note that since the signal FED is the logical value “0”, the information of the operation completion signal ECOM is not registered in the commit stack entry CSE in the cycle 4. Further, since the signal FED has the logical value “0”, the signal ECOMPw1 is maintained at the logical value “0”.

  In cycle 5, the instruction completion control unit CCTL receives exception information EXSIG having a logical value “1” from the arithmetic unit FPU. As a result, the exception information EXSIG having the logical value “1” is held in the latch LAT20. Further, the operation completion signal ECOMP_LCH and the instruction identifier EIID_LCH change to the logical value “1” and the value “12”, respectively.

  Since the signal FED has the logical value “0”, among the instructions registered in the commit stack entry CSE, the status information of the instruction corresponding to the instruction identifier EIID_LCH having the value “12” includes the information (calculation of the operation completion signal ECOMP_LCH). Completed) is set. The operation completion signal ECOMP_LCH having the logical value “1” and the instruction identifier EIID_LCH having the value “12” are held in the latch LAT12.

  In cycle 6, since the value of the pointer PTR1 is 12, among the instructions registered in the commit stack entry CSE, the status information of the instruction corresponding to the instruction identifier of the value “12” (for example, information of the operation completion signal ECOMP_LCH) ) Is read out. As a result, the signal ECOMPc1 changes to the logical value “1”. Then, since the signal ECOMPc1 changes to the logical value “1”, the signal ECOMPs1 changes to the logical value “1”. As a result, the signal ECOMPs1 having the logical value “1” is held in the latch LAT30.

  In addition, the operation completion signal ECOMP_LL and the instruction identifier EIID_LL change to the logical value “1” and the value “12”, respectively. The exception information EXSIG_LCH changes to a logical value “1”. As a result, the contents (exception occurrence) of the exception information EXIG_LCH are set in the status information of the instruction corresponding to the instruction identifier EIID_LL having the value “12” among the instructions registered in the commit stack entry CSE. The signal TRAPs1 is maintained at the logical value “0” in the cycle 6 because the contents of the exception information EXSIG_LCH is not set in the commit stack entry CSE until the cycle 5.

  Since both the exception information EXSIG_LCH and the operation completion signal ECOMP_LL have the logical value “1” and the value of the pointer PTR1 matches the value of the instruction identifier EIID_LL, the output of the AND unit AND2 becomes the logical value “1”. Change. As a result, a signal having a logical value “1” is held in the latch LAT 40.

  In cycle 7, since the signal having the logical value “1” is held in the latch LAT 40 in cycle 6, the signal INH that is the output signal of the latch LAT 40 changes to the logical value “1”. Further, the signal ECOMPsl1 changes to a logical value “1”. Note that since the signal INH has the logical value “1”, the signal COMMIT1 is maintained at the logical value “0” even when the signal ECOMPsl1 changes to the logical value “1”. Therefore, the signals COMMIT2 to COMMIT4 are maintained at the logical value “0” even when the signals ECOMPC2 to ECOMPC4 having the logical value “1” are read from the commit stack entry CSE in the cycle 6, for example.

  Further, since the signals COMMIT1 to COMMIT4 are maintained at the logical value “0”, the value of the pointer PTR1 is also maintained at 12. Since the value of the pointer PTR1 is 12, among the instructions registered in the commit stack entry CSE, the status information of the instruction corresponding to the instruction identifier of the value “12” (for example, information on the operation completion signal ECOMP_LCH, exception information EXSIG_LCH Information) is read out.

  As a result, the signals ECOMPc1 and ECOMPs1 are maintained at the logical value “1”, and the signal TRAPs1 is changed to the logical value “1”. As a result, the signals ECOMPs1 and TRAPs1 having the logical value “1” are held in the latch LAT30. Further, the output of the logical product AND2 changes to the logical value “0” because the exception information EXSIG_LCH and the like has the logical value “0”. As a result, a signal having a logical value “0” is held in the latch LAT 40.

  In cycle 8, since the signal having the logical value “0” is held in the latch LAT 40 in cycle 7, the signal INH that is the output signal of the latch LAT 40 changes to the logical value “0”. Further, the signal ECOMPsl1 is maintained at the logical value “1”. Since the signal ECOMPsl1 is the logical value “1” and the signal INH is the logical value “0”, the signal COMMIT1 changes to the logical value “1”.

  Further, the signal TRAPsl1 changes to a logical value “1”. Thereby, an exception is detected. Since the signal TRAPsl1 has the logical value “1”, the signals COMMIT2 to COMMIT4 are maintained at the logical value “0”. Since the signal COMMIT1 is the logical value “1” and the signals COMMIT2 to COMMIT4 are the logical value “0”, the value of the pointer PTR1 changes to 13 (= 12 + 1). As a result, the pointer PTR1 having the value “13” is held in the pointer portion PT.

  In cycle 9, the value of pointer PTR1m changes to 13 which is the value of pointer PTR1 held in pointer unit PT in cycle 8. Since the signal TRAPsl1 changes to the logical value “1” in cycle 8, exception processing is executed. For example, all instructions following the instruction in which the exception occurred are canceled and deleted from the registration of the commit stack entry CSE. Thereby, the value of the pointer PTR1 is set to 0. Then, exception processing corresponding to the exception that has occurred is executed.

  FIG. 11 shows another example of the operation of the instruction completion control unit CCTL shown in FIG. FIG. 11 shows an example of the operation of the instruction completion control unit CCTL when no operation exception occurs in a state where detection of an operation exception is not suppressed (FED = 0). Detailed descriptions of the same or similar operations as those described in FIGS. 8 to 10 are omitted. FADD (IID = 12) in the figure indicates a pipeline stage of floating point addition based on an instruction corresponding to an instruction identifier (IID = 12) having a value “12”. For example, cycle 4 corresponds to the last operation execution stage X of the floating point addition.

  In cycle 4, the instruction completion control unit CCTL receives the operation completion signal ECOMP having the logical value “1” and the instruction identifier EIID having the value “12” from the arithmetic unit FPU. Note that since the signal FED is the logical value “0”, the information of the operation completion signal ECOM is not registered in the commit stack entry CSE in the cycle 4. Further, since the signal FED has the logical value “0”, the signal ECOMPw1 is maintained at the logical value “0”.

  In cycle 5, the operation completion signal ECOMP_LCH and the instruction identifier EIID_LCH change to the logical value “1” and the value “12”, respectively. Since the signal FED has the logical value “0”, among the instructions registered in the commit stack entry CSE, the status information of the instruction corresponding to the instruction identifier EIID_LCH having the value “12” includes the information (calculation of the operation completion signal ECOMP_LCH). Completed) is set. Note that since the exception information EXSIG is maintained at the logical value “0”, the value held in the latch LAT 20 is also maintained at 0.

  In cycle 6, since the value of the pointer PTR1 is 12, among the instructions registered in the commit stack entry CSE, the status information of the instruction corresponding to the instruction identifier of the value “12” (for example, information of the operation completion signal ECOMP_LCH) ) Is read out. As a result, the signal ECOMPc1 changes to the logical value “1”. Then, since the signal ECOMPc1 changes to the logical value “1”, the signal ECOMPs1 changes to the logical value “1”.

  In addition, the operation completion signal ECOMP_LL and the instruction identifier EIID_LL change to the logical value “1” and the value “12”, respectively. The exception information EXSIG_LCH is maintained at the logical value “0”. Since the exception information EXSIG_LCH has the logical value “0”, the commit stack entry CSE does not update the state information of the instruction identifier EIID_LL having the value “12”. Further, since the exception information EXSIG_LCH has the logical value “0”, the output of the logical product unit AND2 is maintained at the logical value “0”. Therefore, the value held in the latch LAT 40 is also maintained at 0.

  In cycle 7, the signal ECOMPsl1 changes to the logical value “1”, and the signal INH that is the output signal of the latch LAT40 is maintained at the logical value “0”. Since the signal ECOMPsl1 is the logical value “1” and the signal INH is the logical value “0”, the signal COMMIT1 changes to the logical value “1”. Further, for example, the signals COMMIT 2 -COMIT 4 change to the logical value “1” when the completion conditions described in FIG. 5 are satisfied. Since the signal COMMIT1-COMIT4 changes to the logical value “1”, the value of the pointer PTR1 changes to 16 (= 12 + 4). As a result, the pointer PTR1 having the value “16” is held in the pointer portion PT.

  In cycle 8, the value of pointer PTR1m changes to 16, which is the value of pointer PTR1 held in pointer unit PT in cycle 7.

  FIG. 12 shows a comparative example of the operation of the instruction completion control unit CCTL shown in FIG. Detailed description of the same or similar operations as those described in FIGS. 8 to 11 is omitted. FIG. 12 shows an example of the operation of the instruction completion control unit CCTL in which the bypass unit BYP shown in FIG. 5 is omitted. The operation of FIG. 12 corresponds to the operation of FIG. For example, in the operation of FIG. 12, detection of an operation exception is suppressed and an operation exception occurs. In the operation of FIG. 12, since the signal FED has the logical value “1”, even when the instruction completion control unit CCTL receives the exception information EXSIG having the logical value “1” in cycle 5, the exception information EXSIG_LCH is The value is maintained at “0”. For this reason, the signal INH is maintained at the logical value “0”.

  Further, the signal ECOMPw1 and the signal ECOMPc1 in parentheses in FIG. 12 indicate signals that are omitted from the operation in FIG. 8 because the bypass unit BYP is omitted. Therefore, in the operation of FIG. 12, the signal ECOMPs1 received by the latch LAT30 is a signal read from the commit stack entry CSE. Note that FADD (IID = 12) in the figure indicates a pipeline stage of floating point addition based on an instruction corresponding to an instruction identifier (IID = 12) having a value “12”. For example, cycle 4 corresponds to the last operation execution stage X of the floating point addition.

  In cycle 4, the instruction completion control unit CCTL receives the operation completion signal ECOMP having the logical value “1” and the instruction identifier EIID having the value “12” from the arithmetic unit FPU. Since the signal FED is the logical value “1”, among the instructions registered in the commit stack entry CSE, the status information of the instruction corresponding to the instruction identifier EIID having the value “12” includes the information of the operation completion signal ECOMP (calculation Completed) is set.

  In cycle 5, since the value of the pointer PTR1 is 12, among the instructions registered in the commit stack entry CSE, the status information of the instruction corresponding to the instruction identifier of the value “12” (for example, the information of the operation completion signal ECOMP) ) Is read out. As a result, the signal ECOMPs1 changes to the logical value “1”.

  In cycle 6, the signal ECOMPsl1 changes to the logical value “1”. Since the signal ECOMPsl1 is the logical value “1” and the signal INH is the logical value “0”, the signal COMMIT1 changes to the logical value “1”. Further, for example, the signals COMMIT 2 -COMIT 4 change to the logical value “1” when the completion conditions described in FIG. 5 are satisfied. Since the signal COMMIT1-COMIT4 changes to the logical value “1”, the value of the pointer PTR1 changes to 16 (= 12 + 4). As a result, the pointer PTR1 having the value “16” is held in the pointer portion PT.

  In cycle 7, the value of pointer PTR1m changes to 16, which is the value of pointer PTR1 held in pointer unit PT in cycle 5.

  As described above, in the comparative example in which the bypass unit BYP is omitted, the register update stage U is executed in two cycles. On the other hand, the instruction completion control unit CCTL including the bypass unit BYP can execute the register update stage U in one cycle. That is, the arithmetic processing unit PU can start the instruction completion processing one cycle earlier than the operation of the comparative example of FIG. Therefore, the arithmetic processing unit PU can shorten the time from when the arithmetic unit such as the arithmetic unit FPU outputs the arithmetic completion signal ECOM to executing the instruction completion processing when detection of the arithmetic exception is suppressed.

  As described above, the arithmetic processing device and the control method of the arithmetic processing device of the embodiment shown in FIGS. 4 to 11 are the same as the arithmetic processing device and the control method of the arithmetic processing device of the embodiment shown in FIGS. An effect can be obtained. For example, in the bypass unit BYP, detection of an exception caused by the arithmetic processing is suppressed, and the instruction indicated by the operation completion information output from the arithmetic unit OP matches the instruction that is the target of the instruction completion processing. Bypass information ECOMPw indicating completion of the calculation is generated. Thereby, also in this embodiment, when the detection of the operation exception is suppressed, the time from the operation unit OP outputting the operation completion information to executing the instruction completion process can be shortened.

  For example, when the signal FED has a logical value “1” and the value of the pointer PTR1 matches the value of the instruction identifier EIID, the bypass unit BYP generates a logical value based on the operation completion signal ECOMP having the logical value “1”. Bypass information ECOMPw1 having a value “1” is generated. In this case, the information on the operation completion signal ECOMP (for example, the operation completion signal ECOMPsl1) related to the instruction to be processed is transferred to the latch LAT 30 without going through the commit stack entry CSE.

  For this reason, in this embodiment, when the detection of the operation exception is suppressed, the operation unit OP outputs the operation completion signal ECOMP until the information of the operation completion signal ECOMP is notified to the instruction completion unit COMPU2 and the like. You can save time. As a result, in this embodiment, when the detection of the operation exception is suppressed, the time from when the operation unit OP outputs the operation completion information to when the instruction completion processing is executed can be shortened.

  FIG. 13 shows another example of the instruction completion control unit CCTL shown in FIG. The arithmetic processing unit PU having the instruction completion control unit CCTL of FIG. 13 is shown in FIG. 4 except that it has the instruction completion control unit CCTL of FIG. 13 instead of the instruction completion control unit CCTL shown in FIG. This is the same as the arithmetic processing unit PU. The arithmetic processing unit PU having the instruction completion control unit CCTL in FIG. 13 is also an aspect of the arithmetic processing device.

  The instruction completion control unit CCTL in FIG. 13 includes a bypass unit BYP2 instead of the bypass unit BYP shown in FIG. Other configurations of the instruction completion control unit CCTL of FIG. 13 are the same as those of the instruction completion control unit CCTL shown in FIG. Elements similar to those described in FIGS. 1 to 12 are denoted by the same reference numerals, and detailed description thereof will be omitted. In FIG. 13, as in FIG. 5, a module that receives data transfer completion information from the data cache DCM, branch determination completion information from the branch control unit BCTL, operation completion information from the operator EXU, exception information, and the like. Is omitted.

  The instruction completion control unit CCTL includes a pointer unit PT, an addition unit ADD, latches LAT10, LAT12, LAT20, LAT30, LAT40, an inverter INV1, an AND unit AND1, AND2, a selection unit SEL10, SEL20, a commit stack entry CSE, and a bypass unit BYP2. , A comparison unit CMP10, an instruction completion processing unit COMPU1, and an instruction completion unit COMPU2. Each module included in the instruction completion control unit CCTL is the same as or similar to each module included in the instruction completion control unit CCTL shown in FIG. 5 except for the bypass unit BYP2.

  For example, the pointer unit PT, the adding unit ADD, the latches LAT10-LAT40, and the inverter INV1 are the same as or similar to the pointer unit PT, the adding unit ADD, the latches LAT10-LAT40, and the inverter INV1 shown in FIG. The AND units AND1 and AND2, the selection units SEL10 and SEL20, and the commit stack entry CSE are the same as or similar to the AND units AND1 and AND2, the selection units SEL10 and SEL20, and the commit stack entry CSE shown in FIG. The comparison unit CMP10, the instruction completion processing unit COMPU1, and the instruction completion unit COMPU2 are the same as or similar to the comparison unit CMP10, the instruction completion processing unit COMPU1, and the instruction completion unit COMPU2 illustrated in FIG.

  The bypass unit BYP2 is an example of a bypass unit that generates bypass information indicating completion of calculation. For example, the bypass unit BYP2 completes the operation when the detection of the operation exception is suppressed and the instruction indicated by the operation completion information output from the operation unit OP matches the instruction to be processed by the instruction completion process. Bypass information ECOMPw is generated. In addition, the bypass unit BYP2 does not detect an operation exception in a state where detection of the operation exception is not suppressed, and an instruction indicated by the operation completion information output from the operation unit OP and an instruction to be subjected to instruction completion processing Is in agreement, the bypass information ECOMPw indicating the completion of the calculation is generated.

  For example, the bypass unit BYP2 receives the pointers PTR1-PTR4, the signal FED, the exception information EXSIG, the signals ECOMPa, EIDa, and the signals ECOMPc1-ECOMPc4. Then, the bypass unit BYP2 generates signals ECOMPw1 to ECOMPw4 based on the pointers PTR1 to PTR4, the signal FED, the exception information EXSIG, the signals ECOMPa, and EIIDa. Further, the bypass unit BYP2 outputs the logical sum result of the signals ECOMPw1-ECOMPw4 and the signals ECOMPc1-ECOMPc4 to the latch LAT30 as signals ECOMPs1-ECOMPs4.

  As described with reference to FIG. 5, when the signal FED has the logical value “1”, the signals ECOMPa and EIIDa are the same as or similar to the operation completion signal ECOMP and the instruction identifier EIID, respectively. When the signal FED has a logical value “0”, the signals ECOMPa and EIIDa are the same as or similar to the operation completion signal ECOMP_LCH and the instruction identifier EIID_LCH, respectively.

  For example, the bypass unit BYP2 includes a comparison unit CMP20, a logical product unit AND3, logical sum units OR1 and OR2, and an inverter INV2. The comparison unit CMP20 is the same as or similar to the comparison unit CMP20 shown in FIG. 5 except that it receives the signal EIIDa instead of the instruction identifier EIID. For example, the comparison unit CMP20 receives the signal EIIDa from the selection unit SEL20 and receives the pointers PTR1 to PTR4 from the addition unit ADD. Then, the comparison unit CMP20 compares the signal EIDa with the pointers PTR1 to PTR4, and outputs the comparison result to the AND unit AND3.

  For example, when the signal EIDa and the pointer PTR1 match, the comparison unit CMP20 outputs a comparison result (a signal having a logical value “1”) indicating that the signal EIIDa and the pointer PTR1 match with the AND unit AND3. Output to. Further, the comparison unit CMP20 outputs a comparison result (a signal having a logical value “0”) indicating that the signal EIIDa and the pointers PTR2 to PTR3 do not match to the logical product unit AND3.

  The inverter INV2 receives the exception information EXSIG from the state control unit MCTL and outputs an inverted signal of the exception information EXSIG to the logical sum unit OR2. The OR unit OR2 receives the inverted signal of the exception information EXSIG from the inverter INV2, and receives the signal FED from the state control unit MCTL. Then, the logical sum unit OR2 outputs a logical sum result of the inverted signal of the exception information EXSIG and the signal FED to the logical product unit AND3 as the signal FEX.

  The logical product unit AND3 receives the comparison result of the signal EIIDa and the pointers PTR1 to PTR4, the signal ECOMPa, and the signal FEX from the comparison unit CMP20, the selection unit SEL20, and the logical sum unit OR2. Then, the AND unit AND3 outputs a logical product result of the received signals to the OR unit OR1 as bypass information ECOMPw1-ECOMPw4.

  For example, the AND unit AND3 outputs the comparison result of the signal EIIDa and the pointer PTR1, and the logical product result of the three signals ECOMMPa and FEX to the OR unit OR1 as the bypass information ECOMPw1. Further, for example, the logical product unit AND3 outputs the comparison result between the signal EIIDa and the pointer PTR2 and the logical product result of the three signals ECOMMPa and FEX to the logical sum unit OR1 as bypass information ECOMPw2.

  Further, for example, the logical product unit AND3 outputs the comparison result between the signal EIIDa and the pointer PTR3 and the logical product result of the three signals ECOMMPa and FEX to the logical sum unit OR1 as bypass information ECOMPw3. For example, the AND unit AND3 outputs the comparison result of the signal EIIDa and the pointer PTR4 and the logical product result of the three signals ECOMMPa and FEX to the OR unit OR1 as bypass information ECOMPw4.

  The OR unit OR1 receives the signals ECOMPw1-ECOMPw4 from the logical product unit AND3, and receives the signals ECOMPc1-ECOMPc4 from the selection unit SEL10. Then, the logical sum OR1 outputs the logical sum results of the signals ECOMPw1-ECOMPw4 and the signals ECOMPc1-ECOMPc4 to the latch LAT30 as signals ECOMPs1-ECOMPs4.

  The configuration of the bypass unit BYP2 is not limited to this example. Here, when the signal FED has a logical value “1”, the signals ECOMPa and EIIDa are the same as or similar to the operation completion signal ECOMP and the instruction identifier EIID, respectively. Therefore, when the signal FED is the logical value “1”, the input signal of the AND unit AND3 is the same as or similar to the input signal of the AND unit AND3 of the bypass unit BYP shown in FIG. That is, when the signal FED is the logical value “1”, the operation of the bypass unit BYP2 is the same as or similar to the operation of the bypass unit BYP.

  Therefore, when the signal FED is a logical value “1”, the operation of the instruction completion control unit CCTL is the same as or similar to the operation of the instruction completion control unit CCTL shown in FIG. Therefore, the instruction completion control unit CCTL, when the detection of the operation exception is suppressed, until the operation unit OP outputs the operation completion signal ECOMP and notifies the instruction completion unit COMPU2 and the like of the information of the operation completion signal ECOMP. Can be shortened.

  As a result, the instruction completion control unit CCTL can shorten the time from when the operation unit OP outputs the operation completion signal ECOMP to executing the instruction completion process when the detection of the operation exception is suppressed. The operation of the instruction completion control unit CCTL when the signal FED is the logical value “0” will be described with reference to FIGS.

  FIG. 14 shows an example of the operation flow of the instruction completion control unit CCTL shown in FIG. That is, FIG. 14 shows one mode of a method for controlling the arithmetic processing unit. FIG. 14 shows an example of the operation of the instruction completion control unit CCTL when the detection of the operation exception is not suppressed. In the operation of FIG. 14, steps S232 and S234 are added to the operation shown in FIG. 3, and step S250a is executed instead of step S250. Other operations in FIG. 14 are the same as or similar to the operations in FIG.

  The operation of FIG. 14 may be realized only by hardware, or may be realized by controlling the hardware by software. Detailed description of the same or similar operations as those in FIGS. 2 and 3 is omitted. For example, although not shown in FIG. 14, instructions decoded by the instruction decoder DEC are registered in the commit stack entry CSE in the order of decoding.

  In step S200, the selection unit SEL10 reads instructions to be subjected to instruction completion processing from the commit stack entry CSE in the order of decoding.

  In step S210, the instruction completion control unit CCTL determines whether or not calculation completion information (for example, calculation completion signal ECOMP, instruction identifier EIID) has been received. When the operation completion information is received (Yes in step S210), the operation of the instruction completion control unit CCTL proceeds to step S220. On the other hand, when the operation completion information has not been received (No in step S210), the operation of the instruction completion control unit CCTL proceeds to step S250.

  In step S220, the instruction completion control unit CCTL updates the state information of the instruction indicated by the instruction identifier EIID_LCH (signal EIIDa) among the state information held in the commit stack entry CSE to information indicating the completion of the operation. For example, the commit stack entry CSE updates the state information of the instruction indicated by the instruction identifier EIID_LCH (signal EIIDa) to the information of the operation completion signal ECOMP_LCH (signal ECOMPa).

  In step S230, the instruction completion control unit CCTL determines whether an exception is detected. For example, the instruction completion control unit CCTL determines whether or not exception information EXSIG indicating that an operation exception has occurred has been received from the operation unit OP. If an exception is detected (Yes in step S230), the operation of the instruction completion control unit CCTL proceeds to step S240. On the other hand, when no exception is detected (No in step S230), the operation of the instruction completion control unit CCTL proceeds to step S232.

  In step S232, for example, the instruction completion control unit CCTL determines whether or not the instruction of the operation completion signal ECOMP_LCH (signal ECOMPa) is a target of the instruction completion process read in step S200. For example, the instruction completion control unit CCTL determines whether or not the instruction identifier EIID_LCH (signal EIIDa) matches the pointers PTR1 to PTR4. When the instruction of the operation completion signal ECOMP_LCH (signal ECOMPa) is an instruction completion process target (Yes in step S232), the operation of the instruction completion control unit CCTL proceeds to step S234. On the other hand, when the instruction of the operation completion signal ECOMP_LCH (signal ECOMPa) is not the target of instruction completion processing (No in Step S232), the operation of the instruction completion control unit CCTL proceeds to Step S250a.

  In step S234, the bypass unit BYP2 generates bypass information ECOMPw indicating the completion of the calculation based on the calculation completion signal ECOMP_LCH (signal ECOMPa). For example, the bypass unit BYP2 generates bypass information ECOMPw indicating completion of the operation for the instruction indicated by the instruction identifier EIID_LCH (signal EIIDa). Thus, in the state where the detection of the exception is not suppressed, the bypass unit BYP2 does not detect the exception, and the instruction indicated by the operation completion information output from the operation unit OP and the instruction that is the target of the instruction completion process. If they match, bypass information ECOMPw indicating completion of the calculation is generated.

  In step S240, the instruction completion control unit CCTL updates the state information of the instruction indicated by the instruction identifier EIID_LL among the state information held in the commit stack entry CSE to information indicating the occurrence of an exception. For example, the commit stack entry CSE updates the state information of the instruction indicated by the instruction identifier EIID_LL to the contents of the exception information EXIG_LCH.

  In step S250a, the instruction completion control unit CCTL executes instruction completion processing based on the bypass information ECOMPw and the instruction status information (signal ECOMPC) read from the commit stack entry CSE. For example, the instruction completion processing unit COMPU1 generates the signals COMMIT1-COMMIT4 based on the signals ECOMPsl1-ECOMPsl4 that are the logical sums of the signals ECOMPw1-ECOMPw4 and the signals ECOMPc1-ECOMPc4. Then, the instruction completion unit COMPU2 executes instruction completion processing based on the signals COMMIT1 to COMMIT4.

  Note that the operation of the arithmetic processing unit PU is not limited to this example. Further, the operation of the arithmetic processing unit PU when the detection of the arithmetic exception is suppressed (FED flag = 1) is the same as or similar to the operation shown in FIG.

  FIG. 15 shows an example of the operation of the instruction completion control unit CCTL shown in FIG. FIG. 15 shows an example of the operation of the instruction completion control unit CCTL when no operation exception occurs in the state where detection of the operation exception is not suppressed (FED = 0). That is, the operation of FIG. 15 corresponds to the operation of FIG. Detailed description of the same or similar operations as those described in FIGS. 8 to 11 is omitted. FADD (IID = 12) in the figure indicates a pipeline stage of floating point addition based on an instruction corresponding to an instruction identifier (IID = 12) having a value “12”. For example, cycle 4 corresponds to the last operation execution stage X of the floating point addition.

  In the operation of FIG. 15, since no exception occurs, the exception information EXSIG and EXSIG_LCH is maintained at the logical value “0”. For this reason, the signal INH is maintained at the logical value “0”. Further, the inverted signal of the exception information EXSIG is maintained at the logical value “1”.

  In cycle 4, the instruction completion control unit CCTL receives the operation completion signal ECOMP having the logical value “1” and the instruction identifier EIID having the value “12” from the arithmetic unit FPU. Note that since the signal FED is the logical value “0”, the information of the operation completion signal ECOM is not registered in the commit stack entry CSE in the cycle 4.

  In cycle 5, the operation completion signal ECOMP_LCH and the instruction identifier EIID_LCH change to the logical value “1” and the value “12”, respectively. Since the signal FED is the logical value “0”, the instruction identifier EIID_LCH is selected as the signal EIDa, and the operation completion signal ECOMP_LCH is selected as the signal ECOMPa. For this reason, out of the instructions registered in the commit stack entry CSE, the status information of the instruction corresponding to the instruction identifier EIID_LCH (signal EIIDa) having the value “12” is added to the information (calculation of the calculation completion signal ECOMP_LCH (signal ECOMPa)). Completed) is set.

  Further, the inverted signal of the exception information EXSIG is a logical value “1”, and the value of the pointer PTR1 and the value of the instruction identifier EIID_LCH (signal EIIDa) are both 12. For this reason, the signal ECOMPw1 changes to the same logical value “1” as the logical value “1” of the operation completion signal ECOMP_LCH. Then, since the signal ECOMPw1 changes to the logical value “1”, the signal ECOMPs1 changes to the logical value “1”. As a result, the signal ECOMPs1 having the logical value “1” is held in the latch LAT30.

  In cycle 6, since the signal ECOMPs1 having the logical value “1” is held in the latch LAT30 in cycle 5, the signal ECOMPsl1 that is the output signal of the latch LAT30 changes to the logical value “1”. Since the signal ECOMPsl1 is the logical value “1” and the signal INH is the logical value “0”, the signal COMMIT1 changes to the logical value “1”.

  Further, for example, the signals COMMIT 2 -COMIT 4 change to the logical value “1” when the completion conditions described in FIG. 5 are satisfied. For example, when the signal ECOMPc2-ECOMPc4 having the logical value “1” is read from the commit stack entry CSE in the cycle 5, the signal COMMIT2-COMIT4 also changes to the logical value “1” in the cycle 6. Since the signal COMMIT1-COMIT4 changes to the logical value “1”, the value of the pointer PTR1 changes to 16 (= 12 + 4). As a result, the pointer PTR1 having the value “16” is held in the pointer portion PT.

  In cycle 7, the value of pointer PTR1m changes to 16, which is the value of pointer PTR1 held in pointer unit PT in cycle 6.

  In this way, the instruction completion control unit CCTL, for example, if the exception is not detected and the value of the instruction identifier EIID_IID is the same as the value of the pointer PTR1, even if the detection of the exception is not suppressed, Can be executed in two cycles. On the other hand, for example, in the operation of the configuration in which the bypass information ECOMPw1 to ECOMPw4 is not generated when the detection of the exception is not suppressed (for example, the operation of FIG. 11), the register update stage U is executed in three cycles.

  That is, in the operation of FIG. 15, the instruction completion process can be started one cycle earlier than the operation (for example, the operation of FIG. 11) in which the bypass information ECOMPw1 to ECOMPw4 is not generated when the exception detection is not suppressed. . For this reason, the performance of the arithmetic processing unit PU is improved. For example, when the completion condition of the signal COMMIT2-COMIT4 is satisfied, the arithmetic processing unit PU also causes the instruction indicated by the pointer PTR2-PTR4 (the instruction subsequent to the instruction indicated by the pointer PTR1) to be in the same cycle as the instruction indicated by the pointer PTR1. The instruction completion process can be started. That is, the arithmetic processing unit PU also performs instruction completion processing for subsequent instructions as compared to an operation (for example, the operation of FIG. 11) in which bypass information ECOMPw1 to ECOMPw4 is not generated when detection of an exception is not suppressed. Start cycle early.

  Note that the operation of the instruction completion control unit CCTL when an operation exception occurs in a state where detection of an operation exception is not suppressed (FED flag = 0) is the same as or similar to the operation shown in FIG. Further, the operation of the instruction completion control unit CCTL when the detection of the operation exception is suppressed (FED flag = 1) is the same as or similar to the operation shown in FIGS.

  As described above, the arithmetic processing device and the control method of the arithmetic processing device of the embodiment shown in FIGS. 13 to 15 are the same as the arithmetic processing device and the control method of the arithmetic processing device of the embodiment shown in FIGS. An effect can be obtained. For example, in the bypass unit BYP2, detection of an exception caused by the arithmetic processing is suppressed, and the instruction indicated by the arithmetic completion information output from the arithmetic unit OP matches the instruction that is the target of the instruction completion processing. Bypass information ECOMPw indicating completion of the calculation is generated. Thereby, also in this embodiment, when the detection of the operation exception is suppressed, the time from the operation unit OP outputting the operation completion information to executing the instruction completion process can be shortened.

  Further, in this embodiment, even when the detection of the operation exception is not suppressed, when the operation exception is not detected, the time until the instruction completion processing is executed after the operation unit OP outputs the operation completion information is shortened. it can. For example, in the bypass unit BYP2, the operation exception is not detected and the instruction indicated by the operation completion information output from the operation unit OP and the instruction to be processed by the instruction completion process are not detected. If they match, bypass information ECOMPw indicating completion of the calculation is generated.

  Therefore, in this embodiment, even when the detection of the operation exception is not suppressed, when the operation exception is not detected, the operation unit OP outputs the operation completion signal ECOMP, and then the information of the operation completion signal ECOMP is completed. The time until notification to the unit COMPU2 and the like can be shortened. As a result, in this embodiment, even when the detection of the operation exception is not suppressed, when the operation exception is not detected, the time from the operation unit OP outputting the operation completion information to executing the instruction completion processing is increased. Can be shortened.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A decoding unit that decodes an instruction, an operation unit that executes an operation based on the decoded instruction, and a completion control unit that executes instruction completion processing for completing the instruction in the order of decoding,
The completion control unit
When the decoded instructions are registered in the order of decoding, holding state information indicating whether or not an operation based on the registered instruction is completed, and receiving operation completion information indicating completion of the operation by the operation unit A holding unit that updates the state information of the instruction indicated by the calculation completion information to information indicating completion of the calculation;
A selection unit that reads out the instruction to be processed by the instruction completion process from the holding unit in the order of decoding;
When the detection of an exception caused by the arithmetic processing is suppressed and the instruction indicated by the arithmetic completion information output from the arithmetic unit is coincident with the instruction that is the target of the instruction completion processing, A bypass unit for generating bypass information indicating completion;
The instruction completion process is executed based on the bypass information for the instruction in which the bypass information indicating the completion of the operation is generated, and the instruction in which the bypass information indicating the completion of the operation is not generated. And a completion processing unit that executes the instruction completion processing based on the state information of the instruction read from the holding unit.
(Appendix 2)
In the arithmetic processing device according to attachment 1,
The bypass unit is a target of the instruction and the instruction completion process indicated by the calculation completion information output from the calculation unit when the exception detection is not suppressed and the exception is not detected. When the instruction matches, the bypass information indicating completion of the operation is generated.
(Appendix 3)
Whether the operation based on the instruction is completed in the decoding unit that decodes the instruction, the operation unit that executes the operation based on the decoded instruction, and the holding unit that is registered in the order in which the decoded instruction is decoded In the control method of the arithmetic processing unit having a completion control unit that stores state information corresponding to the instruction and executes instruction completion processing for completing the instruction in the order of decoding,
The completion control unit reads the instructions to be processed by the instruction completion process from the holding unit in the order of decoding,
When the completion control unit receives calculation completion information indicating completion of calculation by the calculation unit, among the state information held in the holding unit, the state information of the instruction indicated by the calculation completion information is Update to information indicating the completion of the calculation,
The completion control unit is configured to suppress detection of an exception caused by the arithmetic processing, and the instruction indicated by the arithmetic completion information output from the arithmetic unit matches the instruction that is the target of the instruction completion processing. Generate bypass information indicating the completion of the operation,
The completion control unit executes the instruction completion processing based on the bypass information for the instruction for which the bypass information indicating the completion of the calculation is generated, and the bypass information indicating the completion of the calculation is generated. The control method for the arithmetic processing device, wherein the instruction completion processing is executed based on the state information of the instruction read from the holding unit for the instruction that does not exist.
(Appendix 4)
In the control method of the arithmetic processing unit according to attachment 3,
In the state where the detection of the exception is not suppressed, the completion control unit does not detect the exception, and the instruction indicated by the calculation completion information output from the calculation unit and the target of the instruction completion process When the instruction matches, the bypass information indicating the completion of the operation is generated.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

  ADD: Adder; AND1, AND2, AND3: Logical product; BCTL: Branch controller; BRPRE: Branch prediction mechanism; BYP, BYP2: Bypass unit; CCM: Instruction cache; CCTL: Instruction completion controller: CMP10, CMP20, etc. COMPU. Completion processing unit; COMPU1. Instruction completion processing unit; COMPU2. Instruction completion unit; CSE ... Commit stack entry; DCM ... Data cache; DEC ... Instruction decoder; EXBUF ... Fixed-point update buffer; EXREG ... Fixed-point register EXU, FPU ... arithmetic unit; FAGEN ... instruction fetch address generator; FPBUF ... floating point update buffer; FPREG ... floating point register; INV1, INV2 ... inverter; LAT10, LAT12, LAT20, LAT30, LAT4 Latch; MCTL State control unit; NPC Next program counter; OAGEN Operand address generator; OP Arithmetic unit; OR1, OR2 OR unit; PC Program counter; PT Pointer unit; PU Arithmetic processing unit RS, RSA, RSE, RSF, RSBR ... reservation station; SEL10, SEL20 ... selection unit

Claims (3)

A decoding unit that decodes an instruction, an operation unit that executes an operation based on the decoded instruction, and a completion control unit that executes instruction completion processing for completing the instruction in the order of decoding,
The completion control unit
When the decoded instructions are registered in the order of decoding, holding state information indicating whether or not an operation based on the registered instruction is completed, and receiving operation completion information indicating completion of the operation by the operation unit A holding unit that updates the state information of the instruction indicated by the calculation completion information to information indicating completion of the calculation;
A selection unit that reads out the instruction to be processed by the instruction completion process from the holding unit in the order of decoding;
When the detection of an exception caused by the arithmetic processing is suppressed and the instruction indicated by the arithmetic completion information output from the arithmetic unit is coincident with the instruction that is the target of the instruction completion processing, A bypass unit for generating bypass information indicating completion;
The instruction completion process is executed based on the bypass information for the instruction in which the bypass information indicating the completion of the operation is generated, and the instruction in which the bypass information indicating the completion of the operation is not generated. And a completion processing unit that executes the instruction completion processing based on the state information of the instruction read from the holding unit. The arithmetic processing device according to claim 1,
The bypass unit is a target of the instruction and the instruction completion process indicated by the calculation completion information output from the calculation unit when the exception detection is not suppressed and the exception is not detected. When the instruction matches, the bypass information indicating completion of the operation is generated. Whether the operation based on the instruction is completed in the decoding unit that decodes the instruction, the operation unit that executes the operation based on the decoded instruction, and the holding unit that is registered in the order in which the decoded instruction is decoded In the control method of the arithmetic processing unit having a completion control unit that stores state information corresponding to the instruction and executes instruction completion processing for completing the instruction in the order of decoding,
The completion control unit reads the instructions to be processed by the instruction completion process from the holding unit in the order of decoding,
When the completion control unit receives calculation completion information indicating completion of calculation by the calculation unit, among the state information held in the holding unit, the state information of the instruction indicated by the calculation completion information is Update to information indicating the completion of the calculation,
The completion control unit is configured to suppress detection of an exception caused by the arithmetic processing, and the instruction indicated by the arithmetic completion information output from the arithmetic unit matches the instruction that is the target of the instruction completion processing. Generate bypass information indicating the completion of the operation,
The completion control unit executes the instruction completion processing based on the bypass information for the instruction for which the bypass information indicating the completion of the calculation is generated, and the bypass information indicating the completion of the calculation is generated. The control method for the arithmetic processing device, wherein the instruction completion processing is executed based on the state information of the instruction read from the holding unit for the instruction that does not exist.

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