JP6307469B2 - Inkjet printer - Google Patents

Description

  Embodiments described herein relate generally to an inkjet printer.

  An inkjet head that discharges ink by driving an actuator by applying a positive drive voltage (first voltage: about 18 V) and a negative drive voltage (first negative voltage: about −18 V) (hereinafter referred to as “ink jet head”) The abbreviated head) further includes a positive second voltage (about 5V) lower than the first voltage and a positive third voltage (about 24V) higher than the first voltage. I need. The second voltage is mainly used as an operating voltage of the logic circuit. The third voltage is mainly used as an operating voltage of the analog circuit.

  For this reason, an ink jet printer that performs printing by discharging ink from a head includes a power supply circuit that supplies four types of voltages. The ink jet printer includes a sequence control circuit. The sequence control circuit operates so that four types of voltages are supplied to the head according to a preset sequence when the power is turned on, and stops supplying each voltage in the reverse order to that when the power is turned off.

  Generally, the sequence control circuit controls the sequence of voltage application start and application end by software. For this reason, there is a possibility that the software malfunctions due to unexpected noise or the like, and the voltage is supplied to the head in an order different from the sequence, or the voltage supply is stopped. If the order of voltage supply or stop is changed, the output of the circuit incorporated in the head may become unstable, or the circuit may be destroyed by a through current generated by latch-up of the semiconductor element.

JP 2010-198202 A

  The problem to be solved by the embodiments of the present invention is that even if an abnormality occurs in the sequence control of the voltage application start and the application end, a failure associated with the abnormality can be prevented in advance, and an ink jet printer excellent in reliability Is to provide.

In one embodiment, an inkjet printer includes an inkjet head, a sequence controller, a supply circuit, a discharge circuit, and a gate circuit. The ink jet head operates by applying a first voltage for driving the actuator, a second voltage having a value smaller than the first voltage, and a fifth voltage having a value larger than the first voltage. . The sequence controller outputs a signal for controlling the start and end of application according to a preset sequence for each of the first to third voltages. The supply circuit selectively supplies the first to third voltages to the inkjet head in accordance with a signal for controlling the start of voltage application output from the sequence controller. The discharge circuit selectively discharges the first to third voltages supplied to the inkjet head in accordance with a signal for controlling the end of application of the voltage output from the sequence controller. When a signal for controlling the start of voltage application is output from the sequence controller in a different order from the sequence, the gate circuit outputs the signal to be output before the signal until the signal to be output is output from the sequence controller. A signal is prevented from being output to the supply circuit. Further, when a signal for controlling the end of voltage application is output from the sequence controller in a different order from the sequence, the gate circuit until a signal to be output before the signal is output from the sequence controller. The signal is prevented from being output to the discharge circuit.

The perspective view which decomposes | disassembles and shows a part of inkjet head. FIG. 3 is a cross-sectional view of the front portion of the inkjet head. The longitudinal cross-sectional view in the front part of an inkjet head. The figure for demonstrating the principle of operation of an inkjet head. The block diagram which shows the hardware constitutions of an inkjet printer. FIG. 3 is a block diagram illustrating a specific configuration of a head driving circuit in the ink jet printer. FIG. 3 is a block diagram showing a specific configuration of a sequence control circuit in the ink jet printer. FIG. 3 is a block diagram showing a specific configuration of a supply / discharge circuit in the ink jet printer. FIG. 4 is a timing diagram illustrating an example of a power-on / off sequence in an inkjet printer. The circuit diagram which shows the structure of the circuit for voltage VDD in a supply / discharge circuit. The circuit diagram which shows the structure of the circuit for voltage VAAN in a supply / discharge circuit. The circuit diagram which shows the structure of the circuit for voltage VCC in a supply / discharge circuit. The circuit diagram which shows the structure of the circuit for voltage VAAP in a supply / discharge circuit. FIG. 6 is a timing chart of turning on and off each power supply when the timing of turning on the control signal VCC_ON is delayed from the timing of turning on the control signal VAAP_ON. FIG. 6 is a timing chart of turning on and off each power supply when the timing of turning on the control signal VAAN_ON is delayed from the timing of turning on the control signal VAAP_ON. FIG. 6 is a timing chart of turning on and off each power supply when the timing of turning on the control signal VDD_ON is delayed from the timing of turning on the control signal VAAP_ON. 6 is a timing chart of turning on and off each power supply when the timing at which the control signal VCC_ON is turned off is earlier than the timing at which the control signal VAAP_ON is turned off. FIG. 6 is a timing chart of power on and off when the timing at which the control signal VAAN_ON is turned off is earlier than the timing at which the control signal VAAP_ON is turned off. FIG. 6 is a timing chart of power on / off when the timing for turning off the control signal VDD_ON is earlier than the timing for turning off the control signal VAAP_ON. FIG. The graph which shows the time change of voltage VDD, voltage VAAN, voltage VCC, and voltage VAAN when supply of voltage VDD, voltage VAAN, voltage VCC, or voltage VAAN stops simultaneously. The circuit diagram which shows the other structure of the circuit for voltage VAAN in a supply / discharge circuit. The circuit diagram which shows the other structure of the circuit for voltage VCC in a supply / discharge circuit. The circuit diagram which shows the other structure of the circuit for voltage VAAP in a supply / discharge circuit.

Hereinafter, an embodiment of an ink jet printer that can prevent a failure due to an abnormality even when an abnormality occurs in sequence control of voltage application start and application end will be described with reference to the drawings.
Incidentally, in this embodiment, an ink jet printer using a share mode type ink jet head 100 (see FIG. 1; hereinafter, abbreviated as head 100) is exemplified.

  First, the configuration of the head 100 will be described with reference to FIGS. 1 to 3. 1 is an exploded perspective view showing a part of the head 100, FIG. 2 is a cross-sectional view of the front portion of the head 100, and FIG. 3 is a vertical cross-sectional view of the front portion of the head 100.

  The head 100 has a base substrate 9. In the head 100, the first piezoelectric member 1 is bonded to the upper surface on the front side of the base substrate 9, and the second piezoelectric member 2 is bonded onto the first piezoelectric member 1. The bonded first piezoelectric member 1 and second piezoelectric member 2 are polarized in directions opposite to each other along the plate thickness direction, as indicated by arrows in FIG.

  The head 100 is provided with a number of long grooves 3 from the front end side to the rear end side of the joined piezoelectric members 1 and 2. Each groove 3 has a constant interval and is parallel. Each groove 3 is open at the front end and inclined upward at the rear end.

  The head 100 is provided with electrodes 4 on the side walls and the bottom surface of each groove 3. The electrode 4 has a two-layer structure of nickel (Ni) and gold (Au). Further, the head 100 is provided with an extraction electrode 10 from the rear end of each groove 3 toward the rear upper surface of the second piezoelectric member 2. The extraction electrode 10 extends from the electrode 4.

  The head 100 includes a top plate 6 and an orifice plate 7. The top plate 6 closes the upper part of each groove 3. The orifice plate 7 closes the tip of each groove 3. The head 100 forms a plurality of pressure chambers 15 by the grooves 3 surrounded by the top plate 6 and the orifice plate 7. Such a pressure chamber 15 is also referred to as an ink chamber.

  The top plate 6 includes a common ink chamber 5 on the inner rear side. The orifice plate 7 is formed with nozzles 8 at positions facing the grooves 3. The nozzle 8 communicates with the facing groove 3, that is, the pressure chamber 15. The nozzle 8 is tapered from the pressure chamber 15 side toward the opposite ink discharge side. The nozzles 8 correspond to the three adjacent pressure chambers 15 as one set, and are formed at a certain interval in the height direction of the groove 3 (up and down direction on the paper surface of FIG. 3).

  The head 100 joins the printed circuit board 11 on which the conductive pattern 13 is formed on the upper surface on the rear side of the base substrate 9. The head 100 mounts a drive IC 12 on which a head drive circuit 101 described later is formed on the printed circuit board 11. The drive IC 12 is connected to the conductive pattern 13. The conductive pattern 13 is coupled to each extraction electrode 10 by a conductive wire 14 by wire bonding.

  A set of the pressure chamber 15, the electrode 4, and the nozzle 8 included in the head 100 is referred to as a channel. That is, the head 100 has channels ch.1, ch.2,.

Next, the operation principle of the head 100 configured as described above will be described with reference to FIG.
FIG. 4A shows that the potential of the electrode 4 disposed on each wall surface of the central pressure chamber 15b and the pressure chambers 15a and 15c adjacent to the pressure chamber 15b is the ground potential GND. It shows a certain state. In the state of FIG. 4A, the partition wall 16a sandwiched between the pressure chamber 15a and the pressure chamber 15b and the partition wall 16b sandwiched between the pressure chamber 15b and the pressure chamber 15c are not subjected to any distortion action.

  FIG. 4B shows a state in which a negative voltage VAAN is applied to the electrode 4 of the central pressure chamber 15b and a positive voltage VAAP is applied to the electrodes 4 of the adjacent pressure chambers 15a and 15c. Yes. Incidentally, the voltage VAAN shows the negative polarity of the voltage value VAA. The voltage VAAP indicates the positive polarity of the voltage value VAA. That is, the voltage VAAN and the voltage VAAP have the same voltage value and are inverted in polarity. In the state of FIG. 4B, an electric field twice as large as the voltage VAA acts on each of the partition walls 16a and 16b in a direction orthogonal to the polarization direction of the piezoelectric members 1 and 2. By this action, the partition walls 16a and 16b are deformed outward so as to expand the volume of the pressure chamber 15b.

  FIG. 4C shows a state in which a positive voltage VAAP is applied to the electrode 4 in the central pressure chamber 15b and a negative voltage VAAN is applied to the electrodes 4 in the adjacent pressure chambers 15a and 15c. Yes. In the state of FIG. 4C, an electric field twice as large as the voltage VAA acts on each of the partition walls 16a and 16b in the direction opposite to that in FIG. 4B. By this action, the partition walls 16a and 16b are respectively deformed inward so as to contract the volume of the pressure chamber 15b.

  When the volume of the pressure chamber 15b is expanded or contracted, pressure vibration is generated in the pressure chamber 15b. Due to this pressure vibration, the pressure in the pressure chamber 15b increases, and ink droplets are ejected from the nozzles 8 communicating with the pressure chamber 15b.

  Thus, the partition walls 16a and 16b separating the pressure chambers 15a, 15b and 15c serve as actuators for applying pressure vibration to the inside of the pressure chamber 15b having the partition walls 16a and 16b as wall surfaces. That is, each pressure chamber 15 shares an actuator with the adjacent pressure chamber 15. For this reason, the head drive circuit 101 cannot drive each pressure chamber 15 individually. The head drive circuit 101 drives each pressure chamber 15 by dividing it into (n + 1) groups every n (n is an integer of 2 or more). In this embodiment, the head driving circuit 101 exemplifies a case of so-called three-division driving in which each pressure chamber 15 is divided and driven in groups of three every two groups. Note that the three-division driving is merely an example, and may be four-division driving or five-division driving.

  Next, the configuration of the inkjet printer 200 (hereinafter abbreviated as the printer 200) will be described with reference to FIGS. 5 is a block diagram showing a hardware configuration of the printer 200, FIG. 6 is a block diagram showing a specific configuration of the head drive circuit 101, and FIG. 7 is a specific configuration of the sequence control circuit 211 (see FIG. 5). FIG. 8 is a block diagram showing a specific configuration of the supply / discharge circuit 2112 (see FIG. 7). The printer 200 is applied to an office printer, a barcode printer, a POS printer, an industrial printer, and the like.

  The printer 200 includes a CPU (Central Processing Unit) 201, a ROM (Read Only Memory) 202, a RAM (Random Access Memory) 203, an operation panel 204, a communication interface 205, a transport motor 206, a motor drive circuit 207, a pump 208, and a pump drive. A circuit 209, a power supply circuit 210, a sequence control circuit 211, and the head 100 are provided. The printer 200 includes a bus line 212 such as an address bus or a data bus. The printer 200 directly or directly connects the CPU 201, ROM 202, RAM 203, operation panel 204, communication interface 205, motor drive circuit 207, pump drive circuit 209, sequence control circuit 211, and drive circuit 101 of the head 100 to the bus line 212. Connect via input / output circuit.

  The CPU 201 corresponds to the central part of the computer. The CPU 201 controls each unit to implement various functions as the printer 200 in accordance with an operating system and application programs.

  The ROM 202 corresponds to the main storage portion of the computer. The ROM 202 stores the above operating system and application programs. The ROM 202 may store data necessary for the CPU 201 to execute processing for controlling each unit.

  The RAM 203 corresponds to the main storage portion of the computer. The RAM 203 stores data necessary for the CPU 201 to execute processing. The RAM 203 is also used as a work area where information is appropriately rewritten by the CPU 201. The work area includes an image memory in which print data is expanded.

  The operation panel 204 has an operation unit and a display unit. The operation unit is provided with function keys such as a power key, a paper feed key, and an error release key. The display unit can display various states of the printer 200.

  The communication interface 205 receives print data from a client terminal connected via a network such as a LAN (Local Area Network). For example, when an error occurs in the printer 200, the communication interface 205 transmits a signal notifying the error to the client terminal.

  A motor drive circuit 207 controls driving of the carry motor 206. A transport motor 206 is a drive source of a transport mechanism that transports a recording medium such as printing paper. When the transport motor 206 is driven, the transport mechanism starts transporting the recording medium. The transport mechanism transports the recording medium to the print position by the head 100. The transport mechanism discharges the printed recording medium to the outside of the printer 200 from a discharge port (not shown).

  The pump drive circuit 209 controls the drive of the pump 208. When the pump 208 is driven, ink in an ink tank (not shown) is supplied to the head 100.

  The head 100 includes a head drive circuit 101. The head drive circuit 101 drives the channel group 102 of the head 100 based on the print data. As shown in FIG. 6, the head drive circuit 101 includes a pattern generator 1011, a logic circuit 1012, a buffer circuit 1013, and a switch circuit 1014.

  The pattern generator 1011 generates waveform patterns such as a discharge related waveform, a discharge adjacent waveform, a non-discharge related waveform, and a non-discharge adjacent waveform. The waveform pattern data generated by the pattern generator 1011 is supplied to the logic circuit 1012.

  The logic circuit 1012 accepts input of print data read out line by line from the image memory. The logic circuit 1012 connects the power supply line L1 having the ground potential GND and the power supply line L2 having the positive voltage VDD. The positive voltage VDD is an operating voltage of the logic circuit 1012.

The logic circuit 1012 sets three adjacent channels ch. (I−1), ch.i, and ch. (I + 1) of the head 100 as one set. When print data is input, the logic circuit 1012 determines whether the central channel ch.i is an ejection channel that ejects ink or a non-ejection channel that does not eject ink.
In the case of the ejection channel, the logic circuit 1012 outputs pattern data of the waveform concerned for ejection to this channel ch.i. Further, the logic circuit 1012 outputs the pattern data of the ejection adjacent waveform to both adjacent channels ch. (I−1) and ch. (I + 1).

In the case of a non-ejection channel, the logic circuit 1012 outputs pattern data of the non-ejection waveform to this channel ch.i. Further, the logic circuit 1012 outputs non-ejection both-side waveform pattern data to both adjacent channels ch. (I−1) and ch. (I + 1).
Each pattern data output from the logic circuit 1012 is supplied to the buffer circuit 1013.

  The buffer circuit 1013 includes N prebuffers corresponding to the respective channels ch.1, ch.2,. The buffer circuit 1013 connects the power supply line L3 of the positive voltage VCC and the power supply line L4 of the negative voltage VAAN. Both the positive voltage VCC and the negative voltage VAAN are pre-buffer operating voltages.

  The output of each prebuffer changes according to the signal level of the pattern data given from the logic circuit 1012. Each pre-buffer differs from the logic circuit 1012 depending on whether the corresponding channel ch.k (1 ≦ k ≦ N) is an ejection channel, a non-ejection channel, or a channel adjacent to the ejection channel or the non-ejection channel. Pattern data is given. When the pattern data signal level is high, the pre-buffer outputs a signal of positive voltage VCC. When the pattern data signal level is low, the pre-buffer outputs a signal of negative voltage VAAN. A signal output from each prebuffer is supplied to the switch circuit 1014.

  The switch circuit 1014 includes N drivers corresponding to the channels ch.1, ch.2,. Each driver includes a field effect transistor that functions as an on / off switching element. The switch circuit 1014 connects the power supply line L3 of the positive voltage VCC, the power supply line L5 of the positive voltage VAAP, the power supply line L1 of the ground potential GND, and the power supply line L4 of the negative voltage VAAN. The positive voltage VCC is an operating voltage of the field effect transistor. The positive voltage VAAP, the ground potential GND, and the negative voltage VAAN are operating voltages of each driver.

  Each driver drives an actuator of a corresponding channel ch.1, ch.2,. That is, each driver responds to a signal from the pre-buffer, as described in FIG. 4, with a positive voltage VAAP, a ground potential GND or an electrode of the corresponding channel ch.1, ch.2,. A negative voltage VAAN is selectively applied.

  The power supply circuit 210 generates three types of positive voltages VAAP, VDD, and VCC with respect to the ground potential GND, and one type of negative voltage VAAN. The magnitude relationship among the three types of voltages VAAP, VDD, and VCC is VDD <VAAP <VCC. For example, the voltage VDD is + 5V, the voltage VAAP is + 18V, and the voltage VCC is + 24V. The voltage VAAN is equal to the voltage VAAP and has the opposite polarity, and thus becomes -18V. The power supply circuit 210 supplies these voltages VAAP, VDD, VCC, and VAAN to each unit including the sequence control circuit 211 together with the ground potential GND.

  Here, when the voltage VAAP is the first voltage, the voltage VAAN is a first negative voltage having the same value and the opposite polarity as the first voltage, and the voltage VDD is the same polarity having a value smaller than that of the first voltage. The voltage VCC is a third voltage of the same polarity having a value larger than that of the first voltage.

The sequence control circuit 211 includes a sequence controller 2111 and a supply / discharge circuit 2112 as shown in FIG.
The sequence controller 2111 generates four types of control signals VAAP_ON, VDD_ON, VCC_ON, and VAAN_ON. The sequence controller 2111 outputs each control signal VAAP_ON, VDD_ON, VCC_ON, VAAN_ON to the supply / discharge circuit 2112 according to a preset sequence.

  The control signal VAAP_ON controls the start and end of application of the voltage VAAP to the head 100. The control signal VDD_ON controls the start and end of application of the voltage VDD to the head 100. The control signal VCC_ON controls the start and end of application of the voltage VCC to the head 100. The control signal VAAN_ON controls the start and end of application of the voltage VAAN to the head 100.

  The supply / discharge circuit 2112 is interposed in five types of power supply lines L1, L2, L3, L4, and L5 that connect the power supply circuit 210 and the head drive circuit 101. The power supply line L1 is a line of the ground potential GND. The power supply line L2 is a positive voltage VDD line. The power supply line L3 is a positive voltage VCC line. The power supply line L4 is a negative voltage VAAN line. The power supply line L5 is a positive voltage VAAP line. Specifically, as shown in FIG. 8, the supply / discharge circuit 2112 is interposed in the voltage VDD circuit 300 interposed in the power supply line L2, the voltage VAAN circuit 400 interposed in the power supply line L4, and the power supply line L3. A voltage VCC circuit 500 and a voltage VAAP circuit 600 interposed in the power supply line L5 are included. The power supply line L1 passes through the supply / discharge circuit 2112.

  The voltage VDD circuit 300 supplies the positive voltage VDD to the head drive circuit 101 while the control signal VDD_ON is on. When the control signal VDD_ON is turned off, the voltage VDD circuit 300 stops supplying the positive voltage VDD.

  The voltage VAAN circuit 400 supplies the negative voltage VAAN to the head drive circuit 101 while the control signal VAAN_ON is on. When the control signal VAAN_ON is turned off, the voltage VAAN circuit 400 stops supplying the negative voltage VAAN.

  The voltage VCC circuit 500 supplies the positive voltage VCC to the head drive circuit 101 while the control signal VCC_ON is ON. When the control signal VCC_ON is turned off, the voltage VCC circuit 500 stops supplying the positive voltage VCC.

  The voltage VAAP circuit 600 supplies the positive voltage VAAP to the head drive circuit 101 while the control signal VAAP_ON is on. When the control signal VAAP_ON is turned off, the voltage VAAP circuit 600 stops supplying the positive voltage VAAP.

  FIG. 9 shows a sequence when the inkjet printer 200 applies each voltage VAAP, VDD, VCC, VAAN to the head drive circuit 101 when the power is turned on, and application of each voltage VAAP, VDD, VCC, VAAN when the power is off. It is a timing chart which shows the sequence at the time of complete | finishing.

  When the power is turned on, the inkjet printer 200 first applies the voltage VDD to the head drive circuit 101. Next, the inkjet printer 200 applies the voltage VAAN to the head drive circuit 101. Next, the inkjet printer 200 applies the voltage VCC to the head drive circuit 101. Finally, the inkjet printer 200 applies the voltage VAAP to the head drive circuit 101.

  When the power is turned off, the inkjet printer 200 first ends the application of the voltage VAAP. Next, the inkjet printer 200 stops applying the voltage VCC. Next, the inkjet printer 200 stops applying the voltage VAAN. Finally, the inkjet printer 200 stops applying the voltage VDD.

  A sequence controller 2111 controls the sequence of such voltage application start and application end. That is, upon receiving a power-on command from the CPU 201, the sequence controller 2111 first turns on the control signal VDD_ON, then turns on the control signal VAAN_ON, then turns on the control signal VCC_ON, and finally turns on the control signal VAAP_ON. Turn on. On the other hand, upon receiving a power off command from the CPU 201, the sequence controller 2111 first turns off the control signal VAAP_ON, then turns off the control signal VCC_ON, then turns off the control signal VAAN_ON, and finally turns on the control signal VDD_ON. Turn off. Such on / off switching of each control signal is controlled by software preset in the sequence controller 2111.

  Next, details of the voltage VDD circuit 300, the voltage VAAN circuit 400, the voltage VCC circuit 500, and the voltage VAAP circuit 600 will be described with reference to FIGS.

  FIG. 10 is a circuit diagram showing a configuration of the voltage VDD circuit 300. The voltage VDD circuit 300 includes a supply circuit 301, a discharge circuit 302, a charge / discharge capacitor 303, and a resistor 304 of about 10 megaohms. The capacitor 303 and the resistor 304 are both connected between the power supply line L2 of the voltage VDD and the terminal of the ground potential GND on the head drive circuit 101 side than the supply circuit 301 and the discharge circuit 302.

  Supply circuit 301 includes a PMOS transistor 3011 and an NPN transistor 3012. The PMOS transistor 3011 has a source-drain connected to the power supply line L 2 and a gate connected to the collector of the NPN transistor 3012. The NPN transistor 3012 has an emitter connected to the terminal of the ground potential GND, and a base connected to the signal line L11 for the control signal VDD_ON.

  When the control signal VDD_ON output from the sequence controller 2111 to the signal line L11 is turned on, in the supply circuit 301, the NPN transistor 3012 is turned on and the PMOS transistor 3011 is turned on. As a result, since a current flows between the source and drain of the PMOS transistor 3011, the voltage VDD is supplied to the head drive circuit 101 via the power supply line L2.

  When the control signal VDD_ON is turned off, in the supply circuit 301, the NPN transistor 3012 is turned off and the PMOS transistor 3011 is turned off. As a result, the source and drain of the PMOS transistor 3011 are disconnected, and the supply of the voltage VDD to the head drive circuit 101 is stopped.

  Here, the PMOS transistor 3011 and the NPN transistor 3012 of the supply circuit 301 function as switches that switch whether to supply the voltage VDD to the head drive circuit 101 in accordance with the control signal VDD_ON.

  Discharge circuit 302 includes a discharge resistor 3021, an NMOS transistor 3022, and an NPN transistor 3023. The discharge resistor 3021 has one end connected to the head drive circuit 101 side of the power supply line L2 with respect to the PMOS transistor 3011 and the other end connected to the drain of the NMOS transistor 3022. The NMOS transistor 3022 has a source connected to the terminal of the ground potential GND, and a gate connected between the terminal of the voltage VDD and the collector of the NPN transistor 3023. The NPN transistor 3023 has an emitter connected to the terminal of the ground potential GND and a base connected to the signal line L11 for the control signal VDD_ON.

  When the control signal VDD_ON output from the sequence controller 2111 to the signal line L11 is turned on, the NPN transistor 3023 is turned on and the NMOS transistor 3022 is turned off in the discharge circuit 302. As a result, no current flows through the discharge resistor 3021.

  When the control signal VDD_ON is turned off, in the discharge circuit 302, the NPN transistor 3023 is turned off and the NMOS transistor 3022 is turned on. At this time, since the power supply line L2 is cut off by the PMOS transistor 3011, a current flows from the head drive circuit 101 to the discharge resistor 3021 via the power supply line L2. As a result, a discharge phenomenon occurs, and in the head drive circuit 101, the voltage VDD decreases to the ground potential GND. The time constant at this time is determined by the capacitance of the capacitor 303 and the resistance value of the discharge resistor 3021.

  FIG. 11 is a circuit diagram showing a configuration of the voltage VAAN circuit 400. The voltage VAAN circuit 400 includes a supply circuit 401, a discharge circuit 402, a charge / discharge capacitor 403, a resistor 404 of about 10 megaohms, and an AND gate 405. The capacitor 403 and the resistor 404 are both connected between the power supply line L4 of the voltage VAAN and the terminal of the ground potential GND on the head drive circuit 101 side than the supply circuit 401 and the discharge circuit 402.

  Supply circuit 401 includes an NMOS transistor 4011, a PNP transistor 4012, and an NPN transistor 4013. The NMOS transistor 4011 has a source-drain connected to the power supply line L 4 and a gate connected to the collector of the PNP transistor 4012. The PNP transistor 4012 has an emitter connected to the terminal of the voltage VDD and a base connected to the collector of the NPN transistor 4013. The NPN transistor 4013 has an emitter connected to the terminal of the ground potential GND and a base connected to the output terminal of the AND gate 405.

  The AND gate 405 includes first and second input terminals, the first input terminal is connected to the signal line L11 for the control signal VDD_ON, and the second input terminal is connected to the signal line L12 for the control signal VAAN_ON. To do.

  When the control signal VAAN_ON output from the sequence controller 2111 to the signal line L12 is turned on, the control signal VAAN_ON is output from the AND gate 405 on condition that the control signal VDD_ON output to the signal line L11 is turned on.

  When the control signal VAAN_ON is output from the AND gate 405, in the supply circuit 401, the NPN transistor 4013 is turned on, the PNP transistor 4012 is turned on, and the NMOS transistor 4011 is turned on. As a result, since a current flows between the source and drain of the NMOS transistor 4011, the voltage VAAN is supplied to the head drive circuit 101 via the power supply line L4.

  When the control signal VAAN_ON or the control signal VDD_ON is turned off, the control signal VAAN_ON is not output from the AND gate 405. When the control signal VAAN_ON is not output, in the supply circuit 401, the NPN transistor 4013 is turned off, the PNP transistor 4012 is turned off, and the NMOS transistor 4011 is turned off. As a result, the source-drain of the NMOS transistor 4011 is cut off, and the supply of the voltage VAAN to the head driving circuit 101 is stopped.

  Here, the AND gate 405 constitutes an AND circuit that calculates the logical product of the control signal VDD_ON and the control signal VAAN_ON. The NMOS transistor 4011, the PNP transistor 4012, and the NPN transistor 4013 of the supply circuit 401 switch whether to supply the voltage VAAN to the head drive circuit 101 according to the logical product of the control signal VDD_ON and the control signal VAAN_ON. Functions as a switch.

  The discharge circuit 402 includes a discharge resistor 4021, a PMOS transistor 4022, an NPN transistor 4023, and a PNP transistor 4024. The discharge resistor 4021 has one end connected to the head drive circuit 101 side of the power supply line L4 with respect to the NMOS transistor 4011 and the other end connected to the drain of the PMOS transistor 4022. The PMOS transistor 4022 has a source connected to the terminal of the ground potential GND and a gate connected between the terminal of the ground potential GND and the collector of the NPN transistor 4023. The NPN transistor 4023 has an emitter connected to the terminal of the voltage VAAN and a base connected to the collector of the PNP transistor 4024. The PNP transistor 4024 has an emitter connected to the terminal of the voltage VDD and a base connected to the output terminal of the AND gate 405.

  When the control signal VAAN_ON is output from the AND gate 405, in the discharge circuit 402, the PNP transistor 4024 is turned off, the NPN transistor 4023 is turned off, and the PMOS transistor 4022 is turned off. As a result, no current flows through the discharge resistor 4021.

  When the control signal VAAN_ON is not output from the AND gate 405, in the discharge circuit 402, the PNP transistor 4024 is turned on, the NPN transistor 4023 is turned on, and the PMOS transistor 4022 is turned on. At this time, since the power supply line L4 is cut off by the NMOS transistor 4011, a current flows from the head drive circuit 101 to the discharge resistor 4021 via the power supply line L4. As a result, a discharge phenomenon occurs, and in the head drive circuit 101, the voltage VAAN rises to the ground potential GND. The time constant at this time is determined by the capacitance of the capacitor 403 and the resistance value of the discharge resistor 4021.

  FIG. 12 is a circuit diagram showing a configuration of voltage VCC circuit 500. The voltage VCC circuit 500 includes a supply circuit 501, a discharge circuit 502, a charge / discharge capacitor 503, a resistor 504 of about 10 megaohms, and an AND gate 505. The capacitor 503 and the resistor 504 are both connected between the power supply line L3 of the voltage VCC and the terminal of the ground potential GND on the head drive circuit 101 side than the supply circuit 501 and the discharge circuit 502.

  Supply circuit 501 includes a PMOS transistor 5011 and an NPN transistor 5012. The PMOS transistor 5011 has a source-drain connected to the power supply line L 3 and a gate connected to the collector of the NPN transistor 5012. The NPN transistor 5012 has an emitter connected to the terminal of the ground potential GND and a base connected to the output terminal of the AND gate 505.

  The AND gate 505 includes first to third input terminals, and the first input terminal is connected to the signal line L11 for the control signal VDD_ON, and the second input terminal is connected to the signal line L12 for the control signal VAAN_ON. Then, the third input terminal is connected to the signal line L13 of the control signal VCC_ON.

  When the control signal VCC_ON output from the sequence controller 2111 to the signal line L13 is turned on, the control signal VDD_ON output to the signal line L11 and the control signal VAAN_ON output to the signal line L12 are turned on. A control signal VCC_ON is output from the AND gate 505. When the control signal VCC_ON is output from the AND gate 505, in the supply circuit 501, the NPN transistor 5012 is turned on and the PMOS transistor 5011 is turned on. As a result, since a current flows between the source and drain of the PMOS transistor 5011, the voltage VCC is supplied to the head drive circuit 101 through the power supply line L3.

  When any one of the control signal VCC_ON, the control signal VAAN_ON, and the control signal VDD_ON is turned off, the control signal VCC_ON is not output from the AND gate 505. When the control signal VCC_ON is no longer output from the AND gate 505, in the supply circuit 501, the NPN transistor 5012 is turned off and the PMOS transistor 5011 is turned off. As a result, the source-drain of the PMOS transistor 5011 is cut off, and the supply of the voltage VCC to the head drive circuit 101 is stopped.

  Here, the AND gate 505 constitutes a logical product circuit that calculates a logical product of the control signal VDD_ON, the control signal VAAN_ON, and the control signal VCC_ON. The PMOS transistor 5011 and the NPN transistor 5012 of the supply circuit 501 are switches that switch whether to supply the voltage VCC to the head drive circuit 101 according to the logical product of the control signal VDD_ON, the control signal VAAN_ON, and the control signal VCC_ON. Function.

  Discharge circuit 502 includes a discharge resistor 5021, an NMOS transistor 5022, and an NPN transistor 5023. The discharge resistor 5021 has one end connected to the head drive circuit 101 side of the power supply line L3 with respect to the PMOS transistor 5011 and the other end connected to the drain of the NMOS transistor 5022. The NMOS transistor 5022 has a source connected to the terminal of the ground potential GND, and a gate connected between the terminal of the voltage VDD and the collector of the NPN transistor 5023. The NPN transistor 5023 has an emitter connected to the terminal of the ground potential GND and a base connected to the output terminal of the AND gate 505.

  When the control signal VCC_ON is output from the AND gate 505, in the discharge circuit 502, the NPN transistor 5023 is turned on and the NMOS transistor 5022 is turned off. As a result, no current flows through the discharge resistor 5021.

  When the control signal VCC_ON is not output from the AND gate 505, in the discharge circuit 502, the NPN transistor 5023 is turned off and the NMOS transistor 5022 is turned on. At this time, since the power supply line L3 is cut off by the PMOS transistor 5011, a current flows from the head drive circuit 101 to the discharge resistor 5021 via the power supply line L3. As a result, a discharge phenomenon occurs, and in the head drive circuit 101, the voltage VCC decreases to the ground potential GND. The time constant at this time is determined by the capacitance of the capacitor 503 and the resistance value of the discharge resistor 5021.

  FIG. 13 is a circuit diagram showing the configuration of the voltage VAAP circuit 600. The voltage VAAP circuit 600 includes a supply circuit 601, a discharge circuit 602, a charge / discharge capacitor 603, a resistor 604 of about 10 megaohms, and an AND gate 605. The capacitor 603 and the resistor 604 are both connected between the power supply line L5 of the voltage VAAP and the terminal of the ground potential GND on the head drive circuit 101 side than the supply circuit 601 and the discharge circuit 602.

  Supply circuit 601 includes a PMOS transistor 6011 and an NPN transistor 6012. The PMOS transistor 6011 has a source-drain connected to the power supply line L5 and a gate connected to the collector of the NPN transistor 6012. The NPN transistor 6012 has an emitter connected to the terminal of the ground potential GND and a base connected to the output terminal of the AND gate 605.

  The AND gate 605 includes first to fourth input terminals, the first input terminal is connected to the signal line L11 for the control signal VDD_ON, and the second input terminal is connected to the signal line L12 for the control signal VAAN_ON. Then, the third input terminal is connected to the signal line L13 for the control signal VCC_ON, and the fourth input terminal is connected to the signal line L14 for the control signal VAAP_ON.

  When the control signal VAAP_ON output from the sequence controller 2111 to the signal line L14 is turned on, the control signal VDD_ON output to the signal line L11, the control signal VAAN_ON output to the signal line L12, and the control signal VCC_ON output to the signal line L13 The control signal VAAP_ON is output from the AND gate 605 on the condition that and are turned on. When the control signal VAAP_ON is output from the AND gate 605, in the supply circuit 601, the NPN transistor 6012 is turned on and the PMOS transistor 6011 is turned on. As a result, since a current flows between the source and drain of the PMOS transistor 6011, the voltage VAAP is supplied to the head driving circuit 101 via the power supply line L5.

  When any one of the control signal VAAP_ON, the control signal VCC_ON, the control signal VAAN_ON, and the control signal VDD_ON is turned off, the control signal VAAP_ON is not output from the AND gate 605. When the control signal VAAP_ON is not output from the AND gate 605, the NPN transistor 6012 is turned off and the PMOS transistor 6011 is turned off in the supply circuit 601. As a result, the source-drain of the PMOS transistor 6011 is cut off, and the supply of the voltage VAAP to the head driving circuit 101 is stopped.

  Here, the AND gate 605 constitutes an AND circuit that calculates an AND of the control signal VDD_ON, the control signal VAAN_ON, the control signal VCC_ON, and the control signal VAAP_ON. The PMOS transistor 6011 and the NPN transistor 6012 of the supply circuit 601 determine whether to supply the voltage VAAP to the head drive circuit 101 according to the logical product of the control signal VDD_ON, the control signal VAAN_ON, the control signal VCC_ON, and the control signal VAAP_ON. Function as a switch.

  Discharge circuit 602 includes a discharge resistor 6021, an NMOS transistor 6022, and an NPN transistor 6023. The discharge resistor 6021 has one end connected to the head drive circuit 101 side of the power supply line L5 with respect to the PMOS transistor 6011 and the other end connected to the drain of the NMOS transistor 6022. The NMOS transistor 6022 has a source connected to the terminal of the ground potential GND, and a gate connected between the terminal of the voltage VDD and the collector of the NPN transistor 6023. The NPN transistor 6023 has an emitter connected to the terminal of the ground potential GND and a base connected to the output terminal of the AND gate 605.

  When the control signal VAAP_ON is output from the AND gate 605, the NPN transistor 6023 is turned on and the NMOS transistor 6022 is turned off in the discharge circuit 602. As a result, no current flows through the discharge resistor 6021.

  When the control signal VAAP_ON is not output from the AND gate 605, the NPN transistor 6023 is turned on and the NMOS transistor 6022 is turned on in the discharge circuit 602. At this time, since the power supply line L5 is cut off by the PMOS transistor 6011, a current flows from the head drive circuit 101 to the discharge resistor 6021 via the power supply line L5. As a result, a discharge phenomenon occurs, and in the head drive circuit 101, the voltage VAAP decreases to the ground potential GND. The time constant at this time is determined by the capacitance of the capacitor 603 and the resistance value of the discharge resistor 6021.

  Next, with respect to the operation of the printer 200 when the voltage is supplied to the head 100 or the supply of the voltage is stopped due to an abnormality in the sequence controller 2111, the timing shown in FIGS. This will be described using a chart.

  As described above, the normal sequence for supplying a voltage to the head 100 first supplies the voltage VDD, then supplies the voltage VAAN, then supplies the voltage VCC, and finally supplies the voltage VAAP. The normal sequence for stopping the voltage supplied to the head 100 is to first stop the supply of the voltage VAAP, then stop the supply of the voltage VCC, then stop the supply of the voltage VAAN, and finally stop the supply of the voltage VDD Stop supplying.

  14 to 19, the horizontal axis represents time, and the vertical axis represents voltage. On the time axis, the time point t1 is a timing for supplying the voltage VDD in the normal sequence, the time point t2 is a timing for supplying the voltage VAAN in the normal sequence, and the time point t3 is in the normal sequence. , The timing of supplying the voltage VCC, and the time point t4 is the timing of supplying the voltage VAAP in the normal sequence. Similarly, the time point t5 is a timing at which the supply of the voltage VAAP is stopped in the normal sequence, the time point t6 is a timing at which the supply of the voltage VCC is stopped in the normal sequence, and the time point t7 is a normal sequence. The timing t8 is the timing to stop the supply of the voltage VAAN, and the time point t8 is the timing to stop the supply of the voltage VDD in the normal sequence.

  That is, the sequence controller 2111 turns on the control signal VDD_ON at time t1, turns on the control signal VAAN_ON at time t2, turns on the control signal VCC_ON at time t3, and turns on the control signal VAAP_ON at time t4. The sequence controller 2111 turns off the control signal VAAP_ON at time t5, turns off the control signal VCC_ON at time t6, turns off the control signal VAAN_ON at time t7, and turns off the control signal VDD_ON at time t8.

  FIG. 14 shows a case where the timing of turning on the control signal VCC_ON is delayed from the timing of turning on the control signal VAAP_ON (time point t4). In FIG. 14, time t11 indicates the timing when the control signal VCC_ON is turned on.

  In the case of the example in FIG. 14, the control signal VDD_ON is turned on at the time point t1, so that the PMOS transistor 3011 of the voltage VDD circuit 300 is turned on. As a result, the voltage VDD is supplied to the head drive circuit 101.

  At time t2, since the control signal VAAN_ON is turned on while the control signal VDD_ON is on, the NMOS transistor 4011 of the voltage VAAN circuit 400 is turned on. As a result, the voltage VAAN is supplied to the head drive circuit 101.

  At time t3, the control signal VCC_ON is not turned on even if the control signal VDD_ON and the control signal VAAN_ON are turned on, so that the PMOS transistor 5011 of the voltage VCC circuit 500 remains off. As a result, the voltage VCC is not supplied to the head drive circuit 101.

  At time t4, the control signal VAAP_ON is turned on while the control signal VDD_ON and the control signal VAAN_ON are on. However, since the control signal VCC_ON is not on, the PMOS transistor 6011 of the voltage VAAP circuit 600 remains off. It is. Also, the PMOS transistor 5011 of the voltage VCC circuit 500 remains off. As a result, the voltage VCC and the voltage VAAP are not supplied to the head drive circuit 101.

  At time t11, the control signal VCC_ON is turned on while the control signal VDD_ON, the control signal VAAN_ON, and the control signal VAAP_ON are turned on, so that the PMOS transistor 6011 of the voltage VAAP circuit 600 is turned on. Further, since the control signal VCC_ON is turned on while the control signal VDD_ON and the control signal VAAN_ON are turned on, the PMOS transistor 5011 of the voltage VCC circuit 500 is also turned on. As a result, the voltage VCC and the voltage VAAP are supplied to the head drive circuit 101 at the same time.

  In the example of FIG. 14, the voltage VDD is supplied to the head drive circuit 101 at time t1, the voltage VCCN is applied at time t2, and then the voltage VCC and voltage VAAP are supplied simultaneously at time t11. The Thus, even if the timing at which the control signal VCC_ON is turned on is delayed from the timing at which the control signal VAAP_ON is turned on, the voltage VCC and the voltage VAAP are supplied at the same time, and the order is not changed.

  FIG. 15 shows a case where the timing for turning on the control signal VAAN_ON is delayed from the timing for turning on the control signal VAAP_ON. In FIG. 15, a time point t12 indicates the timing when the control signal VAAN_ON is turned on.

  In the case of the example in FIG. 15, at time t1, the control signal VDD_ON is turned on, so that the PMOS transistor 3011 of the voltage VDD circuit 300 is turned on. As a result, the voltage VDD is supplied to the head drive circuit 101.

  At the time t2, the control signal VAAN_ON is not turned on although the control signal VDD_ON is turned on, so that the NMOS transistor 4011 of the voltage VAAN circuit 400 remains off. As a result, the voltage VAAN is not supplied to the head drive circuit 101.

  At time t3, the control signal VCC_ON is on while the control signal VDD_ON is on, but the control signal VAAN_ON is not on, so the PMOS transistor 5011 of the voltage VCC circuit 500 remains off. Also, the NMOS transistor 4011 of the voltage VAAN circuit 400 remains off. As a result, the voltage VAAN and the voltage VCC are not supplied to the head drive circuit 101.

  At time t4, the control signal VAAP_ON is turned on while the control signal VDD_ON and the control signal VCC_ON are on, but the control signal VAAN_ON is not on, so the PMOS transistor 6011 of the voltage VAAP circuit 600 remains off. It is. Also, the PMOS transistor 5011 of the voltage VCC circuit 500 and the NMOS transistor 4011 of the voltage VAAN circuit 400 remain off. As a result, the voltage VAAN, the voltage VCC, and the voltage VAAP are not supplied to the head driving circuit 101.

  At time t12, since the control signal VAAN_ON is turned on while the control signal VDD_ON, the control signal VCC_ON, and the control signal VAAP_ON are on, the PMOS transistor 6011 of the voltage VAAP circuit 600 is turned on. Further, since the control signal VAAN_ON is turned on while the control signal VDD_ON and the control signal VCC_ON are on, the PMOS transistor 5011 of the voltage VCC circuit 500 is also turned on. Further, since the control signal VAAN_ON is turned on while the control signal VDD_ON is on, the NMOS transistor 4011 of the voltage VAAN circuit 400 is also turned on. As a result, the voltage VAAN, the voltage VCC, and the voltage VAAP are supplied to the head drive circuit 101 at the same time.

  In the example of FIG. 15, after the voltage VDD is supplied to the head driving circuit 101 at time t1, the voltage VAAN, the voltage VCC, and the voltage VAAP are supplied simultaneously at time t12. As described above, even when the timing of turning on the control signal VAAN_ON is delayed from the timing of turning on the control signal VAAP_ON, the voltage VAAN, the voltage VCC, and the voltage VAAP are supplied at the same time, and the order is not changed.

  FIG. 16 shows a case where the timing for turning on the control signal VDD_ON is delayed from the timing for turning on the control signal VAAP_ON. In FIG. 16, a time point t13 indicates a timing when the control signal VDD_ON is turned on.

  In the case of the example of FIG. 16, the control signal VDD_ON is not turned on at the time point t1, so that the PMOS transistor 3011 of the voltage VDD circuit 300 remains off. As a result, the voltage VDD is not supplied to the head drive circuit 101.

  At time t2, the control signal VAAN_ON is turned on, but the NMOS transistor 4011 of the voltage VAAN circuit 400 remains off because the control signal VDD_ON is off. Also, the PMOS transistor 3011 of the voltage VDD circuit 300 remains off. As a result, the voltage VDD and the voltage VAAN are not supplied to the head drive circuit 101.

  At time t3, the control signal VCC_ON is turned on while the control signal VAAN_ON is on, but the control signal VDD_ON is not on, so the PMOS transistor 5011 of the voltage VCC circuit 500 remains off. Also, the PMOS transistor 3011 of the voltage VDD circuit 300 and the NMOS transistor 4011 of the voltage VAAN circuit 400 remain off. As a result, the voltage VDD, the voltage VAAN, and the voltage VCC are not supplied to the head drive circuit 101.

  At time t4, the control signal VAAP_ON is turned on while the control signal VAAN_ON and the control signal VCC_ON are on, but the control signal VDD_ON is not on, so the PMOS transistor 6011 of the voltage VAAP circuit 600 remains off. It is. Also, the PMOS transistor 3011 of the voltage VDD circuit 300, the NMOS transistor 4011 of the voltage VAAN circuit 400, and the PMOS transistor 5011 of the voltage VCC circuit 500 remain off. As a result, the voltage VDD, the voltage VAAN, the voltage VCC, and the voltage VAAP are not supplied to the head drive circuit 101.

  At time t13, since the control signal VDD_ON is turned on while the control signal VAAN_ON, the control signal VCC_ON, and the control signal VAAP_ON are turned on, the PMOS transistor 6011 of the voltage VAAP circuit 600 is turned on. Further, since the control signal VDD_ON is turned on while the control signal VAAN_ON and the control signal VCC_ON are turned on, the PMOS transistor 5011 of the voltage VCC circuit 500 is also turned on. Further, since the control signal VDD_ON is turned on while the control signal VAAN_ON is on, the NMOS transistor 4011 of the voltage VAAN circuit 400 is also turned on. Further, since the control signal VDD_ON is turned on, the PMOS transistor 3011 of the voltage VDD circuit 300 is also turned on. As a result, the voltage VDD, the voltage VAAN, the voltage VCC, and the voltage VAAP are supplied to the head driving circuit 101 at the same time.

  In the case of the example of FIG. 16, the voltage VDD, the voltage VAAN, the voltage VCC, and the voltage VAAP are simultaneously supplied to the head drive circuit 101 at time t13. As described above, even when the timing for turning on the control signal VDD_ON is delayed from the timing for turning on the control signal VAAP_ON, the voltage VDD, the voltage VAAN, the voltage VCC, and the voltage VAAP are supplied at the same time, and the order is not changed. .

  FIG. 17 shows a case where the timing for turning off the control signal VCC_ON is earlier than the timing for turning off the control signal VAAP_ON. In FIG. 17, a time point t21 indicates a timing when the control signal VCC_ON is turned off.

  In the case of the example of FIG. 17, at time t21, the control signal VCC_ON is turned off, so that the PMOS transistor 5011 of the voltage VCC circuit 500 is turned off. Further, although the control signal VAAP_ON is on, the control signal VCC_ON is turned off, so that the PMOS transistor 6011 of the voltage VAAP circuit 600 is also turned off. As a result, the supply of the voltage VCC to the head drive circuit 101 is stopped, and at the same time, the supply of the voltage VAAP is also stopped.

  At time t5, the control signal VAAP_ON is turned off. However, since the PMOS transistor 6011 of the voltage VAAP circuit 600 is already turned off, the voltage supplied to the head driving circuit 101 does not change.

  At time t6, the control signal VCC_ON is already off. For this reason, there is no change in the voltage supplied to the head drive circuit 101.

  At time t7, since the control signal VAAN_ON is turned off, the NMOS transistor 4011 of the voltage VAAN circuit 400 is turned off. As a result, the supply of the voltage VAAN to the head driving circuit 101 is stopped.

  At time t8, since the control signal VDD_ON is turned off, the PMOS transistor 3011 of the voltage VDD circuit 300 is turned off. As a result, the supply of the voltage VDD to the head drive circuit 101 is stopped.

  In the case of the example in FIG. 17, the supply of the voltage VCC and the voltage VAAP to the head drive circuit 101 is stopped simultaneously when the control signal VCC_ON is turned off at time t21 even though the control signal VAAP_ON is on. Thereafter, the supply of the voltage VAAN is stopped at time t7, and the supply of the voltage VDD is stopped at time t8. Thus, even if the timing at which the control signal VCC_ON is turned off is earlier than the timing at which the control signal VAAP_ON is turned off, the supply of the voltage VAAP is stopped simultaneously with the voltage VCC, and the order is not changed.

  FIG. 18 shows a case where the timing for turning off the control signal VAAN_ON is earlier than the timing for turning off the control signal VAAP_ON. In FIG. 18, a time point t22 indicates a timing at which the control signal VAAN_ON is turned off.

  In the case of the example in FIG. 18, at time t22, the control signal VAAN_ON is turned off, so that the NMOS transistor 4011 of the voltage VAAN circuit 400 is turned off. Further, although the control signal VAAP_ON and the control signal VCC_ON are on, the control signal VAAN_ON is turned off, so that the PMOS transistor 6011 of the voltage VAAP circuit 600 and the PMOS transistor 5011 of the voltage VCC circuit 500 are also turned off. As a result, the supply of the voltage VAAN to the head drive circuit 101 is stopped and the supply of the voltage VCC and the voltage VAAP is also stopped.

  At time t5, the control signal VAAP_ON is turned off. However, since the PMOS transistor 6011 of the voltage VAAP circuit 600 is already turned off, the voltage supplied to the head driving circuit 101 does not change.

  At time t6, the control signal VCC_ON is turned off. However, since the PMOS transistor 5011 of the voltage VCC circuit 500 is already turned off, the voltage supplied to the head drive circuit 101 does not change.

  At time t7, the control signal VAAN_ON is already off. For this reason, there is no change in the voltage supplied to the head drive circuit 101.

  At time t8, since the control signal VDD_ON is turned off, the PMOS transistor 3011 of the voltage VDD circuit 300 is turned off. As a result, the supply of the voltage VDD to the head drive circuit 101 is stopped.

  In the case of the example in FIG. 18, the control signal VAAP_ON and the control signal VCC_ON are on, but when the control signal VAAN_ON is off at time t22, the voltage VAAN, the voltage VCC, and the voltage VAAP are Supply stops simultaneously. Thereafter, the supply of the voltage VDD is stopped at time t8. Thus, even when the timing for turning off the control signal VAAN_ON is earlier than the timing for turning off the control signal VAAP_ON, the supply of the voltage VAAP and the voltage VCC is stopped simultaneously with the voltage VAAN, and the order is not changed.

  FIG. 19 shows a case where the timing for turning off the control signal VDD_ON is earlier than the timing for turning off the control signal VAAP_ON. In FIG. 19, a time point t23 indicates a timing when the control signal VDD_ON is turned off.

  In the example of FIG. 19, the control signal VDD_ON is turned off at time t23, so that the PMOS transistor 3011 of the voltage VDD circuit 300 is turned off. Further, although the control signal VAAP_ON, the control signal VCC_ON, and the control signal VAAN_ON are on, the control signal VDD_ON is off. Therefore, the PMOS transistor 6011 of the voltage VAAP circuit 600, the PMOS transistor 5011 of the voltage VCC circuit 500, and the voltage VAAN. The NMOS transistor 4011 of the circuit 400 is also turned off. As a result, the supply of the voltage VDD to the head drive circuit 101 is stopped, and the supply of the voltage VAAN, the voltage VCC, and the voltage VAAP is also stopped.

  At time t5, the control signal VAAP_ON is turned off. However, since the PMOS transistor 6011 of the voltage VAAP circuit 600 is already turned off, the voltage supplied to the head driving circuit 101 does not change.

  At time t6, the control signal VCC_ON is turned off. However, since the PMOS transistor 5011 of the voltage VCC circuit 500 is already turned off, the voltage supplied to the head drive circuit 101 does not change.

  At time t7, the control signal VAAN_ON is turned off. However, since the NMOS transistor 4011 of the voltage VAAN circuit 400 is already turned off, the voltage supplied to the head driving circuit 101 does not change.

  At time t8, the control signal VDD_ON is already off. For this reason, there is no change in the voltage supplied to the head drive circuit 101.

  In the case of the example in FIG. 19, when the control signal VDD_ON is turned off at time t23 even though the control signal VAAP_ON, the control signal VCC_ON, and the control signal VAAN_ON are turned on, the voltage VDD and the voltage VAAN are supplied to the head driving circuit 101. The supply of the voltage VCC and the voltage VAAP is stopped simultaneously. As described above, even when the timing of turning off the control signal VDD_ON is earlier than the timing of turning off the control signal VAAP_ON, the supply of the voltage VAAP, the voltage VCC, and the voltage VAAN is stopped simultaneously with the voltage VDD, and the order is switched. Absent.

  As described above, when the signal for controlling the start of voltage application is output from the sequence controller 2111 in an order different from the sequence, the printer 200 outputs a signal to be output before the signal from the sequence controller 2111. Gate circuits (AND gates 405, 505, and 605) are provided to prevent the signals from being output to the supply circuits 401, 501, and 601 until the signal is output. With this configuration, as described with reference to FIGS. 14 to 16, the printer 200 does not change the order of the voltages supplied to the head drive circuit 101 even if an abnormality occurs in the voltage-on sequence control. Absent.

  Further, when a signal for controlling the end of voltage application is output from the sequence controller 2111 in an order different from the sequence, the printer 200 until a signal to be output before the signal is output from the sequence controller 2111. Gate circuits (AND gates 405, 505, and 605) that block the control signals from being output to the discharge circuits 402, 502, and 602 are provided. With such a configuration, as described with reference to FIGS. 17 to 19, the printer 200 has the order of the voltages at which the supply to the head drive circuit 101 is stopped even if an abnormality occurs in the sequence control of the voltage off. There is no replacement.

  Therefore, according to the present embodiment, there is no possibility that the output of the circuit incorporated in the head 100 becomes unstable when the power supply is turned on or the circuit is destroyed by a through current generated by latch-up of the semiconductor element. Further, even when the power is shut off, there is no possibility that the output of the circuit incorporated in the head 100 becomes unstable or the circuit is destroyed by a through current generated by latch-up of the semiconductor element.

  When the supply of the voltage VDD is stopped, the time T1 required for the voltage VDD to be discharged to zero volts in the head drive circuit 101 is the time constant of the discharge circuit 302, that is, the capacitance of the capacitor 303 and the resistance value of the discharge resistor 3021. It depends on. Similarly, when the supply of the voltage VAAN is stopped, the time T2 required for the head drive circuit 101 to discharge the voltage VAAN to zero volts is the time constant of the discharge circuit 402, that is, the capacitance of the capacitor 403 and the resistance value of the discharge resistor 4021. It depends on. When the supply of the voltage VCC stops, the time T3 required for the voltage VCC to discharge to zero volts is determined by the time constant of the discharge circuit 502, that is, the capacitance of the capacitor 503 and the resistance value of the discharge resistor 5021. When the supply of the voltage VAAP is stopped, the time T4 required for the head drive circuit 101 to discharge the voltage VAAP to zero volts is determined by the time constant of the discharge circuit 602, that is, the capacitance of the capacitor 603 and the resistance value of the discharge resistor 6021. . Therefore, if the relationship of T1> T2> T3> T4 is not satisfied, the sequence may be switched when the supply of the voltage VDD, the voltage VAAN, the voltage VCC, and the voltage VAAP is stopped simultaneously.

  Therefore, in this embodiment, the discharge resistors 3021 and 4021 of the voltage VDD circuit 300, the voltage VAAN circuit 400, the voltage VCC circuit 500, and the voltage VAAP circuit 600 are satisfied so that the relationship of T1> T2> T3> T4 is satisfied. , 5021, 6021 and capacitances of the capacitors 303, 403, 503, 603 are determined. However, the capacities of the capacitors 303, 403, 503, and 603 are uniquely determined from the drive current of the head drive circuit 101. For this reason, the resistance values of the discharge resistors 3021, 4021, 5021, and 6021 may be determined so that the relationship of T1> T2> T3> T4 is satisfied.

  FIGS. 20A and 20B are graphs showing time changes of the voltage VDD, the voltage VAAN, the voltage VCC, and the voltage VAAP when the supply of the voltage VDD, the voltage VAAN, the voltage VCC, or the voltage VAAP is stopped simultaneously. 20, (a) is a graph in which the span of time on the horizontal axis is in units of 1 second, and (b) is a graph in units of 0.1 seconds. Note that the voltage VAAN is represented by replacing a negative voltage with a positive voltage so that changes in the voltages can be easily compared.

  The example of the graph of FIG. 20 is a case where the voltage VDD is + 5V, the voltage VAAP is + 18V, the voltage VCC is + 24V, and the voltage VAAN is −18V. Further, the capacitor 303 has a capacitance of 47 μF, the capacitor 403 has a capacitance of 220 μF, the capacitor 503 has a capacitance of 100 μF, and the capacitor 603 has a capacitance of 220 μF. In this case, the discharge resistance 3021 is 22 kΩ, the discharge resistance 4021 is 680Ω, the discharge resistance 5021 is 820Ω, and the discharge resistance 6021 is 330Ω. Then, as shown in FIG. 20, first, the voltage VAAP becomes zero volts, then the voltage VCC becomes zero volts, then the voltage VAAN becomes zero volts, and finally the voltage VDD becomes zero volts.

  As described above, according to the present embodiment, by optimizing the resistance values of the discharge resistors 3021, 4021, 5021, and 6021, the sequence at the end of voltage application can be reliably protected.

The present invention is not limited to the above embodiment.
For example, in the above-described embodiment, the AND circuit 405 includes the AND circuit 405 that calculates the logical product of the control signal VDD_ON and the control signal VAAN_ON. Further, an AND gate 505 is configured to calculate a logical product of the control signal VDD_ON, the control signal VAAN_ON, and the control signal VCC_ON. Further, an AND gate 605 is configured to calculate a logical product of the control signal VDD_ON, the control signal VAAN_ON, the control signal VCC_ON, and the control signal VAAP_ON. These AND circuits can be realized by arranging transistors without using AND gates.

  FIG. 21 is a circuit diagram in the case where a logical product circuit that calculates a logical product of the control signal VDD_ON and the control signal VAAN_ON is realized by arrangement of transistors. In addition, the same code | symbol is attached | subjected to the part which is common in FIG. 11, and the detailed description is abbreviate | omitted.

  The supply circuit 401 includes an NMOS transistor 4011, PNP transistors 4014 and 4015, and NPN transistors 4016 and 4017. The NMOS transistor 4011 has a source-drain connected to the power supply line L4 and a gate connected to the collector of the PNP transistor 4014. The PNP transistor 4014 has an emitter connected to the collector of the PNP transistor 4015 and a base connected to the collector of the NPN transistor 4016. The NPN transistor 4016 has an emitter connected to the terminal of the ground potential GND, and a base connected to the signal line L12 of the control signal VAAN_ON. The PNP transistor 4015 has an emitter connected to the terminal of the voltage VDD and a base connected to the collector of the NPN transistor 4017. The NPN transistor 4017 has an emitter connected to the terminal of the ground potential GND, and a base connected to the signal line L11 for the control signal VDD_ON.

  The discharge circuit 402 includes a discharge resistor 4021, a PMOS transistor 4022, NPN transistors 4025 and 4027, and PNP transistors 4026 and 4028. The discharge resistor 4021 has one end connected to the head drive circuit 101 side of the power supply line L4 with respect to the NMOS transistor 4011 and the other end connected to the drain of the PMOS transistor 4022. The PMOS transistor 4022 has a source connected to the terminal of the ground potential GND and a gate connected between the terminal of the ground potential GND and the collector of the NPN transistor 4025. The NPN transistor 4025 has an emitter connected to the terminal of the voltage VAAN and a base connected to the collector of the PNP transistor 4026. The PNP transistor 4026 has an emitter connected to the terminal of the voltage VDD and a base connected to the signal line L12 of the control signal VAAN_ON. The NPN transistor 4027 has a collector connected to the collector of the NPN transistor 4025, an emitter connected to the terminal of the voltage VAAN, and a base connected to the collector of the PNP transistor 4028. The PNP transistor 4028 has an emitter connected to the terminal of the voltage VDD and a base connected to the signal line L11 of the control signal VDD_ON.

  In the voltage VAAN circuit 400 of FIG. 21, the supply circuit 401 turns on the NMOS transistor 4011 because the PNP transistor 4014 is turned on when the VAAN_ON signal is turned on while the VDD_ON signal is turned on. As a result, since a current flows between the source and drain of the NMOS transistor 4011, the voltage VAAN is supplied to the head drive circuit 101 via the power supply line L4.

  However, even if the VAAN_ON signal is turned on while the VDD_ON signal is not turned on, the PNP transistor 4014 is not turned on. Therefore, even if the VAAN_ON signal is turned on first, the voltage VAAN is not supplied to the head drive circuit 101 until the VDD_ON signal is turned on.

  In the discharge circuit 402, when the VDD_ON signal and the VAAN_ON signal are turned on, the PNP transistor 4026 is turned off, the NPN transistor 4025 is turned off, the PNP transistor 4028 is turned off, the NPN transistor 4029 is turned off, and the PMOS transistor 4022 is turned off. . As a result, no current flows through the discharge resistor 4021. When one of the VDD_ON signal and the VAAN_ON signal is turned off, the NPN transistor 4025 or the NPN transistor 4029 is turned on, and the PMOS transistor 4022 is turned on. At this time, since the power supply line L4 is cut off by the NMOS transistor 4011, a current flows from the head drive circuit 101 to the discharge resistor 4021 via the power supply line L4. As a result, a discharge phenomenon occurs, and in the head drive circuit 101, the voltage VAAN rises to the ground potential GND. The time constant at this time is determined by the capacitance of the capacitor 403 and the resistance value of the discharge resistor 4021.

  FIG. 22 is a circuit diagram in the case where an AND circuit that calculates the logical product of the control signal VDD_ON, the control signal VAAN_ON, and the control signal VCC_ON is realized by the arrangement of transistors. In addition, the same code | symbol is attached | subjected to the part which is common in FIG. 12, The detailed description is abbreviate | omitted.

  The supply circuit 501 includes an NMOS transistor 5011 and NPN transistors 5013, 5014, and 5015. The NMOS transistor 5011 has a source-drain connected to the power supply line L3 and a gate connected to the collector of the NPN transistor 5013. The NPN transistor 5013 has an emitter connected to the collector of the NPN transistor 5014 and a base connected to the signal line L13 of the control signal VCC_ON. The NPN transistor 5014 has an emitter connected to the collector of the NPN transistor 5015 and a base connected to the signal line L12 of the control signal VAAN_ON. The NPN transistor 5015 has an emitter connected to the terminal of the ground potential GND, and a base connected to the signal line L11 for the control signal VDD_ON.

  The discharge circuit 502 includes a discharge resistor 5021, a PMOS transistor 5022, and NPN transistors 5024, 5025, and 5026. The discharge resistor 5021 has one end connected to the head drive circuit 101 side of the power supply line L3 with respect to the NMOS transistor 5011 and the other end connected to the drain of the PMOS transistor 5022. The PMOS transistor 5022 has a source connected to the terminal of the ground potential GND and a gate connected between the terminal of the voltage VDD and the collector of the NPN transistor 5024. The NPN transistor 5024 has an emitter connected to the collector of the NPN transistor 5025, and a base connected to the signal line L13 of the control signal VCC_ON. The NPN transistor 5025 has an emitter connected to the collector of the NPN transistor 5026 and a base connected to the signal line L12 of the control signal VAAN_ON. The NPN transistor 5026 has an emitter connected to the terminal of the ground potential GND, and a base connected to the signal line L11 for the control signal VDD_ON.

  In the voltage VCC circuit 500 shown in FIG. 22, the supply circuit 501 turns on the PNP transistors 5013, 5014, and 5015 when the VCC_ON signal is turned on while the VDD_ON signal and the VAAN_ON signal are turned on. Turn on. As a result, since a current flows between the source and drain of the NMOS transistor 5011, the voltage VCC is supplied to the head drive circuit 101 via the power supply line L3.

  However, even if the VCC_ON signal is turned on in a state where the VDD_ON signal or the VAAN_ON signal is not turned on, the PNP transistor 5013 is not turned on. Therefore, even if the VCC_ON signal is turned on first, the voltage VCC is not supplied to the head drive circuit 101 until the VDD_ON signal and the VAAN_ON signal are turned on.

  In the discharge circuit 502, the PMOS transistor 5022 is not turned on until the VCC_ON signal is turned off regardless of whether the VAAN_ON signal and the VDD_ON signal are turned on or off. Therefore, even if the VDD_ON signal or the VAAN_ON signal is turned off first, the discharge phenomenon does not occur until the VCC_ON signal is turned off.

  FIG. 23 is a circuit diagram in a case where an AND circuit that calculates the logical product of the control signal VDD_ON, the control signal VAAN_ON, the control signal VCC_ON, and the control signal VAAP_ON is realized by the arrangement of transistors. In addition, the same code | symbol is attached | subjected to the part which is common in FIG. 13, The detailed description is abbreviate | omitted.

  The supply circuit 601 includes an NMOS transistor 6011 and NPN transistors 6013, 6014, 6015 and 6016. The NMOS transistor 6011 has a source-drain connected to the power supply line L5 and a gate connected to the collector of the NPN transistor 6013. The NPN transistor 6013 has an emitter connected to the collector of the NPN transistor 6014 and a base connected to the signal line L14 for the control signal VAAP_ON. The NPN transistor 6014 has an emitter connected to the collector of the NPN transistor 6015 and a base connected to the signal line L13 of the control signal VCC_ON. The NPN transistor 6015 has an emitter connected to the collector of the NPN transistor 6016 and a base connected to the signal line L12 of the control signal VAAN_ON. The NPN transistor 6016 has an emitter connected to the terminal of the ground potential GND, and a base connected to the signal line L11 for the control signal VDD_ON.

  Discharge circuit 602 includes a discharge resistor 6021, a PMOS transistor 6022, and NPN transistors 6024, 6025, 6026 and 6027. The discharge resistor 6021 has one end connected to the head drive circuit 101 side of the power supply line L5 with respect to the NMOS transistor 6011 and the other end connected to the drain of the PMOS transistor 6022. The PMOS transistor 6022 has a source connected to the terminal of the ground potential GND and a gate connected between the terminal of the voltage VDD and the collector of the NPN transistor 6024. The NPN transistor 6024 has an emitter connected to the collector of the NPN transistor 6025 and a base connected to the signal line L14 for the control signal VAAP_ON. The NPN transistor 6025 has an emitter connected to the collector of the NPN transistor 6026 and a base connected to the signal line L13 of the control signal VCC_ON. The NPN transistor 6026 has an emitter connected to the collector of the NPN transistor 6027 and a base connected to the signal line L12 of the control signal VAAN_ON. The NPN transistor 6027 has an emitter connected to the terminal of the ground potential GND, and a base connected to the signal line L11 for the control signal VDD_ON.

  In the voltage VAAP circuit 600 of FIG. 23, the supply circuit 601 turns on the PNP transistors 6013, 6014, 6015, and 6016 when the VAAP_ON signal is turned on while the VDD_ON signal, the VAAN_ON signal, and the VCC_ON signal are turned on. Therefore, the NMOS transistor 6011 is turned on. As a result, since a current flows between the source and drain of the NMOS transistor 6011, the voltage VAAP is supplied to the head driving circuit 101 via the power supply line L5.

  However, even if the VAAP_ON signal is turned on in a state where at least one of the VDD_ON signal, the VAAN_ON signal, and the VCC_ON signal is not turned on, the PNP transistor 6013 is not turned on. Therefore, even if the VAAP_ON signal is turned on first, the voltage VAAP is not supplied to the head driving circuit 101 until the VDD_ON signal, the VAAN_ON signal, and the VCC_ON signal are turned on.

  In the discharge circuit 602, the PMOS transistor 6022 is not turned on until the VAAP_ON signal is turned off regardless of whether the VCC_ON signal, the VAAN_ON signal, and the VDD_ON signal are turned on or off. Therefore, even if the VCC_ON signal, the VDD_ON signal, or the VAAN_ON signal is turned off first, the discharge phenomenon does not occur until the VAAP_ON signal is turned off.

  Moreover, although the said embodiment illustrated the printer 20 using the share mode type head 100, this invention is not limited to this. For example, an ink jet printer provided with an ink jet head that operates by applying a first voltage, a second voltage having a value smaller than the first voltage, and a third voltage having a value larger than the first voltage. In addition, the same technical idea as in the present embodiment can be applied.

  In addition, although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 100 ... Inkjet head (head), 101 ... Head drive circuit, 200 ... Inkjet printer (printer), 201 ... CPU, 210 ... Power supply circuit, 211 ... Sequence control circuit, 2111 ... Sequence controller, 301, 401, 501, 605 ... Supply circuit, 302, 402, 502, 602 ... discharge circuit, 405, 505, 605 ... gate circuit.

Claims (4)

An inkjet head that operates by applying a first voltage for driving an actuator, a second voltage having a value smaller than the first voltage, and a third voltage having a value larger than the first voltage;
A sequence controller that outputs a signal for controlling application start and application end in accordance with a preset sequence for each of the first to third voltages;
A supply circuit that selectively supplies the first to third voltages to the inkjet head in response to a signal for controlling the start of application of the voltage output from the sequence controller;
A discharge circuit that selectively discharges the first to third voltages supplied to the inkjet head in accordance with a signal for controlling the end of application of the voltage output from the sequence controller;
When a signal for controlling the start of voltage application is output from the sequence controller in an order different from the sequence, the signal is supplied until the signal to be output before the signal is output from the sequence controller. When the signal for controlling the end of voltage application is output from the sequence controller in an order different from the sequence, the signal to be output before the signal is prevented from being output to the circuit. A gate circuit for preventing the signal from being output to the discharge circuit until it is output from the sequence controller ;
An ink jet printer comprising: The discharge circuit includes: a first discharge circuit that discharges the first voltage; a second discharge circuit that discharges the second voltage; and a third discharge circuit that discharges the third voltage; Including
The sequence of the sequence at the end of voltage application when the time constants of the first to third discharge circuits are simultaneously output to the first to third discharge circuits to control the end of voltage application. 2. The ink jet printer according to claim 1 , wherein the ink jet printer is set so as not to be replaced. The gate circuit is
A first AND circuit that calculates the logical product of signals that control the start of application of the first and second voltages when the sequence of power supply starts;
A second logical product circuit for calculating a logical product of signals for controlling the start of application to each of the first to third voltages in the sequence at the start of power application;
The ink jet printer according to claim 1 or 2, characterized in that it comprises a. 4. The ink jet printer according to claim 3, wherein the first and second AND circuits are constituted by AND gates or transistors.