JP6283858B2 - Chip that can output multiple divided clocks - Google Patents

Description

  The present invention is a microcomputer used for controlling a gaming machine represented by a pachinko gaming machine, a coin gaming machine, a slot machine, or the like, and in particular, a divided clock from an internal system clock and a divided clock from a timer signal. The present invention relates to a microcomputer for controlling a gaming machine having a plurality of divided clock output terminals.

  Until now, in a gaming machine such as a pachinko machine, a microcomputer (hereinafter referred to as “main chip”) uses a clock input terminal (EX terminal) as an arbitrary frequency division ratio (for example, frequency division by 2). ), The clock is generated and supplied to the CPU and internal circuits. The generated clock is also output to the outside from the clock output terminal.

  The clock that can be used by an external circuit provided outside the chip is only the internal system clock described above. For example, when the clock is used in an external peripheral circuit for starting / controlling a motor drive, etc. However, there is no choice but to divide the internal system clock by mounting a frequency dividing circuit.

As described above, in the case of the conventional chip configuration, it is necessary for the user who is a game machine development manufacturer to divide the internal system clock and to mount another clock outside the chip. It was high.
In addition, pachinko machines and other gaming machines must pass the accreditation and type certification of gaming machines in accordance with the rules of the National Public Safety Commission in accordance with the Customs Business Law. The number of program steps that can be used includes an upper limit. Accordingly, in view of the trend toward more sophisticated or complicated game machine application programs that are more attractive, there has also been a need to reduce the number of program steps required for setting the clock or the frequency dividing circuit.

  Therefore, the present invention aims to reduce the mounting cost and the number of user program steps of the frequency divider circuit and the like by incorporating the function conventionally performed by the frequency divider circuit and the like mounted outside the chip into the chip. With the goal.

  The computer chip for gaming machines of the present invention is a prescaler that divides a CPU, a clock generation circuit, and an internal system clock generated by the clock generation circuit, and divides the internal system clock by a predetermined division ratio. A prescaler that selects and outputs as an external clock from a plurality of frequency-divided clocks, and a timer circuit that divides the internal system clock generated by the clock generation circuit. A plurality of external clocks including a first output signal from the prescaler and a second output signal from the timer circuit are supplied as external clocks.

  The gaming machine computer chip of the present invention further includes a plurality of divisions set in the program management area by specifying a program code for obtaining an external clock having a desired frequency division ratio in the gaming machine application program. By designating a value for identifying the frequency ratio, a frequency-divided clock corresponding to the value designated by the prescaler is output.

  In the gaming machine computer chip of the present invention, the gaming machine application program further includes a first output signal from the prescaler for a clock having a high frequency and a second output signal from the timer circuit for a clock having a low frequency. It is used by.

  According to the gaming machine computer chip of the present invention, a prescaler that divides the internal system clock generated by the clock generation circuit is provided in the gaming machine computer chip. However, the frequency dividing circuit mounted outside the computer chip for gaming machines is not necessary. For this reason, a gaming machine development manufacturer that uses gaming machine computer chips can reduce the manufacturing cost of gaming machines.

  A game machine application program development user uses a plurality of external clocks, a first output signal from a prescaler and a second output signal from the timer circuit, as an external clock of a gaming machine computer chip. Therefore, it is possible to cope with these multiple external clocks for advanced control of the gaming machine.

  Furthermore, in addition to designating a program code for obtaining an external clock having a desired frequency division ratio, it is also possible to store a setting value corresponding to the frequency division ratio in the program management area. When the development user designates a desired set value, the prescaler that has received this can output a first output signal having a frequency division ratio corresponding to the set value to the external terminal. In other words, since the division of the internal system clock to the desired division ratio can be performed in the background, the step for dividing the internal system clock to the desired division ratio is omitted. There is also an effect that the user program is not burdened.

It is an internal block diagram of the computer chip (main chip) for gaming machines. It is a conceptual block diagram showing the relationship of the circuits related to the generation of the external clock in the main chip of one embodiment. It is a block diagram showing an example of mounting of the main chip.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an internal block diagram illustrating a general hardware configuration of a gaming machine computer chip (hereinafter referred to as “main chip”) 1. The CPU 2 can be, for example, Z80 from Zilog, 68HC11 from Motorola, or a compatible software compatible CPU.

The built-in ROM 3 is a ROM whose capacity is limited by related laws and regulations and stores a user program (a program created by a gaming machine manufacturer). The built-in RAM 4 is a RAM used as a work area for user programs.
Via the bus of the CPU 2, a built-in ROM 3, a built-in RAM 4, and some circuits provided in the gaming machine control chip 1 described below are connected.

The external control circuit 10 is a bus interface circuit that reinforces the address bus, the data bus, and the direction control and drive capability of each control signal.
The clock circuit 11 is a circuit that divides the clock input to the clock input terminal (EXTAL terminal) by, for example, two and supplies it to each circuit as an internal system clock, and outputs this clock from the clock output terminal (E terminal). is there.
The timer circuit 5 is, for example, a Z80-CTC compatible timer circuit manufactured by Zylog Corporation. The address decoding circuit 12 is a decoding circuit for an external device of a user program, and outputs a chip select signal (* CSIO). The reset control circuit 6 is a circuit that controls various resets, external interrupt requests, and interrupt requests from the built-in timer circuit 5.

  When an external trigger signal is input, it is passed to the random number acquisition control circuit 8 to monitor whether the random number circuit 9 for generating random numbers and the user program are correctly executed in the designated area, and out of the designated area. When the user program is executed, there is an out-of-designated area running prohibition circuit (not shown) that generates an IAT signal and thereby causes a user reset, but the details are omitted because it is not directly related to the present invention.

FIG. 2 is a conceptual block diagram showing the relationship of circuits related to the generation of an external clock in the main chip of the present embodiment. An external clock signal (EX) is input to the frequency divider 20 in the main chip 1 and is divided by, for example, 1/2 to generate an internal system clock (SCLK). The generated internal system clock (SCLK) is passed to the prescaler 21 and the timer circuit 5.
The reason why the external clock signal (EX) is divided by 1/2 is to adjust the duty ratio of the external clock signal (EX), and the original duty ratio of the external clock signal (EX) is high and ideal. As long as it is close to the pulse train, the frequency divider 20 does not necessarily divide the frequency by 1/2. Further, in the case where an internal clock circuit that generates an internal system clock is mounted in the main chip without using the clock input terminal (EX terminal), SCLK from the internal clock generation circuit is supplied to the prescaler 21 and the timer circuit 5. Sometimes it is passed.

The prescaler 21 divides the internal system clock (SCLK) by a division ratio selected from division ratios such as 1/2, 1/4, and 1/8, which are 1/2 ⁿ , for example. 1 external signal (DCLK) is output. Needless to say, the above-described frequency division ratio is merely an example, and an arbitrary frequency division ratio can be set. The DCLK output from the prescaler 21 can be said to be a circuit for generating a relatively fast clock from the internal system clock (SCLK), as shown by the example frequency division ratio 1/2 ⁿ . Which frequency division ratio to select is determined according to the designation by the user in the game machine application program or the set value from the program management area.
On the other hand, the timer circuit 5 set by the internal system clock (SCLK) is to based-out time-out signal, for example, 1/2 frequency-divided to the setting, and outputs a second external signal (ESCK). In general, the frequency divided from the output of the timer circuit 5 is targeted at a low frequency, so that the ESCK output from the timer 22 can be distinguished from the function of generating a clock slower than DCLK.

  FIG. 3 is a block configuration diagram of circuits and registers related to generation of DCLK and ESCK when FIG. 2 is mounted on an actual main chip. As described above, which frequency division ratio is specifically selected by the prescaler 21 depends on the value specified by the user in the game machine application program or the value read from the user's program management area as the DCLK setting register (DCKS). ).

  In the chip configuration shown in this block diagram, the first external signal (DCLK) and the chip select signal (XCS6) are switched and used by the select circuit 22 for the purpose of increasing the number of terminals. Similarly, the second external signal (ESLK) and the chip select signal (XCS5) are switched and used by the select circuit 23 and the frequency divider 25. For this switching, it is set which one is used in the program management area. Therefore, when the user program is started up, either the first external signal (DCLK) or the chip select signal (XCS6) or the second external signal (ESLK) is determined based on the value set in the program management area. Only one of the functions of the chip select signal (XCS5) can be used.

  According to the main chip of the present embodiment, the fact that the user has conventionally divided the internal system clock by a frequency divider or the like outside the main chip is indicated by the prescaler 21 and the timer circuit 5 mounted in the main chip. Each game machine development manufacturer does not need to implement a frequency divider. In addition, when a value for identifying a plurality of division ratios set in the program management area is specified, data indicating which one to select from the division ratios in the user program management area set in advance is Two bits are sufficient, and a store instruction or the like for setting an initial value in a certain register is unnecessary, which can contribute to reducing the burden on the user program.

  In addition, it is possible to supply a DCLK output to a user who wants to control a motor driver or the like with a clock having a relatively high frequency while supplying a clock having a relatively low frequency from the timer circuit. It became possible to realize the main chip with.

1 Main chip 2 CPU
3 Internal ROM
4 Built-in RAM
5 Timer circuit 6 Reset control circuit 10 External bus control circuit 11 Clock circuit 20 Frequency divider 21 Prescaler 22 Select circuit 23 Select circuit

Claims (3)

A computer chip for a gaming machine used for a gaming machine, at least,
CPU,
A clock generation circuit;
A prescaler that divides the internal system clock generated by the clock generation circuit, and divides the internal system clock by a division ratio selected from a plurality of divided clocks and outputs the divided external system clock as an external clock; With prescaler,
A timer circuit that divides the time-out signal by a predetermined division ratio and outputs it as an external clock ;
A plurality of external clocks including a first output signal from the prescaler with respect to a clock having a high frequency and a second output signal from the timer circuit with respect to a clock having a low frequency are supplied as external clocks of the computer chip for the gaming machine. Computer chips for gaming machines.   By specifying which division ratio to select in the gaming machine application program executed in the gaming machine, or by specifying a value that identifies a plurality of division ratios set in the program management area, The computer chip for gaming machines according to claim 1, wherein the prescaler outputs a divided clock corresponding to a designated value.   3. The gaming machine according to claim 1, further comprising a select circuit that switches to use one of the first external signal or the second external signal and the chip select signal from the address decode circuit. Computer chip.

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