JP6271931B2 - Wireless receiver - Google Patents

Description

  The present invention relates to a radio reception apparatus that receives a signal encoded by differential space-time block coding, and more particularly to a radio reception apparatus that establishes block synchronization prior to decoding of a signal encoded by differential space-time block coding.

  There is differential space time block coding (DSTBC) as one of wireless signal transmission systems (see, for example, Non-Patent Document 1).

  In addition, in a conventional radio receiving apparatus, a known sequence (preamble pattern) included in a transmission signal is received, and synchronization of the received signal is established based on the known sequence (for example, Patent Document 1 and Non-Patent Documents). Reference 2).

JP 2009-303086 A

Chan-Soo Hwang, Seung Hoon Nam, Jaehak Chung, and Vahid Tarokh, “Differential Space Time Block Codes Using Nonconstant Modulus Constellations”, IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL.51, NO.11, NOVEMBER 2003, p.2955-2964 Satoshi Takanashi, Satoshi Aikawa, Yasuhisa Nakamura, “Removal of Regenerative Carrier Phase Uncertainty in Coded Modulation”, IEICE Transactions, B-II, Vol. J75-B-II, no. 12, 1992, pp. 896-905

  Conventionally, when a signal received by differential space-time block coding is received by a wireless receiver, timing (a timing at which information is placed on a transmission signal) is detected from a known sequence, and the received signal is synchronized with the detected timing. . Therefore, there is a problem that synchronization cannot be achieved until a known sequence is received.

  Further, in an environment where the transmission path fluctuates at a high speed and the situation where synchronization cannot be achieved frequently, resynchronization cannot be performed until a known sequence is received, resulting in a problem that communication performance is significantly reduced.

  The present invention has been made to solve these problems, and an object of the present invention is to provide a radio receiving apparatus capable of suppressing a decrease in communication performance.

  In order to solve the above-described problem, a wireless reception device according to the present invention is a wireless reception device that receives a signal encoded by differential space-time block encoding, and demodulates each received signal at different timings. Calculated by a demodulator that generates a demodulated signal, an error calculator that calculates an error between each demodulated signal demodulated by the demodulator, and a known signal on the transmission side estimated from the demodulated signal, and an error calculator A selecting unit that selects a demodulated signal having the smallest error among the errors.

  According to the present invention, a radio receiving apparatus that receives a signal encoded by differential space-time block coding, a demodulator that demodulates each signal received at different timings to generate a demodulated signal, and a demodulator An error calculating unit that calculates an error between each demodulated signal demodulated in this way and a known signal on the transmission side estimated from the demodulated signal, and a demodulator with the smallest error among the errors calculated by the error calculating unit Since a selection unit that selects a signal is provided, it is possible to suppress a decrease in communication performance.

It is a block diagram which shows an example of a structure of the radio | wireless receiving apparatus by Embodiment 1 of this invention. It is a figure which shows an example of the demodulation result of the demodulation part at the time of demodulating with the correct demodulation block timing by Embodiment 1 of this invention. It is a figure which shows an example of the demodulation result of the demodulation part in the case of demodulating with the incorrect demodulation block timing by Embodiment 1 of this invention. It is a block diagram which shows an example of a structure of the error calculation part by Embodiment 2 of this invention. It is a block diagram which shows an example of a structure of the error calculation part by Embodiment 3 of this invention. It is a block diagram which shows an example of a structure of the radio | wireless receiving apparatus by Embodiment 4 of this invention. It is a figure for demonstrating a DSTBC signal and a demodulation block timing. It is a block diagram which shows an example of a structure of the radio | wireless receiver by a premise technique.

  Embodiments of the present invention will be described below with reference to the drawings.

<Prerequisite technology>
First, a technique (a prerequisite technique) which is a premise of the present invention will be described.

  FIG. 7 is a diagram for explaining a differential space-time block coded signal (hereinafter referred to as a DSTBC signal) and a block timing at the time of demodulation.

  As shown in FIG. 7, the DSTBC signal includes data (symbols) subjected to differential space-time block coding. For example, data A0, A1, B0,..., F1, G0, G1 Contains.

  Further, the DSTBC signal is composed of two symbols as one block. For example, data A0 and data A1 are one block,..., Data G0 and data G1 are one block.

  When the DSTBC signal having the above configuration is received by the wireless receiver, if the data A0 and data A1 are recognized as one block,..., The data G0 and data G1 are recognized as one block, the correct demodulation block timing is obtained. Correct data can be obtained from the signal. On the other hand, when data A1 and data B0 are recognized as one block,..., Data F1 and data G0 are recognized as one block, the demodulation block timing is incorrect, and correct data cannot be obtained from the received signal. Here, the demodulation block timing refers to timing for performing subsequent demodulation processing.

  FIG. 8 is a block diagram illustrating an example of a configuration of a wireless reception device according to the base technology.

  As shown in FIG. 8, the wireless reception device according to the base technology includes an input terminal 39, a timing detection unit 40, a timing setting unit 41, a demodulation unit 42, and an output terminal 43.

  A reception signal received by the wireless reception device is input to each of the timing detection unit 40 and the timing setting unit 41 via the input terminal 39.

  The timing detection unit 40 detects a known sequence (preamble pattern) included in the received signal, and outputs the detected known sequence to the timing setting unit 41.

  The timing setting unit 41 sets the correct timing based on the known series input from the timing detection unit 40. At this time, when the received signal is a signal subjected to differential space-time block coding, a correct demodulation block timing as shown in the middle stage of FIG. 7 is set.

  The demodulator 42 performs demodulation processing according to the demodulation block timing set by the timing setting unit 41, and outputs a demodulated signal (hereinafter referred to as a demodulated signal) from the output terminal 43.

  As described above, the above-described conventional radio receiving apparatus has a problem that the received signal cannot be synchronized until a known sequence is received. Further, in an environment where the transmission path fluctuates at a high speed and the situation where synchronization cannot be achieved frequently, resynchronization cannot be performed until a known sequence is received, resulting in a problem that communication performance is significantly reduced.

  The present invention has been made to solve these problems, and will be described in detail below.

<Embodiment 1>
FIG. 1 is a block diagram showing an example of a configuration of a radio reception apparatus according to Embodiment 1 of the present invention.

  As shown in FIG. 1, the radio reception apparatus according to the first embodiment receives a signal (DSTBC signal) encoded by differential space-time block coding, and has an input terminal 1, a delay unit 2, and a demodulation unit. 3, a demodulator 4, an error calculator 5, an error calculator 6, and a selector 7.

  In the first embodiment, a case where the DSTBC signal is configured with two symbols as one block will be described as an example. However, the present invention is applicable even when two symbols or more are configured as one block.

  The DSTBC signal received by the wireless reception device is input to each of the delay unit 2 and the demodulation unit 3 via the input terminal 1.

  The delay unit 2 delays the DSTBC signal input via the input terminal 1 by one symbol, and outputs the delayed DSTBC signal to the demodulation unit 4.

  The demodulator 3 performs demodulation processing on the DSTBC signal input via the input terminal 1 to generate a demodulated signal, and outputs the generated demodulated signal to each of the error calculator 5 and the selector 7.

  The demodulator 4 performs a demodulation process on the DSTBC signal delayed by one symbol input from the delay unit 2 to generate a demodulated signal, and the generated demodulated signal is sent to each of the error calculator 6 and the selector 7. Output.

  As described above, the demodulation units 3 and 4 demodulate each DSTBC signal received at different timings to generate a demodulated signal.

  Here, the demodulation processing in the demodulation units 3 and 4 will be described.

  FIG. 2 is a diagram illustrating an example of a demodulation result (demodulation processing result) of the demodulation units 3 and 4 when demodulated at a correct demodulation block timing. FIG. 3 is a diagram illustrating an example of a demodulation result of the demodulation units 3 and 4 when demodulating at an incorrect demodulation block timing.

  2 and 3, the horizontal axis indicates Ich (in-phase axis), and the vertical axis indicates Qch (orthogonal axis). Further, black dots (reception signal points) in the figure indicate demodulation results in the demodulation units 3 and 4. The received signal (DSTBC signal) is a signal that is modulated and transmitted by the QPSK (Quadrature Phase Shift Keying) method on the transmission side.

  As shown in FIGS. 2 and 3, reception signal points are observed around the QPSK constellation in the demodulation result shown in FIG. 2 rather than the demodulation result shown in FIG. 3, and a correct demodulation result is obtained. I understand that.

  Returning to FIG. 1, the error calculator 5 calculates an error between the demodulated signal input from the demodulator 3 and the known signal on the transmission side estimated from the demodulated signal, and outputs the calculated error to the selector 7. To do. Similarly, the error calculator 6 calculates an error between the demodulated signal input from the demodulator 4 and the known signal on the transmission side estimated from the demodulated signal, and outputs the calculated error to the selector 7.

  The selection unit 7 compares the errors input from the error calculation units 5 and 6, selects the demodulated signal with the smaller error (the error is minimum), and outputs it to the output terminal 8.

  Specifically, when the error calculated by the error calculator 5 is smaller than the error calculated by the error calculator 6, the selector 7 selects the demodulated signal demodulated by the demodulator 3. Output to the output terminal 8. On the other hand, when the error calculated by the error calculator 6 is smaller than the error calculated by the error calculator 5, the selector 7 selects the demodulated signal demodulated by the demodulator 4 and outputs the output terminal 8. Output to.

  The demodulated signal output to the output terminal 8 is subjected to arbitrary signal processing such as decoding processing.

  From the above, according to the first embodiment, it is possible to select a correct demodulation block timing without receiving a signal including a known sequence as in the prior art (that is, the detection accuracy of the demodulation block timing is conventionally improved). Therefore, the received signal can be synchronized at high speed. Accordingly, it is possible to suppress a decrease in communication performance.

<Embodiment 2>
The second embodiment of the present invention is characterized by the configuration of the error calculation units 5 and 6 in the first embodiment (see FIG. 1). Other configurations are the same as those in the first embodiment, and thus description thereof is omitted here.

  FIG. 4 is a block diagram illustrating an example of the configuration of the error calculation units 5 and 6 according to the second embodiment. In the following, the error calculation unit 5 will be described as a representative, but the same applies to the error calculation unit 6.

  As shown in FIG. 4, the error calculation unit 5 according to the second embodiment includes an input terminal 9, a complex estimation unit 10, a complex modulation unit 11, a complex error calculation unit 12, an average value calculation unit 13, And an output terminal 14.

  The demodulated signal output from the demodulator 3 is input to each of the complex estimator 10 and the complex error calculator 12 via the input terminal 9.

  Based on the demodulated signal generated by the demodulator 3, the complex estimator 10 estimates an estimated value of the complex component included in the transmission signal when the DSTBC signal is transmitted from the transmission side. The estimated value is output to the complex modulation unit 11.

  The complex modulation unit 11 inversely modulates the estimated value of the complex component estimated by the complex estimation unit 10 to generate an inverse modulation signal, and outputs the generated inverse modulation signal to the complex error calculation unit 12.

  The complex error calculation unit 12 includes a complex component of the inverse modulation signal generated by the complex modulation unit 11 and a complex component of the demodulation signal input via the input terminal 9 (that is, generated by the demodulation unit 3). And the error of the calculated complex component is output to the average value calculation unit 13. Here, the error of the complex component includes, for example, a square error on the complex plane or the sum of the absolute value of the real part error and the absolute value of the imaginary part error.

  The average value calculation unit 13 calculates the average value of errors of the complex components calculated by the complex error calculation unit 12 as an error average value, and outputs the calculated error average value to the selection unit 7 via the output terminal 14. To do.

  From the above, according to the second embodiment, in addition to the effect of the first embodiment, the error is calculated based on the complex component, so that a more accurate error can be calculated.

<Embodiment 3>
Unlike the second embodiment, the third embodiment of the present invention is characterized in the configuration of the error calculation units 5 and 6 in the first embodiment (see FIG. 1). Other configurations are the same as those in the first embodiment, and thus description thereof is omitted here.

  FIG. 5 is a block diagram illustrating an example of the configuration of the error calculation units 5 and 6 according to the third embodiment. In the following, the error calculation unit 5 will be described as a representative, but the same applies to the error calculation unit 6.

  As shown in FIG. 5, the error calculation unit 5 according to the third embodiment includes an input terminal 15, a phase calculation unit 16, a phase estimation unit 17, a phase error calculation unit 18, an average value calculation unit 19, and And an output terminal 20.

  The demodulated signal output from the demodulator 3 is input to the phase calculator 16 via the input terminal 15.

  The phase calculator 16 calculates the phase of the demodulated signal generated by the demodulator 3 and outputs the calculated phase of the demodulated signal to each of the phase estimator 17 and the phase error calculator 18.

  The phase estimation unit 17 estimates the phase of the transmission signal when the DSTBC signal is transmitted from the transmission side based on the phase of the demodulated signal calculated by the phase calculation unit 16, and sets the phase of the estimated transmission signal to the phase. The result is output to the error calculation unit 18.

  The phase error calculation unit 18 calculates an error between the phase of the demodulated signal calculated by the phase calculation unit 16 and the phase of the transmission signal estimated by the phase estimation unit 17, and calculates the average error of the calculated phase. It outputs to the calculation part 19. Here, examples of the phase error include a square error or an absolute value.

  The average value calculation unit 19 calculates the average value of the phase error calculated by the phase error calculation unit 18 as an error average value, and outputs the calculated error average value to the selection unit 7 via the output terminal 20. .

  From the above, according to the third embodiment, since the error is calculated based on the phase in addition to the effect of the first embodiment, the circuit scale can be reduced.

<Embodiment 4>
In the first embodiment, the radio reception apparatus assuming single antenna reception (that is, one input) has been described. In the fourth embodiment of the present invention, a radio receiving apparatus assuming multi-antenna reception (that is, multi-input) will be described.

  FIG. 6 is a block diagram showing an example of the configuration of the wireless reception apparatus according to the fourth embodiment.

  As shown in FIG. 6, the radio reception apparatus according to the fourth embodiment includes an input terminal 21, a delay unit 22, demodulation units 23 and 24, error calculation units 25 and 26, an input terminal 27, and a delay unit. 28, demodulation units 29 and 30, error calculation units 31 and 32, error synthesis units 33 and 34, demodulated signal synthesis units 35 and 36, a selection unit 37, and an output terminal 38.

  The delay units 22 and 28 correspond to the delay unit 2 in FIG. Further, the demodulation units 23, 24, 29, and 30 correspond to the demodulation units 3 and 4 in FIG. Moreover, the error calculation units 25, 26, 31, and 32 correspond to the error calculation units 5 and 6 in FIG. Therefore, in the following, description of the delay units 22 and 28, the demodulation units 23, 24, 29, and 30 and the error calculation units 25, 26, 31, and 32 is omitted.

  The input terminal 21 and the input terminal 27 are connected to different receiving antennas. In the fourth embodiment, two inputs will be described as an example, but the present invention can be applied even when there are three or more inputs. That is, the demodulation units 23 and 24 and the error calculation units 25 and 26 (or the demodulation units 29 and 30 and the error calculation units 31 and 32) are arranged corresponding to each of the plurality of reception antennas that receive the DSTBC signal. Yes.

  The error combining unit 33 combines the error calculated by the error calculating unit 25 and the error calculated by the error calculating unit 31, and outputs the combined error to the selecting unit 37.

  The error combiner 34 combines the error calculated by the error calculator 26 and the error calculated by the error calculator 32, and outputs the combined error to the selector 37.

  The demodulated signal synthesizer 35 synthesizes the demodulated signal demodulated by the demodulator 23 and the demodulated signal demodulated by the demodulator 29 to generate a composite demodulated signal. Output to.

  The demodulated signal combining unit 36 combines the demodulated signal demodulated by the demodulating unit 24 and the demodulated signal demodulated by the demodulating unit 30 to generate a combined demodulated signal, and selects the generated combined demodulated signal as the selecting unit 37. Output to.

  The selection unit 37 compares the errors input from the error calculation unit 25, the error calculation unit 26, the error calculation unit 31, the error calculation unit 32, the error synthesis unit 33, and the error synthesis unit 34, and the error is the smallest. The demodulated signal or the combined demodulated signal is selected and output to the output terminal 38.

  Specifically, for example, when the error calculated by the error calculation unit 25 is the minimum, the selection unit 37 selects the demodulated signal demodulated by the demodulation unit 23 and outputs it to the output terminal 38. When the error synthesized by the error synthesizer 34 is minimum, the selector 37 selects the synthesized demodulated signal synthesized by the demodulated signal synthesizer 36 and outputs it to the output terminal 38.

  The combining method in each of the error combining units 33 and 34 and the demodulated signal combining units 35 and 36 may employ a maximum ratio combining type, or may perform weighted combining based on the reception quality situation. There is no particular limitation.

  In addition, in order to reduce the circuit scale in the wireless reception device, the same component is not provided separately, but is provided as a single component, and the processing is executed a plurality of times by the single component. Good.

  In a moving environment (in which the transmission path fluctuates due to movement of the wireless transmission device or wireless reception device) when interference from the same wave or interference waves from other systems are mixed in the received signal It is known that the signal power to interference power ratio (Signal-to-Interference Ratio: hereinafter referred to as SIR) in each receiving antenna may be different.

  Under such a moving environment, when the error synthesizers 33 and 34 of the fourth embodiment synthesize errors, the calculation result of the error relating to the received signal received from the receiving antenna in which the SIR is degraded is the SIR. Since it affects the calculation result of errors related to the received signal received from a good receiving antenna, the correct demodulation block timing cannot be selected even if errors are combined (that is, the detection accuracy of the demodulation block timing can be improved). A problem arises in that the communication performance deteriorates.

  On the other hand, in the fourth embodiment, not only the error synthesis results by the error synthesis units 33 and 34 but also the error calculation result itself regarding the received signal received from each receiving antenna is input to the selection unit 37. Therefore, the selection unit 37 is not affected by the error related to the reception signal received from the reception antenna having a deteriorated SIR, and correct demodulation based on the calculation result of the error related to the reception signal received from the reception antenna having a good SIR. Block timing can be selected. As described above, according to the fourth embodiment, it is possible to improve the resistance to interference waves and to select the correct demodulation block timing (that is, the detection accuracy of the demodulation block timing can be improved as compared with the conventional case). ).

  1, 4, 5, 6, delay units 2, 22, 28, demodulation units 3, 4, 23, 24, 29, 30, error calculation units 5, 6, 25, 26, 31, 32, selection 7, 37, complex estimation unit 10, complex modulation unit 11, complex error calculation unit 12, average value calculation units 13, 19, phase calculation unit 16, phase estimation unit 17, phase error calculation unit 18, error synthesis unit 33, 34. Each of the demodulated signal synthesizers 35 and 36 may be configured as hardware (for example, an arithmetic / processing circuit configured to perform a specific calculation or process on an electric signal). At this time, a plurality of circuits having similar functions may be configured as a single circuit. 1, 4, 5, 6, delay units 2, 22, 28, demodulation units 3, 4, 23, 24, 29, 30, error calculation units 5, 6, 25, 26, 31, 32, selection 7, 37, complex estimation unit 10, complex modulation unit 11, complex error calculation unit 12, average value calculation units 13, 19, phase calculation unit 16, phase estimation unit 17, phase error calculation unit 18, error synthesis unit 33, 34. Each of the demodulated signal synthesizers 35 and 36 may be realized by executing program processing using a CPU (Central Processing Unit) based on software. Further, both of the above may be mixed.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

  1 input terminal, 2 delay unit, 3 demodulation unit, 4 demodulation unit, 5 error calculation unit, 6 error calculation unit, 7 selection unit, 8 output terminal, 9 input terminal, 10 complex estimation unit, 11 complex modulation unit, 12 complex Error calculation unit, 13 Average value calculation unit, 14 Output terminal, 15 Input terminal, 16 Phase calculation unit, 17 Phase estimation unit, 18 Phase error calculation unit, 19 Average value calculation unit, 20 Output terminal, 21 Input terminal, 22 Delay , 23 demodulator, 24 demodulator, 25 error calculator, 26 error calculator, 27 input terminal, 28 delay unit, 29 demodulator, 30 demodulator, 31 error calculator, 32 error calculator, 33 error synthesizer , 34 Error synthesis unit, 35 Demodulated signal synthesis unit, 36 Demodulation signal synthesis unit, 37 Selection unit, 38 Output terminal, 39 Input terminal, 40 Timing detection unit, 41 Timing setting unit, 42 Tone portion, 43 an output terminal.

Claims (4)

A radio receiving apparatus for receiving a signal encoded by differential space-time block encoding,
A demodulator that demodulates each signal received at different timings to generate a demodulated signal;
An error calculator that calculates an error between each demodulated signal demodulated by the demodulator and a known signal on the transmission side estimated from the demodulated signal;
A selection unit that selects the demodulated signal having the minimum error among the errors calculated by the error calculation unit;
A wireless receiving device. The error calculator is
A complex estimation unit that estimates an estimated value of a complex component included in a transmission signal when the signal is transmitted based on the demodulated signal generated by the demodulation unit;
A complex modulation unit that demodulates the estimated value estimated by the complex estimation unit to generate a demodulated signal;
A complex error calculation unit that calculates an error between the complex component of the inverse modulation signal generated by the complex modulation unit and the complex component of the demodulation signal generated by the demodulation unit;
The wireless receiver according to claim 1, comprising: The error calculator is
A phase calculator that calculates the phase of the demodulated signal generated by the demodulator;
A phase estimation unit that estimates a phase of a transmission signal when the signal is transmitted based on the phase calculated by the phase calculation unit;
A phase error calculation unit that calculates an error between the phase of the demodulated signal calculated by the phase calculation unit and the phase of the transmission signal estimated by the phase estimation unit;
The wireless receiver according to claim 1, comprising: The demodulator and the error calculator are arranged corresponding to each of a plurality of receiving antennas that receive the signal,
A demodulated signal combining unit that combines the demodulated signals generated by the demodulating units for the signals received at the same timing to generate a combined demodulated signal;
An error synthesis unit that synthesizes each of the errors calculated by the error calculation unit for each of the signals received at the same timing;
Further comprising
The selecting unit selects the demodulated signal or the combined demodulated signal having the minimum error among the errors calculated by the error calculating unit and the errors combined by the error combining unit. The wireless reception device according to claim 1, wherein the wireless reception device is a wireless communication device.

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