JP6263068B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device.

  Patent Document 1 below discloses a memory system that includes a nonvolatile memory such as a NAND flash memory and a controller that controls the nonvolatile memory. The nonvolatile memory has a user data block in which user data is stored and a management block in which management information is stored.

  The controller sequentially writes data to a plurality of management pages in the management block. If a power interruption occurs while data is being written, the controller, when the next power is turned on, among the management pages in the management block, the management page (hereinafter “ Identify the final management page. Then, it is determined whether or not the next management page (hereinafter referred to as “next page”) continuous to the final management page is in the erased state (that is, all “1”). Data is written to a later management page and the next page is invalidated. If the next page is in the erased state, data is written to the next page, and then data is read from the next page. Whether the read data matches the expected value (that is, the updated management information). Verify that. If the read data does not match the expected value as a result of the verification, the data is written to the management page after the next page and the next page is invalidated.

Japanese Patent No. 5142585

  As described above, according to the memory system disclosed in Patent Document 1, when the next page of the final management page is in an erased state, data is written to the next page, and then data is read from the next page. Thus, verifying whether the read data matches the expected value is performed.

  Accordingly, a holding circuit for holding the expected value and a comparison circuit for comparing the read data with the expected value are required, and the circuit scale of the entire system increases. In addition, since the two-step process of determining whether or not the next page is in the erased state and verifying whether or not the read data matches the expected value is performed and the processing contents are complicated, The required time increases. In addition, it is generally necessary to hold an expected value in order to perform verification, but the amount of user data is enormous compared to management information, and the expected value for all user data is held. That is not realistic. Therefore, it is considered that the application target of the memory system disclosed in Patent Document 1 is limited to the management block.

  The present invention has been made to solve such a problem, and obtains a semiconductor memory device that can reduce the circuit scale and the time required for start-up processing and can be applied not only to a management block but also to an arbitrary block. It is for the purpose.

  A semiconductor storage device according to a first aspect of the present invention includes a storage unit having a block including a plurality of pages that are data write units, and a control unit that controls the storage unit, wherein the control unit includes: At the time of data writing, write data and address information for specifying the next write target page of the write target page are written to the write target page. The first page, which is the last page for which data writing has been completed, is specified, and the second page, which is the next page to be written, is specified based on the address information written to the first page. The second page is invalidated, and data is written to the third page, which is the page to be written after the second page.

  According to the semiconductor memory device of the first aspect, the control unit identifies the first page that is the last page for which data writing has been completed among all the pages in the block at the time of power activation, and writes the first page to the first page Based on the stored address information, the second page that is the next writing target page of the first page is specified, the second page is invalidated, and the third writing page that is the writing target page after the second page Write data to the page. In this way, the second page that may be an incomplete page due to power interruption during data writing is always invalidated, and the second page to be written after the second page. By resuming data writing from page 3, verification of whether the second page is an incompletely written page or a completely erased page becomes unnecessary. As a result, since the process of comparing the read data and the expected value for verification can be omitted, it is possible to reduce the circuit scale and the time required for the startup process for the entire apparatus. Further, since it is not necessary to hold an expected value for verification, the present invention can be applied not only to the management block but also to an arbitrary block such as a user data block. Further, at the time of data writing, the control unit writes write data and address information designating the next write target page of the write target page to the write target page. In this way, by adding address information to the write data at the time of data writing and referring to the address information at the time of power-on, the control unit may be an incompletely written page. It becomes possible to specify a page easily.

  The semiconductor memory device according to the second aspect of the present invention is the semiconductor memory device according to the first aspect, in particular, the control unit is updated for each page with respect to the write target page during data writing. The time information is further written, and the page where the latest time information is written among all the pages in the block is specified as the first page when the power is turned on.

  According to the semiconductor memory device of the second aspect, the control unit writes the time-dependent information updated for each page to the page to be written at the time of data writing, and all pages in the block at the time of power activation. The page in which the latest time-lapse information is written is identified as the first page. In this way, by adding the time-lapse information to the write data at the time of data writing and referring to the time-lapse information at the time of power-on, the control unit can simplify the first page, which is the last page for which data writing has been completed. It becomes possible to specify.

  The semiconductor memory device according to a third aspect of the present invention is the semiconductor memory device according to the first aspect, in particular, the control unit performs a page search that traces address information from a predetermined starting page when power is turned on. The last page in which address information is written is specified as the first page.

  According to the semiconductor memory device of the third aspect, the control unit performs a page search that traces the address information from a predetermined starting page when the power is turned on, so that the last page in which the address information is written is the first page. Identifies as a page. In this way, the address information is added to the write data at the time of data writing, and by performing a page search that follows the address information at the time of power activation, the control unit is the first page that is the last page for which data writing has been completed. It becomes possible to specify a page easily.

  The semiconductor memory device according to the fourth aspect of the present invention is the semiconductor memory device according to any one of the first to third aspects, and the address information includes a block address and a page address. Is.

  According to the semiconductor memory device of the fourth aspect, the address information includes a block address and a page address. Therefore, not only when data is written sequentially to a plurality of pages having consecutive physical addresses, but also when data is randomly written to a plurality of pages where physical addresses of blocks or pages are not consecutive. However, the present invention can be applied.

  The semiconductor memory device according to the fifth aspect of the present invention is particularly the semiconductor memory device according to any one of the first to fourth aspects, wherein the control unit executes garbage collection at a predetermined timing. The data in the erased state is written to the page invalidated as the second page.

  According to the semiconductor memory device of the fifth aspect, the control unit writes the erased data to the page invalidated as the second page by executing garbage collection at a predetermined timing. As a result, since the second page can be reused after the garbage collection is performed, it is possible to avoid a reduction in the number of pages that can be used due to the accumulation of the second page.

  According to the present invention, it is possible to obtain a semiconductor memory device that can reduce the circuit scale and the time required for startup processing and can be applied not only to a management block but also to an arbitrary block.

1 is a diagram showing a simplified overall configuration of a semiconductor memory device according to a first embodiment of the present invention. It is a figure which shows the data written in a memory array from a memory controller. It is a figure which shows the outline | summary of the starting process which a control part performs. It is a flowchart which shows concretely the flow of the starting process which a control part performs. FIG. 6 is a diagram schematically showing an overall configuration of a semiconductor memory device according to a second embodiment of the present invention. It is a figure which shows the data written in a memory array from a memory controller. It is a flowchart which shows concretely the flow of the starting process which a control part performs.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the element which attached | subjected the same code | symbol in different drawing shall show the same or corresponding element.

<Embodiment 1>
FIG. 1 is a diagram showing a simplified overall configuration of a semiconductor memory device according to Embodiment 1 of the present invention. As shown in the connection relationship of FIG. 1, the semiconductor memory device includes a memory array 2 using a nonvolatile memory such as a NAND flash memory, and a control unit 1 that controls access to the memory array 2. Yes.

  The control unit 1 includes a memory controller 11, a determination circuit 12, an ECC circuit 13, and a random number generator 14. The memory controller 11 has an NA register 21, a TS register 22, and a counter 23 therein.

  The memory array 2 has a plurality of blocks which are data erasing units. The blocks include a management block that stores management information and a user data block that stores user data. Each block is composed of a plurality of pages which are data write units and data read units.

  The memory controller 11 receives an access request to the memory array 2 from an external host device. When a write request is input, the memory controller 11 writes the write data included in the write request to the specified page of the specified block.

  FIG. 2 is a diagram illustrating data written from the memory controller 11 to the memory array 2. The memory controller 11 writes data in which the next address NA and the time stamp TS are added to the end of the write data in the memory array 2. As for the write data, a plurality of sets of user data (or management information) of a predetermined byte (for example, 1024 bytes) and ECC syndrome of a predetermined byte (for example, 42 bytes) related to the user data (or management information) are repeated. Data structure.

  When writing data across a plurality of pages in the same or different blocks, the memory controller 11 manages the physical addresses of a plurality of pages to be written and the order of writing to the plurality of pages. When writing data to a certain write target page, the memory controller 11 sets next address information for specifying the next write target page of the write target page at the end of the write data to be written to the write target page. It is added as an address NA. The next address NA includes a physical block address of a predetermined byte (for example, 2 bytes) and a physical page address of a predetermined byte (for example, 1 byte).

  The memory controller 11 increments the counter value of the counter 23 every time data writing to the write target page is completed. The counter 23 is a cyclic counter that outputs a counter value of a predetermined byte (for example, 3 bytes) as time-lapse information. When writing data to a certain write target page, the memory controller 11 adds the counter value of the counter 23 at that time as a time stamp TS to the end of the write data to be written to the write target page.

  Hereinafter, a startup process executed by the control unit 1 when the semiconductor memory device is powered on will be described.

  In a non-volatile memory using a NAND flash memory, if a power interruption occurs while data is being written to the memory array, when data is written to an incomplete page after restarting, In spite of data being written, an unwritten page may appear as an erased page (ALL FFh). If data is written to an incompletely written page after restarting after determining the erase state, the data may not be correctly written to the page, and the written data may be damaged or lost, thereby reducing the reliability of the data. .

  Therefore, in order to improve the reliability of data by avoiding the use of pages that may be incompletely written pages, the control unit 1 starts up as follows when the semiconductor memory device is turned on. Execute the process.

  FIG. 3 is a diagram illustrating an outline of the startup process executed by the control unit 1. Here, it is assumed that data writing is performed in the order of pages P0 → P1 → P2 → P3 → P4 → P5. The memory controller 11 manages the physical addresses of pages P0 to P5 to be written and the order of writing to pages P0 to P5. Pages P0 to P5 may be pages in the same block or pages in different blocks. Further, the physical page addresses do not necessarily have to be continuous.

  In this example, the page P3 is a page that has not been written due to the occurrence of power interruption during the data writing to the page P3. In addition, since the data writing to the pages P0 to P2 is completed, the next address NA and the time stamp TS are written to these pages P0 to P2. For example, the page P0 is written with the next address NA for designating the physical address of the page P1 and the time stamp TS at the time of data writing to the page P0. The page P1 has the physical address of the page P2. Is written, and a time stamp TS at the time of data writing to the page P1 is written. On the other hand, since the pages P4 and P5 to which data has not been written are in an erased state, neither the next address NA nor the time stamp TS is written. In addition, the page P3 which is an unfinished page seems to have neither the next address NA nor the time stamp TS written in the same manner as in the erased state.

  When the semiconductor memory device is restarted, the control unit 1 first identifies the last page for which data writing has been completed among all the pages in the block. Specifically, among all the pages in which the time stamp TS is written, the page having the maximum value of the time stamp TS (that is, the page in which the latest time-lapse information is written) is designated as the final write completion page. As specified. In this example, page P2 is specified as the last write completion page.

  Next, the control unit 1 specifies the next writing target page after the last writing completion page based on the next address NA written in the last writing completion page. In this example, since the physical address of the page P3 is written in the page P2 as the next address NA, the page P3 is specified as the page to be written next to the final write completion page.

  Next, the control unit 1 generates invalid data using the random number output from the random number generator 14, and writes the invalid data to the page to be written next to the last write completion page. As a result, the page to be written next to the last write completion page is invalidated. In this example, page P3 is invalidated. Then, the control unit 1 resumes data writing from the write target page next to the invalidated page. In this example, data writing is resumed from page P4. That is, data that should originally be written to page P3 is written to page P4.

  Instead of generating invalid data using random numbers, for example, invalid data of ALL 00h may be used.

  Further, the number of pages to be invalidated is not limited to one page, and a plurality of pages after the last write completion page may be invalidated. For example, in the case of SLC, the next page after the last write completion page is invalidated, and in the case of MLC, the next page after the last write completion page and one page physically continuous to the page (2 in total) Page) and disable. Further, in the case of MLC, a page to be written next to the last write completion page (that is, a page that may be a write incomplete page) is decoded, and the page is a lower page. If this is the case, the next page after the last write completion page is invalidated, and if it is an upper page, the next page after the last write completion page and 3 or 5 that is physically continuous with the page Invalidate pages (4 or 6 pages in total).

  FIG. 4 is a flowchart specifically showing the flow of the startup process executed by the control unit 1. In step S101, a list of currently used blocks is read from the management block, and block conditions such as the number of blocks and the physical block address of each block are set. In steps S102 to S113, the block loop is repeated while incrementing the block number until processing is performed for all blocks. In step S103, page conditions such as the number of pages in one block are set. In step S104, initial values of the NA register 21 and the TS register 22 are set. For example, “0xFFFFFF” is set as the initial value of the NA register 21, and “0” is set as the initial value of the TS register 22, for example. In steps S105 to S110, the page loop is repeated while the page number is decremented until processing is performed for all pages. In step S106, all data written in the target page is read from the memory array 2. Read data of the target page is input to the memory controller 11, the determination circuit 12, and the ECC circuit 13. In step S107, the determination circuit 12 determines whether or not the read data is in the complete erase state (ALL FFh). Even if not in the completely erased state, if the number of bits of “0” included in the read data is less than a predetermined value, it may be determined to be in the erased state. If the determination result of step S107 is “No”, the ECC circuit 13 determines whether or not an ECC failure has occurred in the read data in step S108. If the determination result in step S108 is “No”, the time stamp TS (hereinafter “tmp TS”) and the next address NA (hereinafter “tmp NA”) included in the read data are acquired in step S109. The In step S111, it is determined whether or not the current value of the TS register 22 is less than tmp TS. If the determination result in step S111 is “Yes”, in step S112, the current value of the TS register 22 is updated to the value of tmp TS, and the current value of the NA register 21 is updated to the value of tmp NA.

  If the determination result in step S107 is “Yes”, it is determined in step S115 whether the target page is the first page. When the determination result in step S115 is “Yes”, in step S116, the value of tmp TS is set to “0”, for example, and the value of tmp NA is set to “0xFFFFFF”, for example. If the determination result of step S108 is “Yes”, garbage collection is executed in step S117.

  With the above processing, the next write target page after the last write completion page (that is, a page that may be an incomplete write page) is set as the next address NA finally set in the NA register 21. The physical page address of is acquired. In step S114, the next write target page after the last write completion page is invalidated.

  As described above, according to the semiconductor memory device of the present embodiment, the control unit 1 specifies the last page (hereinafter referred to as “first page”) in which data writing has been completed among all the pages in the block at the time of power activation. To do. In addition, based on the address information written in the first page, the page to be written next to the first page (hereinafter “second page”) is specified. Further, the second page is invalidated, and data is written to a page to be written after the second page (hereinafter “third page”). In this way, the second page that may be an incomplete page due to power interruption during data writing is always invalidated, and the second page to be written after the second page. By resuming data writing from page 3, verification of whether the second page is an incompletely written page or a completely erased page becomes unnecessary. As a result, since the process of comparing the read data and the expected value for verification can be omitted, it is possible to reduce the circuit scale and the time required for the startup process for the entire apparatus. Further, since it is not necessary to hold an expected value for verification, the present invention can be applied not only to the management block but also to an arbitrary block such as a user data block. Furthermore, at the time of data writing, the control unit 1 writes write data and address information designating the next write target page of the write target page to the write target page. As described above, the address information is added to the write data at the time of data writing, and the control unit 1 may be an unwritten page by referring to the address information at the time of power activation. Two pages can be easily specified.

  Further, according to the semiconductor memory device of the present embodiment, the control unit 1 writes the time-dependent information updated for each page to the writing target page at the time of data writing, and the block 1 The page in which the latest time-dependent information is written is identified as the first page. In this way, by adding the time-lapse information to the write data at the time of data writing and referring to the time-lapse information at the time of power-on, the control unit 1 sets the first page that is the last page for which data writing has been completed. It becomes possible to specify easily.

  Further, according to the semiconductor memory device according to the present embodiment, the address information includes a block address and a page address. Therefore, not only when data is written sequentially to a plurality of pages having consecutive physical addresses, but also when data is randomly written to a plurality of pages where physical addresses of blocks or pages are not consecutive. However, the present invention can be applied.

<Embodiment 2>
Hereinafter, the semiconductor memory device according to the second embodiment of the present invention will be described focusing on the differences from the first embodiment.

  FIG. 5 is a diagram schematically showing the overall configuration of the semiconductor memory device according to the second embodiment of the present invention. Compared with the first embodiment, the TS register 22 and the counter 23 are omitted from the memory controller 11.

  FIG. 6 is a diagram showing data written from the memory controller 11 to the memory array 2. Compared to the first embodiment, the addition of the time stamp TS is omitted.

  The second embodiment is different from the first embodiment in the method of specifying the final write completion page.

  The outline of the activation process executed by the control unit 1 is the same as that in FIG. In the example of FIG. 3, page P3 is a page that has not been written due to the occurrence of power interruption during the data writing to page P3. Further, since the data writing to the pages P0 to P2 has been completed, the next address NA is written to these pages P0 to P2. For example, the next address NA that specifies the physical address of the page P1 is written in the page P0, and the next address NA that specifies the physical address of the page P2 is written in the page P1. On the other hand, since the pages P4 and P5 to which data has not been written are in the erased state, the next address NA is not written. Further, the page P3 that is an incompletely written page appears as if the next address NA is not written, as in the erased state.

  When the semiconductor memory device is restarted, the control unit 1 first identifies the last page for which data writing has been completed among all the pages in the block. Specifically, the last page in which the next address NA is written is specified as the last write completion page by performing a page search that traces the next address NA from a predetermined starting page. As the starting page, the page where data writing is first performed after the previous garbage collection is set as the starting page, and the physical address of the starting page is stored in the management block of the memory array 2. In the example of FIG. 3, the next page P1 is specified by the next address NA written in the page P0 that is the starting page, the next page P2 is specified by the next address NA written in the page P1, and the page P2 The next page P3 is specified by the next address NA written in. Since the next address NA is not written in the page P3, the last page in which the next address NA is written becomes the page P2, and as a result, the page P2 is specified as the final write completion page.

  The subsequent processing is the same as in the first embodiment. Next, the control unit 1 specifies the next writing target page after the last writing completion page based on the next address NA written in the last writing completion page.

  Next, the control unit 1 generates invalid data using the random number output from the random number generator 14, and writes the invalid data to the page to be written next to the last write completion page. As a result, the page to be written next to the last write completion page is invalidated. Then, the control unit 1 resumes data writing from the write target page next to the invalidated page.

  FIG. 7 is a flowchart specifically illustrating the flow of the startup process executed by the control unit 1. In step S201, management information is read from the management block of the memory array 2. In step S202, the physical address of the starting page (hereinafter “starting address”) is acquired from the management information. In step S203, the initial value of the NA register 21 is set. A starting address is set as an initial value of the NA register 21. In steps S204 to S210, the page loop is repeated while updating the page number until a page whose read data is in the completely erased state (ALL FFh) appears. In step S205, all data written in the target page is read from the memory array 2. In step S206, it is determined whether or not the read data is in a completely erased state (ALL FFh). If the determination result in step S206 is “No”, it is determined in step S207 whether or not an ECC failure has occurred in the read data. If the determination result of step S207 is “No”, the next address NA (tmp NA) included in the read data is acquired in step S208. In step S209, the current value of the NA register 21 is updated to the value of tmp NA. If the determination result in step S207 is “Yes”, garbage collection is executed in step S212.

  With the above processing, the next write target page after the last write completion page (that is, a page that may be an incomplete write page) is set as the next address NA finally set in the NA register 21. The physical page address of is acquired. In step S211, the next writing target page after the last writing completion page is invalidated.

  As described above, according to the semiconductor memory device according to the present embodiment, the control unit 1 performs a page search that traces address information from a predetermined starting page when power is turned on, so that the last page in which the address information is written. Is specified as the first page. As described above, the address information is added to the write data at the time of data writing, and by performing a page search that traces the address information at the time of power activation, the control unit 1 is the last page that has completed the data writing. One page can be easily specified.

<Modification>
The control unit 1 determines not only when an ECC failure has occurred in the read data within the startup process, but also at a predetermined timing other than the startup process (for example, when the counter value of the counter 23 reaches the maximum value during data writing). ) May perform garbage collection. By executing garbage collection, erased data is written to the invalidated pages accumulated so far. As a result, the invalidated pages can be reused after the garbage collection is executed, so that it is possible to avoid reducing the number of usable pages due to the accumulation of invalidated pages.

DESCRIPTION OF SYMBOLS 1 Control part 2 Memory array 11 Memory controller 12 Judgment circuit 13 ECC circuit

Claims (5)

A storage unit having a block including a plurality of pages as a unit of writing data;
A control unit for controlling the storage unit;
With
The controller is
At the time of data writing, write data and address information specifying the next write target page of the write target page are written to the write target page.
At power on,
Identify the first page of all pages in the block, the last page for which data writing has been completed,
Based on the address information written in the first page, the second page that is the next writing target page of the first page is specified,
A semiconductor memory device that invalidates a second page and writes data to a third page, which is a page to be written after the second page. The controller is
When data is written, the time-dependent information updated for each page is further written to the page to be written,
The semiconductor memory device according to claim 1, wherein a page in which the latest time-dependent information is written among all the pages in the block is specified as a first page when the power is turned on.   2. The semiconductor according to claim 1, wherein the control unit specifies a last page in which address information is written as a first page by performing a page search for tracing address information from a predetermined starting page when power is turned on. Storage device.   4. The semiconductor memory device according to claim 1, wherein the address information includes a block address and a page address. The said control part writes the data of an erasure | elimination with respect to the page invalidated as a 2nd page by performing a garbage collection at predetermined | prescribed timing. Semiconductor memory device.

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