JP6261300B2 - Photoelectric conversion device - Google Patents

Description

  The present invention relates to a photoelectric conversion device.

  There is a photoelectric conversion device (for example, a semiconductor image sensor) used in an image reading device such as a copying machine or a bill discriminator. The photoelectric conversion device includes a plurality of photoelectric conversion elements (pixels) that convert an optical image of an image reading target into an electric signal, and processes the electric signal generated by each pixel by an appropriate circuit, thereby detecting the position of the image reading target. Get information.

  For example, Patent Document 1 and Patent Document 2 disclose a photoelectric conversion device in which a plurality of pixels are arranged in a straight line in a semiconductor chip. The photoelectric conversion devices disclosed in Patent Document 1 and Patent Document 2 are provided with a common wiring in a semiconductor chip for commonly transmitting output signals from a plurality of pixels. Electrical signals generated by photoelectric conversion of a plurality of pixels at the same time are sequentially and exclusively output to a common wiring, and transmitted to a circuit commonly used among the plurality of pixels, such as an output amplifier.

JP 2001-245212 A JP 2005-268937 A

  However, since the common wiring is arranged so as to cross the semiconductor chip, the wiring capacity is large. In addition, the parasitic depletion layer capacitance generated in the output switch from each pixel to the common wiring is doubled by the number of pixels to apply a load to the common wiring. Therefore, in particular, when a large number of pixels are used to improve the resolution of the image reading device or increase the reading range, the parasitic capacitance associated with the common wiring increases, limiting the speeding up of the photoelectric conversion device. Was.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a photoelectric conversion device capable of high-speed operation.

In order to achieve the above object, a photoelectric conversion device according to the present invention includes a plurality of pixel circuits, a plurality of bit circuits, a plurality of common wirings, and a control circuit. The plurality of pixel circuits are arranged side by side in a predetermined direction, each including a photoelectric conversion element that photoelectrically converts incident light, and a reference signal that is not based on photoelectric conversion by the photoelectric conversion element and photoelectric conversion by the photoelectric conversion element sequentially outputs a photoelectric conversion signal that is generated based on. The plurality of bit circuit, a one-to-one correspondence to the plurality of pixel circuits, each of which a corresponding reference signal output from one pixel circuit and the photoelectric conversion signal of the plurality of pixel circuits sequentially The output signal obtained by receiving and amplifying the difference between the received reference signal and the photoelectric conversion signal is output. Each of the plurality of common wires transmits an output signal output from two or more bit circuits of the plurality of bit circuits, and the bit circuits that output the output signals transmitted by the plurality of common wires do not overlap. The control circuit controls the timing of each of the plurality of bit circuit outputs an output signal, each common wiring among the plurality of common lines, two or more to be outputted to the output signal respective common wiring is transmitted Output signals are output in the order in which two or more pixel circuits corresponding to the two or more bit circuits of the plurality of pixel circuits are arranged. Each of the pixel circuits includes a reset transistor that resets a signal in the pixel circuit, and outputs a reference signal when the signal in the pixel circuit is reset by the reset transistor.

  According to the present invention, since signals based on photoelectric conversion signals generated by a plurality of pixel circuits are transmitted by a plurality of common wirings, a photoelectric conversion device capable of high-speed operation can be provided.

It is a block diagram which shows the structure of the photoelectric conversion apparatus which concerns on Embodiment 1 of this invention. 2 is a configuration example of a pixel circuit included in a photoelectric conversion device. It is an example of a structure of the bit circuit with which a photoelectric conversion apparatus is provided. It is a timing chart which shows operation | movement of the photoelectric conversion apparatus which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the photoelectric conversion apparatus which concerns on Embodiment 2 of this invention. It is a timing chart which shows operation | movement of the photoelectric conversion apparatus which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the photoelectric conversion apparatus which concerns on Embodiment 3 of this invention.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the drawings, the same or equivalent parts are denoted by the same reference numerals.

Embodiment 1 FIG.
The photoelectric conversion device according to Embodiment 1 is configured as shown in FIG.

  The photoelectric conversion device 1 includes n pixel circuits PC1 to PCn arranged side by side in a predetermined direction, and n bit circuits BC1 corresponding to the n pixel circuits PC1 to PCn on a one-to-one basis. ˜BCn, common wiring COM1 and common wiring COM2 that transmit signals output from the n bit circuits BC1 to BCn, and amplification circuit AMP_COM1 and amplification circuit that amplify signals that transmit the common wiring COM1 and common wiring COM2, respectively. AMP_COM2, an output selection switch SW_COM1 and an output selection switch SW_COM2 for switching between transmission and interruption of signals amplified by the amplification circuit AMP_COM1 and the amplification circuit AMP_COM2, and an output amplification circuit OUTAMP for amplifying the signal for the external signal processing circuit 10 , External control signals to each part in the photoelectric conversion device 1 It comprises a control circuit 11 for generating the item.

  Each of the n pixel circuits PC1 to PCn includes a photoelectric conversion element that photoelectrically converts incident light, and generates a photoelectric conversion signal based on photoelectric conversion by the photoelectric conversion element. Then, the generated photoelectric conversion signal is output to a corresponding one of the n bit circuits BC1 to BCn. The photoelectric conversion device 1 is mounted on a linear image sensor used in, for example, a copying machine or a banknote discriminator, and is a one-dimensional image reading target using n pixel circuits PC1 to PCn arranged in such a one-dimensional direction. A typical optical image.

  Each of the n pixel circuits PC1 to PCn (hereinafter referred to as “pixel circuit PC”) is configured as shown in FIG. The configuration and operation of the pixel circuit PC will be described with reference to FIG.

  The pixel circuit PC includes an embedded photodiode PINNED_PD that photoelectrically converts incident light, a floating diffusion FD that converts charges transferred from the photodiode PINNED_PD to a voltage, and transfers charges from the photodiode PINNED_PD to the floating diffusion FD. A transfer gate Tr_TX for resetting, a reset transistor Tr_RST for resetting the floating diffusion FD, a source follower transistor Tr_SF for amplifying and reading a signal of the floating diffusion FD, and a constant current for supplying a constant current from the power supply VDD to the source follower transistor Tr_SF A source BIAS_SF.

  The photodiode PINNED_PD functions as a photoelectric conversion element that photoelectrically converts incident light. One end (anode) of the photodiode PINNED_PD is grounded, and the other end (cathode) is connected to the transfer gate Tr_TX.

  The transfer gate Tr_TX receives the transfer signal TX transmitted from the control circuit 11 at an appropriate timing, and switches between transferring and blocking charge from the photodiode PINNED_PD to the floating diffusion FD.

  The reset transistor Tr_RST receives the reset signal RST transmitted from the control circuit 11 at an appropriate timing, and resets the floating diffusion FD to the reset voltage V_RST.

  The source follower transistor Tr_SF receives the signal of the floating diffusion FD at the gate electrode, and outputs the signal whose output voltage is represented by V_PDSF from the source electrode to the corresponding bit circuit among the n bit circuits BC1 to BCn. To do.

  The pixel circuit PC outputs a reference signal that is not based on the photoelectric conversion by the photodiode PINNED_PD and a photoelectric conversion signal that is generated based on the photoelectric conversion by the photodiode PINNED_PD, among the bit circuits BC1 to BCn. Are output sequentially.

  The operation of the pixel circuit PC will be specifically described. In a state where the photodiode PINNED_PD is not irradiated with light, the control circuit 11 blocks charge transfer of the transfer gate Tr_TX. In a state where no charge is transferred from the photodiode PINNED_PD to the floating diffusion FD, the control circuit 11 transmits a reset signal RST to the reset transistor Tr_RST to reset the reset transistor Tr_RST. As a result, a voltage corresponding to the reset voltage V_RST is input to the source follower transistor Tr_SF. At this time, the source follower transistor Tr_SF outputs a signal whose output voltage is represented by V_PDSF_t1 as a reference signal not based on photoelectric conversion.

  After the source follower transistor Tr_SF outputs the reference signal, when the photodiode PINNED_PD starts to be irradiated with light, the control circuit 11 transmits the transfer signal TX to the transfer gate Tr_TX to start charge transfer. As a result, the charge generated by photoelectric conversion by the photodiode PINNED_PD is transmitted to the floating diffusion FD, and the input voltage to the source follower transistor Tr_SF changes. At this time, the source follower transistor Tr_SF outputs a photoelectric conversion signal whose output voltage is represented by V_PDSF_t2.

  By operating in this way, each of the n pixel circuits PC1 to PCn converts the information of the irradiation light detected by the photodiode PINNED_PD into voltage information, and the corresponding one of the n bit circuits BC1 to BCn. Output to the bit circuit.

  The n bit circuits BC1 to BCn are arranged side by side in the same direction as the direction in which the n pixel circuits PC1 to PCn are arranged. Each of the n bit circuits BC1 to BCn receives a photoelectric conversion signal generated by a corresponding one pixel circuit PC (1 bit) among the n pixel circuits PC1 to PCn. Each of the n bit circuits BC1 to BCn processes the received photoelectric conversion signal and outputs a signal based on the received photoelectric conversion signal.

  Each of the n bit circuits BC1 to BCn (hereinafter referred to as “bit circuit BC”) is configured as shown in FIG. The configuration and operation of the bit circuit BC will be described with reference to FIG.

  The bit circuit BC includes a differential amplifier circuit DiffAMP that amplifies an input voltage, a reset switch SW_RST that resets the differential amplifier circuit DiffAMP, and a sample hold that temporarily holds an output of the differential amplifier circuit DiffAMP in a sample hold capacitor CSH. A switch SW_SH, a read buffer BufAMP that reads a sample hold signal held in the sample hold capacitor CSH, and a bit selection switch SW_BITSEL that controls whether or not a signal read by the read buffer BufAMP is output from the bit circuit BC. .

  The bit circuit BC sequentially receives the reference signal and the photoelectric conversion signal output from the corresponding pixel circuit PC among the n pixel circuits PC1 to PCn, and calculates the difference between the received reference signal and the photoelectric conversion signal. An output signal DiffSIGNAL obtained by amplification is output.

  The operation of the bit circuit BC will be specifically described. In a state where the bit circuit BC receives the reference signal from the corresponding pixel circuit PC, the control circuit 11 transmits a control signal to the reset switch SW_RST and switches the reset switch SW_RST from OFF to ON for an appropriate time. Thus, after resetting the differential amplifier circuit DiffAMP, the control circuit 11 transmits a control signal to the reset switch SW_RST and returns the reset switch SW_RST to OFF.

  In this state, when the bit circuit BC receives a photoelectric conversion signal from the corresponding pixel circuit PC, the differential amplifier circuit DiffAMP calculates the difference between the reference signal and the photoelectric conversion signal between the two gain determination capacitors C1 and C2. Amplification is performed with a gain determined by the ratio. Then, the differential amplifier circuit DiffAMP outputs the obtained amplified signal to the sample hold switch SW_SH.

  Specifically, when the voltage of the amplified signal output from the differential amplifier circuit DiffAMP is expressed as V_AMP, the voltage V_AMP of the amplified signal is expressed by the following equation (1): the input voltage V_PDSF_t1 of the reference signal and the input voltage of the photoelectric conversion signal A value obtained by multiplying the difference between V_PDSF_t2 and the ratio between the two gain determination capacitors C1 and C2 and the offset bias voltage V_BIAS is obtained.

  V_AMP = C1 / C2 × (V_PDSF_t2−V_PDSF_t1) + V_BIAS (1)

  In a state where the differential amplifier circuit DiffAMP outputs an amplified signal, the control circuit 11 transmits a control signal to the sample hold switch SW_SH to switch the sample hold switch SW_SH from OFF to ON for an appropriate time, and further, the sample hold switch Return SW_SH to OFF. Thereby, the amplified signal of the differential amplifier circuit DiffAMP is held in the sample hold capacitor CSH through the sample hold switch SW_SH. The amplified signal held in the sample hold capacitor CSH is transmitted to the bit selection switch SW_BITSEL through the read buffer BufAMP.

  The bit selection switch SW_BITSEL switches whether or not to output the amplified signal transmitted from the sample hold capacitor CSH from the bit circuit BC to the outside as the output signal DiffSIGNAL. Switching of the bit selection switch SW_BITSEL is controlled by a bit selection signal BITSEL transmitted from the control circuit 11. The control circuit 11 transmits a bit selection signal BITSEL to the bit circuit BC at an appropriate timing described later, and outputs an amplified signal held in the sample hold capacitor CSH.

  The parasitic depletion layer capacitance of the bit selection switch SW_BITSEL in the bit circuit BC is represented as Cpsw.

  Returning to the description of the photoelectric conversion device 1 shown in FIG. Each of the common wiring COM1 and the common wiring COM2 transmits the output signal DiffSIGNAL output from the bit circuits BC arranged in every other one of the n bit circuits BC1 to BCn.

  More specifically, the common wiring line COM1 includes n / 2 bit circuits (bit circuit BC1, bit circuit BC3, bit circuit BC5,...) Arranged every other bit circuit BC1 to bit circuit BCn-1. And the bit circuit BCn-1). Further, the common line COM2 includes n / 2 bit circuits (bit circuits BC2,...) Arranged every other bit circuit BC2 to bit circuit BCn so that the bit circuits for transmitting signals do not overlap with the common line COM1. Bit circuit BC4, bit circuit BC6,..., And bit circuit BCn).

  For ease of understanding, it is assumed that n is an even number, that is, the photoelectric conversion device 1 includes an even number of pixel circuits and bit circuits. However, the photoelectric conversion device 1 according to the present invention may include an odd number of pixel circuits and bit circuits. When n is an odd number, the common line COM1 is connected to every other (n + 1) / 2 bit circuits from the bit circuit BC1 to the bit circuit BCn, and the common line COM2 is connected from the bit circuit BC2 to the bit circuit BCn−. The same explanation can be made assuming that every other one is connected to every other (n-1) / 2 bit circuits.

  The output signal DiffSIGNAL transmitted through the common line COM1 is amplified by the amplifier circuit AMP_COM1 and transmitted to the output selection switch SW_COM1. The output signal DiffSIGNAL transmitted through the common line COM2 is amplified by the amplifier circuit AMP_COM2 and transmitted to the output selection switch SW_COM2.

  Note that the wiring capacitances of the common wiring COM1 and the common wiring COM2 are represented as Cpcom1 and Cpcom2, respectively. Further, the parasitic input capacitances of the amplifier circuit AMP_COM1 and the amplifier circuit AMP_COM2 are represented as Cpin1 and Cpin2, respectively.

  The output selection switch SW_COM1 and the output selection switch SW_COM2 are signals that transmit signals to the common wiring COM1 and the common wiring COM2, respectively, and transmit signals to the external signal processing circuit 10 through the common output amplifier circuit OUTAMP. It functions as a switching unit that switches between transmission to the output wiring OUT and blocking. That is, while the output selection switch SW_COM1 is closed, a signal transmitted through the common line COM1 is output to the signal processing circuit 10 through the output line OUT. While the output selection switch SW_COM2 is closed, a signal transmitted through the common wiring COM2 is output to the signal processing circuit 10 through the output wiring OUT.

  The control circuit 11 is a shift register, for example, and transmits a control signal to each unit in the photoelectric conversion apparatus 1 to control the operation of each unit. The operation of the photoelectric conversion device 1 will be described specifically with reference to the timing chart shown in FIG.

  The control circuit 11 receives, as an external signal, a clock CLK that periodically repeats a high level and a low level at a predetermined frequency. The control circuit 11 generates various control signals at a timing synchronized with the clock CLK and transmits the various control signals to each unit in the photoelectric conversion device 1.

  More specifically, the control circuit 11 transmits the transfer signal TX and the reset signal RST to the transfer gate Tr_TX and the reset transistor Tr_RST in the pixel circuit PC at appropriate timings, respectively, so that the pixel circuit PC is set as described above. Make it work. Further, the control circuit 11 transmits a control signal to the reset switch SW_RST and the sample hold switch SW_SH in the bit circuit BC at an appropriate timing, and operates the bit circuit BC as described above.

  Further, the control circuit 11 transmits bit selection signals BITSEL1 to BITSELn to the n bit circuits BC1 to BCn, respectively, and controls opening and closing of the bit selection switch SW_BITSEL in the bit circuit BC. Thereby, the control circuit 11 should control the timing at which each of the n bit circuits BC1 to BCn outputs the output signal DiffSIGNAL, and output the output signal DiffSIGNAL to each of the two common lines COM1 and COM2. An output signal DiffSIGNAL generated based on photoelectric conversion of incident light incident at the same time from n / 2 bit circuits to n / 2 pixel circuits corresponding to the n / 2 bit circuits is The output is performed in the order in which n / 2 pixel circuits are arranged. Note that the same time is a time determined to be the same within the time resolution accuracy range of the photoelectric conversion device 1. Even if there is a slight time difference in the incident time to the plurality of pixel circuits, it is determined that the light has entered at the same time.

  For example, FIG. 4 shows the transmission timing of the bit selection signals BITSEL1 to BITSEL4 transmitted to the four bit circuits BC1 to BC4 among the n bit circuits BC1 to BCn.

  When the photoelectric conversion device 1 starts operating in a state where the bit selection switches SW_BITSEL in all the bit circuits BC1 to BCn are OFF (open), the control circuit 11 sends each of the bit selection signals BITSEL1 to BITSELn to the clock CLK. The bit selection switches SW_BITSEL in each bit circuit BC are switched ON (closed) in sequence at a timing synchronized with each other. At this time, the timing at which the bit selection switch SW_BITSEL in each bit circuit BC is turned on is sequentially shifted from the bit selection signal BITSEL1 by a time corresponding to one cycle of the clock CLK.

  When a time corresponding to two cycles of the clock CLK has elapsed since the bit selection switch SW_BITSEL in each bit circuit BC is turned ON, the control circuit 11 sequentially turns the bit selection switch SW_BITSEL in each bit circuit BC to OFF. The output signal DiffSIGNAL from the bit circuit BC is output to any one of the two common lines COM1 and COM2 until the bit selection switch SW_BITSEL is turned on and then turned off. The

For example, the rows of “COM1” and “COM2” in FIG. 4 indicate bit circuits that are output sources of the output signal DiffSIGNAL that transmits the common wiring COM1 and the common wiring COM2, respectively. The common wiring COM1 and the common wiring COM2 transmit the output signal DiffSIGNAL as in the following (1) to (4).
(1) While the bit selection switch SW_BITSEL in the bit circuit BC1 is ON, the common line COM1 transmits the output signal DiffSIGNAL from the bit circuit BC1.
(2) When the bit selection switch SW_BITSEL of the bit circuit BC2 is turned on after a time corresponding to one cycle of the clock CLK after the bit selection switch SW_BITSEL in the bit circuit BC1 is turned on, the common wiring COM2 is connected to the bit circuit BC2. The output signal DiffSIGNAL from is transmitted.
(3) After a time corresponding to one cycle of the clock CLK after the bit selection switch SW_BITSEL in the bit circuit BC2 is turned ON, the bit selection switch SW_BITSEL of the bit circuit BC1 is turned OFF and the bit selection of the bit circuit BC3 When the switch SW_BITSEL is turned on, the common line COM1 transmits the output signal DiffSIGNAL from the bit circuit BC3.
(4) After a time corresponding to one cycle of the clock CLK after the bit selection switch SW_BITSEL in the bit circuit BC3 is turned ON, the bit selection switch SW_BITSEL of the bit circuit BC2 is turned OFF and the bit selection of the bit circuit BC4 When the switch SW_BITSEL is turned on, the common line COM2 transmits the output signal DiffSIGNAL from the bit circuit BC4.

  That is, each of the common line COM1 and the common line COM2 receives the output signal DiffSIGNAL from n / 2 bit circuits arranged every other one of the n bit circuits BC1 to BCn at the same time with two or more bits. The output signal DiffSIGNAL from the circuit is sequentially transmitted exclusively so that it is not transmitted.

  The output signal DiffSIGNAL transmitted through the common wiring COM1 and the common wiring COM2 reaches the output selection switch SW_COM1 or the output selection switch SW_COM2 via the amplification circuit AMP_COM1 or the amplification circuit AMP_COM2. The control circuit 11 transmits control signals to the output selection switch SW_COM1 and the output selection switch SW_COM2, which are both OFF (open) before the operation of the photoelectric conversion device 1, and the ON (closed) and OFF ( Switch between open and open. As a result, the control circuit 11 controls the timing of transmitting a signal from each of the common wiring COM1 and the common wiring COM2 to the output wiring OUT, and the time resolution accuracy of the photoelectric conversion device 1 is transferred to the n pixel circuits PC1 to PCn. A signal based on photoelectric conversion of incident light incident at the same time within the range is sequentially output to the output wiring OUT in the order in which the n pixel circuits PC1 to PCn are arranged.

More specifically, the control circuit 11 transmits a control signal at the timing shown in the rows “SW_COM1” and “SW_COM2” in FIG. 4 and outputs the output selection switch as shown in the following (a) to (d). SW_COM1 and the output selection switch SW_COM2 are alternately switched on and off at a cycle that is twice the cycle of the clock CLK.
(A) The control circuit 11 switches the output selection switch SW_COM1 to ON at a timing within a period during which the output signal DiffSIGNAL from the bit circuit BC1 is transmitted through the common line COM1.
(B) At the timing when the period during which the output signal DiffSIGNAL from the bit circuit BC1 is transmitted through the common line COM1 ends, the control circuit 11 switches the output selection switch SW_COM1 to OFF and turns the output selection switch SW_COM2 to ON. Switch.
(C) At the timing when the period during which the output signal DiffSIGNAL from the bit circuit BC2 is transmitted through the common line COM2 ends, the control circuit 11 switches the output selection switch SW_COM2 to OFF and turns the output selection switch SW_COM1 to ON. Switch.
(D) At the timing when the period in which the output signal DiffSIGNAL from the bit circuit BC3 is transmitted through the common line COM1 ends, the control circuit 11 switches the output selection switch SW_COM1 to OFF and turns the output selection switch SW_COM2 to ON. Switch.

  That is, the control circuit 11 is configured so that one of the output selection switch SW_COM1 and the output selection switch SW_COM2 is ON so that the signal that transmits the common line COM1 and the signal that transmits the common line COM2 are not output at the same time. During this period, the other is kept OFF, and the signals transmitted through the two common lines COM1 and COM2 are sequentially and exclusively selected.

  The row “OUT” in FIG. 4 shows a bit circuit that is an output source of a signal transmitted through the output wiring OUT. As a result of selection by the output selection switch SW_COM1 and the output selection switch SW_COM2, it is output from each of the n bit circuits BC1 to BCn, and is amplified by one of the two amplification circuits AMP_COM1 and AMP_COM2 and the output amplification circuit OUTAMP. The signals are output to the signal processing circuit 10 in the order from the bit circuit BC1 to the bit circuit BCn. That is, signals based on photoelectric conversion of incident light incident on the n pixel circuits PC1 to PCn at the same time pass through the corresponding bit circuit and common wiring, respectively, and the n pixel circuits PC1 to PCn are arranged. The signals are output to the signal processing circuit 10 in this order.

  The signal processing circuit 10 performs appropriate image generation processing on the output signal to obtain a one-dimensional image to be read. Since the signal processing circuit 10 receives a signal based on the photoelectric conversion signal generated in each pixel circuit in the order in which the pixel circuits are arranged in a one-dimensional direction, the signal processing circuit 10 receives the output signal DiffSIGNAL from the n bit circuits BC1 to BCn as 1 An image to be read can be obtained in the same manner as in the case where the signals are sequentially transmitted through the common wiring and output to the signal processing circuit 10.

  As described above, the photoelectric conversion device 1 according to the first embodiment transmits the output signal DiffSIGNAL output from the n bit circuits BC1 to BCn by dividing it into the two common lines COM1 and COM2. To do. When the parasitic capacitances associated with the common wiring COM1 and the common wiring COM2 are expressed as C_COM1 and C_COM2, respectively, the wiring capacitances Cpcom1 and Cpcom2 of each common wiring, and the parasitic input capacitances Cpin1 and Cpin2 of each amplifier circuit are connected to each common wiring. Using the parasitic depletion layer capacitance Cpsw of the bit selection switch SW_BITSEL in the n / 2 bit circuits, the parasitic capacitances C_COM1 and C_COM2 associated with each common wiring are expressed by the following equations (2) and (3): It is expressed as follows.

C_COM1 = Cpcom1 + Cpin1 + Cpsw × n / 2 (2)
C_COM2 = Cpcom2 + Cpin2 + Cpsw × n / 2 (3)

  That is, the parasitic depletion layer capacitance Cpsw of the bit selection switch SW_BITSEL is doubled by the number of bit circuits connected to the common wiring and applies a load to each common wiring. Since the photoelectric conversion device 1 according to the first embodiment connects the bit circuits in half to each of the two common wirings COM1 and COM2, compared to a configuration in which all the bit circuits are connected to one common wiring, The parasitic capacitance per one common wiring can be suppressed.

  Each of the two common lines COM1 and COM2 transmits the output signal DiffSIGNAL output from the bit circuit BC corresponding to every other pixel circuit of the n pixel circuits PC1 to PCn. . The signals transmitted separately to the common line COM1 and the common line COM2 are output to the outside through one common output line OUT after passing through the corresponding output selection switch SW_COM1 or output selection switch SW_COM2, respectively. .

  That is, in the signal transmission path in the photoelectric conversion device 1, the operating frequency in the portion of the common wiring COM1 and the common wiring COM2 having a relatively large parasitic capacitance is obtained from n bit circuits BC1 to BCn for one common wiring. Compared to a configuration in which all output signals are transmitted, it is halved. Then, the operating frequency in the portion subsequent to the output selection switches SW_COM1 and SW_COM2 having relatively small parasitic capacitances returns to the frequency required for image reading. Therefore, the photoelectric conversion apparatus 1 according to Embodiment 1 can operate at high speed even in an image reading apparatus having a high resolution or a large reading range that particularly requires many pixel circuits and bit circuits.

Embodiment 2. FIG.
Hereinafter, the photoelectric conversion apparatus according to Embodiment 2 of the present invention will be described. The photoelectric conversion device 1 according to the first embodiment described above transmits the output signal DiffSIGNAL output from the n bit circuits BC1 to BCn to the two common wiring lines COM1 and COM2. On the other hand, the photoelectric conversion device according to the second embodiment transmits the output signal DiffSIGNAL output from the n bit circuits BC1 to BCn to three common wirings.

  The photoelectric conversion device according to Embodiment 2 is configured as shown in FIG.

  The photoelectric conversion device 2 includes n pixel circuits PC1 to PCn arranged side by side in a predetermined direction, and n bit circuits BC1 corresponding to the n pixel circuits PC1 to PCn on a one-to-one basis. ˜BCn, three common wiring lines COM1, COM2, COM3 that transmit signals output from the n bit circuits BC1 to BCn, and signals that transmit the three common wiring lines COM1, COM2, COM3 are amplified, respectively. Three amplifier circuits AMP_COM1, AMP_COM2, AMP_COM3, three output selection switches SW_COM1, SW_COM2, SW_COM3 for switching between transmission and interruption of signals amplified by the three amplifier circuits AMP_COM1, AMP_COM2, AMP_COM3, and external signal processing Output amplifier circuit OUTAMP for amplifying the signal for circuit 10 , And a control circuit 12 which generates a control signal to each section of the photoelectric conversion device 2 from the external signal.

  Each of the n pixel circuits PC1 to PCn includes a photoelectric conversion element that photoelectrically converts incident light, and generates a photoelectric conversion signal based on photoelectric conversion by the photoelectric conversion element. The configuration and operation of each pixel circuit PC are the same as the configuration and operation described in Embodiment 1 with reference to FIG.

  Each of the n bit circuits BC1 to BCn receives the photoelectric conversion signal generated by the corresponding one pixel circuit PC (1 bit) among the n pixel circuits PC1 to PCn, and receives the received photoelectric circuit. A signal based on the converted signal is output. The configuration and operation of each bit circuit BC are the same as the configuration and operation described with reference to FIG.

  Each of the common lines COM1, COM2, and COM3 transmits an output signal DiffSIGNAL output from every two bit circuits of the n bit circuits BC1 to BCn.

  More specifically, the common wiring line COM1 includes n / 3 bit circuits (bit circuit BC1, bit circuit BC4, bit circuit BC7,...) Arranged every two from the bit circuit BC1 to the bit circuit BCn-2. And the bit circuit BCn-2). Further, the common wiring line COM2 includes n / 3 bit circuits (bit circuits) arranged every two bit circuits BC2 to BCn-1 so that the bit circuit for transmitting signals does not overlap with the common wiring line COM1. BC2, bit circuit BC5, bit circuit BC8,..., And bit circuit BCn-1). Further, the common wiring COM3 includes n / 3 bits arranged every two bits from the bit circuit BC3 to the bit circuit BCn so that the bit circuit for transmitting a signal does not overlap with either the common wiring COM1 or the common wiring COM2. It is connected to circuits (bit circuit BC3, bit circuit BC6, bit circuit BC9,..., And bit circuit BCn).

  In order to facilitate understanding, it is assumed that n is a multiple of 3, that is, the photoelectric conversion device 2 includes a multiple of 3 pixel circuits and bit circuits. However, the photoelectric conversion device 2 according to the present invention may include a number of pixel circuits and bit circuits that are not multiples of 3. When n is not a multiple of 3, the number of bit circuits connected between the three common lines COM1, COM2, and COM3 is not equal, but this can be explained in the same manner as when n is a multiple of 3.

  The output signal DiffSIGNAL transmitted through the common line COM1 is amplified by the amplifier circuit AMP_COM1 and transmitted to the output selection switch SW_COM1. The output signal DiffSIGNAL transmitted through the common line COM2 is amplified by the amplifier circuit AMP_COM2 and transmitted to the output selection switch SW_COM2. The output signal DiffSIGNAL transmitted through the common line COM3 is amplified by the amplifier circuit AMP_COM3 and transmitted to the output selection switch SW_COM3.

  Note that the wiring capacitances of the common wiring COM1, the common wiring COM2, and the common wiring COM3 are represented as Cpcom1, Cpcom2, and Cpcom3, respectively. In addition, the parasitic input capacitances of the amplifier circuit AMP_COM1, the amplifier circuit AMP_COM2, and the amplifier circuit AMP_COM3 are represented as Cpin1, Cpin2, and Cpin3, respectively.

  The output selection switches SW_COM1, SW_COM2, and SW_COM3 are a single output for transmitting signals to the common signal lines COM1, COM2, and COM3 to the external signal processing circuit 10 via the common output amplifier circuit OUTAMP. It functions as a switching unit that switches between transmission to the wiring OUT and blocking. That is, while the output selection switch SW_COM1 is closed, a signal transmitted through the common line COM1 is output to the signal processing circuit 10 through the output line OUT. While the output selection switch SW_COM2 is closed, a signal transmitted through the common wiring COM2 is output to the signal processing circuit 10 through the output wiring OUT. While the output selection switch SW_COM3 is closed, a signal transmitted through the common wiring COM3 is output to the signal processing circuit 10 through the output wiring OUT.

  The control circuit 12 is a shift register, for example, and controls the operation of each unit by transmitting a control signal to each unit in the photoelectric conversion device 2. Specifically, the operation of the photoelectric conversion device 2 will be described with reference to a timing chart shown in FIG.

  The control circuit 12 receives, as an external signal, a clock CLK that periodically repeats a high level and a low level at a predetermined frequency. The control circuit 12 generates various control signals at a timing synchronized with the clock CLK and transmits the various control signals to each unit in the photoelectric conversion device 2.

  Specifically, the control circuit 12 transmits the transfer signal TX and the reset signal RST to the transfer gate Tr_TX and the reset transistor Tr_RST in the pixel circuit PC at appropriate timings, respectively, so that the pixel circuit PC is set as described above. Make it work. Further, the control circuit 12 transmits a control signal to the reset switch SW_RST and the sample hold switch SW_SH in the bit circuit BC at an appropriate timing, and operates the bit circuit BC as described above.

  Further, the control circuit 12 transmits bit selection signals BITSEL1 to BITSELn to the n bit circuits BC1 to BCn, respectively, and controls the opening and closing of the bit selection switch SW_BITSEL in the bit circuit BC. Thus, the control circuit 12 controls the timing at which each of the n bit circuits BC1 to BCn outputs the output signal DiffSIGNAL, and outputs the output signal DiffSIGNAL to each of the three common lines COM1, COM2, and COM3. An output signal DiffSIGNAL generated based on photoelectric conversion of incident light incident on the n / 3 pixel circuits corresponding to the n / 3 bit circuits from the n / 3 bit circuits to be input at the same time. The n / 3 pixel circuits are output in the order in which they are arranged.

  For example, FIG. 6 shows transmission timings of the bit selection signals BITSEL1 to BITSEL6 transmitted to the six bit circuits BC1 to BC6 among the n bit circuits BC1 to BCn.

  When the photoelectric conversion device 2 starts operating in a state in which the bit selection switches SW_BITSEL in all the bit circuits BC1 to BCn are OFF (open), the control circuit 12 sends each of the bit selection signals BITSEL1 to BITSELn to the clock CLK. The bit selection switches SW_BITSEL in each bit circuit BC are switched ON (closed) in sequence at a timing synchronized with each other. At this time, the timing at which the bit selection switch SW_BITSEL in each bit circuit BC is turned on is sequentially shifted from the bit selection signal BITSEL1 by a time corresponding to one cycle of the clock CLK.

  When a time corresponding to three cycles of the clock CLK has elapsed since the bit selection switch SW_BITSEL in each bit circuit BC is turned on, the control circuit 12 sequentially turns the bit selection switch SW_BITSEL in each bit circuit BC to OFF. The output signal DiffSIGNAL from the bit circuit BC is applied to any one of the corresponding three common wirings COM1, COM2, and COM3 until the bit selection switch SW_BITSEL is turned on and then turned off. Is output.

For example, the “COM1”, “COM2”, and “COM3” rows in FIG. 6 indicate the bit circuit that is the output source of the output signal DiffSIGNAL that transmits each of the common lines COM1, COM2, and COM3. The common lines COM1, COM2, and COM3 transmit the output signal DiffSIGNAL as in the following (1) to (6).
(1) While the bit selection switch SW_BITSEL in the bit circuit BC1 is ON, the common line COM1 transmits the output signal DiffSIGNAL from the bit circuit BC1.
(2) When the bit selection switch SW_BITSEL of the bit circuit BC2 is turned on after a time corresponding to one cycle of the clock CLK after the bit selection switch SW_BITSEL in the bit circuit BC1 is turned on, the common wiring COM2 is connected to the bit circuit BC2. The output signal DiffSIGNAL from is transmitted.
(3) When the bit selection switch SW_BITSEL of the bit circuit BC3 is turned on after a time corresponding to one cycle of the clock CLK after the bit selection switch SW_BITSEL in the bit circuit BC2 is turned on, the common wiring COM3 is connected to the bit circuit BC3. The output signal DiffSIGNAL from is transmitted.
(4) After a time corresponding to one cycle of the clock CLK after the bit selection switch SW_BITSEL in the bit circuit BC3 is turned ON, the bit selection switch SW_BITSEL of the bit circuit BC1 is turned OFF and the bit selection of the bit circuit BC4 When the switch SW_BITSEL is turned on, the common line COM1 transmits the output signal DiffSIGNAL from the bit circuit BC4.
(5) After a time corresponding to one cycle of the clock CLK after the bit selection switch SW_BITSEL in the bit circuit BC4 is turned ON, the bit selection switch SW_BITSEL of the bit circuit BC2 is turned OFF and the bit selection of the bit circuit BC5 When the switch SW_BITSEL is turned on, the common line COM2 transmits the output signal DiffSIGNAL from the bit circuit BC5.
(6) After a time corresponding to one cycle of the clock CLK after the bit selection switch SW_BITSEL in the bit circuit BC5 is turned ON, the bit selection switch SW_BITSEL of the bit circuit BC3 is turned OFF and the bit selection of the bit circuit BC6 When the switch SW_BITSEL is turned on, the common line COM3 transmits the output signal DiffSIGNAL from the bit circuit BC6.

  That is, each of the common lines COM1, COM2, and COM3 receives the output signal DiffSIGNAL from every n / 3 bit circuits arranged every two of the n bit circuits BC1 to BCn at the same time with two or more bits. The output signal DiffSIGNAL from the circuit is sequentially transmitted exclusively so that it is not transmitted.

  The output signal DiffSIGNAL that transmits each of the common lines COM1, COM2, and COM3 is associated with one of the output selection switches SW_COM1, SW_COM2, and SW_COM3 via one corresponding amplifier circuit of the amplifier circuits AMP_COM1, AMP_COM2, and AMP_COM3. To reach the amplifier circuit. The control circuit 12 transmits control signals to the three output selection switches SW_COM1, SW_COM2, and SW_COM3, all of which are OFF (open) before the operation of the photoelectric conversion device 2, and these switches are turned ON (closed). And OFF (open). Thereby, the control circuit 12 controls the timing of transmitting a signal from each of the common wirings COM1, COM2, and COM3 to the output wiring OUT, and the time resolution accuracy of the photoelectric conversion device 1 is transferred to the n pixel circuits PC1 to PCn. A signal based on photoelectric conversion of incident light incident at the same time within the range is sequentially output to the output wiring OUT in the order in which the n pixel circuits PC1 to PCn are arranged.

More specifically, the control circuit 12 transmits a control signal at the timings shown in the rows “SW_COM1”, “SW_COM2”, and “SW_COM3” in FIG. 6 as shown in the following (a) to (f). The three output selection switches SW_COM1, SW_COM2, and SW_COM3 are alternately switched on and off at a cycle three times the cycle of the clock CLK.
(A) The control circuit 12 switches the output selection switch SW_COM1 to ON at a timing within a period during which the output signal DiffSIGNAL from the bit circuit BC1 is transmitted through the common line COM1.
(B) At the timing when the period during which the output signal DiffSIGNAL from the bit circuit BC1 is transmitted through the common line COM1 ends, the control circuit 12 switches the output selection switch SW_COM1 to OFF and turns the output selection switch SW_COM2 to ON. Switch.
(C) At the timing when the period during which the output signal DiffSIGNAL from the bit circuit BC2 is transmitted through the common line COM2 ends, the control circuit 12 switches the output selection switch SW_COM2 to OFF and turns the output selection switch SW_COM3 to ON. Switch.
(D) At the timing when the period during which the output signal DiffSIGNAL from the bit circuit BC3 is transmitted through the common wiring COM3 ends, the control circuit 12 switches the output selection switch SW_COM3 to OFF and turns the output selection switch SW_COM1 to ON. Switch.
(E) At the timing when the period in which the output signal DiffSIGNAL from the bit circuit BC4 is transmitted through the common line COM1 ends, the control circuit 12 switches the output selection switch SW_COM1 to OFF and turns the output selection switch SW_COM2 to ON. Switch.
(F) At the timing when the period during which the output signal DiffSIGNAL from the bit circuit BC5 is transmitted through the common line COM2 ends, the control circuit 12 switches the output selection switch SW_COM2 to OFF and turns the output selection switch SW_COM3 to ON. Switch.

  That is, the control circuit 12 includes three output selection switches SW_COM1, so that signals that transmit any two of the three common lines COM1, COM2, and COM3 are not simultaneously output. While one output selection switch of SW_COM2 and SW_COM3 is ON, the remaining two output selection switches are kept OFF, and signals that transmit the three common lines COM1, COM2, and COM3 are sequentially exclusive. Select

  The row “OUT” in FIG. 6 shows a bit circuit that is an output source of a signal transmitted through the output wiring OUT. As a result of selection by the three output selection switches SW_COM1, SW_COM2, and SW_COM3, they are output from each of the n bit circuits BC1 to BCn, and one of the three amplifier circuits AMP_COM1, AMP_COM2, and AMP_COM3 and the output amplifier circuit OUTAMP are output. The signals amplified by the above are output to the signal processing circuit 10 in the order from the bit circuit BC1 to the bit circuit BCn. That is, signals based on photoelectric conversion of incident light incident on the n pixel circuits PC1 to PCn at the same time pass through the corresponding bit circuit and common wiring, respectively, and the n pixel circuits PC1 to PCn are arranged. The signals are output to the signal processing circuit 10 in this order.

  The signal processing circuit 10 performs appropriate image generation processing on the output signal to obtain a one-dimensional image to be read. Since the signal processing circuit 10 receives a signal based on the photoelectric conversion signal generated in each pixel circuit in the order in which the pixel circuits are arranged in a one-dimensional direction, the signal processing circuit 10 receives the output signal DiffSIGNAL from the n bit circuits BC1 to BCn as 1 An image to be read can be obtained in the same manner as in the case where the signals are sequentially transmitted through the common wiring and output to the signal processing circuit 10.

  As described above, the photoelectric conversion device 2 according to the second embodiment transmits the output signal DiffSIGNAL output from the n bit circuits BC1 to BCn to the three common lines COM1, COM2, and COM3. . When the parasitic capacitances associated with the common wirings COM1, COM2, and COM3 are represented as C_COM1, C_COM2, and C_COM3, respectively, the wiring capacitances Cpcom1, Cpcom2, and Cpcom3 of each common wiring, and the parasitic input capacitances Cpin1, Cpin2, and Cpin3 of each amplifier circuit, The parasitic capacitances C_COM1, C_COM2, and C_COM3 associated with each common line are expressed as follows using the parasitic depletion layer capacitance Cpsw of the bit selection switch SW_BITSEL in the n / 3 bit circuits connected to each common line: 4) to (6).

C_COM1 = Cpcom1 + Cpin1 + Cpsw × n / 3 (4)
C_COM2 = Cpcom2 + Cpin2 + Cpsw × n / 3 (5)
C_COM3 = Cpcom3 + Cpin3 + Cpsw × n / 3 (6)

  In other words, the photoelectric conversion device 2 according to the second embodiment has a smaller number of bit circuits connected per common wiring than the photoelectric conversion device 1 according to the first embodiment, and therefore, the photoelectric conversion device 2 according to the second embodiment is further reduced per one common wiring. Parasitic capacitance can be suppressed.

  Each of the three common lines COM1, COM2, and COM3 receives the output signal DiffSIGNAL output from the bit circuit BC corresponding to every two pixel circuits of the n pixel circuits PC1 to PCn. introduce. Therefore, the operating frequency in the common wiring portion is 1/3 compared to a configuration in which one common wiring transmits all signals output from the n bit circuits BC1 to BCn. As a result, the photoelectric conversion device 2 according to the second embodiment can further suppress the operating frequency in the common wiring portion and can be operated at a higher speed than the photoelectric conversion device 1 according to the first embodiment.

Embodiment 3 FIG.
Hereinafter, the photoelectric conversion apparatus according to Embodiment 3 of the present invention will be described. The photoelectric conversion device 1 according to the first embodiment and the photoelectric conversion device 2 according to the second embodiment described above are provided with an output selection switch that switches between transmission and interruption of the signal transmitted divided into two or three common wires. A signal transmitted separately to two or three common wirings is output to the outside through one common output wiring OUT. On the other hand, the photoelectric conversion apparatus according to the third embodiment does not include such an output selection switch, and separately outputs the signals transmitted by being divided into two common wirings.

  The photoelectric conversion device according to Embodiment 3 is configured as shown in FIG.

  The photoelectric conversion device 3 includes n pixel circuits PC1 to PCn arranged side by side in a predetermined direction, and n bit circuits BC1 that correspond to the n pixel circuits PC1 to PCn on a one-to-one basis. ˜BCn, common wiring COM1 and common wiring COM2 that transmit signals output from the n bit circuits BC1 to BCn, and amplification circuit AMP_COM1 and amplification circuit that amplify signals that transmit the common wiring COM1 and common wiring COM2, respectively. AMP_COM2, the output circuit OUTAMP1 and the output amplifier circuit OUTAMP2 that output the signals amplified by the amplifier circuit AMP_COM1 and the amplifier circuit AMP_COM2 to the external signal processing circuit 10, respectively, and control signals to each part in the photoelectric conversion device 3 are external signals And a control circuit 13 generated from the above.

  Similarly to the photoelectric conversion device 1 according to the first embodiment, the photoelectric conversion device 3 according to the third embodiment has bits corresponding to the pixel circuits arranged every other one of the n pixel circuits PC1 to PCn. Two common wires COM1 and COM2 connected to the circuit BC are provided. Then, the output signal DiffSIGNAL output from the n bit circuits BC1 to BCn is divided and transmitted to the two common lines COM1 and COM2.

  The control circuit 13 controls the timing at which each of the n bit circuits BC1 to BCn outputs the output signal DiffSIGNAL, and outputs n / 2 that the output signal DiffSIGNAL should be output to each of the two common lines COM1 and COM2. The output signal DiffSIGNAL generated based on the photoelectric conversion of the incident light incident on the n / 2 pixel circuits corresponding to the n / 2 bit circuits from the plurality of bit circuits at the same time is represented by the n / 2. The pixel circuits are output in the order in which they are arranged.

  On the other hand, the photoelectric conversion device 3 according to the third embodiment is different from the photoelectric conversion device 1 according to the first embodiment in that the switching is performed to switch between transmission and interruption of signals transmitted through the common wiring COM1 and the common wiring COM2. The output selection switches SW_COM1 and SW_COM2 that function as the units are not provided. For this reason, the control circuit 13 does not have a function of transmitting a control signal for switching the selection switch between ON and OFF.

  In the photoelectric conversion device 3, the signals transmitted through the two common wires COM1 and COM2 are separately output to the signal processing circuit 10 without being controlled by the output selection switches SW_COM1 and SW_COM2. More specifically, the output signal DiffSIGNAL transmitted through the common line COM1 is amplified by the amplifier circuit AMP_COM1 and the output amplifier circuit OUTAMP1, and is output to the signal processing circuit 10 through the output line OUT1. The output signal DiffSIGNAL transmitted through the common line COM2 is amplified by the amplifier circuit AMP_COM2 and the output amplifier circuit OUTAMP2, and is output to the signal processing circuit 10 through the output line OUT2.

  The signal processing circuit 10 receives signals output separately from the two output wirings OUT1 and OUT2. Then, the signal processing circuit 10 executes appropriate image processing including processing corresponding to processing by the output selection switch omitted in the photoelectric conversion device 3 on signals separately received from the two output wirings OUT1 and OUT2. Thus, a one-dimensional image to be read is obtained.

  As described above, the photoelectric conversion device 3 according to the third embodiment includes the output selection switch included in the above-described photoelectric conversion device 1 according to the first embodiment and the photoelectric conversion device 2 according to the second embodiment. The signal processing circuit 10 is not provided with the function of the control circuit for controlling the signal, and signals transmitted through the plurality of common wirings are output to the signal processing circuit 10 through separate output wirings. As a result, it is possible to operate the photoelectric conversion device 3 at high speed while simplifying the wiring and control in the photoelectric conversion device 3.

  The present invention can be variously modified and modified without departing from the broad spirit and scope of the present invention. The above-described embodiments are for explaining the present invention and do not limit the scope of the present invention.

  For example, in the above embodiment, the output signal DiffSIGNAL output from the n bit circuits BC1 to BCn is divided and transmitted to two or three common wires. However, the photoelectric conversion device according to the present invention can use a larger number of common wirings. By increasing the number of common wirings, wiring and control become complicated, while parasitic capacitance associated with one common wiring can be further suppressed.

  More specifically, each of the plurality of common wirings provided in the photoelectric conversion device according to the present invention is arranged every number obtained by subtracting 1 from the number of common wirings among the n pixel circuits PC1 to PCn. An output signal DiffSIGNAL output from two or more bit circuits corresponding to two or more pixel circuits can be transmitted. That is, when the photoelectric conversion device includes k (k is an integer of 2 or more) common wirings, each of the k common wirings has a bit circuit that outputs the output signal DiffSIGNAL to be transmitted between the k common wirings. In order not to overlap, the output signal DiffSIGNAL output from two or more bit circuits corresponding to two or more pixel circuits arranged every (k−1) may be transmitted. By increasing the number of common wires to k, the operating frequency of the common wire portion having a large parasitic capacitance can be reduced to 1 / k.

  In addition, the bit circuits that are the output sources of the output signal DiffSIGNAL transmitted by each of the plurality of common wirings included in the photoelectric conversion device according to the present invention are arranged at predetermined intervals in the n bit circuits BC1 to BCn. It doesn't have to be a thing. That is, when the common wirings that output the output signal DiffSIGNAL are arranged in order from the bit circuit BC1 to the bit circuit BCn, the order of the common wirings may not be cyclic among the plurality of common wirings. Good.

  More specifically, each of the plurality of common wirings included in the photoelectric conversion device according to the present invention includes two or more pixels that do not include pixel circuits arranged in a row among the n pixel circuits PC1 to PCn. An output signal DiffSIGNAL output from each of two or more bit circuits corresponding to the circuit can be transmitted. Even if the bit circuit that is the output source of the output signal DiffSIGNAL that transmits each common wiring is not a bit circuit that corresponds to a pixel circuit arranged every predetermined number, a bit circuit that corresponds to a pixel circuit arranged continuously By configuring so as not to occur, it is possible to suppress the speeding up of the operation in the common wiring portion, and it is possible to reduce the operating frequency.

  Further, in the above embodiment, each of the n bit circuits BC1 to BCn includes the differential amplifier circuit DiffAMP, and is obtained by amplifying the difference between the photoelectric conversion signal received from the corresponding pixel circuit PC and the reference signal. The obtained signal was output as an output signal DiffSIGNAL. However, each bit circuit BC may not include the differential amplifier circuit DiffAMP. For example, a process corresponding to the process of the differential amplifier circuit DiffAMP may be executed by a circuit subsequent to the bit circuit BC. In this case, each bit circuit BC holds the photoelectric conversion signal received from the corresponding pixel circuit PC as it is in the sample hold capacitor CSH, and outputs it to the corresponding common line as the output signal DiffSIGNAL. That is, the signal that each bit circuit BC outputs to the common wiring may be a signal obtained by performing processing such as amplification on the photoelectric conversion signal received from the corresponding pixel circuit, or the received photoelectric conversion signal itself. Also good.

  1, 2, 3 photoelectric conversion device, 10 signal processing circuit, 11, 12, 13 control circuit, PC, PC1-PCn pixel circuit, BC, BC1-BCn bit circuit, COM1, COM2, COM3 common wiring, AMP_COM1, AMP_COM2, AMP_COM3 amplifier circuit, SW_COM1, SW_COM2, SW_COM3 output selection switch, OUTAMP, OUTAMP1, OUTAMP2 output amplifier circuit, OUT, OUT1, OUT2 output wiring, Cpcom1, Cpcom2, Cpcom3 wiring capacitance, Cpin1, Cpin2, Cpin3 parasitic input capacitance, Cpsw parasitic depletion Layer capacitance, PINNED_PD photodiode, FD floating diffusion, Tr_TX transfer gate, TX transfer signal, Tr_SF source follower Transistor, Tr_RST reset transistor, V_RST reset voltage, RST reset signal, BIAS_SF constant current source, VDD power supply, V_PDSF output voltage, C1, C2 gain determining capacitance, DiffAMP differential amplifier circuit, SW_RST reset switch, V_BIAS offset bias voltage, SW_SH sample hold switch, CSH sample hold capacity, BufAMP read buffer, SW_BITSEL bit selection switch, BITSEL, BITSEL1 to BITSELn bit selection signal, DiffSIGNAL output signal

Claims (5)

Each includes a photoelectric conversion element that photoelectrically converts incident light, and sequentially outputs a reference signal that is not based on photoelectric conversion by the photoelectric conversion element and a photoelectric conversion signal that is generated based on photoelectric conversion by the photoelectric conversion element. A plurality of pixel circuits arranged side by side in a predetermined direction;
Each said plurality of the corresponding reference signal output from one pixel circuit and the photoelectric conversion signals sequentially received among the pixel circuits, for amplifying a difference between the reference signal and the photoelectric conversion signal received that A plurality of bit circuits which output the output signals obtained by the above-mentioned one-to-one correspondence to the plurality of pixel circuits;
A plurality of common wires that each transmit an output signal output from two or more bit circuits of the plurality of bit circuits, and that do not overlap bit circuits that output output signals to be transmitted;
Controlling the timing at which each of the plurality of bit circuits outputs the output signal, and outputting two or more output signals transmitted by the common wires to the common wires of the plurality of common wires. A control circuit for outputting the output signal in an order in which two or more pixel circuits corresponding to the two or more bit circuits of the plurality of pixel circuits are arranged from a bit circuit;
Equipped with a,
Each of the pixel circuits includes a reset transistor that resets a signal in the pixel circuit, and outputs the reference signal when the signal in the pixel circuit is reset by the reset transistor .   Each of the pixel circuits includes a floating diffusion,
  The signal in the pixel circuit is a signal converted from a charge to a voltage by the floating diffusion,
  Each of the pixel circuits outputs the reference signal when the voltage is reset by the reset transistor.
  The photoelectric conversion device according to claim 1. A switching unit that switches between transmission and interruption of a signal transmitted through each of the plurality of common wirings to one output wiring;
The control circuit controls a timing at which the switching unit transmits a signal from each of the plurality of common wirings to the one output wiring, and outputs a signal based on photoelectric conversion of the incident light in the plurality of pixel circuits. , And sequentially outputting to the one output wiring in the order in which the plurality of pixel circuits are arranged.
The photoelectric conversion device according to claim 1 or 2. Wherein each of the plurality of common lines, the output which is output from each of the consecutive two or more bits circuits corresponding to two or more pixel circuits without the pixel circuits arranged in the plurality of pixel circuits Transmit signal,
The photoelectric conversion apparatus of any one of Claim 1 to 3 . Each of the plurality of common wirings includes two or more pixel circuits corresponding to two or more pixel circuits arranged side by side by the number obtained by subtracting 1 from the number of the plurality of common wirings of the plurality of pixel circuits. Transmitting the output signal output from the bit circuit;
The photoelectric conversion apparatus of any one of Claim 1 to 3 .

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