JP6255982B2 - Verification support program and verification support method - Google Patents

Description

  The present invention relates to a verification support program and a verification support method.

  2. Description of the Related Art Conventionally, a technique is known in which a parameter included in a model function that simulates a circuit performance value is a random variable, and a value that causes the worst circuit performance value among the values of the random variable is searched. For example, a technique that makes the worst condition by searching for the point where the performance value takes the maximum value or the minimum value on the equiprobability plane corresponding to a predetermined yield rate in the space spanned by the random variable or in the area surrounded by the equiprobability plane (For example, refer to Patent Documents 1 and 2 below). In addition, for example, a technique is known in which the entire system is divided into a plurality of small blocks such as memory cells and sense amplifiers, and a system level yield is estimated by executing a Monte Carlo simulation on the value of a random variable for each block ( For example, refer to Patent Document 3 below).

  Conventionally, a technique for calculating a yield by simultaneously considering a memory cell included in an SRAM (Static Random Access Memory) and a sense amplifier is known (for example, see Non-Patent Document 1 below).

International Publication No. 2008/102681 JP 2012-103861 A Special table 2010-512645 gazette

“An Analytical Model for Performance Yield of Nanoscale SRAM Accounting for the Sense Amplifier Strobe Signal”, Joseph F. Ryan, Sudhanshu Kanna, Benton H. et al. Calhoun, ISLPED 2011, pp. 297-302

  However, since it is unlikely that the performance value of each partial circuit included in the verification target circuit will be the worst at the same time, the performance value of the target circuit is calculated based on each value of each random variable where the performance value of each partial circuit is the worst. When verified, the accuracy is low. Further, it takes time to generate each value of the random variable for each partial circuit by Monte Carlo simulation and verify the performance value of the target circuit. As described above, the above-described conventional technique has a problem that the target circuit cannot be efficiently verified.

  In one aspect, an object of the present invention is to provide a verification support program and a verification support method that can improve the efficiency of verification.

  According to one aspect of the present invention, a plurality of performance values of the first circuit included in the verification target circuit and non-defective information indicating the non-defective product ratio of the second circuit different from the first circuit included in the target circuit. For each of the acquired plurality of sets, each value of the plurality of first random variables related to the design of the second circuit, corresponding to the non-defective product rate indicated by the non-defective product information of the set Obtain the performance value of the target circuit based on each value and the performance value of the set, and based on the performance value of the first circuit and the non-defective product information indicating the non-defective product rate of the second circuit A function capable of calculating the performance value of the target circuit is generated from each acquired performance value of the target circuit, and each of the plurality of second random variables related to the design of the first circuit, From a plurality of first combination candidates of each value corresponding to a predetermined range of the yield rate The target calculated by giving to the generated function the performance value of the first circuit based on the first combination candidate and the non-defective product information indicating the non-defective product rate of the second circuit derived based on the first combination candidate A first combination of circuit performance values satisfying a predetermined condition is searched, and from a plurality of second combination candidates of each value corresponding to the non-defective product rate of the second circuit derived based on the first combination obtained by the search, A verification support program and a verification support method are proposed for searching for a second combination in which the performance value of the target circuit based on the performance value of the first circuit based on the first combination and the second combination candidate satisfies a predetermined condition. The

  According to one embodiment of the present invention, verification efficiency can be improved.

FIG. 1 is an explanatory diagram showing an operation example by the verification support apparatus according to the present invention. FIG. 2 is an explanatory diagram showing a circuit example of the memory cell and SA included in the SRAM. FIG. 3 is an explanatory diagram illustrating an example of a read time that is a performance index of the SRAM. FIG. 4 is a block diagram illustrating a hardware configuration example of the verification support apparatus. FIG. 5 is a block diagram illustrating a functional configuration of the verification support apparatus. FIG. 6 is an explanatory diagram showing an example of setting each design parameter of the memory cell. FIG. 7 is an explanatory diagram showing an example of worst case search. FIG. 8 is an explanatory diagram showing an example of the sampling result by each set. FIG. 9 is an explanatory diagram illustrating a setting example of each design parameter of the sense amplifier. FIG. 10 is a flowchart (part 1) illustrating an example of a verification support processing procedure by the verification support apparatus. FIG. 11 is a flowchart (part 2) of the verification support processing procedure example by the verification support apparatus.

  Embodiments of a verification support program and a verification support method according to the present invention will be described below in detail with reference to the accompanying drawings.

  FIG. 1 is an explanatory diagram showing an operation example by the verification support apparatus according to the present invention. The verification support apparatus 100 relates to a combination of values of a plurality of variables related to the design of the first circuit included in the verification target circuit and the design of the second circuit included in the target circuit, in which the performance value of the target circuit is the worst. The computer searches for combinations of values of a plurality of variables. For example, the verification target circuit is an SRAM, the first circuit is a sense amplifier, and the second circuit is a memory cell. The sense amplifier is an amplifier circuit that amplifies the potential difference between the bit lines of the memory cell.

For example, if the variation in transistor characteristics increases, the memory cell is likely to be defective. Examples of variations in transistor characteristics include manufacturing variations such as variations between chips and variations within a chip. In-chip variation is a variation in manufacturing for each transistor. The chip-to-chip variation is a manufacturing variation from chip to chip. Regarding the chip-to-chip variation, all the transistors in the chip are the same variation. Due to the miniaturization of transistors, there is a tendency that the variation between chips in which the characteristics of individual transistors vary randomly is larger than the variation between chips in which the characteristics of a plurality of transistors vary similarly. An SRAM is an analog circuit, and its performance largely depends on the balance of the characteristics of each transistor in the circuit. Therefore, the influence of on-chip variation on the SRAM yield is large. For example, as will be described later with reference to FIG. 2, the memory cell has six transistors. Here, the design parameters of the memory cell include, for example, a channel length L, a channel width W, a threshold voltage Vth, and the like for each transistor included in the memory cell. For example, as will be described later with reference to FIG. 2, the sense amplifier has five transistors. The design parameters of the sense amplifier include, for example, a channel length L, a channel width W, a threshold voltage Vth and the like for each transistor included in the sense amplifier. However, the value of the design parameter that becomes defective is a value that is different from the design value determined based on the specification. For example, in a 10 [MBit] SRAM, when the yield is 99 [%], the memory cell defect rate is (1/100) ^{1 / (10 · 10 6)} . 10 ^ 6 indicates 10 to the sixth power.

Thus, for example, in order to simultaneously analyze both the memory cell and the sense amplifier, there is a technique in which a large number of values of a plurality of design parameters of both the memory cell and the sense amplifier are randomly generated by Monte Carlo simulation. When the defect rate of one memory cell is about 10 ⁻⁹ , simulations of 1 billion times or more are required to obtain sufficient accuracy. As a result, it is possible to accurately identify the combination of the design parameter values at which the performance value of the SRAM is worst, but each time the design parameters are randomly generated, the analog operation of both the memory cell and the sense amplifier is simulated. Done. For example, a circuit simulator such as SPICE (Simulation Program with Integrated Circuit Emphasis) is used for analog operation simulation. For this reason, the accuracy of verification is increased, but the time required for specifying the combination of the parameter values of each transistor giving the worst performance becomes enormous. Here, the performance value of the SRAM is, for example, a read time T _read from the memory cell. The read time T _read is a time until the potential difference between the bit lines of the memory cell becomes the offset potential difference V _OS of the sense amplifier, as will be described later.

Further, there is a case where a combination having the worst read time _Tread is searched for among a plurality of combinations of values of a plurality of variables of the memory cells corresponding to the non-defective product rate designated in the entire SRAM. The search method here is a technique described in Patent Documents 1 and 2, for example. In this case, the performance value of the sense amplifier is treated as a fixed value when a simulation of the analog operation of the memory cell using the combination candidate is performed for each combination candidate of each value of the plurality of variables. The performance value of the sense amplifier is, for example, the offset potential difference V _OS of the sense amplifier. Here, for example, when the analog operation of the sense amplifier is simulated based on a combination of values of a plurality of variables of the sense amplifier corresponding to the non-defective product ratio designated in the entire SRAM, the worst offset potential difference is a fixed value. Are treated as

  In this way, combinations of values of a plurality of variables when both the sense amplifier and the memory cell are worst are specified. However, it is probabilistically low that the state in which the variation is the worst occurs in both the sense amplifier and the memory cell. For this reason, if each value of each variable having the worst variation is used for performance verification of a product using an SRAM, for example, if it is a read time, a delay margin increases in each performance verification. For example, in a high-performance server using SRAM, if the delay margin is large, the performance of the product is lower than the actual capacity.

  Therefore, in the present embodiment, the verification support apparatus 100 generates a function that can calculate the readout time. Then, the verification support apparatus 100 searches each value of a plurality of variables related to the design of the sense amplifier having the worst performance value obtained by the function, and finally uses the value to search for the cell having the worst performance value. Each value of a plurality of variables related to the design is searched from the search result. Thereby, an analysis with the same accuracy as the simultaneous analysis of the sense amplifier and the cell can be efficiently performed. Analysis efficiency is the analysis time for accuracy.

First, as shown in FIG. 1A, the verification support apparatus 100 acquires a plurality of sets of offset potential difference V _OS that is a performance value of the sense amplifier and non-defective product information that indicates a non-defective product rate of the memory cells. The non-defective product information is information indicating the non-defective product rate directly or indirectly. In the present embodiment, the non-defective product rate is represented by the yield or the z score of the performance value that is the boundary between the good product and the defective product. In the example of FIG. 1A, the good product rate is represented by the z score σ _C. The z-score is obtained by subtracting the average value from the sample value and dividing by the standard deviation for a sample value of the probability distribution given the average and standard deviation of the probability distribution. It is a value indicating how many standard deviations are separated from the value. The acquired non-defective product rate of the memory cells and the non-defective product rate of the sense amplifier are determined by, for example, the non-defective product rate designated for the entire SRAM.

Next, as shown in FIG. 1 (1), the verification support apparatus 100 corresponds to the z score σ _C for each of the plurality of sets, each value of the plurality of first variables related to the memory cell design. A read time T _read based on each value and the set offset potential difference is acquired. Each value corresponding to the z score σ _C corresponds to a set of z scores in the space spanned by the first random variable when the multiple first variables related to the memory cell design are the multiple first random variables. Each value of a plurality of first random variables on the equiprobability plane. There are a plurality of combinations of values corresponding to the z score σ _C. The acquired read time T _read is the longest read time T _read ^worst among the read times T _read obtained by the simulation of the analog operation of the memory cell based on each of the combinations. Here, the read time T _read acquired is the read time in the worst case obtained by the worst case search described in Patent Documents 1 and 2, for example. The worst case is a combination having the worst performance value as an index among combinations of values of variables. Since the details of the worst case and the space spanned by the first random variable are described in, for example, Patent Documents 1 and 2, detailed description thereof is omitted. Hereinafter, the simulation of the analog operation of the memory cell is omitted and referred to as memory cell simulation.

Then, as illustrated in FIG. 1B, the verification support apparatus 100 obtains a function that can calculate the read time T _read based on the offset potential difference V _OS and the z score σ _C and acquires each read time T _read. Generate by. Specifically, the verification support apparatus 100 generates the function by performing regression analysis on the read time T _read for each of the plurality of sets. Here, in the example of FIG. 1 (2), the generated function is expressed as f (V _OS , σ _C ), and given the offset potential difference V _OS and the z score σ _C , the longest read time T _read ^{The worst} can be calculated.

Then, as shown in FIG. 1 (3), the verification support apparatus 100 includes a plurality of values of a plurality of second variables relating to the design of the sense amplifier, each corresponding to a predetermined range of the non-defective product ratio of the sense amplifier. The first combination is searched from the first combination candidates. The predetermined range of the non-defective product rate of the sense amplifier is, for example, a range from 0 to the z score of the entire designated SRAM. In the first combination, an offset potential difference based on the first combination candidate and a z score of the memory cell derived based on the first combination candidate, and a read time T _read ^worst calculated by giving the generated function f satisfy a predetermined condition. The first combination candidate. The offset potential difference based on the first combination candidate is an offset potential difference obtained when a simulation of the analog operation of the sense amplifier is performed based on the first combination candidate. The first combination candidate whose read time T _read ^worst satisfies the predetermined condition is the first combination candidate with the longest read time T _read ^worst . As shown in FIG. 1 (3), when a plurality of second variables relating to the design of the sense amplifier are a plurality of second random variables x, each z score within a predetermined range in the space spanned by the second random variables is set. Each value of a plurality of second random variables on the corresponding equiprobability plane. In the example of FIG. 1 (3) shows the _{x 1} and _{x 2} as the second random variable. In the example of FIG. 1 (3), the combination of the values of the second random variables on the circle has the same z-score absolute value. The space spanned by the second random variable is described in, for example, Patent Documents 1 and 2, and the detailed description thereof is omitted. Further, hereinafter, the simulation of the analog operation of the sense amplifier is omitted and referred to as sense amplifier simulation.

Here, the verification support apparatus 100 searches for a combination having the ^worst read time T _read ^worst obtained by the function f by using the worst case search described in Patent Documents 1 and 2, for example. As described above, by using the function f, in the analysis of the sense amplifier, it is possible to indirectly calculate the read time _Tread without simultaneously analyzing the memory cell.

Then, the verification support apparatus 100 searches for a second combination from a plurality of second combination candidates of respective values corresponding to the yield rate of the memory cells derived based on the first combination obtained by the search. The second combination candidate is a second combination candidate in which the read time T _read based on the offset potential difference based on the first combination and the second combination candidate satisfies a predetermined condition. The read time T _read based on the offset potential difference based on the first combination and the second combination candidate is a read time obtained by simulating a memory cell based on the offset potential difference V _OS and the second combination candidate. The second combination candidate that satisfies the predetermined condition is a second combination candidate whose read time T _read is the longest read time T _read . The yield rate of memory cells derived based on the first combination obtained by the search is, for example, the z score σ calculated based on the z score σ _S corresponding to the first combination and the designated z score σ _{T. C.} As shown in FIG. 1 (4), each value of the plurality of first random variables y on the equiprobability plane corresponding to the derived z score σ _C in the space spanned by the first random variable y. In the example of FIG. 1 (4), y ₁ and y ₂ are shown as the first random variable y. Here, the verification support apparatus 100 uses the worst case search described in Patent Literatures 1 and 2 and the like to search for a combination having the worst read time _Tread .

  In this way, verification with the same accuracy as that of the simultaneous verification of the sense amplifier and the cell can be performed efficiently, and the verification efficiency is the analysis time for accuracy.

  FIG. 2 is an explanatory diagram showing a circuit example of the memory cell and SA included in the SRAM. As shown in FIG. 2, a plurality of memory cells cell and a sense amplifier SA that amplifies a potential difference between the first bit line BLT and the second bit line BLC of the plurality of memory cells cell are arranged in one column. The SRAM 200 has a plurality of columns.

The memory cell cell has six transistors Trc _{1 to} Trc ₆ . The transistors Trc ₃ and Trc ₅ are driver transistors and are NMOS. Transistors Trc ₁ and Trc ₆ are access transistors and are NMOS. The transistors Trc ₂ and Trc ₄ are load transistors and are PMOS. The gates of the transistors Trc ₁ and Trc ₄ are connected to a common word line. One terminal of the transistor Trc ₁ is connected to the first bit line BLT, and one terminal of the transistor Trc ₆ is connected to the second bit line BLC. The memory cell cell is connected to the power supply Vdd and the ground GND. Note that the potential of the ground GND is set to zero. When one of the internal nodes n1 and n2 of the memory cell cell is at a power supply potential or a value close thereto, the other is at a ground potential or a value close thereto, and depending on whether n1 or n2 is at a power supply potential or a value close thereto. The cell cell stores 1 and 0 information.

The sense amplifier SA shown in FIG. 2 is a latch-type sense amplifier, and has a configuration of a CMOS (Complementary Metal-Oxide-Semiconductor) inverter. The sense amplifier SA includes five transistors Trs _{1 to} Trs ₅ . The transistors Trs ₁ and Trs ₃ are PMOS. The transistors Trs ₂ and Trs ₄ are NMOS. Node d1 is connected to first bit line BLT, and node d2 is connected to second bit line BLC.

FIG. 3 is an explanatory diagram illustrating an example of a read time that is a performance index of the SRAM. The read time T _read is the time from the read start time to the time when the absolute value of the potential difference between the potential v1 of the first bit line BLT and the potential v2 of the second bit line BLC becomes the offset potential difference V _OS .

(Example of hardware configuration of verification support apparatus 100)
FIG. 4 is a block diagram illustrating a hardware configuration example of the verification support apparatus. 4, the verification support apparatus 100 includes a CPU (Central Processing Unit) 401, a ROM (Read Only Memory) 402, a RAM 403, a disk drive 404, and a disk 405. The verification support apparatus 100 includes an I / F (Inter / Face) 406, an input device 407, and an output device 408. Each unit is connected by a bus 400.

  Here, the CPU 401 governs overall control of the verification support apparatus 100. The ROM 402 stores programs such as a boot program. The RAM 403 is used as a work area for the CPU 401. The disk drive 404 controls reading / writing of data with respect to the disk 405 according to the control of the CPU 401. The disk 405 stores data written under the control of the disk drive 404. Examples of the disk 405 include a magnetic disk and an optical disk.

  The I / F 406 is connected to a network NET such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and is connected to other devices via the network NET. The I / F 406 manages an internal interface with the network NET, and controls data input / output from an external device. For example, a modem or a LAN adapter may be employed as the I / F 406.

  The input device 407 is an interface for inputting various data by a user operation such as a keyboard, a mouse, and a touch panel. The input device 407 can also capture images and moving images from the camera. The input device 407 can also capture audio from a microphone. The output device 408 is an interface that outputs data according to an instruction from the CPU 401. Examples of the output device 408 include a display and a printer.

(Functional configuration example of the verification support apparatus 100)
FIG. 5 is a block diagram illustrating a functional configuration of the verification support apparatus. The verification support apparatus 100 includes a control unit 501. Further, the verification support apparatus 100 obtains cell circuit information 502, SA circuit information 503, cell mounting number cn, SA mounting number sn, variation model information 504, designated yield, and the like as input data, and a first combination or The second combination is output.

  The cell circuit information 502 is circuit information indicating the memory cell cell, and includes, for example, information capable of executing a simulation of the memory cell cell. The cell circuit information 502 can set design parameters of the memory cell based on each of a plurality of first random variables related to the design of the memory cell cell. The SA circuit information 503 is circuit information indicating the sense amplifier SA, and includes, for example, information capable of executing a simulation of the sense amplifier SA. The SA circuit information 503 can set design parameters of the sense amplifier SA based on each of a plurality of second random variables related to the design of the sense amplifier SA.

  The cell mounting number cn is the number of memory cells cell included in the SRAM 200 to be verified. The SA mounting number sn is the number of sense amplifiers SA included in the SRAM 200 to be verified. The designated yield is a yield allowed in the SRAM 200 to be verified, and is a value determined by a verifier or a designer of the SRAM 200. The variation model information 504 is a model expression that can calculate the value of the first random variable by giving a z score for each of the first random variables, or the value of the second random variable by giving the z score for each of the second random variables. Has a model formula that can be calculated.

  The processing of the control unit 501 is coded in a verification support program stored in a storage device accessible by the CPU 401, for example. Then, the CPU 401 reads the verification support program from the storage device, and executes the processing coded in the verification support program. Thereby, the process of each part is implement | achieved. Further, the processing results of the respective units are stored in a storage device such as the RAM 403 and the disk 405, for example. The control unit 501 includes a model function generation unit 511, an SA worst case search unit 512, and a cell worst case search unit 513. Further, the control unit 501 can perform simulation of each of the sense amplifier SA and the memory cell cell by providing the SA circuit information 503 and the cell circuit information 502 to the circuit simulator 514. The circuit simulator 514 is, for example, SPICE.

  The verification support processing procedure in this embodiment is divided into procedures 1 to 3. In procedure 1, the verification support apparatus 100 performs a model function creation process. Next, in procedure 2, the verification support apparatus 100 performs the worst case first search process of the sense amplifier SA using the performance value obtained by the model function as an index. In step 3, the verification support apparatus 100 determines the memory cell cell based on the input offset potential difference based on the worst case obtained by the first search process and the non-defective product rate of the memory cell cell based on the worst case. The worst case second search process is performed. Here, the details of the procedure 1 will be described using the model function generation unit 511, the details of the procedure 2 will be described using the SA worst case search unit 512, and the details of the procedure 3 will be described as the cell worst case. A description will be given using the search unit 513.

<Procedure 1>
First, the model function generation unit 511 acquires non-defective product information indicating the non-defective product rate of the target circuit. Here, the verification target circuit is the SRAM 200. The non-defective product information indicating the non-defective product rate of the SRAM 200 is information indicating the non-defective product rate directly or indirectly. In the present embodiment, the non-defective product rate is represented by the yield or the z score of the performance value that is the boundary between the good product and the defective product obtained by the yield. Then, the model function generation unit 511 determines the range of the non-defective product ratio of the memory cell cell based on the non-defective product rate of the SRAM 200 indicated by the acquired non-defective product information and the value based on the number of sense amplifiers SA and the number of memory cells cell. To derive. The value based on the number of sense amplifiers SA and the number of memory cells cell is the number of cells per SA described later. Next, the model function generation unit 511 acquires a plurality of sets of the performance value of the sense amplifier SA and the non-defective product information indicating the non-defective product rate of the memory cell cell. The non-defective product information indicating the non-defective product rate of the memory cell cell is information indicating the non-defective product rate directly or indirectly. The non-defective product rate indicated by the non-defective product information of each of the plurality of sets is a value included in the derived non-defective product rate range of the memory cell cell.

Specifically, the model function generation unit 511 acquires the designated yield, the number of memory cells cell included in the SRAM 200, and the number of sense amplifiers SA included in the SRAM 200. The number of memory cells cell is referred to as cell mounting number cn, and the number of sense amplifiers SA is referred to as SA mounting number sn. Next, specifically, the model function generation unit 511 calculates the z score σ _T based on the designated yield. More specifically, the model function generation unit 511 calculates the z score σ _T by giving the designated yield ^{1 / SA} mounting number ^sn to a function that can calculate the z score based on the yield. A function that can calculate the z score based on the yield is referred to as a yield σ conversion function. Here, giving the designated yield ^{1 / SA} mounting number ^sn to the yield σ conversion function is also referred to as a yield σ conversion function (specified yield ^{1 / SA} mounting number ^sn ). A function that can calculate the yield based on the z score is shown in the following formula (1). A function that can calculate the yield based on the z score is referred to as a σ yield conversion function. The yield σ conversion function is represented by an inverse function of the σ yield conversion function. For example, when the designated yield is 0.998655, the z score is 3 (unit is standard deviation σ).

  Next, specifically, the model function generation unit 511 calculates the number of cells per sense amplifier SA. The number of cells per sense amplifier SA is referred to as the number of cells per SA. The model function generation unit 511 calculates the number of cells per SA by the following formula (2).

  Number of cells per SA = number of cells mounted cn / number of SA mounted sn (2)

Specifically, the model function generation unit 511 calculates the maximum value of the z score σ _C per memory cell cell. The maximum value of z score σ _C per memory cell cell is expressed as z score σ _C ^max . More specifically, the model function generation unit 511 calculates the z score σ _C ^max by the following equation (3).

σ _C ^max = yield σ conversion function (σ yield conversion function (σ _T ) ^{1 / number of cells per SA} ) (3)

The model function generation unit 511, for example, includes a plurality of offset potential differences V _OS included in the range [0, Vdd / 10] and z scores σ _C included in the range [0, σ _C ^max ]. Get a pair.

Next, for each of the plurality of sets, the model function generation unit 511 has each value of the plurality of first variables related to the design of the memory cell cell, each value corresponding to the non-defective product rate of the set, and the performance value of the set. The performance value of the SRAM 200 based on the above is acquired. Then, the model function generation unit 511 generates a function capable of calculating the performance value of the SRAM 200 based on the offset potential difference V _OS and the non-defective product information indicating the non-defective product rate of the memory cell cell, based on the acquired performance values of the SRAM 200. Specifically, the model function generation unit 511 includes a worst case search unit 521 and a fitting unit 522.

Specifically, for each of the plurality of sets, the worst case search unit 521 performs the performance value of the SRAM 200 based on the combination candidate of each value of the plurality of first variables corresponding to the z score σ _C of the set and the performance value of the set. Among them, a performance value satisfying a predetermined condition is searched. Here, the performance value satisfying the predetermined condition is, for example, the largest performance value. Here, there are a plurality of combination candidates for each value of the first variable.

  Here, for example, a plurality of first variables related to the design of the memory cell cell are set as a plurality of first random variables. Then, the worst case search unit 521 uses each of the plurality of first random variables in the equiprobability plane corresponding to the z score of the combination in the space spanned by the plurality of first random variables or in the region surrounded by the equiprobability plane. The worst case search is performed based on the value and the performance value of the combination. Further, for example, the plurality of first random variables are difference values from the design value, and the origin of the space spanned by the plurality of first random variables is the design value. The design value is a value determined by the specification. The worst case search by the worst case search unit 521 is the same as the worst case search of the performance value of the memory cell cell in the above-described Patent Documents 1 and 2, for example, and will be described briefly here.

  First, the worst case search unit 521 selects a plurality of first random variables on the equiprobability plane or in an area surrounded by the equiprobability plane corresponding to the z score of the combination in the space spanned by the plurality of first random variables. Get each value of. An equiprobability plane is a plane with the same z-score. For example, at the beginning of the search, the worst case search unit 521 acquires the design value or the initial value specified by the designer as the value of the first random variable. During the search, the value updated in the previous stage is acquired.

  Then, the worst case search unit 521 substitutes the obtained values of the plurality of first random variables into a model formula that can calculate each design parameter of the memory cell cell that can be set in the cell circuit information 502, thereby Each design parameter of the cell cell is set.

FIG. 6 is an explanatory diagram showing an example of setting each design parameter of the memory cell. For example, design parameters of the transistor Trc _i (i = 1 to 6) include a channel length Lc _i , a channel width Wc _i, and a threshold voltage Vthc _i . The channel length Lc _i ^d , the channel width Wc _i ^d, and the threshold voltage Vthc _i ^d are design values, respectively. y _j (j = 1 to 18) is a first random variable. SD _Lci , SD _Wci , and SD _vthci are standard deviations of the channel length Lc _i , channel width Wc _i , and threshold voltage Vthc _i (i = 1 to 6), respectively. For example, the channel length Lc ₁ is a design parameter of the transistor Trc _1, by substituting the first value of the random variable y _1, sets the channel length Lc ₁ included in the cell circuit information 502 indicating a memory cell cell.

The worst case search unit 521 shown in FIG. 5 performs a simulation of the memory cell cell based on the cell circuit information 502 after the setting and the offset potential difference V _OS of the set, thereby obtaining the performance value of the memory cell cell. get.

  FIG. 7 is an explanatory diagram showing an example of worst case search. The worst case search unit 521 illustrated in FIG. 5 performs a simulation of the memory cell cell when a predetermined amount is changed from the current value of each first random variable y for each first random variable y. The predetermined amount is a value determined by a verifier, for example. Then, the worst case search unit 521 calculates the gradient of the performance value of the memory cell cell for each of the first random variables y.

  Then, the worst case search unit 521 determines a design parameter based on each value of the plurality of first random variables y estimated that the performance value of the memory cell cell is deteriorated based on the gradient calculated for each of the first random variables y. Set. As described above, the worst case search unit 521 searches for the worst case by repeating the performance value calculation process and the gradient calculation process.

FIG. 8 is an explanatory diagram showing an example of the sampling result by each set. In the table 800, the worst case read time T _read ^worst is set for each of the set of the offset potential difference V _OS and the z score σ _C. In the example of FIG. 8, the range of [0, Vdd / 10] for the offset potential difference V _OS is 0.02 · Vdd, 0.04 · Vdd, 0.06 · Vdd, 0.08 · Vdd, 0.10 · It is divided into five stages of Vdd. The range of [0, σ _C ^max ] for the z score σ _C is 0, 0.2 · σ _C ^max , 0.4 · σ _C ^max , 0.6 · σ _C ^max , 0.8 · σ _C It is divided into five stages of ^max and 1.0 · σ _C ^max .

Next, the fitting unit 522 shown in FIG. 5 performs the read time T based on the offset potential difference V _OS and the z score σ _C of the memory cell cell by regression analysis using the read time T _read ^worst for each set. A model function f that can calculate _read ^worst is generated. The model function is expressed by, for example, the following formula (4). In Equation (4), a, b, and c are coefficients obtained by regression analysis.

T _read ^worst = a · V _OS + b · σ _C + c (4)

<Procedure 2>
The SA worst case search unit 512 determines a predetermined value from a plurality of first combination candidates of a plurality of second variables related to the design of the sense amplifier SA and each value corresponding to a predetermined range of the non-defective product ratio of the sense amplifier SA. A first combination that satisfies the condition is searched. The first combination is a first combination candidate in which the read time T _read ^worst obtained by the model function satisfies a predetermined condition. Here, the offset potential difference V _OS based on the first combination candidate and the z score σ _C of the memory cell derived based on the first combination candidate are given to the model function. The read time T _read ^worst is the predetermined condition is satisfied first combination, the read time T _read ^worst is the longest first combination. In this search for the first combination, instead of searching for the second random variable combination having the worst offset potential difference V _OS, the second random variable having the longest read time T _read ^worst obtained by giving to the model function. Search for combinations. Here, the predetermined range is [0, σ _T ].

For example, a plurality of second variables related to the design of the sense amplifier SA for calculating the offset potential difference V _OS are set as second random variables. The SA worst case search unit 512 reads the read time T obtained by the model function on the equiprobability plane or the area surrounded by the equiprobability plane corresponding to each of the predetermined ranges in the space spanned by the plurality of second random variables. _The worst case search is performed using _read ^worst as an index. The SA worst case search unit 512 uses a model that can calculate the second random variable for each of the second random variables included in the variation model information 504, and the second probability corresponding to any z score σ _s within a predetermined range. Get each value of a variable. The model that can calculate the second random variable is the same as the model that can calculate the first random variable described above.

  The SA worst case search unit 512 sets each design parameter of the sense amplifier SA based on the acquired values of the plurality of second random variables.

FIG. 9 is an explanatory diagram illustrating a setting example of each design parameter of the sense amplifier. For example, design parameters of the transistor Trs _m (m = 1 to 5) include a channel length Ls _m , a channel width Ws _m, and a threshold voltage Vths _m . The channel length Ls _m ^d , the channel width Ws _m ^d, and the threshold voltage Vths _m ^d are design values, respectively. x _n (n = 1 to 15) is a second random variable. SD _Lsm , SD _Wsm , and SD _Vthsm are standard deviations of the channel length Ls _m , the channel width Ws _m , and the threshold voltage Vths _m (m = 1 to 5), respectively. For example, the channel length Ls ₁ that is a design parameter of the transistor Trs ₁ sets the channel length Ls ₁ included in the circuit information indicating the memory cell cell by substituting the value of the second random variable x ₁ .

The SA worst case search unit 512 illustrated in FIG. 5 derives the offset potential difference V _OS by performing a simulation of the sense amplifier SA based on the SA circuit information 503 indicating the sense amplifier SA after setting. The SA worst case search unit 512 calculates the z score σ _C per memory cell cell based on the z score σ _s and the target z score σ _T. More specifically, the SA worst case search unit 512 can calculate the z score σ _C by the following equations (5) and (6).

σ _Ccol ² = σ _T ² _{−σ S} ² (5)
σ _C = yield σ conversion function (σ yield conversion function (σ _Ccol ) ^{number of cells per 1 / SA} ) (6)

σ _Ccol is the z score per column. The SA worst case search unit 512 calculates the read time T _read ^worst by substituting the derived offset potential difference V _OS and the z score σ _C into the model function f.

In addition, the SA worst case search unit 512 performs a simulation when a predetermined amount is changed from the current value of each second random variable x for each second random variable x. Then, the SA worst case search unit 512 calculates the gradient of the read time T _read ^worst for each of the second random variables x.

Then, the SA worst case search unit 512 sets design parameters based on the values of the plurality of second random variables that are estimated to deteriorate the read time T _read ^worst based on the gradient calculated for each of the second random variables. . In this manner, the SA worst case search unit 512 repeats the performance value calculation process and the gradient calculation process, thereby obtaining the first combination from the first combination candidates of the values of the plurality of second random variables. Explore. As described above, the worst case search is the same as in the prior art, and thus detailed description thereof is omitted.

<Procedure 3>
The cell worst case search unit 513 includes a plurality of second combination candidates for each value of the plurality of first random variables y corresponding to the yield rate of the memory cell cell derived based on the first combination obtained by the search. Search for the second combination. The second combination is a second combination candidate in which the performance value of the SRAM 200 based on the offset potential difference V _OS based on the first combination and the second combination candidate satisfies a predetermined condition. The z score σ _C, which is a non-defective product rate of the memory cell cell, can be calculated by the above formulas (5) and (6). In addition, the second combination candidate whose performance value of the SRAM 200 satisfies the predetermined condition is a second combination candidate whose performance value of the SRAM 200 is the worst.

Specifically, as described above, the cell worst case search unit 513 determines each design of the memory cell cell based on the second combination candidate of each value of the plurality of first random variables y corresponding to the non-defective product rate of the memory cell cell. A parameter is set in the cell circuit information 502. Then, the cell worst case search unit 513 derives the read time T _read by simulating the memory cell cell based on the offset potential difference V _OS based on the first combination and the cell circuit information 502 after setting. In this way, the cell worst case search unit 513 searches for a second combination having the longest derived read time T _read from a plurality of second combination candidates using the derived read time T _read as an index. Since the second combination search method is a conventional technique, a detailed description thereof will be omitted.

(Example of verification support processing procedure by the verification support apparatus 100)
10 and 11 are flowcharts illustrating an example of a verification support processing procedure performed by the verification support apparatus. First, the verification support apparatus 100 acquires cell circuit information 502 and SA circuit information 503 as input data (step S1001). The verification support apparatus 100 acquires the cell mounting number cn and the SA mounting number sn as input data (step S1002). The verification support apparatus 100 acquires the variation model information 504 and the specified yield (step S1003). Steps S1001 to S1003 may be performed simultaneously, and the order is not particularly limited.

The verification support apparatus 100 calculates σ _T = yield σ conversion function (designated yield ^{1 / SA mounted number sn} ) (step S1004). The verification support apparatus 100 performs the following operation: number of cells per SA = number of cells mounted cn / number of SA mounted sn (step S1005). The verification support apparatus 100 performs σ _C ^max = yield σ conversion function (σ yield conversion function (σ _T ) ^{1 / number of cells per SA} ) (step S1006). The verification support apparatus 100 generates a set P of representative points (V _OS , σ _C ) from the range [0, Vdd / 10] of the offset potential difference V _OS and the range [0, σ _C ^max ] of the z score σ _C. Obtain (step S1007).

The verification support apparatus 100 acquires T _read ^worst by performing a worst case search for each of the sets included in the set P (step S1008). The verification support apparatus 100 performs regression analysis based on each set included in the set P and the read time T _read ^worst acquired for the set, and generates f (V _OS , σ _C ) (step S1009).

The verification support apparatus 100 reads out the read time T _read calculated by the generated model function from the first combination candidates of the values of the second random variables corresponding to the range [0, σ _T ] of the z score σ _S of the sense amplifier SA. The first combination with the longest ^worst is searched (step S1101). As described above, the verification support apparatus 100 is obtained by simulating the sense score SA based on the z score σ _C derived based on the z score σ _S corresponding to the first combination candidate and the first combination candidate. The offset potential difference is given to the model function f. As a result, the verification support apparatus 100 calculates the read time T _read ^worst .

Next, the verification support apparatus 100 searches for the second combination from the second combination candidates of each value of the first random variable corresponding to the z score σ _C derived based on the first combination (step S1102). Here, as described above, z score sigma _C of the derived based on the first combination is a z score sigma _C derived on the basis of z scores sigma _S corresponding to the first candidate combinations, the above-mentioned formula (5) , (6) etc. The verification support apparatus 100 outputs the first combination, the offset potential difference based on the first combination, the second combination, and the read time T _read ^worst based on the second combination (step S1103), and ends the series of processes. To do.

  As described above, the verification support apparatus 100 generates a function capable of calculating the performance value of the SRAM, searches for the value of the sense amplifier variable having the worst performance value obtained by the function, and uses the search result. A search is made for the value of the variable of the cell having the worst performance value. As a result, the sense amplifier can be verified using the performance value of the SRAM as an index. Therefore, verification can be performed with the same degree of accuracy as the simultaneous analysis of the sense amplifier and the memory cell using the Monte Carlo simulation, and the verification time can be shortened compared to the Monte Carlo simulation. Therefore, the efficiency of verification can be improved.

  In addition, the verification support apparatus 100 determines the yield rate range of a plurality of sets of memory cells to be acquired based on the yield rate of the SRAM and the value based on the number of sense amplifiers and the number of memory cells included in the SRAM. Is derived. As a result, it is possible to generate a function that obtains a performance value that satisfies the non-defective product rate of the designated SRAM, and it is possible to improve the verification accuracy.

  In addition, the verification support apparatus 100 generates a function capable of calculating the performance value of the SRAM by regression analysis. As a result, a function for obtaining a performance value can be easily generated.

  Further, the predetermined range of the non-defective product rate of the sense amplifier when searching for the value of the sense amplifier variable is determined based on the non-defective product rate of the SRAM. Thereby, the value of each variable satisfying the good product rate of the SRAM can be searched, and the verification accuracy can be improved.

  Further, the verification support apparatus 100 determines, for each of a plurality of sets of the sense amplifier performance value and the memory cell non-defective rate, from the SRAM performance value based on each value corresponding to the non-defective product rate of the set and the performance value of the set. The performance value of the target circuit that satisfies the predetermined condition is acquired. As a result, a function can be generated with the worst performance value in each group, and verification accuracy can be improved.

  The verification support method described in the present embodiment can be realized by executing a verification support program prepared in advance on a computer such as a personal computer or a workstation. The verification support program is recorded on a computer-readable recording medium such as a magnetic disk, an optical disk, or a USB (Universal Serial Bus) flash memory, and is executed by being read from the recording medium by the computer. The verification support program may be distributed through a network such as the Internet.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary note 1)
Obtaining a plurality of sets of performance values of the first circuit included in the verification target circuit and non-defective product information indicating the non-defective product rate of the second circuit different from the first circuit included in the target circuit;
For each of the acquired plurality of sets, each value of a plurality of first random variables related to the design of the second circuit, each value corresponding to the non-defective product rate indicated by the non-defective product information of the set, and the set A performance value of the target circuit based on the performance value of
A function capable of calculating the performance value of the target circuit based on the performance value of the first circuit and the non-defective product information indicating the non-defective product rate of the second circuit is generated based on the acquired performance values of the target circuit. ,
Each value of a plurality of second random variables related to the design of the first circuit, from a plurality of first combination candidates of each value corresponding to a predetermined range of the non-defective product ratio of the first circuit, to the first combination candidate The performance value of the target circuit calculated by giving the generated function the non-defective product information indicating the non-defective product rate of the second circuit derived based on the first combination candidate Search for a first combination that satisfies the condition,
From a plurality of second combination candidates of each value corresponding to the non-defective product ratio of the second circuit derived based on the first combination obtained by the search, the performance value of the first circuit based on the first combination and the first Searching for a second combination in which the performance value of the target circuit based on two combination candidates satisfies a predetermined condition;
A verification support program characterized by causing processing to be executed.

(Supplementary note 2) The verification support program according to supplementary note 1, wherein the second circuit is a memory cell, and the first circuit is an amplifier circuit that amplifies between bit lines of the memory cell.

(Supplementary note 3) The verification support program according to supplementary note 2, wherein the performance value of the target circuit is a read time of the target circuit, and the performance value of the amplification circuit is an offset potential difference of the amplification circuit .

(Supplementary note 4)
Obtaining second non-defective product information indicating a non-defective product rate of the target circuit different from the non-defective product information (hereinafter referred to as “first non-defective product information”);
The second circuit based on the non-defective product rate indicated by the second non-defective product information, and a value based on the number of the first circuits included in the target circuit and the number of the second circuits included in the target circuit. Execute the process of deriving the yield rate range of
In the process of acquiring the plurality of sets, the first non-defective product information indicating the non-defective product rate of the second circuit selected from the performance value of the first circuit and the derived non-defective product rate range of the second circuit; The verification support program according to any one of appendices 1 to 3, wherein the plurality of sets are acquired.

(Additional remark 5) The process which produces | generates the said function is produced | generated by the regression analysis using each performance value of the acquired said target circuit, The verification assistance program as described in any one of Additional remarks 1-4 characterized by the above-mentioned.

(Appendix 6)
A process of acquiring second good product information indicating a good product rate of the target circuit different from the good product information (hereinafter referred to as “first good product information”);
The verification support program according to any one of appendices 1 to 5, wherein the predetermined range is based on the non-defective product rate indicated by the acquired second non-defective product information.

(Supplementary note 7) In the process of acquiring the performance value of the target circuit, for each of the acquired sets, each value corresponding to the non-defective product rate indicated by the non-defective product information of the set and the performance value of the set The verification support program according to any one of appendices 1 to 6, wherein the performance value of the target circuit satisfying a predetermined condition is acquired from the performance value of the target circuit based on the above.

(Appendix 8) The computer
Obtaining a plurality of sets of performance values of the first circuit included in the verification target circuit and non-defective product information indicating the non-defective product rate of the second circuit different from the first circuit included in the target circuit;
For each of the acquired plurality of sets, each value of a plurality of first random variables related to the design of the second circuit, each value corresponding to the non-defective product rate indicated by the non-defective product information of the set, and the set A performance value of the target circuit based on the performance value of
A function capable of calculating the performance value of the target circuit based on the performance value of the first circuit and the non-defective product information indicating the non-defective product rate of the second circuit is generated based on the acquired performance values of the target circuit. ,
Each value of a plurality of second random variables related to the design of the first circuit, from a plurality of first combination candidates of each value corresponding to a predetermined range of the non-defective product ratio of the first circuit, to the first combination candidate The performance value of the target circuit calculated by giving the generated function the non-defective product information indicating the non-defective product rate of the second circuit derived based on the first combination candidate Search for a first combination that satisfies the condition,
From a plurality of second combination candidates of each value corresponding to the non-defective product ratio of the second circuit derived based on the first combination obtained by the search, the performance value of the first circuit based on the first combination and the first Searching for a second combination in which the performance value of the target circuit based on two combination candidates satisfies a predetermined condition;
A verification support method characterized by executing processing.

(Supplementary Note 9) Acquire a plurality of sets of performance values of the first circuit included in the verification target circuit and non-defective product information indicating the non-defective product rate of the second circuit different from the first circuit included in the target circuit. ,
For each of the acquired plurality of sets, each value of a plurality of first random variables related to the design of the second circuit, each value corresponding to the non-defective product rate indicated by the non-defective product information of the set, and the set A performance value of the target circuit based on the performance value of
A function capable of calculating the performance value of the target circuit based on the performance value of the first circuit and the non-defective product information indicating the non-defective product rate of the second circuit is generated based on the acquired performance values of the target circuit. ,
Each value of a plurality of second random variables related to the design of the first circuit, from a plurality of first combination candidates of each value corresponding to a predetermined range of the non-defective product ratio of the first circuit, to the first combination candidate The performance value of the target circuit calculated by giving the generated function the non-defective product information indicating the non-defective product rate of the second circuit derived based on the first combination candidate Search for a first combination that satisfies the condition,
From a plurality of second combination candidates of each value corresponding to the non-defective product ratio of the second circuit derived based on the first combination obtained by the search, the performance value of the first circuit based on the first combination and the first Searching for a second combination in which the performance value of the target circuit based on two combination candidates satisfies a predetermined condition;
A recording medium on which a verification support program for causing a computer to execute processing is recorded.

100 Verification support device 200 SRAM
401 CPU
501 Control unit 502 Cell circuit information 503 SA circuit information 511 Model function generation unit 512 SA worst case search unit 513 Cell worst case search unit 514 Circuit simulator 521 Worst case search unit 522 Fitting unit y ₁ , y ₂ , y _j first probability Variables x ₁ , x ₂ , _xn Second random variables σ _C , σ _T , σ _S , σ _Ccol , σ _C ^max z score cell memory cell SA sense amplifier BLT first bit line BLC second bit line V _OS Offset potential difference cn Number of cells mounted Sn Number of SA mounted

Claims (6)

On the computer,
Obtaining a plurality of sets of performance values of the first circuit included in the verification target circuit and non-defective product information indicating the non-defective product rate of the second circuit different from the first circuit included in the target circuit;
For each of the acquired plurality of sets, each value of a plurality of first random variables related to the design of the second circuit, each value corresponding to the non-defective product rate indicated by the non-defective product information of the set, and the set A performance value of the target circuit based on the performance value of
A function capable of calculating the performance value of the target circuit based on the performance value of the first circuit and the non-defective product information indicating the non-defective product rate of the second circuit is generated based on the acquired performance values of the target circuit. ,
Each value of a plurality of second random variables related to the design of the first circuit, from a plurality of first combination candidates of each value corresponding to a predetermined range of the non-defective product ratio of the first circuit, to the first combination candidate The worst-case performance value of the target circuit calculated by giving the generated function the non-defective product information indicating the non-defective product rate of the second circuit derived based on the first combination candidate. searching a first combination of a,
Each value corresponding to the non- defective product information indicating the non-defective product rate of the second circuit derived based on the predetermined range of the non-defective product rate of the first circuit and the non-defective product information indicating the non-defective product rate of the first combination obtained by the search. A second combination in which the performance value of the target circuit based on the performance value of the first circuit based on the first combination and the second combination candidate is worst is searched from the plurality of second combination candidates of
A verification support program characterized by causing processing to be executed.   The verification support program according to claim 1, wherein the second circuit is a memory cell, and the first circuit is an amplifier circuit that amplifies between bit lines of the memory cell. In the computer,
Second non- defective product information indicating the non- defective product information indicating the non- defective product rate of the second circuit (hereinafter referred to as “first non-defective product information”) is acquired.
The second circuit based on the non-defective product rate indicated by the second non-defective product information, and a value based on the number of the first circuits included in the target circuit and the number of the second circuits included in the target circuit. Execute the process of deriving the yield rate range of
In the process of acquiring the plurality of sets, the first non-defective product information indicating the non-defective product rate of the second circuit selected from the performance value of the first circuit and the derived non-defective product rate range of the second circuit; The verification support program according to claim 1, wherein a plurality of sets are acquired. In the computer,
A process for acquiring second non-defective product information indicating the non- defective product rate indicating the non- defective product information indicating the non- defective product rate of the second circuit (hereinafter referred to as “first non-defective product information”);
The verification support program according to claim 1, wherein the predetermined range is based on the non-defective product rate indicated by the acquired second non-defective product information. In the process of acquiring the performance value of the target circuit, for each of the plurality of sets acquired, the target based on each value corresponding to the non-defective product rate indicated by the non-defective product information of the set and the performance value of the set The verification support program according to any one of claims 1 to 4, wherein the worst performance value of the target circuit is acquired from the performance value of the circuit. Computer
Obtaining a plurality of sets of performance values of the first circuit included in the verification target circuit and non-defective product information indicating the non-defective product rate of the second circuit different from the first circuit included in the target circuit;
For each of the acquired plurality of sets, each value of a plurality of first random variables related to the design of the second circuit, each value corresponding to the non-defective product rate indicated by the non-defective product information of the set, and the set A performance value of the target circuit based on the performance value of
A function capable of calculating the performance value of the target circuit based on the performance value of the first circuit and the non-defective product information indicating the non-defective product rate of the second circuit is generated based on the acquired performance values of the target circuit. ,
Each value of a plurality of second random variables related to the design of the first circuit, from a plurality of first combination candidates of each value corresponding to a predetermined range of the non-defective product ratio of the first circuit, to the first combination candidate The worst-case performance value of the target circuit calculated by giving the generated function the non-defective product information indicating the non-defective product rate of the second circuit derived based on the first combination candidate. searching a first combination of a,
Each value corresponding to the non- defective product information indicating the non-defective product rate of the second circuit derived based on the predetermined range of the non-defective product rate of the first circuit and the non-defective product information indicating the non-defective product rate of the first combination obtained by the search. A second combination in which the performance value of the target circuit based on the performance value of the first circuit based on the first combination and the second combination candidate is worst is searched from the plurality of second combination candidates of
A verification support method characterized by executing processing.

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