JP6255692B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  High performance of semiconductor devices such as LSI (Large Scale Integration) has been achieved by miniaturization of MOS transistors, which are basic components.

  However, with the miniaturization, it has become difficult to suppress the short channel effect, and the increase in off-current has become serious.

  Therefore, recently, a three-dimensional transistor (three-dimensional transistor) that has a three-dimensional channel and increases the gate control capability has been attracting attention.

  In a transistor having a three-dimensional structure, channels are formed on both side surfaces and an upper surface of a semiconductor layer (fin) formed so as to protrude on a substrate.

  According to a three-dimensional transistor, it is possible to reduce off-current, increase on-current, and suppress a short channel effect.

JP-A-2005-86024 US Pat. No. 7,326,634

T. Chiarella et al., “Simple Current and Capacitance Methods for Bulk FinFET Height Extraction And Correlation to Device Variability”, 2011 IEEE Conference on Microelectronic Test Structures, April 4-7, Amsterdam, The Netherlands.

  However, in the proposed transistor having a three-dimensional structure, variations in electrical characteristics may occur.

  An object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce variation in electrical characteristics of transistors.

According to one aspect of the embodiment, a step of forming a mask in a first region on a semiconductor substrate, a step of forming a recess in the semiconductor substrate by etching the semiconductor substrate using the mask, Forming an insulating layer on the semiconductor substrate and the mask; polishing the insulating layer to expose an upper surface of the mask; removing the mask; and the semiconductor in the first region A gap is generated between the first semiconductor layer and the insulating layer after the step of growing the first semiconductor layer having the inclined side surface on the substrate and the step of growing the first semiconductor layer. as the the steps of side etching of the insulating layer, wherein after the step of side etching of the insulating layer, said first semiconductor layer of the upper surface and the first semiconductor layer a gate insulating film so as sides to cover the Forming, it possesses a step of forming a gate electrode on the gate insulating layer, and forming a source / drain region in the first semiconductor layer on both sides of the gate electrode, removing the mask After the step, before the step of growing the first semiconductor layer, there is further provided a method for manufacturing a semiconductor device, further comprising a step of injecting impurities into the side surface of the insulating layer .

  According to the disclosed method for manufacturing a semiconductor device, a semiconductor layer having an inclined side surface is grown on a semiconductor substrate in a region defined by an insulating layer for element isolation. Since a gap is generated between the side surface of the semiconductor layer and the side surface of the insulating layer for element isolation, the side surface of the semiconductor layer is not covered with the insulating layer for element isolation. An insulating layer for element isolation is not sandwiched between them. Therefore, it is possible to obtain a semiconductor device having a transistor with a three-dimensional structure in which the gate electrode is surely opposed to the lower end of the semiconductor layer and the variation in electric characteristics is small.

FIG. 1 is a cross-sectional view showing the semiconductor device according to the first embodiment. FIG. 2 is a plan view showing the semiconductor device according to the first embodiment. FIG. 3 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 4 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 5 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 6 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 7 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 8 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 9 is a cross-sectional view (part 1) illustrating the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view (part 2) illustrating the semiconductor device according to the second embodiment. FIG. 11 is a plan view showing the semiconductor device according to the second embodiment. FIG. 12 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 13 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 14 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 15 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 16 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 17 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 18 is a process cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the reference example. FIG. 19 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the reference example. FIG. 20 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the reference example.

  18 to 20 are process cross-sectional views illustrating a method of manufacturing a semiconductor device according to a reference example.

  First, as shown in FIG. 18A, for example, a silicon oxide film 132 is formed on the entire surface of a silicon semiconductor substrate 110 by a thermal oxidation method, and then a CVD (Chemical Vapor Deposition) method is performed. Thus, a silicon nitride film 134 is formed. Next, the hard mask 134 is formed by patterning the silicon nitride film 134 and the silicon oxide film 132 using a photolithography technique. Next, the semiconductor substrate 110 is etched using the hard mask 134 as a mask, thereby forming element isolation grooves 112 (see FIG. 18B). Next, a silicon oxide film 114 is formed on the entire surface, and then the silicon oxide film 114 is polished by CMP (Chemical Mechanical Polishing) until the surface of the hard mask 134 is exposed (FIG. 18 (c)). Next, the silicon nitride film 134 is removed by etching, and the exposed silicon oxide film 132 is further removed by etching. Thus, the element isolation insulating layer 114 of the silicon oxide film is formed in the trench 112 (see FIG. 19A). Next, a semiconductor layer 118 made of, for example, silicon is grown on the exposed semiconductor substrate 10 (see FIG. 19B). Next, the upper portion of the silicon oxide film 114 is etched by, for example, dry etching (see FIG. 19C). Next, a gate insulating film 124 is formed on the upper surface and side surfaces of the semiconductor layer 118 by a thermal oxidation method (see FIG. 20A). Next, a polysilicon film 126 is formed by a CVD method, and then the polysilicon film 126 is patterned to form a polysilicon gate electrode 126 (see FIG. 20B). Thereafter, as shown in FIG. 20C, dopant impurities are introduced into the semiconductor layer 118 on both sides of the gate electrode 126 to form source / drain regions 128. FIG. 20C is a cross-sectional view along the longitudinal direction of the semiconductor layer 118. Thus, a semiconductor device having the three-dimensional transistor 130 having the gate electrode 126 and the source / drain region 128 is manufactured.

  In the semiconductor device according to the reference example, a part of the side surface of the semiconductor layer 118 is covered with the element isolation insulating layer 114 as shown in FIG. Therefore, as shown in FIG. 20B, a part of the element isolation insulating layer 114 is sandwiched between the semiconductor layer 118 and the gate electrode 126. The electrical characteristics of the transistor 130 vary depending on the in-plane variation in the etching amount of the element isolation insulating layer 114.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

(Semiconductor device)
First, the semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 1 is a sectional view of the semiconductor device according to the present embodiment. FIG. 2 is a plan view of the semiconductor device according to the present embodiment. 1A corresponds to the line AA ′ in FIG. 2, and FIG. 1B corresponds to the line BB ′ in FIG.

  Grooves (element isolation grooves and recesses) 12 are formed in the semiconductor substrate 10. For example, a silicon substrate is used as the semiconductor substrate 10. The depth of the groove 12 is, for example, about 50 to 250 nm.

  An insulating layer (insulating film) 14 for element isolation is formed in the groove 12. For example, a silicon oxide film is used as the insulating layer 14. An element isolation region is formed by the insulating layer 14 embedded in the groove 12. The upper part of the insulating layer 14 for element isolation may be convex as shown in FIG. 1 or may be flat.

  A semiconductor layer (body, fin) 18 having a thickness of, for example, about 15 to 60 nm is formed on the semiconductor substrate 10 in the element region 16 defined by the insulating layer 14 for element isolation. The semiconductor layer 18 is selectively epitaxially grown on the exposed surface of the semiconductor substrate 10 (selective epitaxial growth). The cross section of the semiconductor layer 18 is trapezoidal as a whole. The side surface of the semiconductor layer 18 is not perpendicular to the surface of the semiconductor substrate 10 but is inclined. That is, the semiconductor layer 18 has an inclination on the side surface. The angle formed between the upper surface and the side surface of the semiconductor layer 18 is an obtuse angle. The upper corner 20 of the semiconductor layer 18 is rounded. The semiconductor layer 18 is in a single crystal state, for example. The planar shape of the semiconductor layer 18 is, for example, a belt shape as shown in FIG. The width of the semiconductor layer 18, that is, the dimension of the semiconductor 18 in the left-right direction in FIG. 2 is, for example, about 5 to 20 nm. The length of the semiconductor layer 18, that is, the dimension of the semiconductor layer 18 in the vertical direction in FIG. 2 is, for example, about 200 to 500 nm.

  The side surface of the semiconductor layer 18 is not covered with the insulating layer 14 for element isolation. Since the side surface of the semiconductor layer 18 is not covered with the insulating layer 14 for element isolation, the insulating layer 14 for element isolation is not sandwiched between the gate electrode 26 and the semiconductor layers 18 and 22, Thus, the three-dimensional transistor 30 having a small variation in the physical characteristics can be obtained.

  A semiconductor layer 22 having a thickness of, for example, about 5 to 15 nm is formed on the upper surface and side surfaces of the semiconductor layer 18. As described above, the corner 20 at the top of the semiconductor layer 18 is rounded. Moreover, as described above, the angle formed between the upper surface and the lower surface of the semiconductor layer 18 is an obtuse angle. Therefore, according to the present embodiment, it is possible to form the high-quality semiconductor layer 22 on the semiconductor layer 18. As the material of the semiconductor layer 22, a material having a lattice constant different from that of the semiconductor layer 18 is used. By forming the semiconductor layer 22 having a lattice constant different from that of the semiconductor layer 18, stress can be generated in the semiconductor layer 22 and carrier mobility can be improved. When Si is used as the material of the semiconductor layer 18, for example, SiGe or SiC is used as the material of the semiconductor layer 22.

  The material of the semiconductor layer 22 is not limited to SiGe or SiC. A material having a lattice constant different from that of the semiconductor layer 18 can be appropriately used as the material of the semiconductor layer 22.

  On the upper surface and side surfaces of the semiconductor layer 22, for example, a gate insulating film 24 having a thickness of about 2 to 5 nm is formed. As the gate insulating film 24, for example, a silicon oxide film, a silicon nitride film, or the like is used.

  As the gate insulating film 24, a high dielectric constant material such as hafnium oxide may be used.

  A gate electrode 26 is formed on the semiconductor substrate 10 on which the semiconductor layers 18 and 22 and the gate insulating film 24 are formed. The planar shape of the gate electrode 26 is, for example, a belt shape as shown in FIG. The longitudinal direction of the gate electrode 26 intersects the longitudinal direction of the semiconductor layers 18 and 22. The gate electrode 26 is opposed to the upper and side surfaces of the semiconductor layers 18 and 22 with the gate insulating film 24 interposed therebetween. The thickness of the gate electrode 26, that is, the dimension between the upper surface of the semiconductor substrate 10 and the upper surface of the gate electrode 26 is, for example, about 10 to 30 nm. For example, polysilicon is used as the material of the gate electrode 26. In the case of an N-channel transistor, the conductivity type of the gate electrode 26 is N-type. In the case of a P-channel transistor, the conductivity type of the gate electrode 26 is P-type.

  The material of the gate electrode 26 is not limited to polysilicon. For example, a metal may be used as the material for the gate electrode 26. In the case of an N-channel transistor, for example, TaN, Ta, Al or the like is used as the material of the gate electrode 26. In the case of a P-channel transistor, for example, TiN, Ti, Al or the like is used as the material of the gate electrode 26.

  Source / drain regions 28 are formed in the semiconductor layers 18 and 22 on both sides of the gate electrode 26. In the case of an N-channel transistor, an N-type source / drain region 28 is formed. In the case of a P-channel type transistor, a P-type source / drain region 28 is formed.

  Thus, a semiconductor device having the three-dimensional transistor 30 having the gate electrode 26 and the source / drain region 28 is formed.

  Thus, according to the present embodiment, the side surfaces of the semiconductor layers 18 and 22 are inclined. Therefore, part of the side surfaces of the semiconductor layers 18 and 22 are not covered with the element isolation insulating layer 14, and the element isolation insulating layer 14 is provided between the semiconductor layers 18 and 22 and the gate electrode 26. It is not pinched. For this reason, according to the present embodiment, it is possible to obtain a semiconductor device having the three-dimensional transistor 30 in which the gate electrode 26 is reliably opposed to the lower ends of the semiconductor layers 18 and 22 and the variation in electrical characteristics is small.

  In addition, according to the present embodiment, the angle formed between the upper surface and the lower surface of the semiconductor layer 18 is an obtuse angle, and the corner 20 at the top of the semiconductor layer 18 is rounded. Therefore, according to the present embodiment, the high-quality semiconductor layer 22 can be formed on the upper surface and the side surface of the semiconductor layer 18. Since a high-quality semiconductor layer 22 can be formed, desired stress can be generated in the semiconductor layer 22 and carrier mobility can be improved.

(Method for manufacturing semiconductor device)
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 3 to 8 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, a silicon oxide film 32 of, eg, a thickness of about 10 to 20 nm is formed on the semiconductor substrate 10 by, eg, thermal oxidation. For example, a silicon substrate is used as the semiconductor substrate 10.

  Next, a silicon nitride film 34 having a thickness of, for example, about 40 to 100 nm is formed by, eg, CVD. The silicon nitride film 34 is for forming a mask (hard mask).

  Next, the silicon oxide film 34 and the silicon nitride film 32 are patterned using a photolithography technique. Thereby, a hard mask 34 of silicon nitride film is formed (see FIG. 3A). The hard mask 34 is etched away in a later step, and the semiconductor layer 18 is formed in a later step where the hard mask 34 is removed. Accordingly, the planar shape of the hard mask 34 is set to the planar shape of the semiconductor layer 18. The planar shape of the hard mask 34 is, for example, a band shape.

  Next, by using the hard mask 34 as a mask, the semiconductor substrate 10 is dry-etched to form grooves (recesses) 12 in the semiconductor substrate 10 (see FIG. 3B). The groove 12 is for forming the element isolation region 14. The depth of the groove 12 is, for example, about 50 to 250 nm.

  Next, an insulating layer 14 for element isolation having a thickness of, for example, about 100 to 300 nm is formed on the entire surface by, eg, CVD. As a material of the insulating layer 14 for element isolation, a material having etching characteristics different from that of the hard mask 34 is used. Here, for example, a silicon oxide film is formed as the insulating layer 14 for element isolation.

  Next, the insulating layer 14 for element isolation is polished by, for example, CMP until the surface of the hard mask 34 is exposed (see FIG. 4A).

  Next, the hard mask 34 is removed by wet etching, for example. For example, phosphoric acid is used as the etching solution.

  Next, the silicon oxide film 32 existing immediately below the hard mask 34 is removed by wet etching, for example (see FIG. 4B). When the silicon oxide film 32 is removed by etching, the surface of the insulating layer 14 for element isolation is also slightly etched, but the size of the insulating layer 14 for element isolation is sufficiently larger than the thickness of the silicon oxide film 32. Because it is large, no particular problem occurs.

  In this way, the surface of the semiconductor substrate 10 in the region 16 covered with the hard mask 34 is exposed. The upper part of the element isolation insulating layer 14 protrudes upward from the upper surface of the semiconductor substrate 10 (see FIG. 4B).

  Next, as shown in FIG. 5A, impurities are implanted from a direction oblique to the surface of the semiconductor substrate 10 by, eg, ion implantation (gradient ion implantation). The angle at which the impurity is implanted is set so that the impurity is not implanted into the exposed surface of the semiconductor substrate 10. The reason why impurities are not implanted into the exposed surface of the semiconductor substrate 10 is that when the impurities are implanted into the exposed surface of the semiconductor substrate 10, the source region 28 and the drain region 28 are formed on the surface of the semiconductor substrate 10. This is because there is a risk of an electrical short circuit through the impurity layer. In this way, impurity-implanted layers 14a into which impurities are implanted are formed on the upper surface and side surfaces of the isolation layer 14 for element isolation. The reason why the impurity is implanted into the upper surface and the side surface of the insulating layer 14 for element isolation is that the etching rate with respect to an etching solution such as hydrofluoric acid is increased in the portion where the impurity is implanted. If the etching rate is increased, the etching time can be shortened. When the etching time is shortened, the in-plane variation of the etching amount is reduced, and consequently the variation of the electrical characteristics of the three-dimensional transistor 30 is reduced. For example, phosphorus (P), arsenic (As), antimony (Sb), or the like can be used as an impurity to be implanted into the upper surface and side surfaces of the insulating layer 14 for element isolation.

  Next, a semiconductor layer (body) 18 having a thickness of, for example, about 15 to 60 nm is epitaxially grown on the surface of the semiconductor substrate 10 in the element region 16 defined by the element isolation region 14 (see FIG. 5B). For example, a silicon layer is formed as the semiconductor layer 18. At this time, it is preferable to grow the semiconductor layer 18 by selective epitaxial growth. The selective epitaxial growth is a growth method having high selectivity, in which the semiconductor layer 18 is selectively epitaxially grown on the exposed surface of the semiconductor substrate 10. The semiconductor layer 18 can be selectively epitaxially grown by appropriately setting the growth conditions when the semiconductor layer 18 is grown. If selective epitaxial growth is performed, the semiconductor layer 18 does not grow on the insulating layer 14 for element isolation, and the semiconductor layer 18 is selectively epitaxially grown on the surface of the semiconductor substrate 10 in the element region 16 defined by the element isolation region 14. To do.

The conditions for selective epitaxial growth are, for example, as follows. As the raw material gas, for example, _SiH 2 Cl ₂ (dichlorosilane) gas, _{H 2} gas, and, with HCl gas. The flow rate of the SiH ₂ Cl ₂ gas is, for example, about 10 to 50 slm (Standard liter per minute). The flow rate of H ₂ gas is, for example, about 20 to 50 slm. The flow rate of HCl gas is, for example, about 0.1 to 0.3 slm. The growth temperature is about 900 to 1000 ° C., for example. The pressure in the film forming chamber is, for example, about 10 to 20 Torr. When the semiconductor layer 18 is grown under such conditions, the semiconductor layer 18 is selectively epitaxially grown on the exposed surface of the semiconductor substrate 10.

  If the flow rate ratio of HCl gas in the source gas is set large, the growth selection ratio of the semiconductor layer 18 increases, and the growth of the semiconductor layer 18 on the insulating film 14 tends to be suppressed. On the other hand, if the flow rate ratio of HCl gas in the source gas is set small, the growth selection ratio of the semiconductor layer 18 is lowered, and the semiconductor layer 18 tends to grow on the insulating film 14. Accordingly, the flow rate ratio of HCl gas in the source gas is set to be small so that the semiconductor layer 18 is selectively epitaxially grown on the exposed surface of the semiconductor substrate 10.

  Thus, the single crystal semiconductor layer 18 is formed in, for example, a belt shape. The width of the semiconductor layer 18 is, for example, about 5 to 20 nm. The length of the semiconductor layer 18 is, for example, about 200 to 500 nm.

  When the semiconductor layer 18 is grown by selective epitaxial growth, the cross-sectional shape of the semiconductor layer 18 becomes a trapezoid as a whole. The side surface of the semiconductor layer 18 is not perpendicular to the surface of the semiconductor substrate 10 but is inclined. Therefore, a gap is generated between the side surface of the semiconductor layer 18 and the side surface of the element isolation insulating layer 14. The angle formed between the upper surface and the side surface of the semiconductor layer 18 is an obtuse angle. Thus, the semiconductor layer 18 whose side surface is not in contact with the side surface of the element isolation insulating layer 14 is formed.

  Next, a silicon oxide film 36 having a thickness of about 5 to 10 nm is formed on the upper surface and side surfaces of the semiconductor layer 18 by thermal oxidation (see FIG. 6A). The silicon oxide film 36 can function as a sacrificial oxide film.

  Next, the upper part of the insulating layer 14 for element isolation is etched (see FIG. 6B). As the etching method, for example, wet etching is used. For example, hydrofluoric acid is used as the etchant. Since the side surface of the semiconductor layer 18 and the side surface of the element isolation insulating layer 14 are not in contact with each other, the etchant is supplied to the gap between the semiconductor layer 18 and the element isolation insulating layer 14. Therefore, etching proceeds not only from the upper surface of the element isolation insulating layer 14 but also from the side surfaces of the element isolation insulating layer 14. Further, as described above, impurities are introduced into the upper surface and the side surface of the insulating layer 14 for element isolation, and the etching rates with respect to etching solutions such as hydrofluoric acid are compared on the upper surface and the side surface of the insulating layer 14 for element isolation. Is getting faster. Therefore, the etching time for etching the upper portion of the element isolation insulating layer 14 is relatively short. Since the etching time is relatively short, the in-plane variation of the etching amount is relatively small, and hence the variation in the electrical characteristics of the three-dimensional transistor 30 is small. The etched upper surface of the element isolation insulating layer 14 may be convex as shown in FIG. 6B or may be flat. When the upper portion of the insulating layer 14 for element isolation is etched, the silicon oxide film 36 formed on the upper surface and side surfaces of the semiconductor layer 18 is also removed by etching. After the silicon oxide film 36 is removed by etching, the upper corner of the semiconductor layer 18 is rounded as shown in FIG.

  Although the case where only wet etching is used when etching the upper portion of the insulating layer 14 for element isolation has been described here as an example, dry etching and wet etching may be combined. As the dry etching, for example, RIE (Reactive Ion Etching) method or the like can be used. Since the silicon oxide film 36 formed on the upper and side surfaces of the semiconductor layer 18 is formed by a thermal oxidation method, the etching rate is slower than that of the insulating layer 14 for element isolation formed by the CVD method. Therefore, during dry etching, the silicon oxide film 36 formed on the upper surface and side surfaces of the semiconductor layer 18 can function as a protective film for the semiconductor layer 18. Since the silicon oxide film 36 functions as a protective film, damage to the semiconductor layer 18 can be prevented even when dry etching is performed. Although the etching rate of the silicon oxide film 36 is slower than the etching rate of the element isolation insulating layer 14, the silicon oxide film 36 is also gradually etched in the process of etching the element isolation insulating layer 14. If the film thickness of the silicon oxide film 36 becomes too thin, the semiconductor layer 18 cannot be sufficiently protected. Therefore, it is not preferable to etch the upper part of the element isolation insulating layer 14 only by dry etching. Therefore, the dry etching for the element isolation insulating layer 14 is completed before the silicon oxide film 36 becomes excessively thin. Then, the insulating layer 14 for element isolation is further etched by wet etching. When the insulating layer 14 for element isolation is further etched by wet etching, the silicon oxide films 36 on the upper surface and side surfaces of the semiconductor layer 18 are also removed by etching.

  In this manner, the upper portion of the element isolation insulating layer 14 may be etched by combining dry etching and wet etching.

  Next, a semiconductor layer 22 having a thickness of, for example, about 5 to 15 nm is epitaxially grown on the upper surface and side surfaces of the semiconductor layer 18 (see FIG. 7A). As the material of the semiconductor layer 22, a material having a lattice constant different from that of the semiconductor layer 18 is used. By forming the semiconductor layer 22 having a lattice constant different from that of the semiconductor layer 18, stress can be generated in the semiconductor layer 22 and carrier mobility can be improved. The upper corner of the semiconductor layer 18 has an obtuse angle and is rounded. Therefore, a good semiconductor layer 22 can be formed on the semiconductor layer 18. Since a favorable semiconductor layer 22 can be formed, desired stress can be generated and carrier mobility can be sufficiently improved. When the material of the semiconductor layer 18 is Si, for example, SiGe or SiC can be used as the material of the semiconductor layer 22.

The growth conditions when SiGe is used as the material of the semiconductor layer 22 are, for example, as follows. That is, the pressure in the chamber is, for example, about 1 × 10 ⁻³ to 1 × 10 ⁻¹ Pa. The substrate temperature is about 450 to 650 ° C., for example. As source gas, Si ₂ H ₆ gas and GeF ₄ gas are used. The flow rate ratio between Si ₂ H ₆ gas and GeF ₄ gas is, for example, in the range of 40: 1 to 80: 1.

When SiC is used as the material of the semiconductor layer 22, the semiconductor layer 22 is grown as follows. That is, first, the carbonization process is performed under the following conditions. The pressure in the chamber is, for example, about 10 Torr. As the source gas, H ₂ gas and C ₃ H ₈ gas are used. The flow rate of H ₂ gas is, for example, about 1.0 liter / min. The flow rate of the C ₃ H ₈ gas is about 10 sccm. For example, after rapid heating to 1150 ° C. in 2 minutes, carbonization is performed for about 2 minutes, for example. After the carbonization step, SiC is grown under the following conditions. The pressure in the chamber is, for example, about 10 Torr. The substrate temperature is about 1150 ° C., for example. As the source gas, H ₂ gas, C ₃ H ₈ gas, and SiH ₄ gas are used. The flow rate of H ₂ gas is, for example, about 8.0 liters / minute. The flow rate of the C ₃ H ₈ gas is about 1.33 sccm. The flow rate of the SiH ₄ gas is, for example, about 0.8 sccm.

  The material of the semiconductor layer 22 is not limited to SiGe or SiC. A material having a lattice constant different from that of the semiconductor layer 18 can be appropriately used as the material of the semiconductor layer 22. For example, when the material of the semiconductor layer 18 is SiGe or SiC, Si or the like may be used as the material of the semiconductor layer 22.

  Next, a gate insulating film 24 having a film thickness of, for example, about 2 to 5 nm is formed on the upper surface and side surfaces of the semiconductor layer 22 by, eg, thermal oxidation (see FIG. 7B). For example, a silicon oxide film or a silicon nitride film is formed as the gate insulating film 24.

  As the gate insulating film 24, a high dielectric constant film such as hafnium oxide may be formed.

  Next, a polysilicon film 26 of, eg, a thickness of about 10 to 30 nm is formed by, eg, CVD.

  Next, the polysilicon film is patterned using a photolithography technique. As a result, a polysilicon gate electrode 26 is formed (see FIG. 8). The planar shape of the gate electrode 26 is, for example, a band shape. The pattern of the gate electrode 26 is formed so that the longitudinal direction of the gate electrode 26 and the longitudinal direction of the semiconductor layer 18 intersect each other.

  Next, dopant impurities are introduced into the semiconductor layer 18 on both sides of the gate electrode 26 by, for example, ion implantation using the gate electrode 26 as a mask. As a result, source / drain regions 28 are formed in the semiconductor layers 18 and 22 on both sides of the gate electrode 26. At this time, dopant impurities are also introduced into the gate electrode 26. In the case of forming the N-channel transistor 30, an N-type dopant impurity is introduced into the gate electrode 26 and the source / drain region 28. On the other hand, when forming a P-channel transistor 30, a P-type dopant impurity is introduced into the gate electrode 26 and the source / drain region 28.

  Thereafter, heat treatment for activating the dopant impurities introduced into the gate electrode 26 and the source / drain regions 28 is performed.

  Thus, the semiconductor device according to the present embodiment having the three-dimensional transistor 30 is manufactured.

  As described above, according to the present embodiment, the semiconductor layer 18 having an inclined side surface is grown on the region defined by the element isolation insulating layer 14, and therefore, the side surfaces of the semiconductor layer 18 and the element isolation insulating layer are grown. A gap is formed between the two. For this reason, according to the present embodiment, a part of the side surface of the semiconductor layer 18 is not covered with the element isolation insulating layer 14, and the element isolation insulating layer 14 is connected to the semiconductor layers 18 and 22 and the gate. It is not in a state of being sandwiched between the electrodes 26. According to the present embodiment, since the gate electrode 26 is surely opposed to the lower ends of the semiconductor layers 18 and 22, the three-dimensional transistor 30 with small variation in electrical characteristics can be obtained.

  Further, according to the present embodiment, when the upper portion of the element isolation insulating layer 14 is etched, an etchant is formed in the gap between the side surface of the element isolation insulating layer 14 and the side surface of the semiconductor layer 18. Is supplied. Therefore, etching proceeds not only from the upper surface of the element isolation insulating layer 14 but also from the side surfaces of the element isolation insulating layer 14. Further, according to the present embodiment, since impurities are introduced into the upper surface and side surfaces of the element isolation insulating layer 14, the etching rate with respect to an etching solution such as hydrofluoric acid is fast on the upper surface and side surfaces of the element isolation insulating layer 14. It has become. Therefore, according to the present embodiment, the upper portion of the element isolation insulating layer 14 can be etched in a relatively short time. Since the etching time is relatively short, the in-plane variation of the etching amount can be reduced. A small in-plane variation in the etching amount contributes to a reduction in variation in electrical characteristics.

  Thus, according to the present embodiment, a semiconductor device having the three-dimensional transistor 30 with small variation in electrical characteristics can be provided.

[Second Embodiment]
The semiconductor device and the manufacturing method thereof according to the second embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 8 are denoted by the same reference numerals, and description thereof is omitted or simplified.

(Semiconductor device)
First, the semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 9 is a first cross-sectional view of the semiconductor device according to the present embodiment. FIG. 10 is a cross-sectional view (part 2) of the semiconductor device according to the present embodiment. FIG. 11 is a plan view of the semiconductor device according to the present embodiment. 9 corresponds to the AA 'line in FIG. 11, FIG. 10 (a) corresponds to the BB' line in FIG. 11, and FIG. 10 (b) corresponds to the CC 'line in FIG. Corresponds to the line.

  In the semiconductor device according to the present embodiment, impurity layers 38 a and 38 b are formed on the semiconductor substrate 10 in the region 16 immediately below the semiconductor layer 18.

  A region 2A on the left side in FIG. 9 indicates a region where the N-channel transistor 30a is formed, and a region 2B on the right side in FIG. 9 indicates a region where the P-channel transistor 30b is formed. Yes.

  Impurity layers 38 a and 38 b are formed in the semiconductor substrate 10 in the element region 16 defined by the element isolation region 14. In the region 2A where the N-channel transistor is formed, the conductivity type of the impurity layer 38a is P-type. In the region 2B where the P-channel transistor is formed, the conductivity type of the impurity layer 38b is N-type.

  A semiconductor layer 22a is formed on the upper surface and side surfaces of the semiconductor layer 18 in the region 2A where the N-channel transistor is formed. As the material of the semiconductor layer 22a, a material having a lattice constant smaller than that of the semiconductor layer 18 is used. By forming the semiconductor layer 22a having a lattice constant smaller than that of the semiconductor layer 18, a tensile stress can be generated in the semiconductor layer 22a, and carrier mobility can be improved. When the material of the semiconductor layer 18 is Si, for example, SiC or the like can be used as the material of the semiconductor layer 22a.

  A semiconductor layer 22b is formed on the top and side surfaces of the semiconductor layer 18 in the region 2B where the P-channel transistor is formed. As the material of the semiconductor layer 22b, a material having a lattice constant larger than that of the semiconductor layer 18 is used. By forming the semiconductor layer 22b having a lattice constant larger than that of the semiconductor layer 18, a compressive stress can be generated in the semiconductor layer 22b, and carrier mobility can be improved. In the case where the material of the semiconductor layer 18 is Si, for example, SiGe or the like can be used as the material of the semiconductor layer 22b.

  In the region 2A where the N-channel transistor is formed, an N-type dopant impurity is introduced into the gate electrode 26a and the source / drain region 28a.

  In the region 2B where the P-channel transistor is formed, a P-type dopant impurity is introduced into the gate electrode 26b and the source / drain region 28b.

  Thus, an N-channel type three-dimensional transistor 30a having the gate electrode 26a and the source / drain regions 28a is formed. A P-channel type three-dimensional transistor 30b having a gate electrode 26b and source / drain regions 28b is formed.

  As described above, according to the present embodiment, the impurity layers 38 a and 38 b having the conductivity type opposite to that of the source / drain regions 28 a and 28 b are formed on the semiconductor substrate 10 in the region 16 immediately below the semiconductor layer 28. Yes. For this reason, according to this embodiment, it is possible to reliably prevent the source regions 28 a and 28 b and the drain regions 28 a and 28 b from being short-circuited via the semiconductor substrate 10.

(Method for manufacturing semiconductor device)
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 12 to 17 are process cross-sectional views illustrating the semiconductor device manufacturing method according to the present embodiment.

  First, from the step of forming the silicon oxide film 32 on the semiconductor substrate 10 to the step of removing the hard mask 34, the semiconductor device according to the first embodiment described above with reference to FIGS. 3A to 4B is used. Since it is the same as that of a manufacturing method, description is abbreviate | omitted.

  Next, a photoresist film 40 is formed on the entire surface by, eg, spin coating.

  Next, an opening 42 exposing the region 2A where the N-channel transistor is to be formed is formed in the photoresist film 40 by using a photolithography technique.

Next, using the photoresist film 40 as a mask, a P-type dopant impurity is introduced into the upper and side surfaces of the element isolation insulating layer 14 and the surface of the semiconductor substrate 10 in the opening 42 by, for example, ion implantation (see FIG. 12 (a)). At this time, the dopant impurity is inclined with respect to the surface of the semiconductor substrate 10 so that the P-type dopant impurity is introduced into the upper surface and side surfaces of the insulating layer 14 for element isolation in the opening 42 and the surface of the semiconductor substrate 10. (Tilted ion implantation). For example, BF ₂ (boron fluoride) is used as the P-type dopant impurity. Thus, the P-type impurity layer 38 a is formed in the semiconductor substrate 10 in the element region 16 defined by the element isolation region 14. Further, an impurity implantation layer 14b in which a P-type impurity is implanted is formed on the upper surface and side surfaces of the element isolation insulating layer 14.

  Thereafter, the photoresist film 40 is removed by, for example, ashing.

  Next, a photoresist film 44 is formed on the entire surface by, eg, spin coating.

  Next, an opening 46 exposing the region 2B where the P-channel transistor is to be formed is formed in the photoresist film 44 by using a photolithography technique.

  Next, using the photoresist film 44 as a mask, an N-type dopant impurity is introduced into the upper surface and side surfaces of the insulating layer 14 for element isolation and the surface of the semiconductor substrate 10 in the opening 46 by, for example, ion implantation (FIG. 12 (b)). At this time, the dopant impurity is inclined with respect to the surface of the semiconductor substrate 10 so that the N-type dopant impurity is introduced into the upper surface and side surfaces of the insulating layer 14 for element isolation in the opening 46 and the surface of the semiconductor substrate 10. Inject. For example, P, As, Sb, or the like is used as the N-type dopant impurity. Thus, an N-type impurity layer 38 b is formed in the semiconductor substrate 10 in the element region 16 defined by the element isolation region 14. In addition, an impurity implantation layer 14 c in which an N-type impurity is implanted is formed on the upper surface and side surfaces of the element isolation insulating layer 14.

  Thereafter, the photoresist film 44 is removed by, for example, ashing.

  The subsequent steps from the step of forming the semiconductor layer 18 to the etching of the upper portion of the element isolation insulating layer 14 are according to the first embodiment shown in FIGS. 5B to 6B. Since it is the same as the manufacturing method of a semiconductor device, description is abbreviate | omitted.

  Next, a silicon oxide film 48 having a thickness of about 10 to 20 nm is formed on the entire surface by, eg, CVD.

  Next, a silicon nitride film 50 having a thickness of about 20 to 40 nm is formed on the entire surface by, eg, CVD.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

  Next, using a photolithography technique, a planar opening (not shown) of the semiconductor layer 18 is formed in the photoresist film in the region 2A where the N-channel transistor is to be formed.

  Next, the silicon nitride film 50 is etched by wet etching, for example, using the photoresist film as a mask and the silicon oxide film 48 as an etching stopper. For example, phosphoric acid is used as the etching solution. Thus, an opening 52 is formed in the silicon nitride film 50.

  Next, the silicon oxide film 48 exposed in the opening 52 is removed by, for example, wet etching. For example, hydrofluoric acid is used as the etchant.

  Next, a semiconductor layer 22a having a thickness of, for example, about 5 to 15 nm is epitaxially grown on the top and side surfaces of the semiconductor layer 18 in the region 2A where the N-channel transistor is formed (see FIG. 13A). As a material of the semiconductor layer 22a, a material having a lattice constant smaller than that of the semiconductor layer 18 is used. By forming the semiconductor layer 22a having a lattice constant smaller than that of the semiconductor layer 18, a tensile stress can be generated in the semiconductor layer 22a, and carrier mobility can be improved. The upper corner of the semiconductor layer 18 has an obtuse angle and is rounded. For this reason, a good semiconductor layer 22 a can be formed on the semiconductor layer 18. Since a favorable semiconductor layer 22a can be formed, desired stress can be generated in the semiconductor layer 22a, and carrier mobility can be sufficiently improved. When the material of the semiconductor layer 18 is Si, for example, SiC or the like can be used as the material of the semiconductor layer 22a.

  The material of the semiconductor layer 22a is not limited to SiC. A material having a lattice constant smaller than that of the semiconductor layer 18 can be appropriately used as the material of the semiconductor layer 22a. For example, when the material of the semiconductor layer 18 is SiGe, Si may be used as the material of the semiconductor layer 22a.

  Thus, the semiconductor layer 22a is formed on the upper surface and the side surface of the semiconductor layer 18.

  Next, using the silicon oxide film 48 as an etching stopper, the silicon nitride film 50 is removed by wet etching, for example. For example, phosphoric acid is used as the etching solution.

  Next, the silicon oxide film 48 is removed by etching, for example, by wet etching. For example, hydrofluoric acid is used as the etchant.

  Next, a silicon oxide film 54 having a thickness of about 10 to 20 nm is formed on the entire surface by, eg, CVD.

  Next, a silicon nitride film 56 having a thickness of about 20 to 40 nm is formed on the entire surface by, eg, CVD.

  Next, a photoresist film (not shown) is formed on the entire surface by spin coating.

  Next, using a photolithography technique, a planar opening (not shown) of the semiconductor layer 18 is formed in the photoresist film in the region 2B where the P-channel transistor is to be formed.

  Next, the silicon nitride film 56 is etched by wet etching, for example, using the photoresist film as a mask and the silicon oxide film 54 as an etching stopper. For example, phosphoric acid is used as the etching solution. Thus, an opening 58 is formed in the silicon nitride film 56.

  Next, the silicon oxide film 54 exposed in the opening 58 is removed by etching, for example, by wet etching. For example, hydrofluoric acid is used as the etchant.

  Next, a semiconductor layer 22b having a thickness of, for example, about 5 to 15 nm is epitaxially grown on the upper surface and side surfaces of the semiconductor layer 18 in the region 2B where the P-channel transistor is formed (see FIG. 13B). As the material of the semiconductor layer 22b, a material having a lattice constant larger than that of the semiconductor layer 18 is used. By forming the semiconductor layer 22b having a lattice constant larger than that of the semiconductor layer 18, a compressive stress can be generated in the semiconductor layer 22b, and carrier mobility can be improved. The upper corner of the semiconductor layer 18 has an obtuse angle and is rounded. For this reason, a good semiconductor layer 22 b can be formed on the semiconductor layer 18. Since a favorable semiconductor layer 22b can be formed, desired stress can be generated in the semiconductor layer 22b, and carrier mobility can be sufficiently improved. In the case where the material of the semiconductor layer 18 is Si, for example, SiGe or the like can be used as the material of the semiconductor layer 22b.

  Note that the material of the semiconductor layer 22b is not limited to SiGe. A material having a lattice constant larger than that of the semiconductor layer 18 can be appropriately used as the material of the semiconductor layer 22b. For example, when the material of the semiconductor layer 18 is SiC, Si may be used as the material of the semiconductor layer 22b.

  Thus, the semiconductor layer 22b is formed on the upper surface and the side surface of the semiconductor layer 18.

  Next, using the silicon oxide film 54 as an etching stopper, the silicon nitride film 56 is removed by wet etching, for example. For example, phosphoric acid is used as the etching solution.

  Next, the silicon oxide film 54 is removed by etching, for example, by wet etching. For example, hydrofluoric acid is used as the etchant.

  Next, the gate insulating film 24 is formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment described above with reference to FIG. 7B (see FIG. 14A).

  Next, a polysilicon film 26 of, eg, a thickness of about 10 to 30 nm is formed by, eg, CVD.

  Next, the polysilicon film 26 is patterned using a photolithography technique. As a result, a polysilicon gate electrode 26 is formed (see FIG. 14B). The planar shape of the gate electrode 26 is, for example, a band shape. The pattern of the gate electrode 26 is formed so that the longitudinal direction of the gate electrode 26 and the longitudinal direction of the semiconductor layer 18 intersect each other.

  Next, a photoresist film 60 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 60 is patterned using a photolithography technique. As a result, an opening 62 opening the region 2A where the N-channel transistor is to be formed is formed in the photoresist film 60.

  Next, using the photoresist film 60 and the gate electrode 26 as a mask, N-type dopant impurities are introduced into the semiconductor layers 18 and 22a on both sides of the gate electrode 26 by, for example, ion implantation. As a result, N-type source / drain regions 28a are formed in the semiconductor layers 18 and 22a on both sides of the gate electrode 26a. At this time, an N-type dopant impurity is also introduced into the gate electrode 26a.

  Thus, an N-channel type three-dimensional transistor 30a having the gate electrode 26a and the source / drain regions 28a is formed (see FIG. 15).

  Thereafter, the photoresist film 60 is removed by, for example, ashing.

  Next, a photoresist film 64 is formed on the entire surface by, eg, spin coating.

  Next, the photoresist film 64 is patterned using a photolithography technique. As a result, an opening 66 opening the region 2B where the P-channel transistor is to be formed is formed in the photoresist film 64.

  Next, using the photoresist film 64 and the gate electrode 26 as a mask, a P-type dopant impurity is introduced into the semiconductor layers 18 and 22b on both sides of the gate electrode 26 by, for example, ion implantation. Thus, P-type source / drain regions 28b are formed in the semiconductor layers 18 and 22b on both sides of the gate electrode 26b. At this time, a P-type dopant impurity is also introduced into the gate electrode 26b.

  Thus, a P-channel type three-dimensional transistor 30b having the gate electrode 26b and the source / drain regions 28b is formed (see FIG. 16).

  Thereafter, the photoresist film 64 is removed by, for example, ashing.

  Thereafter, heat treatment for activating the dopant impurities introduced into the gate electrodes 26a and 26b and the source / drain regions 28a and 28b is performed.

  Thus, the semiconductor device according to the present embodiment having the N-channel type three-dimensional transistor 30a and the P-channel type three-dimensional transistor 30b is manufactured (see FIG. 17).

  As described above, the impurity layers 38 a and 38 b may be formed in the semiconductor substrate 10 in the region 16 immediately below the semiconductor layer 18. As a result, the source regions 28a and 28b and the drain regions 28a and 28b can be reliably prevented from being short-circuited via the semiconductor substrate 10, and a highly reliable semiconductor device can be provided.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the first embodiment, impurities are introduced into the upper surface and side surfaces of the element isolation insulating layer 14, but it is not necessary to introduce impurities into the upper surfaces and side surfaces of the element isolation insulating layer 14.

2A ... A region where an N-channel transistor is formed 2B ... A region where a P-channel transistor is formed 10 ... Semiconductor substrate 12 ... Groove 14 ... Insulating layers, element isolation regions 14a to 14c ... Implanted layers 16 ... Element region 18 ... Semiconductor layer 20 ... corners 22, 22a, 22b ... semiconductor layer 24 ... gate insulating films 26, 26a, 26b ... gate electrodes 28, 28a, 28b ... source / drain regions 30 ... transistor 30a ... N-channel transistor 30b ... P-channel Type transistor 32 ... silicon oxide film 34 ... silicon nitride film 36 ... silicon oxide films 38a and 38b ... impurity layer 40 ... photoresist film 42 ... opening 44 ... photoresist film 46 ... opening 48 ... silicon oxide film 50 ... silicon nitride Film 52 ... Opening 54 ... Silicon oxide film 56 ... Silicon nitride film 58 ... Opening 60 ... photoresist film 62 ... opening 64 ... photoresist film 66 ... opening

Claims (6)

Forming a mask in a first region on the semiconductor substrate;
Etching the semiconductor substrate using the mask to form a recess in the semiconductor substrate;
Forming an insulating layer on the semiconductor substrate and on the mask;
Polishing the insulating layer to expose an upper surface of the mask;
Removing the mask;
Growing a first semiconductor layer having an inclined side surface on the semiconductor substrate in the first region;
Etching a side surface of the insulating layer so that a gap is formed between the first semiconductor layer and the insulating layer after the step of growing the first semiconductor layer;
After the step of etching the side surface of the insulating layer, forming a gate insulating film so as to cover the upper surface of the first semiconductor layer and the side surface of the first semiconductor layer;
Forming a gate electrode on the gate insulating film;
Have a forming source / drain regions in the first semiconductor layer on both sides of the gate electrode,
A method of manufacturing a semiconductor device, further comprising the step of implanting impurities into the side surface of the insulating layer after the step of removing the mask and before the step of growing the first semiconductor layer . In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein in the step of growing the first semiconductor layer, the first semiconductor layer is selectively grown on the semiconductor substrate in the first region by selective epitaxial growth. In the manufacturing method of the semiconductor device of Claim 1 or 2 ,
The impurity has a conductivity type opposite to that of the source / drain region,
In the step of injecting the impurity, the impurity is also injected into the semiconductor substrate in the first region. In the manufacturing method of the semiconductor device according to any one of claims 1 to 3 ,
After the step of growing the first semiconductor layer and before the step of etching the side surface of the insulating layer, the upper surface of the first semiconductor layer and the side surface of the first semiconductor layer are formed by thermal oxidation. A step of forming an oxide film on
In the step of etching the side surface of the insulating layer, the side surface of the insulating layer is etched by wet etching, and the oxide film is removed by etching. Forming a mask in a first region on the semiconductor substrate;
Etching the semiconductor substrate using the mask to form a recess in the semiconductor substrate;
Forming an insulating layer on the semiconductor substrate and on the mask;
Polishing the insulating layer to expose an upper surface of the mask;
Removing the mask;
Growing a first semiconductor layer having an inclined side surface on the semiconductor substrate in the first region;
Etching a side surface of the insulating layer so that a gap is formed between the first semiconductor layer and the insulating layer after the step of growing the first semiconductor layer;
After the step of etching the side surface of the insulating layer, forming a gate insulating film so as to cover the upper surface of the first semiconductor layer and the side surface of the first semiconductor layer;
Forming a gate electrode on the gate insulating film;
Forming source / drain regions in the first semiconductor layer on both sides of the gate electrode,
After the step of growing the first semiconductor layer and before the step of etching the side surface of the insulating layer, the upper surface of the first semiconductor layer and the side surface of the first semiconductor layer are formed by thermal oxidation. A step of forming an oxide film on
The step of etching the side surface of the insulating layer includes the step of etching the insulating layer by dry etching while protecting the first semiconductor layer by the oxide film, and further etching the insulating layer by wet etching. And a step of etching away the oxide film. A method of manufacturing a semiconductor device, comprising: Forming a mask in a first region on the semiconductor substrate;
Etching the semiconductor substrate using the mask to form a recess in the semiconductor substrate;
Forming an insulating layer on the semiconductor substrate and on the mask;
Polishing the insulating layer to expose an upper surface of the mask;
Removing the mask;
Growing a first semiconductor layer having an inclined side surface on the semiconductor substrate in the first region;
Etching a side surface of the insulating layer so that a gap is formed between the first semiconductor layer and the insulating layer after the step of growing the first semiconductor layer;
After the step of etching the side surface of the insulating layer, forming a gate insulating film so as to cover the upper surface of the first semiconductor layer and the side surface of the first semiconductor layer;
Forming a gate electrode on the gate insulating film;
Forming source / drain regions in the first semiconductor layer on both sides of the gate electrode,
After the step of etching the side surface of the insulating layer and before the step of forming the gate insulating film, the first surface of the first semiconductor layer and the side surface of the first semiconductor layer are formed on the first surface of the first semiconductor layer. A method for manufacturing a semiconductor device, further comprising forming a second semiconductor layer having a lattice constant different from that of the semiconductor layer.

Images