JP6254617B2 - 改良3dトーラス - Google Patents

改良3dトーラス Download PDF

Info

Publication number
JP6254617B2
JP6254617B2 JP2015558103A JP2015558103A JP6254617B2 JP 6254617 B2 JP6254617 B2 JP 6254617B2 JP 2015558103 A JP2015558103 A JP 2015558103A JP 2015558103 A JP2015558103 A JP 2015558103A JP 6254617 B2 JP6254617 B2 JP 6254617B2
Authority
JP
Japan
Prior art keywords
torus
data traffic
host
node
nodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2015558103A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016513321A5 (enExample
JP2016513321A (ja
Inventor
フリッカー ジャン−フィリップ
フリッカー ジャン−フィリップ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2016513321A publication Critical patent/JP2016513321A/ja
Publication of JP2016513321A5 publication Critical patent/JP2016513321A5/ja
Application granted granted Critical
Publication of JP6254617B2 publication Critical patent/JP6254617B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356Indirect interconnection networks
    • G06F15/17368Indirect interconnection networks non hierarchical topologies
    • G06F15/17393Indirect interconnection networks non hierarchical topologies having multistage networks, e.g. broadcasting scattering, gathering, hot spot contention, combining/decombining
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/10Flow control; Congestion control
    • H04L47/24Traffic characterised by specific attributes, e.g. priority or QoS
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/54Store-and-forward switching systems 
    • H04L12/56Packet switching systems
    • H04L12/5691Access to open networks; Ingress point selection, e.g. ISP selection
    • H04L12/5692Selection among different networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Between Computers (AREA)
JP2015558103A 2013-02-13 2014-02-12 改良3dトーラス Active JP6254617B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/766,115 US9424229B2 (en) 2013-02-13 2013-02-13 Parallel torus network interconnect
US13/766,115 2013-02-13
PCT/US2014/016045 WO2014127012A1 (en) 2013-02-13 2014-02-12 Enhanced 3d torus

Publications (3)

Publication Number Publication Date
JP2016513321A JP2016513321A (ja) 2016-05-12
JP2016513321A5 JP2016513321A5 (enExample) 2017-03-16
JP6254617B2 true JP6254617B2 (ja) 2017-12-27

Family

ID=50280464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015558103A Active JP6254617B2 (ja) 2013-02-13 2014-02-12 改良3dトーラス

Country Status (6)

Country Link
US (1) US9424229B2 (enExample)
EP (1) EP2956866A1 (enExample)
JP (1) JP6254617B2 (enExample)
KR (1) KR102031269B1 (enExample)
CN (1) CN105051717B (enExample)
WO (1) WO2014127012A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101995056B1 (ko) 2015-12-30 2019-07-02 한국전자통신연구원 분산 파일 시스템 및 이의 운영방법
KR102025801B1 (ko) 2016-01-26 2019-09-26 한국전자통신연구원 분산 파일 시스템 및 이의 데이터 내결함성 지원 방법
KR102610984B1 (ko) * 2017-01-26 2023-12-08 한국전자통신연구원 토러스 네트워크를 이용하는 분산 파일 시스템 및 토러스 네트워크를 이용하는 분산 파일 시스템의 운영 방법
CN107645744B (zh) * 2017-09-11 2021-06-22 深圳市盛路物联通讯技术有限公司 物联网通信方法及第一中继器
CN107612805B (zh) * 2017-09-11 2021-01-26 深圳市盛路物联通讯技术有限公司 物联网通信方法及物联网网关
US11531637B2 (en) * 2020-03-26 2022-12-20 Graphcore Limited Embedding rings on a toroid computer network

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5689719A (en) 1991-06-28 1997-11-18 Sanyo Electric O., Ltd. Parallel computer system including processing elements
US5592610A (en) 1994-12-21 1997-01-07 Intel Corporation Method and apparatus for enhancing the fault-tolerance of a network
US7433931B2 (en) * 2004-11-17 2008-10-07 Raytheon Company Scheduling in a high-performance computing (HPC) system
US20060146825A1 (en) * 2004-12-30 2006-07-06 Padcom, Inc. Network based quality of service
JP2006215816A (ja) * 2005-02-03 2006-08-17 Fujitsu Ltd 情報処理システムおよび情報処理システムの制御方法
GB2424545A (en) * 2005-03-24 2006-09-27 Orange Personal Comm Serv Ltd Packet radio communications system where at least one ran is arranged to operate with a different communication standard than the other rans
US7797664B2 (en) * 2006-06-23 2010-09-14 National Institute Of Advanced Industrial Science And Technology System for configuring an integrated circuit and method thereof
WO2008114440A1 (ja) * 2007-03-20 2008-09-25 Fujitsu Limited 一意情報集団通信プログラム、コンピュータ、一意情報集団通信方法、および記録媒体
US7644254B2 (en) 2007-04-18 2010-01-05 International Business Machines Corporation Routing data packets with hint bit for each six orthogonal directions in three dimensional torus computer system set to avoid nodes in problem list
EP2286546B1 (en) * 2008-06-13 2014-01-15 Telefonaktiebolaget L M Ericsson (PUBL) Network traffic transfer between a radio base station node and a gateway node
CN101656861B (zh) * 2009-09-14 2012-07-18 中兴通讯股份有限公司 一种录制节目的方法和多媒体系统
US8612386B2 (en) * 2011-02-11 2013-12-17 Alcatel Lucent Method and apparatus for peer-to-peer database synchronization in dynamic networks

Also Published As

Publication number Publication date
EP2956866A1 (en) 2015-12-23
KR102031269B1 (ko) 2019-10-11
US9424229B2 (en) 2016-08-23
KR20150118170A (ko) 2015-10-21
JP2016513321A (ja) 2016-05-12
US20140226479A1 (en) 2014-08-14
CN105051717A (zh) 2015-11-11
CN105051717B (zh) 2018-05-15
WO2014127012A1 (en) 2014-08-21

Similar Documents

Publication Publication Date Title
JP6254617B2 (ja) 改良3dトーラス
US10084692B2 (en) Streaming bridge design with host interfaces and network on chip (NoC) layers
US9253085B2 (en) Hierarchical asymmetric mesh with virtual routers
RU2543558C2 (ru) Способ и усройство маршрутизации ввода-вывода и карта
US9825809B2 (en) Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
US9160627B2 (en) Multiple heterogeneous NoC layers
US10050843B2 (en) Generation of network-on-chip layout based on user specified topological constraints
JP2005318495A (ja) 異なる仮想チャネルへのトランザクションの分離
CN110495137A (zh) 分布式交换机上的可扩展数据中心网络拓扑
US11100040B2 (en) Modular remote direct memory access interfaces
CN107430574A (zh) 用于分析系统的io、处理和存储器带宽的优化的方法和装置
US10523599B2 (en) Buffer sizing of a NoC through machine learning
CN112188325A (zh) 使用具有一对多光交换机的光网络的可重新配置的计算平台
CN105224501B (zh) 改进圆环面网络及其确定数据包传输路径的方法和装置
CN107018071B (zh) 一种基于“包-电路”交换技术的路由模式切换配置器
US9774498B2 (en) Hierarchical asymmetric mesh with virtual routers
US9762474B2 (en) Systems and methods for selecting a router to connect a bridge in the network on chip (NoC)
CN119743450B (zh) 片上网络的报文传输方法、装置、电子设备及存储介质
Morimoto et al. Design and implementation of SDN-enhanced MPI broadcast targeting a fat-tree interconnect
US9928204B2 (en) Transaction expansion for NoC simulation and NoC design
HK40081215A (en) Reconfigurable computing pods using optical networks with one-to-many optical switches
HK40081215B (zh) 使用具有一对多光交换机的光网络的可重新配置的计算平台
CN118656335A (zh) 具有连接板的计算系统
HK40044238B (en) Reconfigurable computing pods using optical networks with one-to-many optical switches
HK40044238A (en) Reconfigurable computing pods using optical networks with one-to-many optical switches

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151008

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20151013

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170206

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20170206

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20170206

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20170404

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170418

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170711

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170808

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20171030

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20171107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20171130

R150 Certificate of patent or registration of utility model

Ref document number: 6254617

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250