JP6249401B2 - Communication apparatus and communication system - Google Patents

Description

  The present invention relates to a communication device and a communication system.

  2. Description of the Related Art In recent years, communication systems that transmit and receive data with a relatively small capacity wirelessly, such as near field communication (Near Field Communication), RFID (Radio Frequency Identification) communication, and M2M (Machine to Machine) communication are known. Conventionally, a method using a Manchester code in which a state transition of a logical value always occurs within one bit is disclosed so that a clock can be easily reproduced even when the receiver continuously receives data of the same value (for example, , See Patent Document 1).

  In addition, the first waveform is assigned to data of logical value “0”, the second waveform is assigned to data of non-continuous logical value “1”, and logical value “ 11 "is also disclosed in which a third waveform is assigned to perform communication (see, for example, Patent Document 2).

JP 2011-215865 A Japanese Patent No. 3803364

  FIG. 19 shows a data string encoded by the Manchester code used in the conventional communication method. By using a Manchester code that always causes a logical state transition within one bit, even if the distance between the transmitter and the receiver fluctuates, it is difficult to synchronize the clock and tolerate noise-resistant communication. can do.

  However, in the data string using the Manchester code, the rising timing of data (timing of state transition from the logical value “0” to the logical value “1”) changes depending on the data string to be transmitted / received. Such a clock recovery circuit is required. When the clock recovery circuit is used to recover the clock, there is a problem that power consumption increases and a startup time is required until the clock recovery circuit is locked.

  FIG. 20 shows a data string encoded using the third waveform used in the conventional communication method. In the data string shown in FIG. 20, the first waveform, the second waveform, and the third waveform are used so that the rising timing of the data becomes a constant period. Therefore, compared to the case where the rising timing of the data changes, It is easy to reproduce a clock with a fixed period. However, a specific method for decoding data without using a clock recovery circuit such as a phase locked loop circuit has not been studied.

  Therefore, the present invention has been made in view of these points, and a communication device that can decode received data without using a clock recovery circuit such as a phase-locked loop circuit, and an encoding that can be decoded by the communication device. An object of the present invention is to provide a communication device that generates data.

  The communication device according to the first aspect of the present invention corresponds to the first encoded data corresponding to the first waveform transmitted from another communication device, and any one of the second waveform, the third waveform, and the fourth waveform. A communication device that receives and decodes encoded data including second encoded data that changes to a second level according to a first state transition in a second waveform and a first state transition in a third waveform And a signal generator for generating a composite signal that changes to a first level in response to the first state transition in the first waveform immediately after the second waveform and the first state transition in the first waveform immediately after the fourth waveform; An output unit that outputs decoded data obtained by synchronizing the synthesized signal with the first state transition timing in the encoded data. The second waveform is assigned to a single second encoded data sandwiched between a plurality of first encoded data, and the third waveform is a plurality of continuous second encoded data. The fourth waveform is assigned to the last second encoded data among a plurality of continuous second encoded data.

  The first sandwiched between the first second encoded data of the plurality of consecutive second encoded data and the last second encoded data of the plurality of consecutive second encoded data. For example, one of the first waveform and the second waveform is assigned to the 2 encoded data.

  The second waveform includes, for example, a first polarity pulse before the first state transition and a second polarity pulse having a polarity different from the first polarity after the first state transition. For example, includes a first polarity pulse before the first state transition, and the fourth waveform includes a second polarity pulse after the first state transition.

  The width of the first polarity pulse of the third waveform is equal to the width of the second polarity pulse of the fourth waveform, and the second encoded data of the third waveform and the second encoded data of the fourth waveform May be equal to the length of the first level period before the first state transition and the length of the second level period after the first state transition.

  The signal generator generates, for example, a first synchronization signal obtained by synchronizing the inverted signal obtained by inverting the encoded data with the first state transition timing of the delayed signal obtained by delaying the encoded data by a predetermined delay time. A first synchronization unit that generates a second synchronization signal in which the delay signal is synchronized with the first state transition timing of the encoded data, and a first state transition of the second synchronization signal And a synthesizing unit that generates a synthesized signal that changes to the second level according to the first state and changes to the first level according to the second state transition of the first synchronization signal.

  The first synchronization unit includes, for example, an inverting circuit that generates an inverted signal obtained by inverting the encoded data, a delay circuit that generates a delayed signal by delaying the encoded data, and the inverted signal is input to the data input terminal. And a first flip-flop circuit to which the delay signal generated by the delay circuit is input to the clock terminal, and the second synchronization unit inputs the delay signal to the data input terminal and A second flip-flop circuit in which the digitized data is input to the clock terminal.

  The first synchronization unit outputs an inverting circuit that generates an inverted signal obtained by inverting the encoded data, a high-pass filter that receives the inverted signal, a low-pass filter that receives the encoded data, and a high-pass filter. And a first flip-flop circuit to which a delayed signal output from the low-pass filter is input to the clock terminal, and the second synchronization unit is configured to input the delayed signal to the data input terminal. You may have the 2nd flip-flop circuit which is input into a terminal and encoded data is input into a clock terminal.

  The first synchronization unit includes an inverting circuit that generates an inverted signal obtained by inverting the encoded data, a high-pass filter to which the inverted signal is input, a bandpass filter to which the encoded data is input, and a high-pass filter. A first flip-flop circuit in which a signal to be output is input to the data input terminal and a delay signal output from the bandpass filter is input to the clock terminal, and the second synchronization unit includes the delay signal May be input to the data input terminal, and the second flip-flop circuit may be provided in which the encoded data is input to the clock terminal.

  The signal generating unit synchronizes the inverted signal obtained by inverting the encoded data with the first state transition timing of the first delay signal obtained by delaying the encoded data by a predetermined first delay time. And a second synchronization signal generated by synchronizing a second delay signal obtained by delaying the encoded data by a predetermined second delay time at a first state transition timing of the encoded data. And a synthesized signal that changes to the second level according to the first state transition of the second synchronization signal and changes to the first level according to the second state transition of the first synchronization signal. And a synthesizing unit to be generated.

  The first synchronization unit receives an inverting circuit that generates an inverted signal obtained by inverting encoded data, a first low-pass filter to which encoded data is input, and a signal output from the first low-pass filter. A logic circuit; and a first flip-flop circuit in which the inverted signal is input to the data input terminal and a delay signal output from the logic circuit is input to the clock terminal. The unit includes a second low-pass filter to which encoded data is input, a second flip-flop circuit in which a signal output from the second low-pass filter is input to a data input terminal, and the encoded data is input to a clock terminal You may have.

  The signal generation unit generates a first synchronization signal that inverts the encoded data and synchronizes the encoded data with the first state transition timing of the delayed signal delayed by a predetermined delay time. A synchronization unit, a second synchronization unit for generating a second synchronization signal in which the delay signal is synchronized with the first state transition timing of the inverted signal obtained by inverting the encoded data, and a second synchronization signal A combining unit that generates a combined signal that changes to the second level in response to the first state transition and changes to the first level in response to the second state transition of the first synchronization signal.

  The delay time is, for example, larger than the width of the first polarity pulse and the width of the second polarity pulse. In addition, the second waveform, the third waveform, and the fourth waveform change from the first level to the second level at the respective central positions, and the delay time is half of the period of the first encoded data and the second encoded data. It may be shorter than the length of.

  The communication apparatus according to the second aspect of the present invention includes encoded data including first encoded data corresponding to input data having a first logical value and second encoded data corresponding to input data having a second logical value. A first waveform corresponding to the first encoded data, a second waveform corresponding to a single second encoded data sandwiched between a plurality of the first encoded data, continuous Corresponding to the third waveform corresponding to the first second encoded data among the plurality of second encoded data and the last second encoded data among the plurality of continuous second encoded data. A waveform generation unit that generates a fourth waveform, a selection unit that selects one waveform from the first waveform, the second waveform, the third waveform, and the fourth waveform based on the pattern of the input data; Is provided.

  For example, the selection unit includes a first delay signal obtained by delaying the input data by a first delay time, a second delay signal obtained by delaying the input data by a second delay time, and a third delay of the input data. A delay circuit that generates a third delay signal delayed by time, and based on the first delay signal, the second delay signal, and the third delay signal, the first waveform, the second waveform, And a selection circuit that selects one waveform from the third waveform and the fourth waveform.

  A communication system according to a third aspect of the present invention is a communication system including a first communication device and a second communication device, and corresponds to a first waveform transmitted from the second communication device. The first communication device that receives and decodes the encoded data and the encoded data including the second encoded data corresponding to any of the second waveform, the third waveform, and the fourth waveform includes the second waveform, Generates a composite signal that changes to the second level according to the first state transition in the third waveform and changes to the first level according to the first state transition in the first waveform immediately after the second and fourth waveforms. A signal generating unit that outputs the decoded data obtained by synchronizing the synthesized signal with the first state transition timing in the encoded data, and the second communication device receives the first communication device. The first encoding corresponding to the first waveform Chromatography comprising data and second waveform, the transmission unit for transmitting the encoded data including the second coded data corresponding to one of the third waveform and the fourth waveform. The second waveform is assigned to a single second encoded data sandwiched between a plurality of first encoded data, and the third waveform is a plurality of continuous second encoded data. The fourth waveform is assigned to the last second encoded data among a plurality of continuous second encoded data.

  According to the present invention, it is possible to decode received data without using a clock recovery circuit such as a phase-locked loop circuit.

It is a figure which shows the structure of the communication system of 1st Embodiment. It is a figure which shows the kind of waveform of the encoding data transmitted / received between several communication apparatuses. It is a figure which shows the structure of the encoding part which concerns on 1st Embodiment. It is a figure which shows the structure of a waveform generation part. It is a figure which shows the structure of a selection part. FIG. 6 is a timing chart showing a procedure for generating encoded data in the encoding unit shown in FIGS. 3 to 5. It is a figure which shows the structure of the decoding part which concerns on 1st Embodiment. FIG. 8 is a timing chart showing a procedure for converting encoded data into decoded data in the decoding unit shown in FIG. 7. It is a figure which shows the structure of the decoding part which concerns on 2nd Embodiment. FIG. 10 is a timing chart showing a procedure for converting encoded data into decoded data in the decoding unit shown in FIG. 9. It is another example of the timing diagram which shows the procedure which converts into the decoding data from coding data in the decoding part which concerns on said embodiment. It is a figure which shows the structure of the 1st synchronization part which concerns on 4th Embodiment. It is a figure which shows the structure of the 1st synchronization part which concerns on 5th Embodiment. It is a figure which shows the structure of the 1st synchronization part which concerns on 6th Embodiment. It is a figure which shows the structure of the 1st synchronization part which concerns on 7th Embodiment. It is a figure which shows the structure of the decoding part which concerns on 8th Embodiment. FIG. 17 is a timing chart showing a procedure for converting encoded data into decoded data in the decoding unit shown in FIG. 16. FIG. 8 is another example of a timing diagram showing a procedure for converting encoded data into decoded data in the decoding unit shown in FIG. 7. The data sequence encoded by the Manchester code | cord | chord used with the conventional communication system is shown. The data sequence encoded using the 3rd waveform used with the conventional communication system is shown.

<First Embodiment>
[Configuration of Communication System S]
FIG. 1 is a diagram illustrating a configuration of a communication system S according to the first embodiment. The communication system S includes a plurality of communication devices 1 (communication device 1-1 and communication device 1-2). The communication device 1-1 and the communication device 1-2 exchange data with each other via the wireless communication line 2.

  The communication device 1-1 is, for example, a mobile terminal, an RFID card, or an IC tag that uses a short-range wireless communication method such as NFC (Near Field Communication). The communication device 1-1 operates by receiving power from the communication device 1-2 via the wireless communication line 2. The communication device 1-2 is, for example, an IC card reader / writer that transmits / receives data to / from a mobile terminal, an RFID card, or an IC tag by a short-range wireless communication method. The communication device 1-2 periodically detects whether or not the communication device 1-1 is in the vicinity. When the communication device 1-1 is detected, the communication device 1-2 supplies power to the communication device 1-1 by electromagnetic induction.

[Configuration of Communication Device 1]
Hereinafter, the configuration and operation common to the communication device 1-1 and the communication device 1-2 will be described using the communication device 1-1 as an example.
The control unit 10 is a CPU, for example. The storage unit 20 is a memory such as a ROM or a RAM, for example. The memory | storage part 20 memorize | stores the data transmitted / received between the communication apparatuses 1-2. The storage unit 20 may store a communication control program executed by the control unit 10.

  The encoding unit 30 generates encoded data to be transmitted to the communication device 1-2. Specifically, the encoding unit 30 transmits the data of the logical value “0” and the logical value “1” to be transmitted to the communication device 1-2 to the first encoded data and the second encoded data to which a predetermined waveform is assigned. It converts into the encoded data comprised from encoded data, and outputs it with respect to the transmission part 40. FIG. A first waveform is assigned to the first encoded data. Any one of the second waveform, the third waveform, and the fourth waveform is assigned to the second encoded data. Details of the first waveform, the second waveform, the third waveform, and the fourth waveform will be described later.

  The transmission unit 40 modulates the encoded data generated by the encoding unit 30 and transmits it to the communication device 1-2 via the antenna. For example, the transmission unit 40 generates a modulation signal in a 13.56 MHz frequency band used in NFC, and transmits the modulation signal wirelessly.

  The receiving unit 50 demodulates the modulated signal received from the communication device 1-2 via the wireless communication line 2 to generate a demodulated signal, and outputs the demodulated signal to the decoding unit 60. The demodulated signal includes any of the first waveform, the second waveform, the third waveform, and the fourth waveform.

  The decoding unit 60 performs a decoding process based on the type of waveform included in the demodulated signal input from the receiving unit 50, and includes a logical value “0” and a logical value “1”. Generate data. The decryption unit 60 outputs the decrypted data to the control unit 10.

[Types of transmitted and received waveforms]
FIG. 2 is a diagram illustrating the types of waveforms of encoded data transmitted and received between the plurality of communication apparatuses 1. Between the plurality of communication apparatuses 1, encoded data including first encoded data corresponding to the first waveform and second encoded data corresponding to any of the second waveform, the third waveform, and the fourth waveform is present. Sent and received. The first encoded data is, for example, data corresponding to input data whose logical value is “0”. The second encoded data is, for example, data corresponding to input data whose logical value is “1”. In the present embodiment, it is assumed that the length of one bit of the first encoded data and the second encoded data is T. The plurality of communication devices 1 transmit and receive a data sequence composed of a plurality of first encoded data and a plurality of second encoded data.

  As shown in FIG. 2, a first waveform in which a first state transition (for example, a rising transition from a low level to a high level) occurs once in the middle of one bit is assigned to the first encoded data. One of the second waveform, the third waveform, and the fourth waveform is assigned to the second encoded data according to the type of the second encoded data.

  The second waveform is assigned to a single second encoded data sandwiched between the first encoded data, such as “1” in the data string “010”. The second waveform includes a first polarity pulse before the first state transition and a second polarity pulse having a polarity different from the first polarity after the first state transition. That is, the second waveform changes to the low level after t2 after the change to the high level following the first polarity pulse that changes to the high level after the elapse of t2 after the change from the high level to the low level. Including a second polarity pulse.

  The third waveform is assigned to the first second encoded data among a plurality of continuous second encoded data, like the first “1” in the data string “01110”. The third waveform includes a first polarity pulse before the first state transition. That is, the third waveform includes one pulse of the first polarity that changes to the high level after t3 has elapsed since the change from the high level to the low level.

  The fourth waveform is assigned to the last second encoded data among a plurality of continuous second encoded data, like the last “1” in the data string “01110”. The fourth waveform includes a second polarity pulse after the first state transition. That is, the fourth waveform includes one pulse of the second polarity that changes to the low level after t4 has elapsed since the change from the low level to the high level.

  Note that the first waveform is assigned to the second encoded data sandwiched between the plurality of second encoded data, like the second “1” in the data string “01110”. That is, the first waveform is assigned between the third waveform and the fourth waveform.

  Here, the total value of the high level period and the total value of the low level period in each of the first waveform and the second waveform are equal. For example, the first waveform assigned to the second encoded data between the second encoded data of the third waveform and the second encoded data of the fourth waveform is the first level before the first state transition. The length of the period (for example, low level) is equal to the length of the period of the second level (for example, high level) after the first state transition. Further, the width t3 of the first polarity pulse of the third waveform is equal to the width t4 of the second polarity pulse of the fourth waveform. When the first waveform, the second waveform, the third waveform, and the fourth waveform satisfy these conditions, fluctuations in the DC component in the encoded data can be suppressed.

  In the first waveform, the second waveform, the third waveform, and the fourth waveform, the first state transition occurs only once. That is, the first state transition occurs only once in the 1-bit length of the first encoded data and the second encoded data. The first state transition occurs, for example, at an intermediate timing between the start timing and the end timing of the first encoded data and the second encoded data.

[Encoding Procedure by Encoding Unit 30]
The encoding unit 30 generates encoded data by the following procedure, for example. The encoding unit 30 determines the logical value of the data input from the control unit 10. The encoding unit 30 outputs the first waveform when the logical value of the input data is “0”. If the logical value of the data input subsequent to the input data of logical value “0” is “1”, the encoding unit 30 determines that the logical value of the next input data is “0”. Two waveforms are output, and if the logical value of the next input data is “1”, the third waveform is output. When the logical value of the data input subsequent to the input data having the continuous logical value “1” is “0”, the encoding unit 30 performs the fourth waveform on the input data having the last logical value “1”. Is output. The encoding unit 30 is input data having a logical value “1” that is input subsequent to input data having a continuous logical value “1”, and the logical value of the next input data is “1”. In response to this, the first waveform is output.

FIG. 3 is a diagram illustrating a configuration of the encoding unit 30 according to the first embodiment.
The encoding unit 30 includes a waveform generation unit 31 and a selection unit 32. The selection unit 32 includes a delay circuit 33 and a selection circuit 34.

  The waveform generation unit 31 generates a waveform corresponding to the first encoded data and the second encoded data constituting the encoded data. Specifically, the waveform generation unit 31 includes a first waveform corresponding to the first encoded data, a second waveform corresponding to a single second encoded data sandwiched between the plurality of first encoded data, and a continuous waveform. A third waveform corresponding to the first second encoded data of the plurality of second encoded data to be processed, and a fourth waveform corresponding to the last second encoded data of the plurality of consecutive second encoded data. Generate a waveform.

  FIG. 4 is a diagram illustrating a configuration of the waveform generation unit 31. The waveform generation unit 31 includes an exclusive OR circuit 311, an exclusive OR circuit 312, a D flip-flop circuit 313, a D flip-flop circuit 314, an OR circuit 315, an AND circuit 316, and an OR circuit 317. The exclusive OR circuit 311 receives a clock signal CLK synchronized with input data and a reset signal RST that resets the encoding unit 30 at a logical value of 0. The output signal of the exclusive OR circuit 311 is input to the data input terminal of the D flip-flop circuit 313.

  The exclusive OR circuit 312 receives the clock signal 2CLK obtained by multiplying the clock signal CLK by 2 and the reset signal RST. The output signal of the exclusive OR circuit 312 is input to the data input terminal of the D flip-flop circuit 314.

A clock signal 4CLK obtained by multiplying the clock signal CLK by 4 is input to clock input terminals of the D flip-flop circuit 313 and the D flip-flop circuit 314. The data input to the data input terminal of the D flip-flop circuit 313 is latched by 4CLK, and the first waveform signal is output from the non- inverting output terminal. Similarly, the data input to the data input terminal of the D flip-flop circuit 314 is latched by 4CLK, and the second waveform signal is output from the inverted output terminal .

The logical sum circuit 315 receives the first waveform signal and the second waveform signal, and the logical sum output of these signals becomes the third waveform signal. The AND circuit 316 receives the first waveform signal and the second waveform signal, and the logical product output of these signals becomes the fourth waveform signal.
With the above configuration, the waveform generation unit 31 can generate the first waveform signal, the second waveform signal, the third waveform signal, and the fourth waveform signal with a small-scale circuit configuration.

  Three clock signals CLK, 2CLK, and 4CLK are input to the OR circuit 317. These logical sum outputs DCLK are input to the selection unit 32 and provide the operation timing of the selection unit 32.

  FIG. 5 is a diagram illustrating a configuration of the selection unit 32. The delay circuit 33 configuring the selection unit 32 includes a D flip-flop circuit 331, a D flip-flop circuit 332, and a D flip-flop circuit 333. The input data output from the control unit 10 is input to the data input terminal of the D flip-flop circuit 331. The DCLK output from the waveform generator 31 is input to the clock input terminal of the D flip-flop circuit 331. The D flip-flop circuit 331 latches the input data at the rising timing of DCLK, and outputs the first delay signal Q1 to the data input terminal of the D flip-flop circuit 332.

The D flip-flop circuit 332 latches the first delay signal Q1 input from the D flip-flop circuit 331 at the rising timing of DCLK, and sends the second delay signal Q2 to the data input terminal of the D flip-flop circuit 333. Output.
Similarly, the D flip-flop circuit 333 latches the second delay signal Q2 input from the D flip-flop circuit 332 at the rising timing of DCLK, and outputs a third delay signal Q3.

  The first delay signal Q1, the second delay signal Q2, and the third delay signal Q3 generated in the delay circuit 33 and the inverted signals Q1 *, Q2 *, and Q3 * are input to the selection circuit 34. The selection circuit 34 selects one waveform from the first waveform, the second waveform, the third waveform, and the fourth waveform based on the first delay signal, the second delay signal, and the third delay signal. That is, the selection circuit 34, based on the values of Q1, Q2, Q3, Q1 *, Q2 *, and Q3 *, the first waveform signal, the second waveform signal, the third waveform signal, and the first waveform signal generated by the waveform generation unit 31. Of the four waveform signals, which signal to output is selected.

  The selection circuit 34 includes logical product circuits 341, 342, 343, 344, and 345 and a logical sum circuit 346. The logical sum circuit 346 outputs the logical sum of the output signals of the logical product circuits 341, 342, 343, 344, and 345.

  The AND circuit 341 receives the first waveform signal and Q2 *. The AND circuit 341 outputs the first waveform signal to the OR circuit 346 when the value of Q2 is zero. That is, the AND circuit 341 outputs the first waveform signal via the OR circuit 346 when (Q1, Q2, Q3) = (X, 0, X). X indicates that it may be 0 or 1.

  The AND circuit 342 receives the second waveform signal and Q1 *, Q2, Q3 *. When the logical product circuit 342 outputs (Q1, Q2, Q3) = (0, 1, 0), that is, outputs a single second encoded data sandwiched between a plurality of first encoded data. The second waveform signal is output via the OR circuit 346.

  The AND circuit 343 receives the third waveform signal and Q1, Q2, Q3 *. When the logical product circuit 342 outputs (Q1, Q2, Q3) = (1, 1, 0), that is, outputs the first second encoded data among a plurality of continuous second encoded data. The third waveform signal is output via the OR circuit 346.

  The AND circuit 344 receives the first waveform signal and Q1, Q2, and Q3. The logical product circuit 342 passes the logical sum circuit 346 when (Q1, Q2, Q3) = (1, 1, 1), that is, when three or more second encoded data are continuously output. To output the first waveform signal.

  The AND circuit 345 receives the fourth waveform signal and Q1 *, Q2, and Q3. When the logical product circuit 342 outputs (Q1, Q2, Q3) = (0, 1, 1), that is, outputs the last second encoded data among a plurality of continuous second encoded data. The fourth waveform signal is output via the OR circuit 346.

  FIG. 6 is a timing chart showing a procedure for generating encoded data in the encoding unit shown in FIGS. When input data 1011100001 is input, signals are output in the order of the second waveform, the first waveform, the third waveform, the first waveform, the fourth waveform, the first waveform, the first waveform, the first waveform, and the first waveform. It can be seen that encoded data to be generated is generated.

[Configuration of Decoding Unit 60 and Decoding Procedure]
FIG. 7 is a diagram illustrating a configuration of the decoding unit 60 according to the first embodiment. FIG. 8 is a timing chart showing a procedure for converting encoded data into decoded data in the decoding unit 60 shown in FIG. Hereinafter, the configuration and operation of the decoding unit 60 will be described with reference to FIGS. 7 and 8.

  The decoding unit 60 includes a signal generation unit 61 and an output unit 62. The signal generator 61 changes to the second level (for example, high level) according to the first state transition in the second waveform and the first state transition in the third waveform, and the first waveform in the first waveform immediately after the second waveform. A composite signal that changes to a first level (for example, a low level) is generated in response to the first state transition and the first state transition in the first waveform immediately after the fourth waveform. That is, as shown in FIG. 8, when the encoded data composed of the data string “01011100” is input, the signal generator 61 generates a composite signal (NE in FIG. 8).

  Specifically, the signal generator 61 changes the composite signal from a low level to a high level at the rising transition timing in the second waveform of the second bit, and at the rising transition timing in the first waveform of the third bit, The composite signal is changed from high level to low level. Further, the signal generator 61 changes the composite signal from the low level to the high level at the rising transition timing in the fourth waveform of the fourth bit, and the first waveform of the seventh bit immediately after the fourth waveform of the sixth bit. The composite signal is changed from the high level to the low level at the timing of the rising transition at.

  The details of the configuration of the signal generator 61 in the present embodiment will be described below. The signal generation unit 61 includes a first synchronization unit 610, a second synchronization unit 630, and a synthesis unit 650.

  The first synchronization unit 610 includes an inverting circuit 611, a delay circuit 612, and a D flip-flop circuit 613. The encoded data received from the communication device 1-2 via the receiving unit 50 is input to the inverting circuit 611, the delay circuit 612, and the D flip-flop circuit 631. The first synchronization unit 610 synchronizes the inverted signal obtained by inverting the encoded data with the first state transition timing of the delayed signal obtained by delaying the encoded data by a predetermined delay time (FIG. 8). NA) in

  The inverting circuit 611 inverts the logic of the input encoded data and generates an inverted signal. The inverting circuit 611 inputs the generated inverted signal to the data input terminal of the D flip-flop circuit 613. The delay circuit 612 has an even number of inversion circuits, and generates a delay signal obtained by delaying encoded data by a delay time d larger than the delay time generated by the inversion circuit 611. The delay circuit 612 inputs the generated delay signal to the clock terminal of the D flip-flop circuit 613.

  Here, the delay time d in the delay circuit 612 includes the pulse width t2 of the first polarity and the second polarity included in the second waveform, the pulse width t3 of the second polarity included in the third waveform, and the fourth waveform. Is greater than the pulse width t4 of the first polarity pulse included in. That is, t2, t3, t4 <d. The second waveform, the third waveform, and the fourth waveform change from the first level to the second level at the respective central positions, and the delay time d is the period T of the first encoded data and the second encoded data. Shorter than half the length T / 2.

  The D flip-flop circuit 613 generates the first synchronization signal by latching the inverted signal input from the inverting circuit 611 at the rising timing of the delayed signal input from the delay circuit 612. The D flip-flop circuit 613 outputs the generated first synchronization signal to the synthesis unit 650.

  Second synchronization section 630 generates a second synchronization signal (NB in FIG. 8) obtained by synchronizing the delay signal generated by delay circuit 612 with the first state transition timing of the encoded data. Specifically, the second synchronization unit 630 generates the second synchronization signal by latching the delay signal input from the delay circuit 612 at the rising timing of the encoded data.

  The combining unit 650 generates a combined signal that changes to the second level according to the first state transition of the second synchronization signal and changes to the first level according to the second state transition of the first synchronization signal. The synthesizer 650 includes a pulse generation circuit 651, a pulse generation circuit 652, and an SR flip-flop circuit 653.

  The pulse generation circuit 651 generates a low-level pulse (NC in FIG. 8) at the falling timing of the first synchronization signal output from the inverting circuit 611. Specifically, the pulse generation circuit 651 includes an inverting circuit that inverts the first synchronization signal, and a logical sum (OR) circuit that calculates a logical sum of the signal output from the inverting circuit and the first synchronization signal. Have The pulse generation circuit 651 outputs the pulse generated by the logical sum (OR) circuit to the reset terminal of the SR flip-flop circuit 653.

  The pulse generation circuit 652 outputs a low-level pulse (ND in FIG. 8) at the rising timing of the second synchronization signal output from the D flip-flop circuit 631. Specifically, the pulse generation circuit 651 includes an inverting circuit that inverts the second synchronization signal, and a negative logical product that calculates an inverted value of the logical product of the signal output from the inverting circuit and the second synchronization signal. (NAND) circuit. The pulse generation circuit 652 outputs the pulse generated by the NAND circuit to the set input terminal of the SR flip-flop circuit 653.

  When a low level pulse is input from the pulse generation circuit 652, the SR flip-flop circuit 653 transitions a signal output to the output unit 62 to a high level, and when a low level pulse is input from the pulse generation circuit 651. The signal output to the output unit 62 is changed to the low level. That is, the SR flip-flop circuit 653 outputs a composite signal (NE in FIG. 8) that transitions to a high level at the rising timing of the second synchronization signal and transitions to a low level at the falling timing of the first synchronization signal.

  The output unit 62 outputs decoded data obtained by synchronizing the synthesized signal with the first state transition timing in the encoded data. Specifically, the output unit 62 is a D flip-flop circuit, for example, and generates decoded data by latching the composite signal at the rising transition timing in the encoded data. In FIG. 8, it can be seen that decoded data “010111...” Is generated starting from the rising transition timing of the second waveform of the second bit of the received encoded data.

[Effect in the first embodiment]
As described above, according to the communication device 1 according to the first embodiment, the signal generation unit 61 changes to the second level according to the first state transition in the second waveform and the first state transition in the third waveform. A composite signal that changes to the first level in response to the first state transition in the first waveform immediately after the second waveform and the first state transition in the first waveform immediately after the fourth waveform is generated. As described above, the communication device 1 performs the conversion process determined according to the type of waveform at the timing of the first state transition of the received encoded data, thereby allowing the clock recovery circuit such as a phase locked loop to generate a clock. Can be obtained from the encoded data composed of the first waveform, the second waveform, the third waveform, and the fourth waveform without reproducing the waveform, and the decoded data changing in synchronization with the rising transition timing of each waveform can be obtained. it can.

  In addition, the delay time d is a pulse width t2 of the first polarity and the second polarity included in the second waveform, a pulse width t3 of the second polarity pulse included in the third waveform, and the first waveform included in the fourth waveform. It is larger than the pulse width t4 of the polarity. When the delay time d satisfies such a condition, the decoding unit 60 can generate a first synchronization signal for detecting the second waveform and the fourth waveform.

  Further, the delay time d is shorter than the length T / 2 which is half the period T of the first encoded data and the second encoded data. When the delay time d satisfies such a condition, the decoding unit 60 can generate a second synchronization signal for detecting the second waveform and the third waveform.

  According to the present embodiment, the decoded data can be obtained with a small-scale circuit as compared with the case where the clock recovery circuit is used, so that power consumption can be reduced. Therefore, it is possible to reduce the size of the power storage capacitor built in the non-contact IC card. In addition, unlike the case of using a clock recovery circuit, it does not require a start-up time until locking, so that a small amount of data can be received efficiently.

<Second Embodiment>
[Composition Unit 650 is Configured Using Exclusive OR Circuit]
FIG. 9 is a diagram illustrating a configuration of the decoding unit 60 according to the second embodiment. FIG. 10 is a timing chart showing a procedure for converting encoded data into decoded data in the decoding unit 60 shown in FIG. Hereinafter, the configuration and operation of the decoding unit 60 according to the present embodiment will be described with reference to FIGS. 9 and 10. The decoding unit 60 in the present embodiment is the same in other respects, except for the configuration of the synthesis unit 650, which is different from the configuration of the synthesis unit 650 in the decoding unit 60 shown in FIG. 7 according to the first embodiment.

The synthesizing unit 650 in this embodiment includes an exclusive OR circuit 654, a D flip-flop circuit 655, and an OR circuit 656.
The exclusive OR circuit 654 generates an exclusive OR signal (NF in FIG. 10) indicating the exclusive OR of the first synchronization signal and the second synchronization signal, and the generated exclusive OR signal Input to the clock terminal of the D flip-flop circuit 655.

The D flip-flop circuit 655 latches the second encoded data input to the data input terminal with the exclusive OR signal input from the exclusive OR circuit 654, and the latch signal (NG in FIG. 10). Output.
The OR circuit 656 outputs a logical sum signal indicating the logical sum of the first synchronization signal output from the D flip-flop circuit 613 and the latch signal output from the D flip-flop circuit 655 as a combined signal. The composite signal output from the OR circuit 656 is input to the data input terminal of the output unit 62.

  The composite signal input to the data input terminal of the output unit 62 is latched at the rising transition timing in the encoded data, and decoded data is generated. Also in FIG. 10, as in FIG. 8, it can be seen that decoded data “010111...” Is generated starting from the rising transition timing of the second waveform of the second bit of the received encoded data.

<Third Embodiment>
[Decode encoded data whose rise timing interval is not constant]
FIG. 11 is another example of a timing diagram showing a procedure for converting encoded data into decoded data in the decoding unit 60 according to the above embodiment. In the encoded data in the timing diagram shown in FIG. 11, the second waveform, the third waveform, and the fourth waveform rise at positions different from the center positions of the respective waveforms. Moreover, the widths of the pulses included in the second waveform, the third waveform, and the fourth waveform are different from the encoded data shown in FIGS.

  In the second waveform of FIG. 11, the pulse width t21 of the first polarity at the low level is shorter than the pulse width t22 of the second polarity at the high level, and t21 <t2 <t22. The time from the start timing of the second waveform to the falling timing of the first polarity pulse is t20, and the time from the start timing of the second waveform to the rising timing of the first polarity pulse is t20 + t21. The rising timing of the first polarity pulse is earlier than the timing of the center position of the second waveform, and t20 + t21 <T / 2. In this case, when the delay time d in the delay circuit 612 is larger than the pulse width t22 of the second polarity and smaller than the total value t21 + t22 of the pulse width of the first polarity and the pulse width of the second polarity, the decoding is performed. The encoding unit 60 can decode the encoded data.

  Further, in the third waveform of FIG. 11, the pulse width t31 of the first polarity at the low level is shorter than the pulse width t3 shown in FIGS. Further, the rising timing of the first polarity pulse is later than the timing of the center position of the third waveform, and the time t30 from the start timing of the third waveform to the rising timing of the pulse is longer than T / 2. In this case, when the delay time d in the delay circuit 612 is larger than the pulse width t31 of the first polarity and smaller than Tt30-t31, the decoding unit 60 can decode the encoded data.

  In the fourth waveform of FIG. 11, the high-level second-polarity pulse width t41 is shorter than the pulse width t4 shown in FIGS. Further, the rising timing of the second polarity pulse is later than the timing of the center position of the fourth waveform, and the time t40 from the start timing of the fourth waveform to the rising timing of the pulse is longer than T / 2. In this case, when the delay time d in the delay circuit 612 is larger than the pulse width t41 of the second polarity and smaller than Tt40-t41, the decoding unit 60 can decode the encoded data.

  As described above, according to the third embodiment, in the decoding unit 60, the first state transition timing in the encoded data matches the timing of the center position of the second waveform, the third waveform, and the fourth waveform. Even if not, it can be decrypted. Therefore, the decoding unit 60 can perform decoding without using a clock recovery circuit even when the encoded data has jitter.

<Fourth Embodiment>
FIG. 12 is a diagram illustrating a configuration of the first synchronization unit 610 according to the fourth embodiment. In the first synchronization unit 610 according to the present embodiment, a high-pass filter including a capacitor 614 and a resistor 615 is provided between the inverting circuit 611 and the data input terminal of the D flip-flop circuit 613. 7 and FIG. 9 are different from the configuration shown in FIG.

The first synchronization unit 610 according to the present embodiment is different from the configuration illustrated in FIGS. 7 and 9 in that the delay circuit 612 includes a low-pass filter including a resistor 616 and a capacitor 617. Between the low-pass filter and the clock terminal of the D flip-flop circuit 613, there is provided a buffer 618 having a Schmitt trigger circuit whose output level changes with hysteresis with respect to a change in input level.
According to the configuration of this embodiment, the number of inversion circuits included in the delay circuit 612 can be reduced, so that power consumption can be reduced.

<Fifth Embodiment>
FIG. 13 is a diagram illustrating a configuration of the first synchronization unit 610 according to the fifth embodiment. In the first synchronization unit 610 according to the present embodiment, a resistor 619 is provided before the high-pass filter configured by the capacitor 614 and the resistor 615 in the first synchronization unit 610 shown in FIG. Further, in the first synchronization unit 610 shown in FIG. 12, a capacitor 620 is provided in front of a low-pass filter composed of a resistor 616 and a capacitor 617, and a band-pass filter is configured.

  As described above, a high-pass filter in which the resistor 619 is connected in series is provided at the input stage to the data input terminal of the D flip-flop circuit 613, and a band-pass filter is provided at the input stage to the clock terminal of the D flip-flop circuit 613. By providing, the phase difference between the data input signal input to the data input terminal of the D flip-flop circuit 613 and the clock signal input to the clock terminal of the D flip-flop circuit 613 can be easily adjusted. If the phase difference between the data input signal and the clock signal can be easily adjusted, the allowable range for fluctuations in the pulse width and pulse position of the second waveform, the third waveform, and the fourth waveform included in the encoded data is increased. Can do. As a result, according to the configuration of the first synchronization unit 610 according to the present embodiment, there is an effect that it is less susceptible to the influence of noise in the wireless communication line 2.

<Sixth Embodiment>
FIG. 14 is a diagram illustrating a configuration of the first synchronization unit 610 according to the sixth embodiment. The first synchronization unit 610 according to the present embodiment is illustrated in FIG. 7 in that the delay circuit 612 includes a low-pass filter including a resistor 616 and a capacitor 617, an inverting circuit 621, and an inverting circuit 622. It differs from the 1st synchronization part 610 which concerns on 1st Embodiment and 2nd Embodiment shown in FIG. The inverting circuit 622 has a Schmitt trigger circuit in which the output level changes with hysteresis with respect to the change in the input level.

  The second synchronization unit 630 includes a low-pass filter 633 including a resistor 634 and a capacitor 635 connected to the data input terminal of the D flip-flop circuit 631. Different from the two synchronization unit 630. The delay time in the low-pass filter 633 is different from the delay time in the delay circuit 612.

  The delay time of the delay circuit 612 can be adjusted based on the constants of the resistor 616 and the capacitor 617, and the delay time by the low-pass filter 633 can be adjusted based on the constants of the resistor 634 and the capacitor 635. The constants of the resistor 616, the capacitor 617, the resistor 634, and the capacitor 635 are selected so as to satisfy a predetermined condition.

Specifically, t = t2 = t3 = t4, the delay time of each of the inverting circuit 621 and the inverting circuit 622 is d, the resistance value of the resistor 616 is R1, the capacitance value of the capacitor 617 is C1, and the D flip-flop circuit 613 When the threshold value is V (where 0 <V <1), the output signal of the delay circuit 612 needs to fall below the threshold value between the first falling edge and the rising edge of the second waveform. It is required to satisfy the condition of Eq.

Further, since the total value of the delay time by the low-pass filter composed of the resistor 616 and the capacitor 617 and the delay time by the inversion circuit 621 and the inversion circuit 622 needs to exceed t, it is required to satisfy the following condition.

Furthermore, when the fourth waveform is input to the delay circuit 612, it is necessary to output a signal exceeding the threshold value, and therefore, the following condition is required.

本実施形態の構成によれば、遅延回路６１２が有する反転回路の個数を減らせるので、消費電力を低減することができる。 Further, when the resistance value of the resistor 634 is R2, the capacitance value of the capacitor 635 is C2, and the threshold value of the D flip-flop circuit 631 is V, when the second waveform and the third waveform are input to the low-pass filter 633, Since it suffices if the threshold value is exceeded after the time t has elapsed from the time point when it falls, it is required to satisfy the following conditions.

According to the configuration of this embodiment, the number of inversion circuits included in the delay circuit 612 can be reduced, so that power consumption can be reduced.

<Seventh Embodiment>
FIG. 15 is a diagram illustrating a configuration of the first synchronization unit 610 according to the seventh embodiment. In the first synchronization unit 610 according to the present embodiment, a capacitor 623 is provided between a connection point between the resistor 616 and the capacitor 617 in the first synchronization unit 610 illustrated in FIG. Unlike the configuration of the first synchronization unit 610 according to the sixth embodiment illustrated in FIG. 14, the configuration is the same in other respects.

  When the power supply voltage varies, the threshold values of the D flip-flop circuit 613, the inverting circuit 621, and the inverting circuit 622 vary. If the potential of the encoded data input to the inverting circuit 621 does not change in synchronization with the threshold value, the probability that an error will occur in the decoded data increases. According to the present embodiment, by providing the capacitor 623, the potential at the connection point between the resistor 616 and the capacitor 617 in the low-pass filter can be changed in synchronization with the change in the power supply voltage. The probability that an error will occur in the digitized data can be reduced.

<Eighth Embodiment>
FIG. 16 is a diagram illustrating a configuration of the decoding unit 60 according to the eighth embodiment. FIG. 17 is a timing chart showing a procedure for converting encoded data into decoded data in the decoding unit 60 shown in FIG.

  The first synchronization unit 610 in the decoding unit 60 shown in FIG. 16 inverts the received encoded data and synchronizes the encoded data with the first state transition timing of the delayed signal delayed by a predetermined delay time. A first synchronization signal is generated. The second synchronization unit 630 generates a second synchronization signal in which the delay signal is synchronized with the first state transition timing of the inverted signal obtained by inverting the encoded data. The combining unit 650 generates a combined signal that changes to the second level according to the first state transition of the second synchronization signal and changes to the first level according to the second state transition of the first synchronization signal.

  That is, the first synchronization unit 610 according to the present embodiment uses the point that the encoded data is input to the data input terminal of the D flip-flop circuit 613 without being inverted, and the delay circuit 624 uses an odd number of inversion circuits. This is different from the first synchronization unit 610 according to the first embodiment shown in FIG. 7 in that the encoded data is delayed. Further, the second synchronization unit 630 according to the present embodiment relates to the first embodiment shown in FIG. 7 in that a signal obtained by inverting the encoded data is input to the clock terminal of the D flip-flop circuit 631. Different from the second synchronization unit 630. Further, the output unit according to the first embodiment shown in FIG. 7 is also inputted to the clock terminal of the output unit 62 according to the present embodiment in that data obtained by inverting the encoded data by the inverting circuit 625 is input. 62.

  As shown in FIG. 17, in the encoded data of this embodiment, the first waveform, the second waveform, the third waveform, and the fourth waveform are inverted with respect to the waveform of the encoded data shown in FIG. doing. Thus, according to the present embodiment, decoded data can be generated even when the waveform constituting the encoded data has the opposite polarity to the waveform shown in FIG.

<Ninth Embodiment>
FIG. 18 is a timing chart showing a procedure for converting encoded data into decoded data in the decoding unit 60 shown in FIG. The encoded data shown in FIG. 18 is shown in FIG. 8 in that the second waveform is used as a waveform between the third waveform and the fourth waveform in a data string in which three or more “1” s are continuous. Different from the encoded data shown. That is, in FIG. 18, between the first second encoded data among the plurality of continuous second encoded data and the last second encoded data among the plurality of continuous second encoded data. A second waveform is assigned to the second encoded data sandwiched between the two.

  Comparing FIG. 18 and FIG. 8, the waveforms of NA and NB are different, but the waveforms of NC, ND, and NE and the waveform of decoded data are the same. As described above, the decoding unit 60 according to the present invention changes to the second level according to the first state transition in the second waveform and the first state transition in the third waveform, and the second state immediately after the second waveform. By generating a composite signal that changes to the first level in response to the first state transition in one waveform and the first state transition in the first waveform immediately after the fourth waveform, decoded data is generated. Therefore, the waveform between the third waveform and the fourth waveform is decoded to “1” regardless of the waveform between the third waveform and the fourth waveform in the data string in which three or more “1” s are continuous. Is done. Thus, it can be seen that the decoding unit 60 according to the present invention can be applied to various encoded data.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  For example, in the above embodiment, the first polarity pulse is a pulse that transitions to a high level after transitioning from a high level to a low level, and the second polarity pulse is transitioned to a low level after transitioning from a low level to a high level. Although described as a pulse, the reverse combination may be used. In the above embodiment, the first level is described as low level, and the second level is described as high level. However, the reverse combination may be used.

  In the above embodiment, the communication device 1-1 will be described using a portable terminal, an RFID card, or an IC tag using a short-range wireless communication method such as NFC (Near Field Communication) as an example of the communication device 1-1. Although the description has been made using the IC card reader / writer as an example of 1-2, the communication device 1-1 and the communication device 1-2 can be applied to other devices. For example, the present invention can be applied to a device having an arbitrary communication function, such as a sensor network that transmits and receives information between sensors using the M2M communication method.

  Further, the configuration of the encoding unit 30 is not limited to the configuration shown in FIGS. 3 to 5, and can be realized by other configurations. For example, the waveform generator 31 has a memory that stores patterns of the first waveform, the second waveform, the third waveform, and the fourth waveform, and selects a signal that is repeatedly output in synchronization with the input clock. You may output with respect to the part 32. FIG.

  The selecting unit 32 selects a waveform from the first waveform, the second waveform, the third waveform, and the fourth waveform based on the decoding circuit that decodes the signal output from the delay circuit 33 and the output of the decoding circuit. You may comprise with a selector circuit.

DESCRIPTION OF SYMBOLS 1 ... Communication apparatus, 2 ... Wireless communication line, 10 ... Control part, 20 ... Memory | storage part, 30 ... Encoding part, 40 ... Transmission part, 50 ... Reception part , 60 ... Decoding unit, 61 ... Signal generation unit, 62 ... Output unit, 610 ... First synchronization unit, 611 ... Inversion circuit, 612 ... Delay circuit, 613 ··· flip-flop circuit, 614 ··· capacitor, 615 ··· resistor, 616 ··· resistor, 617 ··· capacitor, 618 ··· buffer, 619 ··· resistor, 620 ··· capacitor, 621 ..Inverter circuit, 622... Inverter circuit, 623... Capacitor, 624... Delay circuit, 625... Inverter circuit, 630... Second synchronization unit, 631. 632... Inversion circuit, 633... Low pass filter 634... Resistor, 635... Capacitor, 650... Synthesis unit, 651... Pulse generation circuit, 652... Pulse generation circuit, 653. Sum circuit, 655... Flip-flop circuit, 656... OR circuit

Claims (16)

Received first encoded data corresponding to the first waveform transmitted from another communication device, and encoded data including second encoded data corresponding to any one of the second waveform, the third waveform, and the fourth waveform. A communication device for decoding,
The second state changes to the second level in response to the first state transition in the second waveform and the first state transition in the third waveform, and the first state transition and the fourth in the first waveform immediately after the second waveform. A signal generator for generating a composite signal that changes to a first level in response to a first state transition in the first waveform immediately after the waveform;
An output unit that outputs decoded data obtained by synchronizing the synthesized signal with a first state transition timing in the encoded data;
With
The second waveform is assigned to a single second encoded data sandwiched between a plurality of the first encoded data,
The third waveform is assigned to the first second encoded data among a plurality of continuous second encoded data,
The fourth waveform is assigned to the last second encoded data among the plurality of continuous second encoded data.
Communication device. The first encoded data of the plurality of consecutive second encoded data and the last encoded data of the plurality of consecutive second encoded data are sandwiched between the second encoded data Either the first waveform or the second waveform is assigned to the second encoded data.
The communication apparatus according to claim 1. The second waveform includes a first polarity pulse before the first state transition, and a second polarity pulse different from the first polarity after the first state transition,
The third waveform includes a pulse of the first polarity before the first state transition;
The fourth waveform includes the second polarity pulse after the first state transition,
The communication apparatus according to claim 1 or 2. The width of the pulse of the first polarity of the third waveform is equal to the width of the pulse of the second polarity of the fourth waveform,
The second encoded data between the second encoded data of the third waveform and the second encoded data of the fourth waveform is the length of the first level period before the first state transition. And the length of the second level period after the first state transition is equal,
The communication apparatus according to claim 3. The signal generator is
A first synchronization unit for generating a first synchronization signal obtained by synchronizing an inverted signal obtained by inverting the encoded data with a first state transition timing of a delayed signal obtained by delaying the encoded data by a predetermined delay time; ,
A second synchronization unit for generating a second synchronization signal obtained by synchronizing the delay signal with the first state transition timing of the encoded data;
A synthesis that generates the composite signal that changes to the second level in response to a first state transition of the second synchronization signal and changes to the first level in response to a second state transition of the first synchronization signal. And
Having
The communication apparatus according to any one of claims 1 to 4. The first synchronization unit includes:
An inverting circuit for generating the inverted signal obtained by inverting the encoded data;
A delay circuit that delays the encoded data to generate the delayed signal;
A first flip-flop circuit in which the inverted signal is input to a data input terminal, and the delay signal generated by the delay circuit is input to a clock terminal;
Have
The second synchronization unit includes:
A second flip-flop circuit in which the delayed signal is input to a data input terminal and the encoded data is input to a clock terminal;
The communication device according to claim 5. The first synchronization unit includes:
An inverting circuit for generating the inverted signal obtained by inverting the encoded data;
A high-pass filter to which the inverted signal is input;
A low-pass filter to which the encoded data is input;
A first flip-flop circuit in which a signal output from the high-pass filter is input to a data input terminal, and the delayed signal output from the low-pass filter is input to a clock terminal;
Have
The second synchronization unit includes:
A second flip-flop circuit in which the delayed signal is input to a data input terminal and the encoded data is input to a clock terminal;
The communication device according to claim 5. The first synchronization unit includes:
An inverting circuit for generating the inverted signal obtained by inverting the encoded data;
A high-pass filter to which the inverted signal is input;
A bandpass filter to which the encoded data is input;
A first flip-flop circuit in which a signal output from the high-pass filter is input to a data input terminal, and the delayed signal output from the band-pass filter is input to a clock terminal;
Have
The second synchronization unit includes:
A second flip-flop circuit in which the delayed signal is input to a data input terminal and the encoded data is input to a clock terminal;
The communication device according to claim 5. The signal generator is
A first synchronization signal is generated by synchronizing an inverted signal obtained by inverting the encoded data with a first state transition timing of a first delay signal obtained by delaying the encoded data by a predetermined first delay time. A synchronization unit;
A second synchronization unit that generates a second synchronization signal obtained by synchronizing a second delay signal obtained by delaying the encoded data by a predetermined second delay time at a first state transition timing of the encoded data;
A synthesis that generates the composite signal that changes to the second level in response to a first state transition of the second synchronization signal and changes to the first level in response to a second state transition of the first synchronization signal. And
Having
The communication apparatus according to any one of claims 1 to 4. The first synchronization unit includes:
An inverting circuit for generating the inverted signal obtained by inverting the encoded data;
A first low-pass filter to which the encoded data is input;
A logic circuit to which a signal output from the first low-pass filter is input;
A first flip-flop circuit in which the inverted signal is input to a data input terminal and the delay signal output from the logic circuit is input to a clock terminal;
Have
The second synchronization unit includes:
A second low-pass filter to which the encoded data is input;
A second flip-flop circuit in which a signal output from the second low-pass filter is input to a data input terminal, and the encoded data is input to a clock terminal;
The communication apparatus according to claim 9. The signal generator is
A first synchronization unit that generates a first synchronization signal that inverts the encoded data and synchronizes the encoded data with a first state transition timing of a delayed signal delayed by a predetermined delay time;
A second synchronization unit for generating a second synchronization signal in which the delay signal is synchronized with a first state transition timing of an inverted signal obtained by inverting the encoded data;
A synthesis that generates the composite signal that changes to the second level in response to a first state transition of the second synchronization signal and changes to the first level in response to a second state transition of the first synchronization signal. And
Having
The communication apparatus according to any one of claims 1 to 4. The delay time is greater than the width of the first polarity pulse and the width of the second polarity pulse;
The communication device according to any one of claims 5 to 11. The second waveform, the third waveform, and the fourth waveform change from the first level to the second level at the respective central positions;
The delay time is shorter than half the period of the first encoded data and the second encoded data.
The communication device according to any one of claims 5 to 12. A communication device for generating encoded data including first encoded data corresponding to input data of a first logical value and second encoded data corresponding to input data of a second logical value,
A first waveform corresponding to the first encoded data, a second waveform corresponding to a single second encoded data sandwiched between the plurality of first encoded data, and a plurality of continuous second encoded data A waveform generating unit that generates a third waveform corresponding to the first second encoded data and a fourth waveform corresponding to the last second encoded data among the plurality of consecutive second encoded data When,
A selection unit that selects one waveform from the first waveform, the second waveform, the third waveform, and the fourth waveform based on the pattern of the input data;
A communication device comprising: The selection unit includes:
A first delay signal obtained by delaying the input data by a first delay time; a second delay signal obtained by delaying the input data by a second delay time; and a third delay signal obtained by delaying the input data by a third delay time. A delay circuit for generating a delay signal;
A selection circuit that selects one waveform from the first waveform, the second waveform, the third waveform, and the fourth waveform based on the first delay signal, the second delay signal, and the third delay signal; ,
Having
The communication apparatus according to claim 14. A communication system comprising a first communication device and a second communication device,
Encoded data including first encoded data corresponding to the first waveform transmitted from the second communication device, and second encoded data corresponding to any one of the second waveform, the third waveform, and the fourth waveform. The first communication device that receives and decodes
The second waveform and the third waveform change to the second level according to the first state transition, and the second waveform and the fourth waveform immediately after the first waveform according to the first state transition. A signal generator for generating a composite signal that changes to one level;
An output unit that outputs decoded data obtained by synchronizing the synthesized signal with a first state transition timing in the encoded data;
With
The second communication device receives any one of the first encoded data corresponding to the first waveform, the second waveform, the third waveform, and the fourth waveform received by the first communication device. A transmission unit for transmitting the encoded data including the second encoded data corresponding to
The second waveform is assigned to a single second encoded data sandwiched between a plurality of the first encoded data,
The third waveform is assigned to the first second encoded data among a plurality of continuous second encoded data,
The fourth waveform is assigned to the last second encoded data among the plurality of continuous second encoded data.
Communications system.

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