JP6239210B1 - Control device, equipment and control program - Google Patents

Abstract

In the control device, the first processing unit (51) executes the calculation of the output value for control by the digital arithmetic device (21) as the first processing. The second processing unit (52) calculates the input value input to the first processing unit (51) in order to increase the calculation accuracy of the first processing as the second processing. The digital arithmetic unit (21) executes an arithmetic operation that increases the operational accuracy of. The schedule processing unit (54) sets the calculation amount and calculation frequency of the second process to the second processing unit (52) in accordance with the restriction between the usage time of the digital calculation device (21) and the calculation accuracy of the first process. Adjust at least one of the following.

Description

  The present invention relates to a control device, a device, and a control program.

  Power electronics equipment such as an electric motor and a power control device is generally realized using a combination of a switching element and a control device. A part or many parts of the control mechanism of the control device are generally realized by software operating on a microcomputer.

  The demand for power electronics equipment in recent years is higher than before. In particular, low loss and downsizing are required.

  In order to meet the requirements, it is necessary to control the lower loss elements at high switching speeds. It is necessary to perform control in a shorter time.

  On the other hand, matters to be considered regarding control are increasing. In order to realize electrically and physically low noise control in consideration of multiple inputs, multiple outputs, and multiple constraints, it is necessary to realize complex control such as model predictive control. Model predictive control is described in Non-Patent Document 1.

  For the purpose of cost reduction, it is often necessary to realize not only control but also communication or abnormality monitoring associated with control with a single microcomputer. In such a case, it is often necessary to realize processing other than control with low response or long processing time in addition to control with high response or short processing time.

  Therefore, it is necessary to secure other necessary processing time while ensuring the processing time for control so as to keep the control quality appropriately.

  Patent Documents 1 and 2 describe techniques related to task scheduling.

  Patent Document 3 describes a technique that omits a part of the processing according to the remaining time.

Japanese Patent Laying-Open No. 2015-136259 International Publication No. 2012/104901 JP 2007-252056 A

Li Dai, Yuanqing Xia, Mengyin Fu and Magdi S. Mahmud, “Discrete-Time Model Predictive Control”, Chapter 4, “Advanceds in Discrete Time Systems”, book edited by Magdi S. Mahmaud, December 5, 2012

  In the techniques described in Patent Document 1 and Patent Document 2, a mechanism for adjusting the processing time for control is not provided. Therefore, it is not possible to secure a necessary processing time other than the control.

  In the technique described in Patent Document 3, a mechanism for maintaining control quality is not provided. Therefore, when the remaining time becomes short, the control quality deteriorates. Then, an event deviating from the assumed control sequence occurs, such as motor step-out.

  It is an object of the present invention to secure other necessary processing time while ensuring the processing time for control so as to keep the control quality appropriately.

A control device according to one aspect of the present invention includes:
As a first process, a first processing unit that executes calculation of an output value for control by a digital arithmetic device;
The second process is a calculation of an input value input to the first processing unit in order to increase the calculation accuracy of the first process, and an operation in which the calculation accuracy of the first process increases as the calculation amount increases. A second processing unit executed by the arithmetic device;
A schedule processing unit that adjusts at least one of the calculation amount and the calculation frequency of the second processing with respect to the second processing unit in accordance with the restriction between the usage time of the digital arithmetic device and the calculation accuracy of the first processing. With.

  In the present invention, calculation of an output value for control is executed as the first process. The second process is an input value calculation for increasing the calculation accuracy of the first process, and an operation in which the calculation accuracy of the first process increases as the calculation amount increases. At least one of the calculation amount and the calculation frequency of the second process is adjusted according to the restriction between the usage time of the digital calculation device and the calculation accuracy of the first process. For this reason, it is possible to secure other necessary processing time while ensuring the processing time for control so as to appropriately maintain the control quality.

FIG. 2 is a circuit diagram illustrating a configuration of a device according to Embodiment 1. FIG. 2 is a block diagram showing a hardware configuration of a control device according to the first embodiment. The figure which shows the example of the gate voltage control by PWM. FIG. 2 is a block diagram showing a functional configuration of a control device according to the first embodiment. FIG. 3 is a diagram illustrating an operation example of a feedforward control unit of the control device according to the first embodiment. FIG. 3 is a diagram illustrating an input / output example of a feedback control unit of the control device according to the first embodiment. 6 is a graph showing an example of calculation of an estimation error by a control accuracy prediction unit of the control device according to Embodiment 1. 5 is a flowchart showing an operation of a control accuracy prediction unit of the control device according to the first embodiment. 4 is a table illustrating a map example of a control accuracy prediction unit of the control device according to the first embodiment. 5 is a flowchart showing an operation of a scheduling execution unit of the control device according to the first embodiment. FIG. 3 is a sequence diagram illustrating an example of cooperative operation between functional elements of the control device according to the first embodiment. FIG. 3 is a sequence diagram illustrating an example of cooperative operation between functional elements of the control device according to the first embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals. In the description of the embodiments, the description of the same or corresponding parts will be omitted or simplified as appropriate. The present invention is not limited to the embodiments described below, and various modifications can be made as necessary. For example, the embodiment described below may be partially implemented.

Embodiment 1 FIG.
This embodiment will be described with reference to FIGS.

*** Explanation of configuration ***
With reference to FIG. 1, the structure of the apparatus 10 which concerns on this Embodiment is demonstrated.

  The device 10 is specifically a power electronics device. The device 10 includes a synchronous motor 11, a switching element 12, and a control device 13.

  The synchronous motor 11 may be replaced with an asynchronous motor, or may be replaced with a power control device or the like. That is, the device 10 may include an arbitrary element such as an electric motor or a power control device as an element to be controlled.

  The switching element 12 is an element for adjusting a current input to the synchronous motor 11. The switching element 12 is, for example, a MOSFET. “MOSFET” is an abbreviation for Metal-Oxide-Semiconductor Field-Effect Transistor.

  The control device 13 is a device that controls the rotation of the synchronous motor 11 by controlling the gate voltage of the switching element 12 via the gate signal line 14. Part or many parts of the control mechanism of the control device 13 are realized by software operating on a microcomputer.

  With reference to FIG. 2, the hardware configuration of the control device 13 according to the present embodiment will be described.

The control device 13 is a microcomputer or a device including a microcomputer. The control device 13 includes a digital arithmetic device 21, a memory 22, a real-time clock 23, an AD converter 24, a serial communication device 25, a general-purpose IO 26, a pulse width modulator 27, a flash ROM 28, a watchdog timer 29, and an interrupt controller 30. Other hardware is provided. “AD” is an abbreviation for Analog to Digital. “IO” is an abbreviation for Input / Output. “ROM” is an abbreviation for Read Only Memory. In the figure, “RTC” is an abbreviation for Real Time Clock. “GPIO” is an abbreviation for General Purpose Input / Output. "PWM" is Pulse Width
Abbreviation for Modulator. “WDT” is an abbreviation for Watchdog Timer. The digital arithmetic unit 21 is connected to other hardware via the bus 31 and controls these other hardware.

  The digital arithmetic unit 21 is a processor in the present embodiment. The processor is an IC that performs various processes. “IC” is an abbreviation for Integrated Circuit. The processor is, for example, a CPU. “CPU” is an abbreviation for Central Processing Unit.

  The memory 22 is, for example, a RAM. “RAM” is an abbreviation for Random Access Memory.

  The AD converter 24 is a device for acquiring the sensor value of the synchronous motor 11.

  The serial communication device 25 is a device for receiving an operation request from the outside via the input / output port 32.

  The pulse width modulator 27 is a device for controlling the gate voltage of the switching element 12 via the input / output port 32 by PWM. “PWM” is an abbreviation for Pulse Width Modulation.

  FIG. 3 shows an example of gate voltage control by PWM.

  In PWM control, a fixed carrier cycle is often set. The energization ratio is adjusted by the duty ratio, which is the ratio of the on time to the carrier period, and the voltage or current is controlled. As a result, an AC wave is generated and the synchronous motor 11 can be controlled.

  Actually, the carrier wave 42 is compared with the reference wave 41 to be output. By setting only the time zone in which the carrier wave 42 exceeds the reference wave 41 as the energization time, the PWM waveform 43 is realized. When viewed globally, the voltage generated by the PWM waveform 43 matches the reference wave 41.

  With reference to FIG. 4, the functional configuration of the control device 13 according to the present embodiment will be described.

  The control device 13 includes a first processing unit 51, a second processing unit 52, a third processing unit 53, and a schedule processing unit 54 as functional elements. The functions of the first processing unit 51, the second processing unit 52, the third processing unit 53, and the schedule processing unit 54 are realized by software.

  The first processing unit 51 includes a feedforward control unit 61 that directly controls output, and a sensor value acquisition unit 64 that provides a sensor value to the feedback control unit 62.

  The second processing unit 52 includes a feedback control unit 62 that controls the operation of the feedforward control unit 61 globally while confirming the sensor value.

  The third processing unit 53 includes a communication processing unit 63 that executes communication processing as processing other than control.

  The schedule processing unit 54 includes a control accuracy prediction unit 65 that calculates an estimated error value for scheduling, and a scheduling execution unit 66 that creates a schedule.

  The flash ROM 28 stores a control program that is a program for realizing the functions of the first processing unit 51, the second processing unit 52, the third processing unit 53, and the schedule processing unit 54. The control program is loaded into the memory 22 and executed by the digital arithmetic device 21.

  Information, data, signal values, and variable values indicating the processing results of the first processing unit 51, the second processing unit 52, the third processing unit 53, and the schedule processing unit 54 are stored in the memory 22 or the digital arithmetic unit 21. Stored in a register or cache memory.

  The control device 13 may include a plurality of digital arithmetic devices that replace the digital arithmetic device 21. The plurality of digital arithmetic units share the execution of the control program. Each digital arithmetic device is a processor, like the digital arithmetic device 21.

  The control program may be stored in a portable recording medium such as a magnetic disk and an optical disk.

*** Explanation of operation ***
With continued reference to FIG. 4, the operation of the control device 13 according to the present embodiment will be described. The operation of the control device 13 corresponds to the control method according to the present embodiment.

  The first processing unit 51 executes the calculation of the output value for control by the digital arithmetic device 21 as the first processing. The first process may be an arbitrary high response process, but is a feedforward control process in the present embodiment. Specifically, the first process is calculation of the duty ratio of a signal output to the switching element 12 for controlling the synchronous motor 11. The first process is executed by the feedforward control unit 61.

  The second processing unit 52 is a calculation of an input value input to the first processing unit 51 in order to increase the calculation accuracy of the first process as the second process, and the calculation accuracy of the first process increases as the calculation amount increases. The ascending calculation is executed by the digital calculation device 21. The second process may be any quasi-high response process, but is a feedback control process in the present embodiment. The second process may be a process using an arbitrary control method, but is a process using model predictive control in the present embodiment. Specifically, the second process is an operation command value input to the first processing unit 51 according to the measurement value of the position sensor of the synchronous motor 11 acquired by the sensor value acquisition unit 64. The second process is executed by the feedback control unit 62.

  The third processing unit 53 executes a process different from the first process and the second process by the digital arithmetic device 21 as the third process. The third process may be any low response process, but is a communication process in the present embodiment. Specifically, the third process is a communication process that is not directly related to the control of the synchronous motor 11. The third process is executed by the communication processing unit 63.

  The schedule processing unit 54 adjusts at least one of the calculation amount and the calculation frequency of the second processing with respect to the second processing unit 52 in accordance with the restriction between the usage time of the digital calculation device 21 and the calculation accuracy of the first processing. To do. In the present embodiment, both the calculation amount and the calculation frequency of the second process are adjusted.

  The schedule processing unit 54 further determines whether or not to cause the third processing unit 53 to execute at least a part of the third process in accordance with the restriction between the usage time of the digital arithmetic device 21 and the calculation accuracy of the first process. . Specifically, the schedule processing unit 54 causes the third processing unit 53 to execute the third process according to the restriction between the usage time of the digital arithmetic device 21 and the calculation accuracy of the first process, or one of the third processes. Or whether to execute the third process.

  Note that a predetermined time may be reserved for the third process, and the remaining time may be allocated to the first process and the second process by the schedule processing unit 54. That is, the schedule processing unit 54 determines that the time required for executing the first process and the second process is within the remaining time obtained by subtracting the time reserved for the third process from the upper limit value of the usage time of the digital arithmetic device 21. And the calculation amount of the second process and the calculation frequency may be adjusted so that the calculation accuracy of the first process exceeds the threshold.

  The details of the operation of the control device 13 will be described with reference to FIGS.

  FIG. 5 shows an operation example of the feedforward control unit 61.

  In this example, the feedforward control unit 61 receives an operation mode, a voltage command value, a measurement mechanical angle of the synchronous motor 11 and a measurement time as an operation command value from the feedback control unit 62. The feedforward control unit 61 calculates the predicted mechanical angle θ of the synchronous motor 11 by an internal calculation using the mechanical angle predictor 71. The feedforward control unit 61 executes a duty value conversion 72 to calculate a three-phase duty ratio with respect to the predicted mechanical angle θ and the voltage command value. The operation mode takes one of an operating state and a stopped state. The feedforward control unit 61 executes the operation mode determination 73 and outputs a three-phase duty ratio when the operation mode is in the operating state. The feedforward control unit 61 does not output a three-phase duty ratio when the operation mode is in a stopped state.

  FIG. 6 shows an input / output example of the feedback control unit 62.

  The feedback control unit 62 receives the position sensor value obtained from the sensor value acquisition unit 64 and the calculation accuracy obtained from the scheduling execution unit 66 as inputs, and outputs an operation command value to the feedforward control unit 61.

  The feedback control unit 62 performs control based on the operation plan determined by the scheduling execution unit 66.

The control performed by the feedback control unit 62 needs to satisfy the following properties.
An algorithm that can operate even if the schedule elements such as the accuracy and the execution frequency specified by the scheduling execution unit 66 are changed is used.
-Control quality can be estimated on some scale with respect to the degree of computation.
・ Determine the time required for the degree of computation.
The feedforward control unit 61 operates with a certain degree of control quality even during a period when the feedback control unit 62 does not operate.

  Model predictive control can be used as control satisfying such properties. Model predictive control is also called Receding Horizon control.

  Model predictive control includes an algorithm for searching for an optimal solution. The accuracy of the obtained result varies depending on the number of times the search operation is performed. Since the calculation is repeatedly performed, it takes a calculation time for the number of executions when the search calculation is repeated.

The procedure of model predictive control will be briefly described.
A control prediction for a fixed time corresponding to the predicted horizon based on a control plan for a fixed time corresponding to the control horizon is performed based on the plant model. The gap between the predicted horizon and the control horizon is filled with a fixed value or the like.
・ The prediction result is applied to the evaluation function to measure good or bad.
Based on the evaluation function, an optimization search using the control plan as a solution space is performed.

  Refer to Non-Patent Document 1 for details of model predictive control.

  As shown in FIG. 4, the communication processing unit 63 presents a deadline, request processing time, minimum processing time, and error response time in accordance with the current processing load and interrupt. Specifically, when a communication request comes, the communication processing unit 63 differs in required processing and deadline for each communication type, so that the request processing time, minimum processing time, and error response time are estimated immediately after message analysis. Add a quote.

  A deadline is a target response time. The request processing time is a time during which all requests currently held by the communication processing unit 63 can be processed. The minimum processing time is a time during which the communication processing unit 63 can process a high priority request currently held. The error response time is a time required for returning an error to a request that cannot be processed by the communication processing unit 63.

  When an error is notified from the scheduling execution unit 66, the communication processing unit 63 performs a process of returning an error without performing an actual process on a request scheduled to be processed. For example, when the communication processing unit 63 is requested by the communication source to read the setting value placed on the flash ROM 28, if the error is notified by the scheduling execution unit 66, the error is not read from the flash ROM 28. To return.

  The control accuracy prediction unit 65 has an algorithm for predicting the execution time of the control of the feedback control unit 62. The control accuracy prediction unit 65 searches for a schedule candidate for the requested processing time using this algorithm. The scheduling execution unit 66 executes scheduling for determining a schedule from the result of the control accuracy prediction unit 65 with respect to the requested processing time.

  The control accuracy predicting unit 65 determines that the accuracy is higher as the estimated deviation from the “control state” that can be generated is smaller. In the present embodiment, the estimated divergence amount is calculated as a scale for measuring accuracy degradation mainly due to feedback correction and calculation error, but another scale may be used.

In the present embodiment, the control accuracy prediction unit 65 evaluates and searches the schedule based on the following information.
・ Control quality to be assured by the element to be controlled, that is, calculation accuracy, calculation time for iteration count and execution cycle, that is, calculation time according to the calculation amount and calculation frequency, reliability decrease when feedback is not performed Sequence, i.e. the time until the control quality drops to standard quality when feedback control is not used

  FIG. 7 shows a calculation example of the estimation error by the control accuracy prediction unit 65 in a graph of the error estimation amount with respect to time. The estimated error amount corresponds to the aforementioned estimated divergence amount.

  As the estimated error amount increases, the accuracy deteriorates. On the other hand, the accuracy is restored by the occurrence of feedback by the feedback control unit 62. By changing the number of feedback iterations and the execution period, the change pattern represented by the solid line can be changed to the change pattern represented by the broken line.

  Hereinafter, an example of estimation by the control accuracy prediction unit 65 will be described.

Let EEi (n) be the prediction error of the internal state at time n. Let EEext be the error deterioration estimation coefficient in the interaction with the outside world. The transition with respect to the unit time lapse of the error when the feedforward control unit 61 operates alone without feedback is
EEi (n + 1) = EEi (n) * EEext
It is expressed.

When feedback occurs, the estimated error amount decreases. The contribution of processing by the feedback control unit 62 is defined as FE. Let EEip be the estimated error value of the input value. Let EEc be the calculation error. The error when feedback occurs is
EEi (n + 1) = (1-FE) * EEi (n) * EEext + FE * EEc * EEip
Is formulated.

The deadline time is d, the elapsed time from the last feedback is c, and the feedback period is y. From the above recurrence formula, the estimated error amount at the time of the deadline can be calculated by the following formula.

  With reference to FIG. 8, the operation of the schedule search by the control accuracy prediction unit 65 will be described.

  In step S <b> 101, the control accuracy prediction unit 65 searches for the condition of the cycle y and the number of operations x that satisfy the request processing time treq in the schedule.

と表せる。制御精度予測部６５は、ｔｒｅｓ（ｙ，ｘ，ｄ，ｃ）＜ｔｒｅｑとなる周期ｙおよび演算回数ｘの組み合わせを算出する。The estimated calculation time per evaluation operation is tev, and the operation time per cycle of the feedforward control unit 61 is th. The time tres until the deadline is

It can be expressed. The control accuracy predicting unit 65 calculates a combination of the cycle y and the number of operations x where tres (y, x, d, c) <treq.

  In step S102, the control accuracy prediction unit 65 searches for the schedule with the best accuracy.

The schedule is a combination of the cycle y and the operation count x. The calculation error EEc is defined as a function EEc (x) of the number of calculations x. The estimated error value EEd (y, x, d, c) at the time of deadline can be determined by the following equation.

  The control accuracy predicting unit 65 searches for a combination of the cycle y and the number of times of calculation x that minimizes the EEd result.

  In many cases, it is faster to use a fixed pattern for searching. Therefore, in practice, it is preferable to prepare a map for deriving the cycle y and the number of operations x with respect to the frequently used deadline d and elapsed time c values and the requested processing time treq.

  FIG. 9 shows a configuration example of the map. The control accuracy prediction unit 65 searches the map and, if there is a corresponding combination, uses the value of that combination. The control accuracy prediction unit 65 uses the above-described algorithm or another simple algorithm outside the map range.

  With reference to FIG. 10, the operation of schedule determination by the scheduling execution unit 66 will be described.

  In step S <b> 201, the scheduling execution unit 66 searches for a schedule with the best accuracy for securing the requested processing time notified from the communication processing unit 63.

  In step S202, the scheduling execution unit 66 determines whether or not a schedule that can secure the requested processing time satisfies the required accuracy.

  If the required accuracy is satisfied in step S202, in step S203, the scheduling execution unit 66 outputs a schedule that can secure the required processing time as a result.

  If the required accuracy is not satisfied in step S202, in step S204, the scheduling execution unit 66 searches for a schedule with the best accuracy for securing the minimum processing time notified from the communication processing unit 63.

  In step S205, the scheduling execution unit 66 determines whether a schedule that can secure the minimum processing time satisfies the required accuracy.

  If the required accuracy is satisfied in step S205, in step S206, the scheduling execution unit 66 outputs a schedule that can secure the minimum processing time as a result.

  If the required accuracy is not satisfied in step S205, in step S207, the scheduling execution unit 66 returns an error to the communication processing unit 63, and limits the processing of the communication processing unit 63 to error return only. Thereby, the required accuracy can be ensured and the safety of the control can be ensured. In addition, priority can be given to the process of the communication process part 63, and safety | security can also be ensured by shifting a control process to an abnormal process.

  As described above, the schedule processing unit 54 regards the time taken to execute the first process as a fixed time. The schedule processing unit 54 is notified from the third processing unit 53 with the time required for executing the third processing as the requested processing time. In step S201, the schedule processing unit 54 falls within the first remaining time obtained by subtracting the fixed time and the requested processing time from the upper limit value of the usage time of the digital arithmetic device 21 for the time taken to execute the second processing, And the combination of the calculation amount and calculation frequency of a 2nd process in which the calculation precision of a 1st process exceeds a threshold value is searched. Thereby, in step S202, the schedule process part 54 adjusts the calculation amount and calculation frequency of a 2nd process.

  The schedule processing unit 54 is notified from the third processing unit with the time taken to execute a part of the third processing as the minimum processing time. In step S202, if there is no combination of the amount of calculation and the calculation frequency of the second process within which the time required for executing the second process falls within the first remaining time and the calculation accuracy of the first process exceeds the threshold, step The process of S204 is performed. In step S204, the schedule processing unit 54 falls within the second remaining time obtained by subtracting the fixed time and the minimum processing time from the upper limit value of the usage time of the digital arithmetic device 21, and the time taken to execute the second processing. And the combination of the calculation amount and calculation frequency of a 2nd process in which the calculation precision of a 1st process exceeds a threshold value is searched. Thereby, in step S206, the schedule process part 54 adjusts the calculation amount and calculation frequency of a 2nd process.

  In step S205, if there is no combination of the amount of calculation and the calculation frequency of the second process within which the time taken to execute the second process falls within the second remaining time and the calculation accuracy of the first process exceeds the threshold value, step The process of S207 is performed. In step S207, the schedule processing unit 54 falls within the third remaining time obtained by subtracting the fixed time from the upper limit value of the usage time of the digital arithmetic device 21, and the time required for executing the second process is within the first process. The combination of the calculation amount and the calculation frequency of the second process in which the calculation accuracy of the second calculation exceeds the threshold value is searched. Thereby, in step S207, the schedule process part 54 adjusts the calculation amount and calculation frequency of a 2nd process.

  With reference to FIG. 11, an example of cooperative operation between the functional elements of the control device 13 will be described.

  In step S301 and step S302, the scheduling execution unit 66 drives the feedforward control unit 61 based on the schedule at each time point. In step S <b> 321, the scheduling execution unit 66 receives a request from the communication processing unit 63. In step S331, the scheduling execution unit 66 reviews the schedule. In step S341, the scheduling execution unit 66 performs the processing after step S201 in FIG. If necessary, in step S342, the scheduling execution unit 66 performs the processing after step S204 in FIG. In step S332, the scheduling execution unit 66 executes scheduling and sets the cycle and the number of operations. In step S <b> 351, the scheduling execution unit 66 issues an operation permission to the communication processing unit 63. In step S361, the communication processing unit 63 executes actual processing. Since this process is a low-priority process, it is always preempted by the processes of the feedforward control unit 61 and the feedback control unit 62.

  In step S303 and step S304, the scheduling execution unit 66 drives the feedforward control unit 61 based on the schedule at each time point. In step S311, the scheduling execution unit 66 drives the feedback control unit 62 based on the schedule at that time. In step S305 and step S306, the scheduling execution unit 66 drives the feedforward control unit 61 based on the schedule at each time point.

  Although not shown, after the deadline has elapsed, the scheduling execution unit 66 reviews the schedule again and continues the operation.

  With reference to FIG. 12, an example in which an appropriate schedule is not found and an error response is performed will be described.

  In step S451 instead of step S351, the scheduling execution unit 66 issues an error response to the communication processing unit 63. In step S461 instead of step S361, the communication processing unit 63 executes error processing.

*** Explanation of the effect of the embodiment ***
With the above operation, a minimum control quality can be secured for the control of the control target element. In addition, the time required for low response processing such as communication processing can be ensured as much as possible. If time cannot be secured, error processing can be performed.

  In the present embodiment, calculation of an output value for control is executed as the first process. The second process is an input value calculation for increasing the calculation accuracy of the first process, and an operation in which the calculation accuracy of the first process increases as the calculation amount increases. At least one of the calculation amount and the calculation frequency of the second process is adjusted according to the restriction between the usage time of the digital calculation device 21 and the calculation accuracy of the first process. For this reason, it is possible to secure other necessary processing time while ensuring the processing time for control so as to appropriately maintain the control quality.

In the present embodiment, the switching control system realized by the digital arithmetic device 21 includes the following elements for controlling the control target elements.
A feedforward control unit 61 that is controlled by the feedback control unit 62 and / or the feedback control unit 62 that can adjust at least one of the control frequency and the control accuracy, but operates autonomously within a certain range.
A control accuracy prediction unit 65 that searches for a combination of a schedule capable of realizing the constraint based on the calculation amount and the calculation accuracy of the feedback control unit 62
A scheduling execution unit 66 that performs scheduling and calculation accuracy designation based on the search result of the control accuracy prediction unit 65

  According to the present embodiment, in the switching control system realized by the digital arithmetic unit 21, the time used for the control processing is ensured so as to keep the control quality appropriately, and the time required for other processing is reduced. Can be secured.

  In the present embodiment, the schedule processing unit 54 is provided with a process for calculating a plan based on the control accuracy and the processing time, and a schedule that balances the control accuracy and the time for processing other than the control can be determined. it can.

  In the present embodiment, the efficiency can be improved by using a table for searching for scheduling and calculation accuracy designation in the switching control system.

  In this embodiment, when scheduling is impossible in the switching control system, error processing is executed as processing other than control, thereby reducing the load and ensuring control accuracy.

*** Other configurations ***
In the present embodiment, the functions of the first processing unit 51, the second processing unit 52, the third processing unit 53, and the schedule processing unit 54 are realized by software, but as a modification, the first processing unit 51, the second processing unit 54, The functions of the processing unit 52, the third processing unit 53, and the schedule processing unit 54 may be realized by a combination of software and hardware. That is, some of the functions of the first processing unit 51, the second processing unit 52, the third processing unit 53, and the schedule processing unit 54 may be realized by a dedicated electronic circuit, and the rest may be realized by software.

  The dedicated electronic circuit is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, a logic IC, a GA, an FPGA, or an ASIC. “GA” is an abbreviation for Gate Array. “FPGA” is an abbreviation for Field-Programmable Gate Array. “ASIC” is an abbreviation for Application Specific Integrated Circuit.

  As another modification, the functions of the first processing unit 51, the second processing unit 52, the third processing unit 53, and the schedule processing unit 54 may be realized by hardware. That is, the digital arithmetic device 21 is a processor in the present embodiment, but may be an arithmetic device such as an FPGA.

  DESCRIPTION OF SYMBOLS 10 apparatus, 11 synchronous motor, 12 switching element, 13 control apparatus, 14 gate signal line, 21 digital arithmetic unit, 22 memory, 23 real time clock, 24 AD converter, 25 serial communication device, 26 general purpose IO, 27 pulse width modulator 28 Flash ROM, 29 Watchdog timer, 30 Interrupt controller, 31 Bus, 32 Input / output port, 41 Reference wave, 42 Carrier wave, 43 PWM waveform, 51 First processing unit, 52 Second processing unit, 53 Third processing Unit, 54 schedule processing unit, 61 feed forward control unit, 62 feedback control unit, 63 communication processing unit, 64 sensor value acquisition unit, 65 control accuracy prediction unit, 66 scheduling execution unit, 71 mechanical angle predictor, 72 duty value conversion 73 Operation mode judgment.

Claims (7)

As a first process, a first processing unit that executes calculation of an output value for control by a digital arithmetic device;
The second process is a calculation of an input value input to the first processing unit in order to increase the calculation accuracy of the first process, and an operation in which the calculation accuracy of the first process increases as the calculation amount increases. A second processing unit executed by the arithmetic device;
As a third process, a third processing unit that executes a process different from the first process and the second process by the digital arithmetic device;
The time required to execute the first process is regarded as a fixed time, the time required to execute the third process is notified from the third processing unit as the required processing time, and the time required to execute the second process is the digital time. In the second process, the calculation time of the second process is within a first remaining time obtained by subtracting the fixed time and the required processing time from the upper limit value of the use time of the arithmetic device , and the calculation accuracy of the first process exceeds a threshold value . by searching for a combination of computing amount and calculating the frequency control device and a schedule processing section for adjusting the operation amount and the operation frequency at the second processing. The schedule processing unit is notified from the third processing unit with a time required for execution of a part of the third processing as a minimum processing time, and a time required for execution of the second processing falls within the first remaining time. In addition, if there is no combination of the calculation amount and the calculation frequency of the second process in which the calculation accuracy of the first process exceeds the threshold value, the time required to execute the second process is equal to the usage time of the digital calculation device. Calculation amount and calculation frequency of the second process that fall within a second remaining time obtained by subtracting the fixed time and the minimum processing time from an upper limit value, and the calculation accuracy of the first process exceeds the threshold value by searching for a combination of the control device according to claim 1 for adjusting the amount of computation and calculation frequency of the second processing. The schedule processing unit includes a calculation amount and a calculation frequency of the second process in which the time taken to execute the second process is within the second remaining time and the calculation accuracy of the first process exceeds the threshold value. If the combination is not included, the time required to execute the second process falls within the third remaining time obtained by subtracting the fixed time from the upper limit value of the use time of the digital arithmetic device, and the first process calculation accuracy is above the threshold, by searching a combination of the operation amount and operation frequency of the second processing, the control apparatus according to claim 2 for adjusting the amount of computation and calculation frequency of the second processing. The first process is a process of feedforward control,
The second process, the control device according to any one of claims 1 3 is a process feedback control. The second process, the control device according to claim 1, any one of 4 is a process using a model predictive control. A control device according to any one of claims 1 to 5 ;
A device comprising an electric motor controlled by the control device. In a computer equipped with a digital arithmetic device,
A first process that is a calculation of an output value for control;
A second process that is a calculation of an input value for increasing the calculation accuracy of the first process, and the calculation accuracy of the first process increases as the calculation amount increases;
A third process which is a process different from the first process and the second process;
The time required to execute the first process is regarded as a fixed time, the time required to execute the third process is notified as the required processing time, and the time required to execute the second process is equal to the usage time of the digital arithmetic device . The amount of computation and the computation frequency of the second processing that fall within the first remaining time obtained by subtracting the fixed time and the requested processing time from the upper limit, and the computation accuracy of the first processing exceeds a threshold value by searching for a combination, the control program for executing the scheduling for adjusting the amount of computation and calculation frequency at the second processing.

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