JP6227151B2 - アドレスへの書き込みに対する監視命令を実行するスケーラブル機構 - Google Patents

アドレスへの書き込みに対する監視命令を実行するスケーラブル機構 Download PDF

Info

Publication number
JP6227151B2
JP6227151B2 JP2016545961A JP2016545961A JP6227151B2 JP 6227151 B2 JP6227151 B2 JP 6227151B2 JP 2016545961 A JP2016545961 A JP 2016545961A JP 2016545961 A JP2016545961 A JP 2016545961A JP 6227151 B2 JP6227151 B2 JP 6227151B2
Authority
JP
Japan
Prior art keywords
cache
core
address
monitoring
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016545961A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016532233A5 (zh
JP2016532233A (ja
Inventor
リウ、エン−チェン
ファヒム、バハー
ジー． ハルノア、エリック
ジー． ハルノア、エリック
ディー． チャンベルライン、ジェフリー
ディー． チャンベルライン、ジェフリー
ドレン、ステファン アール． バン
ドレン、ステファン アール． バン
ジュアン、アントニオ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority claimed from PCT/US2014/059130 external-priority patent/WO2015048826A1/en
Publication of JP2016532233A publication Critical patent/JP2016532233A/ja
Publication of JP2016532233A5 publication Critical patent/JP2016532233A5/ja
Application granted granted Critical
Publication of JP6227151B2 publication Critical patent/JP6227151B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

JP2016545961A 2014-10-03 2014-10-03 アドレスへの書き込みに対する監視命令を実行するスケーラブル機構 Active JP6227151B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2014/059130 WO2015048826A1 (en) 2013-09-27 2014-10-03 Scalably mechanism to implement an instruction that monitors for writes to an address

Publications (3)

Publication Number Publication Date
JP2016532233A JP2016532233A (ja) 2016-10-13
JP2016532233A5 JP2016532233A5 (zh) 2017-08-10
JP6227151B2 true JP6227151B2 (ja) 2017-11-08

Family

ID=56973722

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016545961A Active JP6227151B2 (ja) 2014-10-03 2014-10-03 アドレスへの書き込みに対する監視命令を実行するスケーラブル機構

Country Status (3)

Country Link
JP (1) JP6227151B2 (zh)
KR (1) KR101979697B1 (zh)
CN (1) CN105683922B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3872629A3 (en) * 2020-07-20 2022-01-05 Beijing Baidu Netcom Science And Technology Co., Ltd. Method and apparatus for executing instructions, device, and computer readable storage medium

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10394678B2 (en) * 2016-12-29 2019-08-27 Intel Corporation Wait and poll instructions for monitoring a plurality of addresses
US10860487B2 (en) * 2019-04-17 2020-12-08 Chengdu Haiguang Integrated Circuit Design Co. Ltd. Multi-core processing device and method of transferring data between cores thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7363474B2 (en) * 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
US7213093B2 (en) * 2003-06-27 2007-05-01 Intel Corporation Queued locks using monitor-memory wait
US20070282928A1 (en) * 2006-06-06 2007-12-06 Guofang Jiao Processor core stack extension
US20080005504A1 (en) * 2006-06-30 2008-01-03 Jesse Barnes Global overflow method for virtualized transactional memory
US9081687B2 (en) * 2007-12-28 2015-07-14 Intel Corporation Method and apparatus for MONITOR and MWAIT in a distributed cache architecture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3872629A3 (en) * 2020-07-20 2022-01-05 Beijing Baidu Netcom Science And Technology Co., Ltd. Method and apparatus for executing instructions, device, and computer readable storage medium
US11748099B2 (en) 2020-07-20 2023-09-05 Beijing Baidu Netcom Science And Technology, Co., Ltd. Method for executing instructions, device, and computer readable storage medium

Also Published As

Publication number Publication date
CN105683922B (zh) 2018-12-11
CN105683922A (zh) 2016-06-15
JP2016532233A (ja) 2016-10-13
KR20160041950A (ko) 2016-04-18
KR101979697B1 (ko) 2019-05-17

Similar Documents

Publication Publication Date Title
TWI556161B (zh) 用以實施監測寫入至一位址的指令之處理器、系統和方法
JP6708335B2 (ja) ユーザレベルの分岐及び結合を行うプロセッサ、方法、システム、及び命令
JP6143872B2 (ja) 装置、方法、およびシステム
JP6240964B2 (ja) 装置、方法、およびシステム
CN108885586B (zh) 用于以有保证的完成将数据取出到所指示的高速缓存层级的处理器、方法、系统和指令
US11030108B2 (en) System, apparatus and method for selective enabling of locality-based instruction handling
US9361233B2 (en) Method and apparatus for shared line unified cache
US9471494B2 (en) Method and apparatus for cache line write back operation
US20170185515A1 (en) Cpu remote snoop filtering mechanism for field programmable gate array
US20190303303A1 (en) System, method, and apparatus for detecting repetitive data accesses and automatically loading data into local cache to avoid performance inversion and waste of uncore resources
US20210374848A1 (en) Systems, Apparatuses, and Methods for Resource Bandwidth Enforcement
CN109661656B (zh) 用于利用条件所有权请求的智能存储操作的方法和装置
US9898298B2 (en) Context save and restore
US20170286301A1 (en) Method, system, and apparatus for a coherency task list to minimize cache snooping between cpu and fpga
US11531562B2 (en) Systems, methods, and apparatuses for resource monitoring
WO2019133172A1 (en) Processor, method, and system for reducing latency in accessing remote registers
JP6227151B2 (ja) アドレスへの書き込みに対する監視命令を実行するスケーラブル機構
US20180121353A1 (en) System, method, and apparatus for reducing redundant writes to memory by early detection and roi-based throttling
US9436605B2 (en) Cache coherency apparatus and method minimizing memory writeback operations
US9418024B2 (en) Apparatus and method for efficient handling of critical chunks
US10296464B2 (en) System, apparatus and method for dynamic profiling in a processor
US20180165200A1 (en) System, apparatus and method for dynamic profiling in a processor

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20160324

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160324

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170404

A524 Written submission of copy of amendment under article 19 pct

Free format text: JAPANESE INTERMEDIATE CODE: A524

Effective date: 20170703

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170912

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20171010

R150 Certificate of patent or registration of utility model

Ref document number: 6227151

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250