JP6217344B2 - Method and apparatus for controlling access to shared memory - Google Patents

Description

  The present invention relates to an access control method and apparatus for a shared memory.

  Conventionally, when a device that accesses a shared memory from a plurality of interfaces is incorporated in the device, the memory access of each device is managed in the device. Therefore, the management of the memory access timing is easy. On the other hand, for example, when a memory is shared with a non-embedded device such as an IC tag reader / writer, the timing for performing memory access between the embedded device and the non-embedded device has been clearly different. There was less need to consider collisions due to simultaneous access to memory.

  However, in recent years, devices such as contact-type or non-contact-type IC tags that perform memory access due to reception of signals transmitted from external devices such as reader / writers are increasing. For example, a contact-type or non-contact-type IC tag communicates with an external device such as a reader / writer, takes out data and a clock signal placed on a carrier wave, and writes the data to the memory of the IC card. In recent years, a configuration in which a device such as a display device is mounted so that a part of information held in an IC tag can be displayed visually is known (for example, see Patent Document 1).

  In such a configuration, the CPU and the controller of the IC tag that writes the data received via the antenna share the memory of the IC tag, and write and read to the memory of the IC tag, respectively.

  For example, when the other device is a display device, a carrier wave is received from the reader / writer and the CPU is activated. Then, a hardware control program for display and display information (for example, billing information) are displayed from the memory of the IC tag. Read and perform display control. On the other hand, in communication with an external device such as a reader / writer, the controller of the IC tag performs writing to or reading from the memory in the IC tag based on a command received via an antenna or an electrical contact. In such a configuration, the timing for accessing the controller of the CPU and the IC tag is the same, so simultaneous writing to the memory occurs unless appropriate control is performed.

Therefore, it is necessary to avoid simultaneous writing to the shared memory, but conventionally, contention due to simultaneous access to the shared memory has been avoided by the following method.
a) Prioritize the memory access of the previously accessed device, and do not accept the access of other devices until the memory access by the previously accessed device is completed (see, for example, Patent Document 2).
b) Always give priority to access from either device. For example, when there is an access from the device A while the device B is accessing, the access from the device B is disconnected and the access from the device A is preferentially started (see, for example, Patent Document 3).

JP 2004-265176 A Japanese Patent Laid-Open No. 11-272822 JP 2002-31234 A

  As in Patent Documents 2 and 3, by separately providing a control circuit for realizing exclusive access, prohibiting or giving priority to access from any of the input / output interfaces does not change the circuit configuration. In other words, the number of necessary parts increases and the configuration becomes complicated. Further, it may be difficult to adjust the access timing on the external device side due to the configuration of the external device. For example, in an example of an IC tag, a device having a reader / writer function is often a smartphone or the like, but communication control is often performed by firmware located in a lower layer in the OSI reference model, and communication operation is performed. Modification is difficult.

  The present invention has been made in view of such problems, and the object of the present invention is a memory that does not have a memory access exclusive control mechanism (assuming that it has a plurality of input / output interfaces). However, an object of the present invention is to provide a method and apparatus that avoids collision of access requests from a plurality of different objects by simple and reliable means.

  In order to achieve the above object, the present invention provides a shared memory having a first input / output interface and a second input / output interface, and the first of the shared memories. A first device connected to the input / output interface; and a second device connected to the second input / output interface of the shared memory. When the power is supplied, the second device and The first device is activated, and then the first device and the second device are activated in an apparatus in which the second device and the first device start accessing the shared memory. Thereafter, the first device is made to wait for a predetermined time as a standby time setting, and after the predetermined time elapses, the first device is stored in the shared memory. Characterized by comprising an access adjustment means for avoiding simultaneous access to the shared memory by access.

  According to a second aspect of the present invention, in addition to the first aspect of the invention, when the first device accesses the shared memory after the predetermined time has elapsed and detects the occurrence of a collision, The apparatus further comprises means for updating the waiting time setting.

  According to a third aspect of the present invention, in addition to the first aspect of the present invention, the first device waits for a time designated by the standby time setting, and then accesses the shared memory to perform collision. When the occurrence is detected, after waiting further for a predetermined retry interval time, the access to the shared memory is retried. When the access to the shared memory is detected successfully, the retry interval is set in the wait time setting. The apparatus further comprises means for updating the waiting time setting by adding the time.

  According to a fourth aspect of the present invention, in addition to the first aspect of the present invention, after the first device waits for a time specified by the standby time setting, the shared memory is accessed and the shared memory is accessed. When detecting that the access to the memory is successful, the apparatus further comprises means for updating the standby time setting by subtracting a predetermined adjustment time from the standby time setting.

  According to a fifth aspect of the present invention, in addition to the first aspect of the present invention, the access adjusting means is the first in the access to the shared memory at a time specified by the standby time setting. The apparatus further comprises means for updating the waiting time setting by adding a time obtained by multiplying the number of retries after the collision has occurred and a predetermined retry interval time.

  According to a sixth aspect of the present invention, in addition to the first aspect of the present invention, after the first device waits for a predetermined time as the standby time setting, the shared memory is accessed and the shared memory is accessed. When it is detected that the access to the network is successful, a predetermined adjustment time is subtracted from the standby time setting, the standby time setting is updated, and the access adjusting means is designated by the updated standby time setting. After the first device is made to wait for a predetermined time, the access to the shared memory is detected and it is detected that the access to the shared memory is successful. The apparatus further comprises means for updating the waiting time setting by subtracting the adjustment time.

  According to a seventh aspect of the present invention, in addition to the first aspect of the present invention, the access adjusting means is configured to provide the first device for a time specified by the updated waiting time setting. It is characterized by making it wait.

  According to an eighth aspect of the present invention, there is provided an IC tag having an antenna for receiving a reception signal from a reader / writer or transmitting a transmission signal to the reader / writer, a first input / output interface, and a second input / output interface A memory, an embedded device, and an IC tag controller that accesses the IC tag memory for reading and writing signals transmitted to and received from the reader / writer via the antenna, and the embedded device are connected to control the embedded device A CPU for accessing the IC tag memory for reading and writing a control program and data, and an activation means for activating the IC tag controller and the CPU when receiving a wake-up signal from the reader / writer A first input / output of the IC tag memory In the IC tag device in which the CPU is connected to the interface and the IC tag controller is connected to the second input / output interface, after the IC tag controller and the CPU are activated by the activation means, a predetermined standby time setting is set. It is characterized by comprising an access adjusting means for avoiding simultaneous access to the IC tag memory by causing the CPU to wait for a certain time and allowing the CPU to access the memory after the predetermined time has elapsed.

  According to a ninth aspect of the present invention, in addition to the eighth aspect of the invention, the access adjustment means may access the IC tag memory after the CPU waits for a time specified by the standby time setting. When the occurrence of collision is detected, after waiting further for a predetermined retry interval time, the access to the IC tag memory is retried, and when the access to the IC tag memory is detected, the waiting time setting is performed. Further, the standby time setting is updated by adding the retry interval time.

  According to a tenth aspect of the present invention, in addition to the eighth aspect of the invention, after the CPU waits for a time designated by the standby time setting, the IC tag memory is accessed and the IC tag memory is accessed. When it is detected that the access to is successful, the standby time setting is updated by subtracting a predetermined adjustment time from the standby time setting.

  The invention according to claim 11 is a shared memory having a first input / output interface and a second input / output interface; a first device connected to the first input / output interface of the shared memory; A second device connected to the second input / output interface of the shared memory, and when powered, the second device and the first device are activated, and then the second device And the first device in a device for initiating access to the shared memory to avoid simultaneous access to the shared memory, wherein the first device and the second device are activated. After that, the first device is made to wait for a predetermined time as a standby time setting, and the first device is in front of the first device after the predetermined time has elapsed. Characterized in that to access the shared memory.

  In this configuration, one device connected to one of the plurality of interfaces of the shared memory waits for a certain period of time to avoid collision. According to this configuration, even a memory that does not have an exclusive control mechanism for memory access can realize a configuration for avoiding access collision to the shared memory with a simple and reliable configuration.

In addition, according to the second embodiment of the present invention, a learning mode is provided on one device side, and an optimal waiting time is learned. As an example of the learning mode, for example, when one device side waits for T ₁ + T ₂ hours and then accesses the shared memory, if collision does not occur, the variable wait time, which is a waiting time setting, is set to T ₁ + T ₂ To do. Thereafter, the shared memory is accessed in a shorter time than Variable Wait Time = T ₁ + T ₂ , and if no collision occurs, the Variable Wait Time is reset. The process is repeated to determine the optimum variable wait time. According to this configuration, even if the device has a different access time depending on the model, environment, etc., the waiting time can be set to an optimum time and collision can be avoided.

It is a figure which illustrates notionally the access with respect to the shared memory which has several input / output interfaces concerning embodiment of this invention. It is a block diagram which shows the internal structure of the IC tag apparatus concerning the 1st Embodiment of this invention. It is a flowchart of the collision avoidance processing in the IC tag device according to the first embodiment of the present invention. It is a block diagram which shows the internal structure of the IC tag apparatus concerning the 2nd Embodiment of this invention. It is a flowchart of the collision avoidance process in the IC tag apparatus which has learning mode concerning 2 Embodiment of this invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In this specification, memory access means writing, reading, erasing, etc. to the memory. Collision means a collision of a plurality of communications, and a wakeup action is a transition from a state where the IC tag does not accept commands (sleep state) to a state where commands can be accepted (wakeup state). It is a trigger for starting up the CPU in the device, and means an operation detected by a sensor or the like. For example, in the case of an IC tag, this means that a trigger signal (carrier wave) for starting the controller and the CPU is detected. The input / output interface includes, in addition to a serial interface such as I ² C, SPI, and UART, an RF interface for inputting / outputting data and the like obtained by wireless communication. Note that, in this specification, a configuration in which a CPU arranged in a housing of an IC tag device and a reader / writer that reads from and writes to the IC tag device performs memory access is described as an example. Any type of device may be used as long as the device reads and writes to the shared memory.

[First Embodiment]
FIG. 1 is a diagram conceptually illustrating access to a shared memory having a plurality of input / output interfaces. As the plurality of input / output interfaces, a configuration is described in which input / output is performed via two input / output ports, but the number of input / output ports is not limited to two. Further, the device that accesses the shared memory is not limited to the example of the IC tag, and any device may be used.

  In FIG. 1, the shared memory is one room, and each interface is like a door. Basically, the shared memory can only be entered from one door. For example, if the shared memory information is also rewritten from the interface B while the shared memory is being rewritten from the interface A, a collision may occur and the rewrite operation may not be completed normally. Here, the device connected to the interface A in FIG. 1 is provided with an access adjustment means, and waits for access to the shared memory for a predetermined time. Thereby, collision due to simultaneous memory access with the interface B is avoided. As an example of using a plurality of conceptual input / output interfaces shown in FIG. 1, an IC tag is taken as an example in FIG.

  FIG. 2 shows an internal configuration example of the IC tag 10 according to an embodiment of the present invention. The IC tag memory 102 is a nonvolatile or volatile memory, and includes, for example, RAM, FRAM (registered trademark), EEPROM, or the like. The IC tag memory 102 according to the present invention has a plurality of input / output interfaces (input / output interfaces 1 and 2). The input / output interface 1 is connected to the CPU 101, and the input / output interface 2 receives the signal via the antenna 110. It is connected to a controller 104 that reads and writes commands and the like in the IC tag memory 102. The CPU 101 may be configured to control a device such as the display device 111 or an audio output device.

  The antenna 110 transmits and receives signals in a non-contact manner using a predetermined frequency (for example, a high frequency such as a UHF band or a low frequency such as an HF band). A rectifier circuit 108 and a power supply circuit 109 are connected to the antenna 110, the rectifier circuit 108 rectifies the carrier wave received by the antenna 110, the power supply circuit 109 accumulates the energy of the rectified carrier wave, and the demodulation circuit 106, A driving power source for the CPU 101 or the like is used.

  The clock signal generation circuit 105 extracts a clock signal from the received carrier wave and supplies it to the controller 104. The demodulation circuit 106 demodulates the modulated carrier wave and supplies it to the controller 104. As described above, the controller 104 reads / writes digital data from / to the IC tag memory 102 via the input / output interface 2. The modulation circuit 107 modulates a signal from the controller 104 and transmits a carrier wave via the antenna 110. The reader / writer A 122 and the reader / writer B 123 transmit and receive commands and data to and from the IC tag 10, and include a control unit 113, an antenna 112, a modulation circuit and a demodulation circuit (not shown), and the like.

  FIG. 3 is a flowchart of collision avoidance processing in the IC tag device according to the embodiment of the present invention.

  In step S201, the reader / writer A122 or B123 transmits a wake-up signal, which is a command for returning the tag from the sleep state, to the IC tag 10. When the IC tag 10 receives the wake-up signal, the power supply circuit 109 supplies power, and shifts from the sleep state to the wake-up state in step S203. When the CPU 101 is activated, a specific area (for example, a reset vector) in the memory is accessed and the activation program is read. Since this specific area is different from an area referred to by another device, it is considered that no collision occurs at this time.

  In step S204, the reader / writer A122 or B123 transmits a request command for requesting access. Then, in step S205, the controller 104 of the IC tag device transmits its UID or the like and responds thereto. Thereafter, in step S207, the reader / writer A122 or B123 and the IC tag 10 (controller 104) exchange conditions such as communication speed with each other. On the other hand, the CPU 101 in the IC tag 10 starts standby in step S206.

  When a transition is made to a state in which a command is transmitted by mutual exchange of conditions with the IC tag 10, the reader / writer A122 or B123 transmits a command in step S208. In step S209, based on the command or data received from the reader / writer A122 or B123, the controller 104 in the IC tag 10 starts memory access in step S209. In step S210, the memory access is terminated. Thereafter, in step S211, the CPU 101 cancels the standby state, and starts memory access in step S212.

In the present embodiment, after the CPU 101 is activated, the IC tag memory 102 is accessed by waiting for a predetermined time (T ₁ + T ₂ ) that is predetermined as a waiting time setting (Variable Wait Time), and then accessing the IC tag memory 102. Avoid simultaneous writing to. Here, T ₁ is the time from when the CPU starts waiting until the controller 104 starts memory access, and T ₂ is the time from the start of memory access to the end of memory access. .

Depending on the type of reader / writer, T ₁ may be a shorter time T ₁₁ , and T ₂ may be a shorter time T ₂₂ . In such a case, if the time from the actual memory access start to the memory access end is the waiting time, a collision may occur. Therefore, a time (T ₁ + T ₂ ) longer than the time T ₂ from the actual start of access to the end of access is set as the standby time in advance in the CPU 101 side, so that after the wakeup signal is transmitted by the reader / writer model. A difference in time (T ₀ + T ₁ ) until the memory is accessed can be absorbed.

[Second Embodiment]
FIG. 4 is a configuration diagram showing an internal configuration of the IC tag device according to the second embodiment. The difference from the internal configuration of the IC tag device according to the first embodiment is that a memory 301 is connected to the CPU 101 and a variable wait time 302 is recorded. In this embodiment, an example of an IC tag is described as a specific example, but includes all devices that access a shared memory having a plurality of input / output interfaces regardless of the IC tag. In other words, memory access collision is avoided by causing any one of a plurality of devices accessing the shared memory to wait for the value set in the variable wait time 302.

  In the present embodiment, the same reference numerals are assigned to the same configurations as those in the first embodiment.

  FIG. 5 is a flowchart when waiting for the operation of one of a plurality of devices accessing the shared memory based on the variable wait time 302 in the second embodiment. Since the operation until the CPU 101 in the IC tag 10 starts standby in step S206 is the same as that in the first embodiment, a description thereof will be omitted.

The CPU 101 refers to the value of the variable wait time 302 recorded in the memory 301 and starts waiting for T ₁ + T ₂ hours. In step S211, the CPU 101 ends the standby, and the IC tag memory 102 is accessed in step S212. Then, the access of the controller 104 based on the signal received from the reader / writer A122 or B123 is not yet completed, and a collision occurs. Next, in step S213, the CPU 101 waits for a predetermined retry interval time (T ₃ ), and then retry the memory access. Even at this point, collision occurs. In step S214, the CPU 101 continues to retry the memory access after waiting for the retry interval time (T ₃ ). Then, since the access of the controller 104 is completed at that time, no collision occurs and the memory access is successful. In step S215, the CPU 101 rewrites the contents of the memory 301 to update the variable wait time 302 to T ₁ + T ₂ + T ₃ + T ₃ by adding the retry time (T ₃ + T ₃ ) after the end of standby. Note that if a collision occurs even after waiting for the set time (T ₁ + T ₂ + T ₃ + T ₃ ) of the variable wait time 302 next time, the access is made again after the retry interval time (T ₃ ), and then the access is successful. For example, the variable wait time 302 is updated to T ₁ + T ₂ + T ₃₊ T ₃₊ T ₃ .

In other words, the CPU 101 adds a time obtained by multiplying the retry count time (T ₃ ) after the first occurrence of collision in one memory access to the variable wait time 302, thereby adding a new variable wait time 302. The value is

Note that the timing for starting the retry interval time (T ₃ ) may be either the time when the CPU 101 starts access or the time when the memory access is interrupted by detecting a collision. For example, if the retry interval time (T ₃ ) is 1 second, a retry is performed when 1 second has elapsed since the time when the CPU 101 started access or when 1 second had elapsed since the time when the CPU 101 interrupted memory access. .

As an operation opposite to this, first, when the CPU 101 accesses the IC tag memory 102 after waiting for the waiting time (T ₁ + T ₂ ), if no collision occurs, the variable wait time 302 is changed to T ₁ + T ₂ . Set. Thereafter, the memory 102 is accessed at a time shorter than Variable Wait Time = T ₁ + T ₂ , for example, a time obtained by subtracting a preset adjustment time (for example, T ₂₂ ), Variable Wait Time = T ₁ + T ₂ −T _22. If no collision occurs, the variable wait time 302 is reset to T ₁ + T ₂ −T ₂₂ . The process is repeated to determine the optimum variable wait time 302.

  According to the present embodiment, in order to avoid collision according to the communication status with the other device accessing the shared memory (in the case of an IC tag, reader / writer A122 or B123), the specification of the other device, and the like. The optimal waiting time can be set.

1 Memory having a plurality of input / output interfaces 10 IC tag 11 Input / output interface 1
22 I / O interface 2
101 CPU
102 IC Tag Memory 104 Controller 105 Clock Signal Generation Circuit 106 Demodulation Circuit 107 Modulation Circuit 108 Rectifier Circuit 109 Power Supply Circuit 110 Antenna 111 Other Device such as Display Device 112 Antenna 113 Control Unit 122 Reader / Writer A
123 Reader / Writer B
301 Memory 302 Variable Wait Time

Claims (11)

A shared memory having a first input / output interface and a second input / output interface;
A first device connected to the first input / output interface of the shared memory;
A second device connected to the second input / output interface of the shared memory,
In the apparatus in which when the power is supplied, the second device and the first device are activated, and then the second device and the first device start access to the shared memory.
After the first device and the second device are activated, the first device waits for a predetermined time as a standby time setting, and the first device accesses the shared memory after the predetermined time has elapsed. An access adjusting means for avoiding simultaneous access to the shared memory. The said 1st device accesses the said shared memory after progress of the said predetermined time, and when the generation | occurrence | production of a collision is detected, the said standby time setting is further updated, The means for updating is further provided. Equipment. When the first device waits for the time specified by the waiting time setting and then accesses the shared memory and detects the occurrence of a collision, the first device waits for a predetermined retry interval time and then waits for the shared memory. And a means for updating the waiting time setting by adding the retry interval time to the waiting time setting when detecting that the access to the shared memory is successful. The apparatus according to claim 1, wherein the apparatus is characterized. After the first device waits for the time specified in the standby time setting and detects that the access to the shared memory is successful by accessing the shared memory, a predetermined time is determined from the standby time setting. The apparatus of claim 1, further comprising means for updating the waiting time setting by subtracting the adjusted time. The access adjusting means multiplies the time specified in the standby time setting by the number of retries after the first collision occurs in a single access to the shared memory and a predetermined retry interval time. The apparatus according to claim 1, further comprising means for updating the waiting time setting by adding the determined times. After the first device waits for a predetermined time as the standby time setting and detects that the access to the shared memory is successful by accessing the shared memory, a predetermined time is set from the standby time setting. Subtract the adjustment time, update the waiting time setting,
The access adjusting means waits for the first device for the time specified in the updated waiting time setting, and then accesses the shared memory and succeeds in accessing the shared memory. The apparatus according to claim 1, further comprising means for updating the waiting time setting by subtracting the predetermined adjustment time from the waiting time setting again when detected. The apparatus according to any one of claims 1 to 6, wherein the access adjustment unit causes the first device to wait for a time specified by the updated waiting time setting. An antenna for receiving a signal from the reader / writer or transmitting a signal to the reader / writer;
An IC tag memory having a first input / output interface and a second input / output interface;
An embedded device,
An IC tag controller that accesses the IC tag memory for reading and writing signals transmitted to and received from the reader / writer via the antenna;
A CPU connected to the embedded device and accessing the IC tag memory for reading and writing a control program and data for controlling the embedded device;
Upon receiving a wake-up signal from the reader / writer, the IC tag controller and an activation unit for activating the CPU are included.
In the IC tag device in which the CPU is connected to the first input / output interface of the IC tag memory and the IC tag controller is connected to the second input / output interface.
After the IC tag controller and the CPU are activated by the activation means, the CPU is made to wait for a predetermined time as a standby time setting, and after the predetermined time has elapsed, the CPU is made to access the IC tag memory. An IC tag device comprising access adjusting means for avoiding simultaneous access to the IC tag memory. The access adjustment means, after the CPU waits for the time specified in the waiting time setting, detects the occurrence of collision by accessing the IC tag memory, and after waiting further for a predetermined retry interval time, When the access to the IC tag memory is retried and it is detected that the access to the IC tag memory is successful, the waiting time setting is updated by adding the retry interval time to the waiting time setting. The IC tag device according to claim 8. After the CPU waits for the time specified in the standby time setting and detects that the access to the IC tag memory is successful, the predetermined time is set from the standby time setting. The IC tag device according to claim 8, wherein the waiting time setting is updated by subtracting an adjustment time. A shared memory having a first input / output interface and a second input / output interface;
A first device connected to the first input / output interface of the shared memory;
A second device connected to the second input / output interface of the shared memory,
When the power is supplied, the second device and the first device are activated, and then the second device and the first device start an access to the shared memory in the apparatus A method of avoiding simultaneous access to shared memory,
After the first device and the second device are activated, the first device waits for a predetermined time as a standby time setting, and the first device accesses the shared memory after the predetermined time has elapsed. A method with letting.

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