JP6216590B2 - Image decoding device - Google Patents

Description

  The present invention relates to an image decoding apparatus that decompresses and decodes encoded image data.

    2. Description of the Related Art Conventionally, there is an image encoding device that compresses and encodes image data for the purpose of reducing the burden on communication, etc., and image decoding that decompresses the encoded image data that is the reverse process and restores the original image An apparatus is also known. In recent years, an encoding standard that can be compressed at a higher compression rate has been proposed (see Non-Patent Document 1).

  FIG. 11 shows a schematic configuration of an image decoding apparatus according to the standard. As shown in FIG. 11, the image decoding apparatus 100 includes a bitstream analysis unit 110, a VLC decoding unit 120, an adaptive scan unit 130, a coefficient inverse prediction unit 140, an inverse quantization unit 150, The frequency inverse transform unit 160 and the color space inverse transform unit 170 are included. Note that VLC in the name of the VLC decoding unit 120 is an abbreviation of Variable Length Coding and is a variable length coding method.

  The bitstream analysis unit 110 analyzes the input bitstream, extracts image information, separates encoded image data, and inputs the separated image data to the VLC decoding unit 120.

  In the encoded image data, a pixel area composed of 256 pixels of 16 pixels (horizontal direction) × 16 pixels (vertical direction) out of pixels (pixels) which is the minimum unit of an image is defined as a macroblock. Is divided into blocks each of 4 × 4 pixels (16 pixels) divided into 4 in the horizontal direction and the vertical direction, respectively, and the first layer data (HP coefficients of 16 blocks) from the one with the high frequency band frequency-converted at the time of compression ), Second layer data (one block LP coefficient) and third layer data (one pixel DC coefficient).

  The first layer data is called an HP (high pass) coefficient and corresponds to 15 pixels excluding the upper left pixel of 4 × 4 pixels in each of 16 blocks, and the second layer data is called an LP (low pass) coefficient. The upper left pixels of 4 × 4 pixels of each of the 15 blocks excluding the upper left block of the first layer data correspond to 15 pixels subjected to frequency conversion, and the third layer data includes a DC (direct current) coefficient and It is called and corresponds to a direct current component, and the upper left pixel of 4 × 4 pixels in the upper left block of the first layer data corresponds to one pixel subjected to frequency conversion.

  The VLC decoding unit 120 performs variable length decoding that is VLC decoding processing on the first layer data, the second layer data, and the third layer data that are the image encoded data separated by the bitstream analysis unit 110. Processing is performed and output to the adaptive scan unit 130 as coefficient data obtained by concatenating the decoded upper data and the extracted lower data.

  As shown in FIG. 12, the VLC decoding unit 120 includes a macroblock counter unit 121, a model bits update unit 122, a data linking unit 123, a higher data processing unit 126, and a lower data processing unit 131, and the higher data processing unit The unit 126 includes an upper data decoding unit 127, an upper data storage unit 128, and an upper data distribution unit 129. The lower data processing unit 131 includes a lower data extraction unit 132, a lower data code determination unit 133, and a lower data code inversion unit. 134 and a lower data selection unit 135. Hereinafter, description will be made while collating with each step of the processing flow of the VLC decoding unit shown in FIG.

  First, the upper data U (i), which is the upper part of the coefficient data, has a high correlation with adjacent macroblocks and coefficients between blocks, and becomes a numerical value near the zero value in the difference processing between adjacent blocks. Variable-length) encoded, but the lower data L (i), which is the lower part of the coefficient data, has a low correlation with adjacent macroblocks and coefficients between blocks, and the coefficient is random even by the difference processing. The remaining data is not compressed so much even if it is encoded with variable length, so it is concatenated with the original data.

  In this VLC decoding unit 120, the upper data U (i) decoded by the upper data processing unit 126 and the lower data L (i) extracted by the lower data processing unit 131 are displayed by the data linking unit 123. As shown in FIG. 16, coefficient data Z (i) is generated by concatenation. For example, if the length of the upper data U (i) is 4 bits and the length of the lower data L (i) is 12 bits, the coefficient length which is the length of the coefficient data Z (i) is 16 bits long It becomes. The coefficient length becomes a constant value within the image processing if the conditions for processing the one image are determined.

  In the standard of Non-Patent Document 1, the length of the lower data is a value of a variable called model bits indicating the bit length (initial values are DC = 8, LP = 4, HP = 0). This term is also referred to as model bits. The model bits are updated by the model bits updating unit 122 for each macroblock (step S47) and used by the lower data processing unit.

  Hereinafter, the processing of the VLC decoding unit will be described in order.

  The upper data processing unit 126 stores the upper data U (i) decoded by the upper data decoding unit 127 in the upper data storage unit 126, and the stored upper data U (i) The data is output from the data distribution unit 129 and distributed.

  Specifically, the upper data decoding unit 127 decodes the encoded data group data separated by the bitstream analysis unit 110 one code at a time by the upper data decoding unit 127 to generate upper data U (i). Then, the data is output to the upper data storage unit 126 and the macroblock counter unit 121. At this time, if the value of the model bit is zero, only the upper data U (i) is decoded (step S32). If the value of the model bit is non-zero, the upper data U (i) is decoded. After (step S33), the lower data L (i) is extracted.

  The upper data storage unit 128 stores the upper data U (i) input from the upper data decoding unit 127 until there are 15 blocks. Further, the macroblock counter unit 121 counts the number of upper data U (i) input from the upper data decoding unit 127, and whether or not the macroblock unit has reached 15 blocks or 16 blocks. Is determined and notified to the VLC decoding unit.

  In addition, when the macrobit counter unit 121 finishes decoding the high-order data for one macroblock and the data concatenation unit 123 finishes concatenating the last data of the macroblock, The value of the model bits is updated based on the statistical information regarding the non-zero of the upper data L (i) accumulated so far (step S47).

  The lower data processing unit inputs the data from the lower data extraction unit 132 and the upper data distribution unit 129 to the lower data code determination unit 133, and the lower data code determination unit 133 uses the data information to determine the lower data Based on this determination information, the lower data selection unit selects either the original lower data or the lower data whose code is inverted by the lower data code inversion unit 134 based on this determination information, The data is input to the data connection unit 123. Here, sign inversion means that a minus sign is added before the lower data. For example, if the lower data is 3 (0003h), the value whose sign is inverted is -3 (FFFDh).

  Specifically, the lower data extraction unit 132 selects the lower data L (i from the lower data group input from the bitstream analysis unit 110 based on the value of the model bits input from the model bits update unit 122. ) And a sign flag S (i) indicating positive and negative signs.

  As shown in FIG. 13, the lower data extractor 141 extracts lower data L (i) for the length of the model bits from the input lower data group (step S35), and the sign flag extractor 142 further The 1-bit sign flag S (i) following the lower data L (i) is extracted.

  FIG. 17 illustrates the separation of the lower data L (i) and the sign flag S (i). The low-order data L (i) of the model bits length and the 1-bit length of the sign flag S (i) are separated. The case where the sign flag S (i) exists as shown in the upper diagram of FIG. In this case, the sign flag S (i) may not exist, and in the main separation, the presence or absence of the sign flag S (i) cannot be determined. S (i) is extracted beforehand.

  The lower data L (i) extracted by the lower data extraction unit 132 is input to the lower data code determination unit 133, the lower data code inversion unit 134, and the lower data selection unit 135, and the sign flag S (i) It is input only to the code determination unit 133.

  The lower data code determination unit 133 is based on the lower data L (i) input from the lower data extraction unit 132, the sign flag S (i), and the higher data U (i) input from the upper data distribution unit 129. Lower data code information K (i) is determined.

  The lower data code information K (i) is determined as shown in FIG. That is, the upper data positive / negative zero determiner 143 determines whether the input upper data U (i) is non-zero or zero (steps S36 and S37), and inputs the determination information to the lower data code selector 146. If the upper data U (i) is non-zero, the sign indicating whether the data is positive or negative is determined (step S38), and the lower data code selector 146 is used as the upper code information. input.

  The lower data non-zero determiner 145 determines whether the input lower data L (i) is non-zero or zero (step S39), and inputs the determination information to the sign flag selector 144. The sign flag selector 144 selects the sign flag S (i) input from the lower data extraction unit if the input determination information is non-zero (step S40), and if the determination information is zero, A value of 0 is selected and input to the lower data code selector 146 as the lower code.

  The lower data code selector 146 selects the higher code input from the upper data positive / negative zero determiner 143 if the determination information is non-zero based on the determination information from the upper data positive / negative zero determiner 143, If the determination information is zero, the lower code input from the sign flag selector 144 is selected and input to the lower data selection unit 135 as lower data code information K (i).

  The lower data code inverting unit 134 inputs the data obtained by inverting the sign of the lower data L (i) input from the lower data extracting unit 132 to the lower data selecting unit 135 (step S42), and the lower data selecting unit 135, based on the lower data code information K (i) from the lower data code determination unit 133, if the determination information is positive, selects the lower data L (i) input from the lower data extraction unit 132. If the determination information is negative, the sign-inverted data input from the lower-order data sign inversion unit 134 is selected and input to the data concatenation unit 123 as signed lower-order data L (i).

  The data concatenation unit 123 concatenates the upper data U (i) input from the upper data distribution unit 129 and the lower data L (i) input from the lower data selection unit 135 as coefficient data Z (i), The data is output to the adaptive scan unit 130 (step S43).

  The processing of the lower data L (i) is performed for each data, and the processing in the lower data processing unit is repeated until the processing of 15 data in units of one block is completed (steps S35 to S45). The processing of each block is repeated for 16 blocks constituting one macro block (step S46).

  Then, when the processing of the macroblock is completed and the last connection of the upper data U (i) and the lower data L (i) is completed, the data connection unit 123 inputs the completion signal to the model bits update unit 122. The model bits update unit 122 updates the model bits (step S47). This VLC decoding process is repeated until the processing of all macroblocks in one image data is completed (step S48).

  Each time the processing of one block of the VLC decoding unit 120 is completed, the adaptive scanning unit 130 performs the following processing on the first layer data and the second layer data whose pixel order is changed by a method determined at the time of compression. The coefficient data is replaced by a procedure reverse to the compression, and processing for returning to the original pixel order is performed. This replacement process collects non-zero coefficients on the lower side of the frequency band at the upper left of the block during compression (conversely, those with zero coefficient values gather on the higher side of the lower right frequency band) This is performed in order to increase the compression rate in encoding.

  The coefficient inverse prediction unit 140 compares coefficients between adjacent blocks for the first layer data, second layer data, and third layer data for each block input from the adaptive scanning unit 130. The prediction mode is derived and the pixel value before the prediction processing in the compression is calculated by adding the corresponding pixel value of the highly correlated block to the target pixel according to the set arithmetic expression with respect to the prediction mode. Restore (reverse prediction). Then, the first layer data, the second layer data, and the third layer data after inverse prediction are input to the inverse quantization unit 150 for each block.

  The inverse quantization unit 150 performs inverse quantization by multiplying the first layer data, the second layer data, and the third layer data inversely predicted by the coefficient inverse prediction unit 140 by respective set quantization parameters. Processing is performed, and the processed first layer data, second layer data, and third layer data are input to the frequency inverse transform unit 160 for each block.

  The frequency inverse transform unit 160 sequentially processes the coefficient data inversely quantized by the inverse quantization unit 150 in the raster direction with 4 × 4 pixels as one block, and converts the coefficient data for each frequency band into pixel data. Process to convert to. The frequency inverse transform unit 160 converts the first layer data, the second layer data, and the third layer data separated for each frequency band into a two-dimensional space of one block (4 × 4 pixels) for each color component. Returning to the data, the data is input to the color space inverse transform unit 170.

  The color space inverse transform unit 170 processes the image data for each color component input from the frequency inverse transform unit 160 for each pixel, and when the color space inverse transform is unnecessary, the color space inverse transform is not performed. When space inverse transformation is necessary, color space inverse transformation is performed and the processed pixel data is output to the outside as image data for one image.

  Note that the necessity of color space reverse conversion depends on the pixel format representing the image format defined in the standard of Non-Patent Document 1, and when the pixel format requires conversion, An image whose image data before reverse conversion is in YUV format is converted into RGB format, and an image whose image data before reverse conversion is in YUVK format is converted into CMYK format. Further, when the pixel format does not require color space reverse conversion, color space reverse conversion is not performed.

JPEG XR Recommendation ITU-T T.832: Information technology -JPEG XR image coding system-Image coding specification. [Online] .Recommendation T.832 (01/12). Approval 2012-01-13. Status: In force. Retrieved from the Internet: <URL: http://www.itu.int/rec/T-REC-T.832-201201-I/en>.

  The amount of data of the compressed image data to be decompressed has increased rapidly due to the improvement in resolution accompanying technological advancement, and the conventional image decoding apparatus 100 takes a long time to process due to the increase in the amount of data. There is a need for further efficiency.

  In particular, in the lower data processing unit 131 in the VLC decoding unit 120, after the VLC decoding of the upper data U (i) for each block, the sign flag S (i) generated depending on the condition from the lower data group , The lower data L (i) is extracted, and the process of connecting to the higher data U (i) is defined as one cycle for the number of coefficient data Z (i) after the connection. Therefore, the process has to be repeated for the same number of cycles as the total number of the first hierarchy data, the second hierarchy data, and the third hierarchy data, and the process takes a long time. For this reason, the processing of the conventional low-order data processing unit 131 has become one of the bottleneck factors that reduce the processing efficiency of the image decoding apparatus 100.

  However, as described in the background art, the low order data L (i) may or may not have the sign flag S (i), and when processing one coefficient at a time as in the background art, Although there is no particular problem at the time of realization, when this data processing is performed simultaneously on a plurality of lower-order data, the number of cases where the lower-order data L (i) and the sign data S (i) are arranged increases. In particular, in the case of decoding processing, concatenated data exists and must be extracted in order from the current decoding position, so that the lower data L (i) and the sign flag S (i) are extracted. It was difficult.

  FIG. 18 shows an example of extracting three consecutive lower data L (i) together with the sign flag S (i) from the lower data group. The first lower data L (1) is constant at the position from the current decoding position to the position of the model bits length, but there is a sign flag S (1) associated with the lower data L (1). There are cases [(A) to (D)] and cases [(E) to (H)] that do not exist.

  When the sign flag S (1) is present, the low-order data L (2) is present after the sign flag S (1). Therefore, the model bit length from the position immediately after the position of the model bit length + 1 bit. If the sign flag S (1) does not exist, it exists immediately after the lower order data L (1). Therefore, the model bit length from the position immediately after the model bit length position is present. It will exist up to the position of length.

  Furthermore, when the sign flag S (2) associated with the lower data L (2) exists [(A), (B), (E), (F)] and when it does not exist [(C), (D), ( G), (H)], the positions of the sign flag S (2) and the next lower data L (3) are different. Further, when the sign flag S (3) associated with the lower data L (3) exists [(A), (C), (E), (G)] and when it does not exist [(B), (D), (F), (H)], the position where the sign flag S (3) exists differs.

  Thus, as shown by the arrow surrounded by the dotted-line ellipse at the bottom of FIG. 18, as the case classification of the start position of each data, the lower order data L (1) and the sign flag S (1) are one way, The lower data L (2) and the sign flag S (2) are in two ways, the lower data L (3) and the sign flag S (3) are in three ways, and the number in the starting position increases one by one. Become. This is the same when the number of lower-order data to be processed simultaneously is increased to 4 or more. Every time the argument i of L (i) is increased by 1, the number at the start position is increased by one. .

  As described above, when decompressing the compressed image data, the extraction from the lower data group is performed in parallel to increase the processing efficiency. For the lower data L (i) and the sign flag S (i), the sign flag S It must be configured to be able to cope with any position where the start position of each low-order data L (i) and sign flag S (i) with or without (i) is taken.

  Note that FIG. 19 shows the timing of this conventional VLC decoding process, and it takes time to process the LP and HP sub-data processing arrows indicated by the dotted ellipse. Met. Therefore, as shown in the timing diagram of FIG. 20, if the processing time of the portion represented by the arrow of the lower data processing in the portion surrounded by the dotted line ellipse is shortened, the processing time of the VLC decoder, and consequently, the image decoding The processing time of the entire converter can be increased. Further, as shown in FIGS. 19 and 20, in the standard of Non-Patent Document 1, there are 16 blocks of HP processing, and there are repetitions of processing for 16 blocks. It is considered that the shortening effect is great.

  The present invention has been made in view of the above circumstances, and is an image decoding apparatus capable of improving the overall processing efficiency by reducing the processing time of the lower data processing unit in the VLC decoding unit. The purpose is to provide

In order to solve the above-described problem, an image decoding apparatus according to the present invention decodes higher-order data that is higher-order data of coefficient data from compressed image data encoded using n coefficient data as one block unit. A higher-order data decoding unit, a lower-order data processing unit that extracts lower-order data that is lower-order data of the coefficient data, and a data connection that restores coefficient data by connecting the higher-order data and the lower-order data A decoding unit comprising:
An inverse quantization unit that inversely quantizes the coefficient data in units of blocks decoded by the decoding unit;
In an image decoding apparatus comprising: a frequency inverse transform unit that inversely frequency transforms coefficient data in block units inversely quantized by the inverse quantization unit to generate image data;
The lower data processing unit extracts, in parallel, lower data candidates and sign flag candidates in block units for all possible combinations of the lower data and a combination of sign flags indicating the sign of the lower data. A data parallel extractor;
A lower data parallel code presence / absence determination unit that generates code presence / absence determination information indicating whether or not a sign flag subsequent to the lower data exists based on the upper data and the lower data candidates;
A lower data distribution unit that selects and distributes n sets of lower data and sign flags in block units in parallel from the lower data candidates and the sign flag candidates based on the code presence / absence determination information.
However, n is an integer of 2 or more.

  According to the image decoding apparatus according to the present invention having the above-described configuration, first, in the low-order data parallel extraction unit, from among the compressed image data having several combinations of the low-order data and sign flag pairs, Lower data candidates and sign flag candidates for all combinations are extracted in parallel.

  Then, in the lower data parallel code presence / absence determination unit, code presence / absence determination information indicating whether or not there is sign data subsequent to the lower data is generated in parallel based on the upper data and the extracted lower data candidates.

  Finally, the lower data distribution unit is selected from the lower data candidates extracted by the lower data parallel extraction unit and the sign flag candidates using the code presence / absence determination information generated by the lower data parallel code presence / absence determination unit. Select lower level data and sign flag to be output in parallel and distribute.

  In this way, among the consecutive lower data and sign flag data, all combinations of lower data candidates and sign flag candidates are listed, the conditions under which the sign flag exists are determined, and the lower data to be selected And n sign flags in units of blocks can be acquired in parallel.

Further, the lower data processing unit of the image decoding apparatus according to the present invention is configured so that each of n low-order data and high-order data in a block unit is processed in one cycle or a plurality of cycles, where m is the number of processes in one cycle. Process iteratively.
However, n is an integer of 2 or more, m is an integer of 2 or more and n or less, and m and n are equal when the repetition of the process ends in one cycle.

  According to the image coding apparatus according to the present invention having the above-described configuration, the acquisition of the n low-order data and the sign flag in units of the blocks, which has been conventionally performed in n cycles, is performed in one cycle or Can be implemented in multiple cycles.

  Here, since the number m to be processed in one cycle is two or more, even when the processing is performed in a plurality of cycles, the processing can be performed in half or less than the conventional processing in n cycles. .

Furthermore, the low-order data parallel extraction unit of the image decoding apparatus according to the present invention sets the low-order data of q-bit length and the 1-bit-long sign flag, which may or may not exist, following the low-order data. As a set, all of the candidates for the lower data and the candidates for the sign flag for the possible combinations of the first to m-th lower data and the sign flag from the lower data group in which m sets are continuously connected. Are extracted in parallel.
However, a dummy value of 0 or 1 is put in a candidate for a sign flag when the sign flag following the lower data does not exist, n is an integer of 2 or more, and m is 2 or more and n The following integers, q is an integer of 1 to p, and p is an integer of 1 or more.

  According to the lower-order data parallel extraction unit of the image decoding apparatus according to the present invention having the above-described configuration, one q-bit lower-order data and one-bit sign flag that may or may not exist thereafter are provided. As a set, m subordinate data candidates and sign flag candidates for the number of processes in one cycle from among the subordinate data group in which m sets are concatenated, are comprehensively simultaneously selected from all combinations. Can be extracted. In some cases, the sign flag does not exist. In this case, a dummy value of 0 or 1 is entered.

  Specifically, since the first lower data is at the head of the data, there is one lower data candidate, but the second lower data candidate may be preceded by a sign flag, There are two candidates, and the third lower data candidate may be further shifted depending on the presence or absence of the second sign flag. As the number increases, the number of candidates increases by one as the number increases. There are m lower data candidates.

  The same applies to the sign flag. For the sign flag of the first lower data, since the first lower data is at the head of the data, the candidate for the sign flag is the one next to the position of the first lower data. Be a candidate. And the second sign flag candidate may be further shifted by 1 bit, so there are two, and the third sign flag candidate is three, so as the number increases, the candidate increases by one, There are m candidates for the mth sign flag.

  Further, in this configuration, the bit length of the lower data is set to one q in the range 1 to p that can be taken. This is because the lower data with this q bit length is considered as a lower data candidate. This means that it is only necessary to be able to extract sign flag candidates. For example, the lower data candidates and sign flag candidates are comprehensively extracted for lower data of all bit lengths 1 to p, Finally, a candidate for low-order data having a bit length of q and a candidate for a sign flag may be selected.

  Also, for example, with this configuration, for example, the bit length q is variable, and from the beginning, only the lower data candidates and the sign flag candidates for the bit length q of the lower data and the bit length 1 of the sign flag are exhaustively extracted. You may be able to do it.

Furthermore, the lower-order data parallel code presence / absence determining unit of the image decoding apparatus according to the present invention is unique based on the condition that sign data following the lower-order data exists only when the higher-order data is zero and the lower-order data is non-zero. The presence or absence of a sign flag following the first lower-order data is determined from the higher-order data corresponding to the first lower-order data, and the second lower-order data is started by determining the presence or absence of the first sign flag. A sign flag following the second lower data from the upper data corresponding to the determined second lower data is determined by estimating the positional deviation and determining the second lower data from the second lower data candidates. The third subordinate data is determined based on the cumulative number of sign flags following the subordinate data up to the previous one, and the start position of the subordinate data is not determined. And the presence or absence of a sign flag subsequent to the lower-order data from the higher-order data corresponding to the determined lower-order data. After that, similarly, from 1 to mth, the presence / absence of a sign flag following each of the lower order data is judged in parallel, and the sign following each of the determined lower order data of the first to mth is determined. The flag presence / absence determination information is output as code presence / absence determination information.
However, the n is an integer of 2 or more, and the m is an integer of 2 or more and n or less.

  According to the low-order data parallel code presence / absence determining unit of the image decoding apparatus according to the present invention having the above configuration, sign data following the low-order data exists only when the high-order data is zero and the low-order data is non-zero. Based on the conditions, for m pieces of lower-order data processed in one cycle, the presence / absence of the following sign flag is judged in parallel, and the sign flag that follows each of the first to mth lower-order data thus judged The presence / absence determination information can be output as code presence / absence determination information.

  Specifically, it is determined whether or not each subordinate data has a sign flag based on the above-mentioned condition that the sign flag exists. Since the first lower data has only one lower data candidate, it can be easily determined from the sign flag existence condition.

  For the second lower data, if there is no sign flag in the first lower data, the second lower data candidate closest to the head is selected, and if the first lower data has a sign flag, The second nearest lower data candidate is selected, and the presence or absence of a sign flag is determined from the higher order data corresponding to the selected lower data based on the sign flag existence condition.

  For the third subordinate data, the number with the sign flag after the first and second subordinate data is accumulated, and if the number is zero, the candidate of the third subordinate data nearest from the top is selected. If the number is 1, select the third subordinate data candidate closest to the second from the top, and if the number is 2, select the third subordinate data candidate closest to the top from the top, and The presence / absence of a sign flag is determined from the upper data corresponding to the selected lower data based on the sign flag existence condition.

  Also for the fourth and subsequent lower data, the number with the sign flag after the first to the previous lower data is accumulated, and the lower order data from the first to the lower A data candidate is selected, and the presence / absence of a sign flag is determined based on the sign flag existence condition from the upper data corresponding to the selected lower data.

  This process is performed for the mth lower data, which is the number of processes in one cycle, and the presence or absence of a sign flag is determined.

  Then, the presence / absence information of the sign flag determined in parallel for the 1st to mth is output as the code presence / absence determination information.

Furthermore, the lower-order data distribution unit of the image decoding apparatus according to the present invention selects the first lower-order data and the sign flag that are uniquely determined as they are, and the second lower-order data according to the code presence / absence determination information of the first lower-order data. The start position deviation of the data is estimated, the second lower data and the sign flag are selected from the second lower data candidate and the sign flag candidate, and the third lower data and the sign flag are The start position shift of the second lower data is estimated by accumulating the number of existing codes in the lower data until the th, and the second lower data candidate and sign flag candidate are The lower order data and the sign flag are selected, and thereafter, similarly, the first lower order data and the sign flag are selected in parallel from the 1st to mth, and the first lower order data to the 1st to mth are selected. Outputs data and sign flags dispensing.
However, when the sign flag does not exist, a dummy value of 0 or 1 is entered in the sign flag, the n is an integer of 2 or more, and the m is an integer of 2 or more and n or less. .

  According to the low-order data distribution unit of the image decoding apparatus according to the present invention having the above configuration, the low-order data parallel extraction unit generates the low-order data parallel extraction unit based on the code presence / absence determination information generated by the low-order data parallel code presence / absence determination unit. Select the lower data to be selected from the 1st to mth lower data candidates and select the sign flag to be selected from the 1st to mth sign flag candidates generated by the lower data parallel extraction unit. The selected sub-data from the 1st to m-th and the sign flag are output and distributed.

  Specifically, since there is only one candidate for the first lower data and the sign flag, they are output as they are. The same applies to the following, but when there is no sign flag, a dummy value of 0 or 1 is put in the output of the sign flag.

  There are two candidates for the second lower data and the sign flag, and when there is no code presence / absence determination information for the first lower data, the second lower data candidate and the sign flag closest to the top Select candidates and output.

  There are three candidates for the third subordinate data and sign flag, and the number of sign flags after the first and second subordinate data is accumulated. If the number of the nearest third lower data candidate and sign flag candidate is selected and the number is 1, then the third lower data candidate and sign flag candidate that are the second closest from the top are selected, and if the number is 2, The third lower data candidate and the sign flag candidate that are the third closest to the head are selected and output.

  For the fourth and subsequent subordinate data and the sign flag, the number of sign flags after the first to the previous subordinate data is accumulated, and in order from the smallest number to the top Select and output the second lower data candidate and sign flag candidate.

  This process is performed for the mth lower data and the sign flag, which is the number of processes in one cycle, and the selected lower data and the sign flag are output.

  And the said process is implemented in parallel about 1-mth.

  In the decoding process, with regard to extraction / selection of lower data and sign flag, up to a predetermined number of lower data candidates and sign flag candidates are exhaustively extracted and succeeded to each lower data up to the predetermined number. Since the code presence / absence determination information related to the sign flag is generated and the code presence / absence determination information can be used to select the predetermined number of lower data and the sign flag in parallel, the lower data and the sign flag are extracted. -Selection processing can be parallelized, and by dividing into one cycle or a relatively small number of cycles and performing parallel processing, it becomes possible to reduce the number of cycles required for processing of the lower data processing unit compared to the conventional method. The processing speed of the entire image decoding apparatus can be improved.

It is the block diagram which showed schematic structure of the image decoding apparatus which concerns on one Embodiment of this invention. It is the block diagram which showed the structure of the VLC decoding part which concerns on this embodiment. It is the block diagram which showed the structure of the low-order data parallel extraction part which concerns on this embodiment. It is the block diagram which showed the structure of the 3rd low-order data extraction part which concerns on this embodiment. It is the block diagram which showed the structure of the 3rd sign flag extraction part which concerns on this embodiment. It is the block diagram which showed the structure of the low-order data parallel code presence / absence determination part which concerns on this embodiment. It is the block diagram which showed the structure of the low-order data parallel code determination part which concerns on this embodiment. It is the block diagram which showed the structure of the low-order data distribution part which concerns on this embodiment. It is the flowchart which showed the process sequence in the VLC decoding part which concerns on this embodiment. It is the flowchart which showed a part of processing procedure in the VLC decoding part which concerns on this embodiment. It is the block diagram which showed schematic structure of the conventional image decoding apparatus. It is the block diagram which showed the structure of the conventional VLC decoding part. It is the block diagram which showed the structure of the conventional low-order data extraction part. It is the block diagram which showed the structure of the conventional low-order data code determination part. It is the flowchart which showed the process sequence in the conventional VLC decoding part. It is explanatory drawing for demonstrating an example of the connection of the high-order data and low-order data of the conventional VLC encoding part. It is explanatory drawing for demonstrating an example of the isolation | separation of the low-order data and the sign flag of the conventional VLC decoding part. It is explanatory drawing for demonstrating the combination of the appearance of the low-order data of the encoded data with which three low-order data were connected, and a sign flag. It is explanatory drawing for demonstrating an example of the timing chart in the conventional VLC decoding part. It is explanatory drawing for demonstrating an example of the timing chart in the VLC decoding part used as a subject solution.

  Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the image decoding apparatus 1 according to this embodiment.

  As shown in FIG. 1, the image decoding device 1 of this example replaces the VLC decoding unit 120 in the conventional image decoding device 100 of FIG. 11 with a VLC decoding unit 10 having a different configuration from this. Only in this respect, the configuration of the conventional image decoding apparatus 100 is different. Therefore, the other components are denoted by the same reference numerals as those in the image decoding device 100, and detailed description thereof is omitted.

  As shown in FIG. 2, the VLC decoding unit 10 includes a macroblock counter unit 11, a model bits update unit 12, a data parallel connection unit 13, an upper data processing unit 16, and a lower data processing unit 21. The data processing unit 16 includes an upper data decoding unit 17, an upper data storage unit 18, and an upper data distribution unit 19. The lower data processing unit 21 includes a lower data parallel extraction unit 22, a lower data parallel code presence / absence determination unit 23, A lower data parallel code determination unit 24, a lower data distribution unit 25, a lower data parallel code inversion unit 26, and a lower data parallel selection unit 27 are included.

  In the VLC decoding unit 10 as well, as in the VLC decoding unit 120 described above, the first layer data and the second layer data in the code data output from the bitstream analysis unit 110 are in units of macroblocks. Furthermore, each macroblock is processed in units of blocks. In the following, the processing of the first layer data will be described, but the same applies to the processing of the second layer data.

  According to the image decoding apparatus 1 of the present embodiment having the above configuration, first, the bit stream analysis unit 110 analyzes an input bit stream, extracts image information, and encodes an encoded image. The upper data group and the lower data group are extracted from the coefficient data and input to the VLC decoding unit 10.

  Similarly to the conventional VLC decoding unit 120, the VLC decoding unit 10 according to the present embodiment also includes the upper layer data group of the first layer data, the second layer data, and the third layer data input from the bitstream analysis unit 110. For the lower data group, for each block, the upper data group is subjected to VLC decoding to obtain upper data, the lower data is extracted from the lower data group, and the upper data and the lower data are concatenated as coefficient data to be used as an adaptive scan unit. Input to 130.

  Although the configuration and operation of the VLC decoding unit 10 in FIG. 2 will be described, the configuration and operation of the VLC decoding units other than the lower data processing unit 21 are almost the same as those of the prior art. The operation of the data processing unit 21 will be described in detail. Further, description will be made while comparing each step of the processing flow of VLC decoding shown in FIG. 9 with detailed steps of step S6 shown in FIG. In the low-order data processing of the image decoding apparatus according to the present embodiment, an example in which three low-order data are processed in one cycle and this is repeated five times (in five cycles) to process one block. Indicates.

  The VLC decoding unit 10 determines whether the value of the model bits initially set or updated by the model bits update unit 12 is zero (step S1). If the model bits are zero, the upper data decoding is performed. The unit 17 performs only decoding of the higher order data U (i) from the higher order data group of the coefficient data input from the bitstream analysis unit 110 (step S2). The decoded upper data U (i) is input to the upper data storage unit 18 and stored in units of blocks.

  If the model bits are not zero, the upper data decoding unit 17 decodes the upper data U (i) from the upper data group (step S3), and the lower data processing unit 21 performs the bit stream analysis. The lower data L (i) is extracted from the lower data group of the coefficient data input from the unit 110, and the higher data U (i) and the lower data L (i) are connected by the data parallel connection unit (step S13). .

  In addition, the update of the model bits is performed when the decoding count of the upper data in the macro block counter unit 11 reaches the number of macro blocks, and the connection processing of the last upper data and the lower data of the macro block is completed. This is performed by the model bits updating unit 12 (step S17).

  After the decoding of the upper data U (i) for one block is completed (step S3), the lower data parallel extraction unit 22 acquires a lower data group from the bit stream analysis unit (step S5), and the first to third The lower data L (i) and the sign flag S (i) up to the first are extracted (step S6).

  As shown in FIG. 3, the lower data parallel extraction unit 22 includes an upper lower data extraction unit and a lower sign flag extraction unit. The upper data extraction unit includes a first lower data extraction unit 31a to a fifteenth lower data extraction unit 31o corresponding to the lengths of model bits 1 to 15, respectively, and three consecutive lower levels corresponding to each model bit. A combination of data L (i) is extracted in parallel. Since the value of model bits is determined to be one for each macroblock, it corresponds to the current model bits from among the combinations of the third lower data L (i) extracted by the first to fifteenth lower data extraction units. The combinations of the lower data L (i) up to the third are selected (step S21). The combination of the lower data L (i) up to the third is the same as that shown in FIG.

  More specifically, as shown in FIG. 4, the third subordinate data extraction unit having a model bit length of 3 includes six extractors of the subordinate data L_1_1 extraction unit 31c1 to the subordinate data L_3_3 extraction unit 31c6. Composed. Note that, for example, L_3_2 in the center of the name of each extractor indicates that L (i) related to the second combination of the third coefficient of the lower data L is targeted.

  Compared with the bit position example in the case of model bit length = 3 shown in the lower part of FIG. 18, corresponding to the outputs L_1_1 to L_3_3 of each extractor, L_1_1 is [0: 2] and L_2_1 is [3: 5. ], L_2_2 is [4: 6], L_3_1 is [6: 8], L_3_2 is [7: 9], and L_3_3 is [8:10]. The cut-out position of each bit from the beginning of the lower data group is represented by [*: *].

Since this cut-out is performed for all model bits values defined in Non-Patent Document 1, all cases can be covered with respect to the third subordinate data L (i). Extraction is performed individually and in parallel, and only those corresponding to the current model bits are selected, so that a high-speed combination of subordinate data can be extracted.

  The same applies to the sign flag extraction unit on the lower side of FIG. 3. The sign flag extraction unit 33 a to the 15th sign flag extraction unit 33 o correspond to the lengths 1 to 15 of the model bits. The selector 34 selects a combination of sign flags corresponding to model bits corresponding to the current macroblock.

  For example, the third sign flag extraction unit having a model bit length of 3 will be described. The third sign flag extraction unit includes six extractors, that is, a sign flag S_1_1 extraction unit 33c1 to a sign flag S_3_3 extraction unit 33c6. Is done. Similarly to the case of the lower data L (i), when comparing the bit position example in the case of the model bit length = 3 in FIG. 18, S_1_1 is [3], S_2_1 is [6], S_2_2 is [7], Bit extraction of [9] is performed for S_3_1, [10] for S_3_2, and [11] for S_3_3. Since the sign flag is 1 bit long, the cutout position is represented by [*] starting from the beginning of the lower data group.

  The extraction of the combination of sign flags is also performed in parallel individually and exhaustively with respect to the third subordinate data, so that the combination of sign flags can be extracted at high speed.

  The lower data parallel code presence / absence determining unit 23 uses the lower data L (i) for the third lower data L (i) extracted by the lower data parallel extracting unit 22 based on the upper data U (i) and the value of the model bits. The presence / absence of the sign flag S (i) following i) is determined to generate code presence / absence determination information J (i) (step S22).

  As shown in FIG. 6, the low-order data parallel code presence / absence determining unit 23 includes six non-zero determiners 35, 37a, 37b, 39a-39c, three zero determiners 36, 38, 40, and three logics. The multipliers 41a to 41c, two selectors 42a and 42b, three adders 43a to 43c, and a multiplier 44 are included.

  The condition that the sign flag S (i) exists after the lower data L (i) is that the upper data U (i) corresponding to the lower data L (i) is zero (step S8), and the lower data L (I) is non-zero (step S10). However, for the subsequent lower data L (i + 1), the lower data L (i + 1) to be compared varies depending on whether the immediately preceding lower data L (i) has the sign flag S (i) or not. For this purpose, the presence information (present: 1, none: 0) of the previous lower data sign flags is added, and the lower data U (i) to be compared is selected by this selector with the selector. It is configured to do.

  Specifically, the first lower data L_1_1 is input to the non-zero determiner 35, the corresponding upper data U_1 is input to the zero determiner 36, and the result (true: 1, false: 0) is logically calculated. The result is input to the multiplier 41a, and the result is output as first code presence / absence determination information J_1. If J_1 is 1, there is a sign flag, and if J_1 is 0, there is no sign flag.

  Regarding the second lower data, there are two cases of L_2_1 and L_2_2, and L_2_1 and L_2_2 are input to the non-zero determiners 37a and 37b, respectively, and if the code presence / absence determination information J_1 is 0, the non-zero determiner If the code presence / absence determination information J_1 is 1, the output of the non-zero determiner 37b is selected by the selector 42a and the second higher order data U_2 is input to the zero determiner 38. And the logical product 41b, and outputs the result of the logical product as the second code presence / absence determination information J_2. Since J_1 and J_2 are used for selection of the third lower data, both are input to the adder 43a and the addition result is output.

  For the third lower order data, there are three cases of L_3_1, L_3_2, and L_3_3, and L_3_1, L_3_2, and L_3_3 are input to the non-zero determiners 39a, 39b, and 39c, respectively, and the adder 43a that has been output above If the output of the adder 43a is 1, if the output of the adder 43a is 1, then the output of the non-zero determiner 39a is non-zero. The selector 43b selects the output of the determiner 39c, inputs the third higher order data U_3 to the zero determiner 40 together with the output of the result, and inputs the result of the logical product to the third code. Output as presence / absence determination information J_3. Since the addition result of J_1, J_2, and J_2 is used to generate bit shift information for preparing the next encoded data, the output of the adder 43a that is the addition result of J_1 and J_2 and J_3 are added. The result is input to the device 43c and the addition result is output.

  Since there are three subordinate data to be processed, the value of the model bit is input to the multiplier 44, and the output result obtained by multiplying this by 3 times and the output of the adder 43b output above are input to the adder 43c. Then, the output result is input to the bitstream analysis unit 110 as a processing code length to be actually used.

  With this configuration, it is possible to reliably generate the code presence / absence determination information J (i) indicating whether or not each sign flag is present for the three lower-order data, and the bit length of the data to be actually used is represented by the bit stream. It can be transmitted to the analysis unit 110.

  The lower data parallel code determination unit 24 determines the codes of the three lower data in parallel. The lower data parallel code determination unit 24 includes upper data U (i), code presence / absence determination information J (i), and a lower data distribution unit 25 described later. This is determined based on the finally distributed sign flag S ′ (i).

  As shown in FIG. 7, the lower data parallel code determination unit 24 includes three lower data code determination units 45 to 47, each corresponding to the codes 45 to 47, each having one higher data positive / negative zero. It comprises decision units 45a to 47c, sign flag selectors 45b to 47b, and lower data code selectors 45c to 47c. Different data is input to each lower data code determination unit, and the operation is the same and parallel. Execute the process.

  The lower data code determining unit 45 determines the code of the first lower data among the three lower data, the lower data code determining unit 46 determines the code of the second lower data, and the lower data code determining unit 47. Determines the sign of the third subordinate data.

  Taking the lower data code determination unit 45 as an example, the upper data positive / negative zero decision unit 45a receives the upper data U_1 from the upper data distribution unit 19 and determines whether the upper data is non-zero or zero. The zero information and the code of the upper data are input to the lower data code selector 45c, and the sign flag selector 45b receives the selection signal of the code presence / absence determination information J_1 from the lower data parallel code presence / absence determination unit 23 and the lower data distribution unit 25. The final sign flag S′_1 from is input, and if J_1 is 1 (present), S′_1 is selected, and if J_1 is 0 (not present), a value of 0 is selected. The data is input to the data code selector 45c.

  The lower data code selector 45c selects the upper code if the non-zero / zero information input from the upper data positive / negative zero determiner 45a is non-zero, and if the non-zero / zero information is zero, the lower code Is output to the lower data parallel selection unit 27 as lower data code determination information K_1.

  The lower data code determination unit 46 receives the code presence / absence determination information J_2, the upper data U_2, and the final sign flag S′_2 as the second input data. Code determination information K_2 is generated and output to the lower data parallel selection unit 27.

  For the lower data code determination unit 47, the code presence / absence determination information J_3, the upper data U_3, and the final sign flag S'_3 are input as the third input data, and the third lower data is processed in the same manner as described above. The code determination information K_3 is generated and output to the lower data parallel selection unit 27.

  Since the lower data code determination information K_1 to K_3 are generated at the same time, the lower data parallel selection unit 27 can perform code addition processing on the lower data in parallel.

  Based on the code presence / absence determination information J (i) input from the lower data parallel code presence / absence determination unit 23, the lower data distribution unit 25 signs the lower data candidate L (i) input from the lower data parallel extraction unit 22 and the sign. From the flag candidates S (i), the lower data L ′ (i) and the sign flag S ′ (i) to be selected are selected, and the sign flag S ′ (i) is sent to the lower data parallel code determination unit 24. The lower data L ′ (i) is input to the lower data parallel code inverting unit 26 and the lower data parallel selecting unit 27 (step S23).

  As shown in FIG. 8, the low-order data distribution unit 25 includes two adders 48a and 48b and four selectors 49a to 49d. The selection of the lower data is controlled by the first and second code presence / absence determination information J_1 and J_2.

  Since there is no other candidate in the first lower data L_1_1, it is output as it is as the lower data L′ _1, and the second lower data L_2_1 and L_2_2 are selected by the selector 49a if the code presence / absence determination information J_1 is 0. If L_2_1 is selected and the code presence / absence determination information J_1 is 1, L_2_2 is selected and is output as the selected lower data L′ _2. The code presence / absence determination information J_1 and J_2 are respectively input to the adder 48a and added to be used for selecting the third lower order data.

  For the third lower-order data L_3_1, L_3_2, and L_3_3, if the output of the adder 48a that is the addition value of the code presence / absence determination information J_1 and J_2 is 0 by the selector 49b, L_3_1 is selected and the output of the adder 48a If L_3_2 is selected, L_3_2 is selected. If the output of the adder 48a is 2, L_3_3 is selected and is output as the selected lower data L′ _3.

  The selection and distribution of the sign flag is the same as described above, and the first sign flag S_1_1 has no other candidates, so it is output as it is as the lower data S′_1, and the second sign flags S_2_1 and S_2_2 are If the code presence / absence determination information J_1 is 0, the selector 49c selects S_2_1. If the code presence / absence determination information J_1 is 1, S_2_2 is selected and is output as the selected lower data S′_2. The code presence / absence determination information J_1 and J_2 are respectively input to the adder 48b and added to be used for selection of the third sign flag.

  For the third sign flags S_3_1, S_3_2, and S_3_3, if the output of the adder 48b that is the addition value of the code presence / absence determination information J_1 and J_2 is 0 by the selector 49d, S_3_1 is selected and the output of the adder 48b Is 1, S_3_2 is selected, and if the output of the adder 48b is 2, S_3_3 is selected and is output as the selected lower data S′_3.

  Thus, by using the code presence / absence determination information J (i) generated by the lower data parallel code presence / absence determination unit 23, the lower data to be selected from the plurality of candidates for the lower data and the sign flag, and The sign flag can be selected reliably.

  The lower data parallel code inverting unit 26 reverses the sign of the three lower data L ′ (i) input from the lower data distributing unit 25 in parallel (step S12). Here, sign inversion means that a minus sign is added before the lower data. For example, if the lower data is 3 (0003h), the value whose sign is inverted is -3 (FFFDh).

  If the lower data code information K (i) from the lower data parallel code determination unit 24 is positive (+) for the three lower data, the lower data parallel selection unit 27 receives the lower data from the lower data distribution unit 25. If L ′ (i) is selected and the lower data code information K (i) is negative (−), the lower data obtained by inverting the lower data L ′ (i) by the lower data parallel code inverting unit 26 is selected. (Step S9), it is input to the data parallel concatenation unit 13 as lower data L ″ (i). Thereby, the three lower data can be converted into signed data in parallel.

  The data parallel concatenation unit 13 concatenates the three lower data L ″ (i) selected by the lower data parallel selection unit 27 and the corresponding upper data U (i) from the upper data distribution unit 19 in parallel. Then, the coefficient data Z (i) is input to the adaptive scan unit 130 (step S13), whereby three pairs of upper data and lower data can be converted into three coefficient data in parallel. The connection state is as described above with reference to FIG.

  The processing of the lower data L (i) is performed for every three data (step S14), and the processing in the lower data processing unit is repeated until the processing of 15 data in units of one block is completed (step S15). (Steps S5 to S15). Further, the processing of each block described above is repeated for 16 blocks constituting one macro block (step S16).

  Then, when the processing of the macroblock is completed and the last connection of the upper data U (i) and the lower data L ″ (i) is completed, the data parallel connection unit 13 sends the completion signal to the model bits update unit 12. Then, the model bits update unit 12 updates the model bits (step S17) Note that this VLC decoding process is repeated until the processing of all macroblocks in one image data is completed ( Step S18).

  The adaptive scanning unit 130 performs processing for replacing the coefficient data for each block with respect to the first layer data and the second layer data. This replacement process collects non-zero coefficients on the side where the pixel position in the block is small (low frequency side) for the data after frequency conversion at the time of compression, and zeros on the side where the pixel position of the block is large (high frequency side) This is carried out in order to increase the compression rate at the time of encoding by collecting coefficient data having continuous values. The first layer data, the second layer data, and the third layer data on which the replacement process is not performed are input to the coefficient inverse prediction unit 140.

  The coefficient inverse prediction unit 140 similarly derives a prediction mode for the first tier data, the second tier data, and the third tier data for each block, and in accordance with the calculation formula set for the prediction mode, By adding the value of the corresponding pixel to the target pixel, the pixel value before the prediction process in compression is restored (reverse prediction). Then, the first layer data, the second layer data, and the third layer data after inverse prediction are input to the inverse quantization unit 150 for each block.

  The inverse quantization unit 150 performs inverse quantization by multiplying the first layer data, the second layer data, and the third layer data inversely predicted by the coefficient inverse prediction unit 140 by respective set quantization parameters. And the processed first layer data, second layer data, and third layer data are input to the frequency inverse transform unit 160.

  The frequency inverse transform unit 160 sequentially processes the macroblock unit (16 × 16 pixels) in the block unit (4 × 4 pixels) in the raster direction, and converts the coefficient data for each frequency band into the image of each pixel. Data is converted into data, and the processed image data is input to the color space inverse conversion unit 170 for each block.

  The color space inverse transform unit 170 converts the image data input from the frequency inverse transform unit 160 into a color space inverse transform corresponding to the pixel format of the image data, or is not subjected to the color space inverse transform. The final image data is output to the outside.

  As described above in detail, according to the image decoding apparatus 1 of the present example, the low-order data processing unit 21 in the VLC decoding unit 10 performs processing for extracting low-order data from the low-order data group in one cycle. Since the three subordinate data are processed and this processing is executed in five cycles, the processing time can be shortened and the subordinate data extraction processing can be efficiently performed as compared with the conventional subordinate data processing unit 131. As a result, the processing speed of the entire image decoding apparatus 1 can be increased, and an efficient decoding process can be realized.

  Note that one cycle of processing is performed within one clock of the clock used as the processing timing. Therefore, in this example, one block of lower-level data extraction processing is executed in five clocks. .

  As mentioned above, although one Embodiment of this invention was described, the specific aspect which this invention can take is not limited to this at all. For example, in the above example, the low-order data extraction process in the low-order data processing unit 21 in the VLC decoding unit 10 is generated in five cycles. Lower data may be extracted in a cycle, and if possible, 15 lower data constituting one block may be extracted in one cycle.

  In this case, it is necessary to set the number of subordinate data extracted in one cycle according to the number of processing cycles. However, the subordinate data extraction number in the subordinate data parallel extraction unit 22 is referred to from the gist of the present invention. Thus, it is important to enable processing with a smaller number of cycles than the number of coefficient data.

  The lower data parallel extraction unit 22 is provided with first to 15th extraction units corresponding to each model bit, and the pre-selection unit selects the lower data and sign flag candidates by model bits. However, the present invention is not limited to this, and a configuration may be adopted in which candidates for lower data and a sign flag are selected directly from the value of model bits using a barrel shifter.

  Further, the lower data parallel code determination unit 24 selects the sign flag S ′ (i) using the code presence / absence determination information J (i) from the lower data parallel code presence / absence determination unit 23. The sign flag S ′ (i) may be selected using a condition that the upper data U (i) is zero and the lower data L (i) is non-zero.

DESCRIPTION OF SYMBOLS 1 Image decoding apparatus 10 VLC decoding part 11 Macroblock counter part 12 Model bits update part 13 Data parallel connection part 16 High-order data processing part 17 High-order data decoding part 18 High-order data storage part 19 High-order data distribution part 21 Low-order data processing Unit 22 Lower data parallel extraction unit 23 Lower data parallel code presence / absence determination unit 24 Lower data parallel code determination unit 25 Lower data distribution unit 26 Lower data parallel code inversion unit 27 Lower data parallel selection unit 31a to 31o Lower data extraction units 31c1 to 31c6 Lower data extractor 32 Pre-lower data selector 33a to 33o Sign flag extractor 33c1 to 33c6 Sign flag extractor 34 Presign flag selector 35 Non-zero determiner 36 Zero determiner 37a, 37b Non-zero determiner 38 Zero determiner 39a-39c B Determinator 40 Zero determinator 41a-41c AND circuit 42a, 42b Selector 43a-43c Adder 44 Multiplier 45-47 Lower data code determination unit 45a-47a Upper data positive / negative zero determiner 45b-47b Sign flag selector 45c to 47c Lower data code selector 48a, 48b Adder 49a to 49d Selector 110 Bit stream analysis unit 120 VLC decoding unit 121 Macroblock counter unit 122 Model bits update unit 123 Data concatenation unit 126 Upper data processing unit 127 Upper data Decoding unit 128 Upper data storage unit 129 Upper data distribution unit 130 Adaptive scan unit 131 Lower data processing unit 132 Lower data extraction unit 133 Lower data code determination unit 134 Lower data code inversion unit 135 Lower data selection unit 140 Coefficient inverse Predictor 141 Lower data extractor 142 Sign flag extractor 143 Upper data positive / negative zero determiner 144 Sign flag selector 145 Lower data non-zero determiner 146 Lower data code selector 150 Inverse quantizer 160 Frequency inverse converter 170 Color space Inverse conversion unit

Claims (5)

An upper data decoding unit that decodes higher-order data, which is higher-order data of the coefficient data, from compressed image data encoded with n pieces of coefficient data as one block unit; and a lower-order part of the coefficient data A decoding unit composed of a lower data processing unit that extracts lower data that is data, and a data concatenation unit that concatenates the upper data and the lower data to restore coefficient data;
An inverse quantization unit that inversely quantizes the coefficient data in units of blocks decoded by the decoding unit;
In an image decoding apparatus comprising: a frequency inverse transform unit that inversely frequency transforms coefficient data in block units inversely quantized by the inverse quantization unit to generate image data;
The lower data processing unit extracts, in parallel, lower data candidates and sign flag candidates in block units for all possible combinations of the lower data and a combination of sign flags indicating the sign of the lower data. A data parallel extractor;
A lower data parallel code presence / absence determination unit that generates code presence / absence determination information indicating whether or not a sign flag subsequent to the lower data exists based on the upper data and the lower data candidates;
A lower data distribution unit for selecting and distributing n sets of lower data and sign flags in block units in parallel from the lower data candidates and the sign flag candidates based on the code presence / absence determination information; An image decoding apparatus characterized by comprising.
However, n is an integer of 2 or more. The lower-order data processing unit is configured to process each of n pieces of lower-order data and higher-order data in units of blocks, with the number of processes in one cycle being m, in one cycle or by repeating a plurality of cycles. The image decoding apparatus according to claim 1, wherein:
However, n is an integer of 2 or more, m is an integer of 2 or more and n or less, and m and n are equal when the repetition of the process ends in one cycle. The low-order data parallel extraction unit takes m sets of low-order data of q-bit length and a 1-bit-long sign flag that may or may not exist following the low-order data as one set. Extracting all lower data candidates and sign flag candidates in parallel for the possible combinations of the first to mth lower data and the sign flag from the consecutively connected lower data group The image decoding apparatus according to claim 2.
However, a dummy value of 0 or 1 is put in a candidate for a sign flag when the sign flag following the lower data does not exist, n is an integer of 2 or more, and m is 2 or more and n The following integers, q is an integer of 1 to p, and p is an integer of 1 or more. The lower data parallel code presence / absence determining unit uniquely determines the first lower order based on the condition that the sign data following the lower data exists only when the upper data is zero and the lower data is non-zero. From the upper data corresponding to the data, the presence or absence of a sign flag following the first lower data is determined, and the start position shift of the second lower data is estimated by determining the presence or absence of the first sign flag. The second lower data is determined from the lower data candidates, and the presence or absence of a sign flag subsequent to the second lower data is determined from the higher data corresponding to the determined second lower data, and the third For the lower order data, the start position deviation of the lower order data is estimated by the cumulative number of sign flags following the previous lower order data, and the lower order data. The lower order data is determined from the data candidates, and the presence or absence of a sign flag following the first lower order data is determined from the higher order data corresponding to the determined lower order data. Until the mth, the presence / absence of a sign flag following each of the lower order data is judged in parallel, and the judgment information of the presence / absence of the sign flag following each of the decided first to mth lower order data is encoded or not The image decoding apparatus according to claim 2, wherein the image decoding apparatus outputs the determination information.
However, the n is an integer of 2 or more, and the m is an integer of 2 or more and n or less. The lower-order data distribution unit selects the first lower-order data and the sign flag that are uniquely determined as they are, and estimates the start position deviation of the second lower-order data based on the code presence / absence determination information of the first lower-order data. The second lower data and the sign flag are selected from the second lower data candidate and the sign flag candidate. For the third lower data and the sign flag, the presence / absence of the sign of each previous lower data Estimating the start position shift of the second lower data by accumulating the number of existing judgment information, and selecting the lower data and the sign flag from among the lower data candidates and the sign flag candidates, Thereafter, similarly, from the 1st to the mth, each lower order data and the sign flag are selected in parallel, and each of the selected 1st to mth lower order data and the sign flag are output and separated. The image decoding apparatus according to claim 2, characterized by.
However, when the sign flag does not exist, a dummy value of 0 or 1 is entered in the sign flag, the n is an integer of 2 or more, and the m is an integer of 2 or more and n or less. .