JP6215726B2 - Associative memory - Google Patents

Description

  The present invention relates to an associative memory, and more particularly to a technique for extending the number of dimensions of a clock count type associative memory.

  In recent years, applications that require pattern matching typified by character recognition and image recognition have attracted much attention. In particular, by realizing pattern matching on LSI (Large Scale Integrated circuit), it will be applicable to high-function applications such as artificial intelligence and mobile devices in the future, and the realization of this technology has received much attention. .

  In pattern matching, "complete match search process" that searches for a pattern that completely matches the search data from multiple reference data stored in the database, and "most similar search" that searches for the most similar pattern to the search data. Treatment ".

  The former is called CAM (Content Addressable Memory), and is used to realize the routing of the IP address table of the network router and the cache of the processor. In order for a computer to perform flexible search / comparison such as the human brain, it is indispensable to realize the latter most similar search process. A memory having such a function for realizing a flexible comparison is particularly called an associative memory.

  As an example of an associative memory, one that performs a most similar search process using a Manhattan distance or a Euclidean distance between search data and reference data is known (see Non-Patent Document 1).

S. Sasaki et al., "Digital Associative Memory for Word-Parallel Manhattan-Distance-Based Vector Quantization," ESSCIRC'2012, 2012, pp.185-188

  The inventor of the present application has so far provided a clock count type associative memory including a mechanism (effective bit setting unit) for reducing a clock count number for search and a square calculation circuit (distance calculation circuit) for Euclidean distance search. Was disclosed in Japanese Patent Application No. 2013-255465 (hereinafter referred to as the prior application). As a result, an Euclidean / Manhattan distance search associative memory capable of high-speed search even when the data scale increases is realized with error-free and high power efficiency.

  However, there are restrictions on the data size that can be implemented in hardware. Although the associative memory according to the invention of the prior application has no restriction on the data size in principle, the operating frequency is lowered by the increase of the data size. In this regard, if 1NN (1-Nearest Neighbor) search up to a large dimension can be realized with small hardware, the efficiency is improved.

  In view of the above problems, an object of the present invention is to provide an associative memory capable of extending the number of dimensions when a larger data size is required on an application.

  The associative memory according to one aspect of the present invention stores search data that stores E × M-dimensional search data (where E and M are integers of 2 or more) divided into M times in E times. A circuit, a reference data storage circuit that stores R (where R is an integer equal to or greater than 2) E × M-dimensional reference data divided into R M-dimensional E times, and the search data storage Each time new data is stored in the circuit and the reference data storage circuit, a partial distance in each dimension between the search data stored in the search data storage circuit and the individual reference data stored in the reference data storage circuit A distance calculation circuit that calculates a partial distance of each dimension calculated by the distance calculation circuit for each reference data each time new data is stored in the search data storage circuit and the reference data storage circuit Dimensionality expansion circuit for accumulatively adding, and the E × M dimensional search data and the R E × M dimensional reference data are divided into E times and stored in the search data storage circuit and the reference data storage circuit, respectively. After that, for each reference data, the partial distances cumulatively added by the dimension number extension circuit are summed to obtain the distance between the E × M dimensional search data and each E × M dimensional reference data. A distance / clock number conversion circuit that outputs a timing signal indicating the timing of calculating and counting the number of clocks corresponding to the distance is provided.

  According to this, E × M-dimensional search data and reference data are stored in the search data storage circuit and the reference data storage circuit divided into E times for each M dimension, and new data is stored in the search data storage circuit and the reference data storage circuit. Each time the data is stored, the partial distance of each dimension of the search data and the reference data is calculated and further cumulatively added. As a result, the number of dimensions of the E × M dimensional data is compressed to the M dimension, and it becomes possible to substantially handle the E × M dimensional data in the associative memory that can handle only the M dimensional data at the maximum.

  In the content addressable memory, the dimension extension circuit may include first and second multiplexers, full adders, and first and second D flip-flops. The multiplexer is supplied with the first dimension partial distance calculated by the distance calculation circuit and the output of the first D flip-flop as first and second inputs, respectively, and the first control signal causes the first And the second input may selectively output one of the second input, the second multiplexer may include the second dimension partial distance calculated by the distance calculation circuit and the second D. The outputs of the flip-flops are given as first and second inputs, respectively, and one of the first and second inputs is selectively selected by the first control signal. The full adder may be a full adder of the output of the first multiplexer and the output of the second multiplexer, and the first D flip-flop The output of the full adder may be data-inputted, and the storage of input data may be controlled by a second control signal. The second D flip-flop The storage of input data may be controlled by a third control signal that is input and is an inversion of the second control signal.

  According to this, the partial distances of each dimension calculated by the distance calculation circuit can be accumulated and added together for two dimensions, and data signal lines can be reduced.

  The distance calculation circuit may calculate a difference absolute value of each dimension between the search data stored in the search data storage circuit and individual reference data stored in the reference data storage circuit as the partial distance. .

  According to this, the Manhattan distance between the search data and the reference data can be calculated.

  The distance calculation circuit may calculate a difference square value of each dimension between the search data stored in the search data storage circuit and individual reference data stored in the reference data storage circuit as the partial distance. .

  According to this, the Euclidean distance between the search data and the reference data can be calculated.

  According to the present invention, the number of data dimensions that can be handled by an associative memory can be arbitrarily expanded. As a result, the clock count type associative memory can be applied to an application that requires a large data size.

FIG. 5 is a schematic diagram for explaining dimension expansion in an associative memory according to an embodiment of the present invention. 1 is a schematic configuration diagram of an associative memory according to an embodiment of the present invention. Timing chart of an example timing signal Configuration diagram of dimension extension circuit according to an example The figure which shows the operation example of the dimension number expansion circuit of FIG. The figure following FIG. 5A which shows the operation example of the dimension expansion circuit of FIG. Configuration diagram of a control circuit according to an example Timing chart of input / output signals of the control circuit of FIG. Configuration diagram of DC control circuit according to an example Timing chart of input / output signals of DC control circuit of FIG. Configuration diagram of a DEC control circuit according to an example Timing chart of input / output signals of the DEC control circuit of FIG.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. Further, the present invention is not limited to the following embodiment.

≪Overview of dimension expansion≫
An associative memory according to an embodiment of the present invention is such that the number of dimensions of search data and reference data can be expanded in the associative memory according to the invention of the prior application. In other words, the associative memory according to the invention of the prior application can handle only M-dimensional data (M is an integer of 2 or more) specified at the time of design, whereas the associative memory according to the present embodiment has the number of data dimensions. Can be expanded to E × M dimensions (E is an integer of 2 or more).

FIG. 1 is a schematic diagram for explaining dimension expansion in an associative memory according to an embodiment of the present invention. When the number of data dimensions is E × M, if a = h between the search data and the reference data and the square calculation result (partial distance) of the j-th dimension is dh _{, (h−1) M + j} , A distance (for example, Euclidean distance) D _E between the search data and the reference data is calculated as the following equation (1).

Here, the calculation of Σ _{a = 1} ^E is performed first in the equation (1). That is, as shown in FIG. 1, when E × M dimensional data is expressed in a matrix format of E rows × M columns, first, cumulative addition in the column direction (broken line frame in the figure) is performed. As a result, the number of dimensions of E × M dimensional data is compressed to M dimensions, and it is possible to substantially handle E × M dimensional data in the associative memory according to the prior application that can handle only M dimensional data at the maximum. Become.

  The associative memory according to the present embodiment is obtained by adding the function of compressing the number of dimensions of E × M-dimensional data to M-dimensional data as described above to the associative memory according to the prior invention. Details of the associative memory according to the present embodiment will be described below.

<< Configuration example of associative memory according to this embodiment >>
FIG. 2 shows a schematic configuration of an associative memory according to an embodiment of the present invention. The associative memory 100 according to the present embodiment includes a memory array unit 10 and a Winner detector 20.

  Memory array unit 10 includes a memory unit 1, a row decoder 2, a column decoder 3, a read / write circuit 4, and a search data storage circuit 5.

Memory unit 1, the reference data storage circuit _{(Storage Cell) SC 11 ~SC 1M} , SC 21 ~SC 2M, ..., SC R1 and _{to SC RM,} the distance calculation circuit _{(Distance Calculator) DC 11 ~DC 1M} , DC 21 ~ DC _2M ,..., DC _{R1 to} DC _RM , Dimensional Extension Circuits DEC _{11 to} DEC _{1M / 2} , DEC _{21 to} DEC _{2M / 2} ,..., DEC _{R1 to} DEC _{RM / 2} , and distance / clock number conversion circuit and a _{(Distance Evaluator) DE 1 ~DE R} . M and R are both integers of 2 or more.

The row decoder 2 designates an address in the row direction of the memory unit 1. The column decoder 3 designates an address in the column direction of the memory unit 1. The read / write circuit 4 writes the reference data to the reference data storage circuits SC _{11 to} SC _1M , SC _{21 to} SC _2M ,..., SC _{R1 to} SC _RM designated by the row decoder 2 and the column decoder 3 and retrieves them. Data is written into the search data storage circuit 5.

Distance calculating circuit _DC 11 _{to DC 1M,} respectively, are provided corresponding to the reference data storage circuit _SC 11 _{to SC 1M.} The distance calculating circuit _DC 21 _{to DC 2M} are respectively provided corresponding to the reference data storage circuit _SC 21 _{to SC 2M.} In the same manner, the distance calculating circuit _DC R1 _{to DC RM} are each provided corresponding to the reference data storage circuit _SC R1 _{to SC RM.}

One dimension expansion circuit DEC _{11 to} DEC _{1M / 2} is provided corresponding to two adjacent ones of the distance calculation circuits DC _{11 to} DC _1M , respectively. Further, the number of dimensions expand circuit _DEC 21 _{~DEC 2M / 2,} respectively, one is provided corresponding to two adjacent distance calculating circuit _DC 21 _{to DC 2M.} Hereinafter, similarly, one dimension extension circuit DEC _{R1 to} DEC _{RM / 2} is provided corresponding to two adjacent ones of the distance calculation circuits DC _{R1 to} DC _RM , respectively.

The distance / clock number conversion circuit DE ₁ is provided corresponding to the dimension number expansion circuits DEC _{11 to} DEC _{1M / 2} . The distance / clock number conversion circuit DE ₂ is provided corresponding to the dimension number expansion circuits DEC _{21 to} DEC _{2M / 2} . In the same manner, the distance / clock number conversion circuit DE _R is provided corresponding to the number of dimensions expansion circuit _DEC R1 _{~DEC RM / 2.}

Reference data storage circuits SC _{11 to} SC _1M , SC _{21 to} SC _2M ,..., SC _{R1 to} SC _RM store reference data written by the row decoder 2, the column decoder 3, and the read / write circuit 4. In this case, the reference data storage circuits SC _{11 to} SC _1M store N × M (N is an integer of 1 or more) bits of reference data 1. The reference data storage circuits SC _{21 to} SC _2M store N × M bit reference data 2. Similarly, the reference data storage circuits SC _{R1 to} SC _RM store N × M bits of reference data R. That is, the reference data storage circuits SC _{11 to} SC _1M , SC _{21 to} SC _2M ,..., SC _{R1 to} SC _RM store R M-dimensional reference data (each dimension is N-bit data).

  The search data storage circuit 5 stores N × M bit search data. That is, the search data storage circuit 5 stores M-dimensional search data (each dimension is N-bit data).

As described above, the search data storage circuit 5 and the reference data storage circuits SC _{11 to} SC _1M , SC _{21 to} SC _2M ,..., SC _{R1 to} SC _RM can store the number of dimensions of search data and reference data in M dimensions. Therefore, E × M-dimensional search data and reference data are divided into E times and stored in these data storage circuits. Specifically, the search data storage circuit 5 stores the E × M-dimensional search data by dividing the M-dimensional search data into E times. On the other hand, the reference data storage circuits SC _{11 to} SC _1M , SC _{21 to} SC _2M ,..., SC _{R1 to} SC _RM store R pieces of E × M-dimensional reference data by dividing each of the R M-dimensional reference data into E times. To do.

Note that the E × M-dimensional search data and the R E × M-dimensional reference data are stored in a memory (not shown), and are read out from the memory M times in E times by a control circuit (not shown). Then, the M-dimensional search data and the R M-dimensional reference data read from the memory are stored in the search data storage circuit 5 and the reference data storage by the row decoder 2, the column decoder 3, and the read / write circuit 4, respectively. circuit _{SC 11 ~SC 1M, SC 21 ~SC} 2M, ..., are respectively written to the SC R1 _{to SC RM.}

The distance calculation circuits DC _{11 to} DC _1M respectively store N × M stored in the search data storage circuit 5 each time new data is stored in the search data storage circuit 5 and the reference data storage circuits SC _{11 to} SC _1M. A partial distance in each dimension between the bit search data and the N × M bit reference data 1 stored in the reference data storage circuits SC _{11 to} SC _1M is calculated. The distance calculating circuit _DC 21 _{to DC 2M,} respectively, each time a new data is stored in the search data storage circuit 5 and the reference data storage circuit _SC 21 _{to SC 2M,} stored in the search data storage circuit 5 N A partial distance in each dimension between the search data of × M bits and the reference data 2 of N × M bits stored in the reference data storage circuits SC _{21 to} SC _2M is calculated. In the same manner, the distance calculating circuit _DC R1 _{to DC RM,} respectively, each time a new data is stored in the search data storage circuit 5 and the reference data storage circuit _SC R1 _{to SC RM,} the search data storage circuit 5 A partial distance of each dimension between the stored N × M bit search data and the N × M bit reference data R stored in the reference data storage circuits SC _{R1 to} SC _RM is calculated. The partial distances are calculated in parallel by these distance calculation circuits DC _{11 to} DC _1M , DC _{21 to} DC _2M ,..., DC _{R1 to} DC _RM .

  The partial distance may be either a difference absolute value or a difference square value of each dimension between the search data and the reference data. When the distance between the search data and the reference data is evaluated by the Manhattan distance, the difference absolute value may be used as the difference distance. When the distance between the search data and the reference data is evaluated by the Euclidean distance, a difference square value may be used as the difference distance. The specific circuit configuration of the distance calculation circuit is described in detail in the specification and drawings of the prior application. In the following description, for the sake of convenience, the description will be made assuming that the difference square value is used as the partial distance.

Dimensionality expansion circuit _DEC 11 _{~DEC 1M / 2,} respectively, each time a new data is stored in the search data storage circuit 5 and the reference data storage circuit _SC 11 _{to SC 1M,} by the distance calculation circuit _DC 11 _{to DC 1M} The calculated partial distances in each dimension are accumulated and added together for two dimensions. Further, the dimension number expansion circuits DEC _{21 to} DEC _{2M / 2} are respectively connected to the distance calculation circuits DC _{21 to} DC each time new data is stored in the search data storage circuit 5 and the reference data storage circuits SC _{21 to} SC _2M. The partial distances of each dimension calculated by _2M are cumulatively added together for two dimensions. Hereinafter, in the same manner, the dimension number expansion circuits DEC _{R1 to} DEC _{RM / 2} each time the new data is stored in the search data storage circuit 5 and the reference data storage circuits SC _{R1 to} SC _RM , respectively. The partial distances of each dimension calculated by DC _{R1 to} DC _RM are cumulatively added together for two dimensions. These dimensional number increasing circuit _{DEC 11 ~DEC 1M / 2, DEC} 21 ~DEC 2M / 2, ..., cumulative addition of the partial distance by the _DEC R1 ~DEC _{RM / 2} is performed in parallel.

The dimension expansion circuit may be arranged so as to correspond to the distance calculation circuits DC _{11 to} DC _1M , DC _{21 to} DC _2M ,..., DC _{R1 to} DC _RM one by one, but E is a power of 2 If represented, an extra bit number is required by log ₂ E. In the case of E = 64, it is possible to process up to 64 times the dimension prepared on the hardware, but it is necessary to prepare an extra 6 bits per dimension. Therefore, in order to reduce data signal lines, it is preferable to perform cumulative addition of partial distances for two dimensions in each dimension number expansion circuit as in this embodiment.

From the distance calculation circuits DC _{11 to} DC _1M , DC _{21 to} DC _2M ,..., DC _{R1 to} DC _RM , 2N-bit partial distances (differential square values) are output. Therefore, the two-dimensional partial distance output from the two distance calculation circuits is 4N bits. At this time, when the partial distances of each dimension output from each distance calculation circuit are sequentially accumulated from a = 1 to a = E, the output bit width of each dimension number expansion circuit is 4N + 2 log ₂ E bits per two dimensions. Necessary. On the other hand, as in the present embodiment, by performing cumulative addition of the partial distances for two dimensions output from the two distance calculation circuits, the output bit width of each dimension number expansion circuit is (2N + 1). ) + Log ₂ E bits. For example, when the dimension extension of E = 2 ^2N-1 is performed, the output bit widths of the dimension extension circuits DEC _{11 to} DEC _{1M / 2} , DEC _{21 to} DEC _{2M / 2} ,..., DEC _{R1 to} DEC _{RM / 2} are 4N bits, which can be made equal to 4N bits, which are two-dimensional partial distances output from two distance calculation circuits. For example, when N = 8 bits, that is, E = 32768 times of dimension extension, the dimension extension circuits DEC _{11 to} DEC _{1M / 2} , DEC _{21 to} DEC _{2M / 2} ,..., DEC _{R1 to} DEC _RM The output bit width of _{/ 2} is 4N = 32 bits. Here, if M = 16 dimensions, the associative memory 100 according to the present embodiment can handle data expanded to about 500,000 dimensions.

The distance / clock number conversion circuit DE ₁ divides the E × M dimensional search data and the R E × M dimensional reference data into E times, respectively, for the search data storage circuit 5 and the reference data storage circuits SC _{11 to} SC _1M. Are stored in the dimensionality expansion circuit DEC _{11 to} DEC _{1M / 2} , and the distances accumulated by the dimensional number expansion circuits DEC _{11 to} DEC _{1M / 2} are added to calculate the distance between the E × M dimensional search data and the E × M dimensional reference data 1. A timing signal C ₁ indicating the timing at which the number of clocks corresponding to the distance is counted is output. Further, the distance / clock number conversion circuit DE ₂ divides the E × M dimensional search data and the R E × M dimensional reference data into E times, respectively, for the search data storage circuit 5 and the reference data storage circuit SC ₂₁ . After being stored in the SC _2M , the partial distances accumulated and added by the dimension number extension circuits DEC _{21 to} DEC _{2M / 2} are summed to obtain the distance between the E × M dimensional search data and the E × M dimensional reference data 2. It computes, and outputs a timing signal C ₂ which shows the timing obtained by counting the number of clocks corresponding to the distance. In the same manner, the distance / clock number conversion circuit DE _R, the search data storage circuit 5 and the reference data stored E × M dimensional search data and the R E × M-dimensional reference data is divided into E times each The partial distances accumulated by the dimension extension circuits DEC _{R1 to} DEC _{RM / 2} after being stored in the circuits SC _{R1 to} SC _RM are summed to obtain E × M dimensional search data and E × M dimensional reference data R distance to the calculation of the outputs a timing signal C _R indicating the timing obtained by counting the number of clocks corresponding to the distance. According to these distance / clock number conversion circuit DE ₁ ~DE _R, the number of clocks counted in accordance with the distance is performed in parallel.

Winner detector 20, respectively receives a timing signal _C 1 -C _R from the distance / clock number conversion circuit _DE 1 _{~DE R.} FIG. 3 is a timing chart of timing signals according to an example. Then, Winner detector 20, among the received timing signal _C 1 -C _R, k matches timing in chronological order (k is an integer satisfying a 1 ≦ k ≦ R) detects the number of timing signals, and the detection The k timing signals are output as match signals M _{1 to} M _k indicating the similarity between the search data and the reference data.

≪Configuration example of dimension extension circuit≫
As described above, when cumulative addition is performed on the two-dimensional partial distances output from the two distance calculation circuits, the expression (1) is transformed into the following expression (2).

The dimension extension circuits DEC _{11 to} DEC _{1M / 2} , DEC _{21 to} DEC _{2M / 2} ,..., DEC _{R1 to} DEC _{RM / 2} respectively calculate Σ _{a = 1} ^E in Equation (2).

  FIG. 4 shows a configuration example of the dimension number extension circuit. The dimension extension circuit includes two multiplexers (MUX) 11a and 11b, a full adder (Full Adder) 12, and two D flip-flops (DFF) 13a and 13b.

The MUX 11a is a partial distance d _{i (2j−1} ) calculated by a distance calculation circuit DC _{i (2j−1)} (i is an integer satisfying 1 ≦ i ≦ R, j is an integer satisfying 1 ≦ j ≦ M / 2). ₎ Is given as input in0, and the output of DFF 13a is given as input in1, and either one of in0 or in1 is selectively outputted by control signal SDD. The partial distance d _{i (2j−1)} is a difference square value, and its bit width is 2N bits.

The MUX 11b is provided with the partial distance d _{i (2j)} calculated by the distance calculation circuit DC _{i (2j)} as an input in0, the output of the DFF 13b as an input in1, and either one of in0 or in1 by the control signal SDD. Selectively output. The partial distance d _{i (2j)} is a difference square value, and its bit width is 2N bits.

  Both the MUX 11a and the MUX 11b output in0 when the SDD is “0”, and output in1 when the SDD is “1”.

  The full adder 12 is a 2N-bit full adder that performs the full addition of A and B by receiving the output of the MUX 11a as the input A and the output of the MUX 11b as the input B, respectively. CB (Carry Before) and CN (Carry Next) are a carry signal from the previous bit and a carry signal to the next bit, respectively.

  The DFF 13a receives the output OUT of the full adder 12 as data, and the storage of the input data is controlled by the control signal SD. Specifically, the DFF 13a stores input data at the timing of the rising edge of SD.

  The DFF 13b receives the output OUT of the full adder 12 as data and the storage of input data is controlled by the control signal SDQ. SDQ is an inverted signal of SD. Specifically, the DFF 13b stores input data at the timing of the rising edge of SDQ.

  5A and 5B are diagrams illustrating an operation example of the dimension number extension circuit of FIG. An example of the operation of the dimension extension circuit having the above configuration will be described with reference to FIGS. 5A and 5B. In addition, the arrow in a figure represents the flow of data.

In step 1: a = 1, M-dimensional search data and R M-dimensional reference data are stored in the associative memory 100, and a partial distance of each dimension between the search data and each reference data is calculated. Since SDD is “0”, two-dimensional d _{i (2j−1)} and d _{i (2j)} are input to the full adder 12 and added. Although the addition result of the full adder 12 is input to the DFF 13a and DFF 13b, it is not captured by either of them at this time.

  step 2: SD changes from “0” to “1”, and SDQ changes from “1” to “0”. When SD rises, the DFF 13a stores the addition result of the full adder 12, and the stored value is output from the DFF 13a.

Step 3: a new M-dimensional search data and R M-dimensional reference data are stored in the associative memory 100 at a = 2, and a partial distance of each dimension between the search data and each reference data is calculated. The Since SDD is “0”, the updated two-dimensional _{di (2j−1)} and _{di (2j)} are input to the full adder 12 and added. The addition result of the full adder 12 is input to the DFF 13a and DFF 13b, but since SD remains “1” and SDQ remains “0”, the addition result of the full adder 12 is taken into the DFF 13a and DFF 13b. I can't.

  step 4: SD changes from “1” to “0”, and SDQ changes from “0” to “1”. When the SDQ rises, the DFF 13b stores the addition result of the full adder 12, and the stored value is output from the DFF 13b.

Step 5: The SDD changes from “0” to “1”, and the output of the DFF 13a and the output of the DFF 13b are input to the full adder 12 and added. Thus, the addition result of the _{d i} in the case of a = _{1 (2j-1)} and _{d i (2j),} and the addition result of the _{d i} in the case of a = 2 _(2j-1) and _{d i (2j)} Is added. That is, the partial distances for two dimensions from a = 1 to a = 2 are cumulatively added. The addition result of the full adder 12 is input to the DFF 13a and DFF 13b. However, since SD remains “0” and SDQ remains “1”, the addition result of the full adder 12 is taken into the DFF 13a and DFF 13b. I can't.

  Step 6: SD changes from “0” to “1”, and SDQ changes from “1” to “0”. When SD rises, the DFF 13a stores the addition result of the full adder 12, that is, the cumulative addition value of the partial distances for two dimensions from a = 1 to a = 2, and the stored value is output from the DFF 13a. At this time, the output of the DFF 13b and the updated output of the DFF 13a are added in the full adder 12, and a new addition result is input to the DFF 13a and the DFF 13b. However, since neither SD nor SDQ rises, The updated addition result of the full adder 12 is not taken into the DFF 13b.

Step 7: New M-dimensional search data and R M-dimensional reference data are stored in the associative memory 100 at a = 3, and a partial distance of each dimension between the search data and each reference data is calculated. The The SDD changes from “1” to “0”, and updated two-dimensional _{di (2j−1)} and _{di (2j)} are input to the full adder 12 and added. The addition result of the full adder 12 is input to the DFF 13a and DFF 13b, but since SD remains “1” and SDQ remains “0”, the addition result of the full adder 12 is taken into the DFF 13a and DFF 13b. I can't.

  Step 8: SD changes from “1” to “0”, and SDQ changes from “0” to “1”. When the SDQ rises, the DFF 13b stores the addition result of the full adder 12, and the stored value is output from the DFF 13b.

Step 9: The SDD changes from “0” to “1”, and the output of the DFF 13 a and the output of the DFF 13 b are input to the full adder 12 and added. Thus, a = from 1 to _{a = 2 d i (2j-} 1) and _{d i} and accumulation result of _{(2j), d i} in the case of a = 3 _(2j-1) and _{d i (2j)} Are added together. In other words, two-dimensional partial distances from a = 1 to a = 3 are cumulatively added. The addition result of the full adder 12 is input to the DFF 13a and DFF 13b. However, since SD remains “0” and SDQ remains “1”, the addition result of the full adder 12 is taken into the DFF 13a and DFF 13b. I can't.

  Step 10: SD changes from “0” to “1”, and SDQ changes from “1” to “0”. When SD rises, the DFF 13a stores the addition result of the full adder 12, that is, the cumulative addition value of the partial distances for two dimensions from a = 1 to a = 3, and the stored value is output from the DFF 13a. At this time, the output of the DFF 13b and the updated output of the DFF 13a are added in the full adder 12, and a new addition result is input to the DFF 13a and the DFF 13b. However, since neither SD nor SDQ rises, The updated addition result of the full adder 12 is not taken into the DFF 13b.

Thereafter, by repeating the same processing until a = E, the cumulative addition value of the two-dimensional partial distances from a = 1 to a = E is stored in the DFF 13a, and the cumulative addition value D _{i (2j−1} ) is stored from the DFF 13a. ₎ Is output. As described above, the number of dimensions of the E × M-dimensional data is compressed to M dimensions by the dimension number expansion circuit. Thereby, in the associative memory 100 having the memory array unit 10 that can handle only M-dimensional data at the maximum, the number of dimensions of data that can be processed can be arbitrarily expanded.

≪Example of control circuit configuration≫
Next, data writing to the memory array 10, a distance calculation circuit _{DC 11 ~DC 1M, DC 21 ~DC} 2M, ..., control of DC R1 _{to DC RM,} and dimensionality expansion circuit _DEC 11 _{~DEC 1M /} 2, _{DEC 21 ~DEC 2M / 2, ...} , DEC R1 ~DEC RM / 2 of the control will be described.

  FIG. 6 shows a configuration example of the control circuit. The control circuit 200 according to this example includes a DC control circuit (control circuit for distance calculation circuit) 210 and a DEC control circuit (control circuit for dimension extension circuit) 220. “D-FF” in the drawing represents a negative edge type D flip-flop. FIG. 7 is a timing chart of input / output signals of the control circuit 200.

  FIG. 8 shows a configuration example of the DC control circuit 210. “FDIV” in the figure represents a frequency dividing circuit (frequency division by 2). FIG. 9 is a timing chart of input / output signals of the DC control circuit 210. In the DC control circuit 210, when SQG rises, RSTDQ falls as an inverted signal of CLK. Then, by counting one clock, the output of the frequency dividing circuit FDVI becomes “1”. Since SQG is also “1”, SQD becomes “1” one clock after SQG.

  FIG. 10 shows a configuration example of the DEC control circuit 220. In the figure, “FDIV” represents a frequency dividing circuit (frequency division by 2), and “SRFF” represents an SR flip-flop. FIG. 11 is a timing chart of input / output signals of the DEC control circuit 220. In the DEC control circuit 220, when SQG falls for the first time, the output of the frequency dividing circuit FDVI becomes “1”. As a result, the timings of SQG and SD become equal thereafter, and SDD becomes an inverted signal of SD. Strictly speaking, SDD is a signal synchronized with CLK.

  Next, an operation example of the control circuit 200 will be described with reference to the timing chart of FIG.

step I: R M-dimensional reference data (reference data when a = 1), which is partial data of R E × M-dimensional reference data, are reference data storage circuits SC ₁₁ to SC _1M , SC ₂₁ to SC _2M ,..., SC _{R1 to} SC _RM are stored (processing A). Further, M-dimensional search data (search data when a = 1), which is partial data of E × M-dimensional search data, is stored in the search data storage circuit 5 (Process B). Process A and process B are performed while switching the row decoder 2 and the column decoder 3 one clock at a time. When process A and process B are completed, SQ rises. SQ is output from a CPU (not shown). Thereafter, SQ continues to rise until a = E, that is, until winner is detected by E × M-dimensional data search.

  step II: When SQ rises, SQG which is the logical product of SQ and GCLKQ rises. GCLKQ is an inverted signal of GCLK, and GCLK is a signal that becomes “1” when the square calculation (partial distance calculation) is completed in the distance calculation circuit. SQG is used as a latch signal in the distance calculation circuit for storing the absolute difference value AD of each dimension between the search data and the reference data in the latch circuit. SQGSY synchronizes SQG with the clock signal CLK. When RSTD rises in one clock after SQGSY rises, the D flip-flop for square calculation (not shown) in the distance calculation circuit is reset. Then, SQD rises at the timing when RSTD rises again. The SQD is used for switching a multiplexer (not shown) in the distance calculation circuit. That is, the absolute value difference calculation is switched to the square calculation, and the partial products are sequentially added each time the clock is input. The square calculation is completed in N clocks after SQD rises, and GCLK rises. The specific configuration of the distance calculation circuit that performs the square calculation is described in detail in the specification and drawings of the prior application.

  Step III: Process A and process B are started again in response to the rising edge of GCLK. When process A and process B are completed, RSTDC rises. That is, in this step, data writing and absolute value difference calculation when a = 2 are performed.

  step IV: When RSTDC rises, GCLK falls. Since SQG rises due to the fall of GCLK, the absolute value difference is latched in the distance calculation circuit. The above operations are repeated for RSTD, SQD, and SQG related to the distance calculation circuit. Since a = 2, the signal change timings of SQGSY and SD are equal. When SQGSY rises when a = 2, SD rises, and the calculation result when a = 1 is stored in the DFF 13a in the dimension extension circuit.

  step V: The calculation of the partial distance when a = 2 is completed in the previous step. And SQG falls when GCLK rises. SQGSY also falls in synchronization with CLK, and SD also falls. When SD falls, SDQ rises, and the calculation result when a = 2 is stored in DFF 13b in the dimension extension circuit. Then, the SDD operates as an SDQ clock synchronization signal from a = 2. When the SDD rises, the MUXs 11a and 11b in the dimension extension circuit are switched, and the partial distances when a = 1 and a = 2 are cumulatively added. In this step, processing A and processing B in the case of a = 3 are performed at the same time. When the process ends and SD rises when RSTDC rises, a cumulative addition result from a = 1 to a = 2 is stored in DFF 13a in the dimension number extension circuit. Then, SDD rises after one clock.

By repeating the above operation, the E × M dimensional search data is divided into E times for each M dimension and stored in the search data storage circuit 5, and R E × M dimensional reference data are R M The data is stored in reference data storage circuits SC _{11 to} SC _1M , SC _{21 to} SC _2M ,..., SC _{R1 to} SC _RM divided into E times for each dimension, and the processing in the distance calculation circuit and the dimension number expansion circuit is pipelined Is done.

  As described above, according to this embodiment, the number of data dimensions that can be handled by the associative memory 100 can be arbitrarily expanded. As a result, the clock count type associative memory can be applied to an application that requires a large data size.

  Note that if the number of data dimensions is expanded, the distance between the search data and the reference data also increases, so that it is expected that the processing time (clock number count) in the distance / clock number conversion circuit will increase. Therefore, as disclosed in the prior application, the number of clock counts can be reduced by providing an effective bit setting unit for setting effective bits in the distance / clock number conversion circuit.

In the associative memory 100 according to the present embodiment, E × M-dimensional data is divided into E times for each M dimension from a memory (not shown), and the search data storage circuit 5 and the reference data storage circuits SC _{11 to} SC _1M and SC _{21 to} SC _2M. ,..., SC _{R1 to} SC _RM are stored in the associative memory by expanding the capacity of the associative memory 100 and storing all the E × M dimensional search data and the R E × M dimensional reference data. You may store in 100. For example, is it possible to provide a selection circuit for selecting M-dimensional partial data from E × M-dimensional data and inputting it to the distance calculation circuits DC _{11 to} DC _1M , DC _{21 to} DC _2M ,..., DC _{R1 to} DC _RM Alternatively, the search data storage circuit 5 and the reference data storage circuits SC _{11 to} SC _1M , SC _{21 to} SC _2M ,..., SC _{R1 to} SC _RM are composed of a FIFO (First-In First Out) type stack memory or the like. Such a modification is possible. In such a modification, R pieces of M-dimensional data can be processed in parallel.

  The associative memory according to the present invention can be used in fields such as pattern recognition / learning, similarity search processing, intelligent information processing, intelligent home appliances, monitoring systems, and security authentication.

100 associative memory 5 search data storage circuit SC reference data storage circuit DC distance calculation circuit DEC dimension number expansion circuit DE distance / clock number conversion circuit 11a MUX (first multiplexer)
11b MUX (second multiplexer)
12 Full adder 13a DFF (first D flip-flop)
13b DFF (second D flip-flop)

Claims (4)

A search data storage circuit that stores search data of E × M dimensions (where E and M are integers equal to or greater than 2) divided into M times in E times;
A reference data storage circuit that stores R (where R is an integer equal to or greater than 2) E × M-dimensional reference data divided into R M-dimensional reference E times;
Each time new data is stored in the search data storage circuit and the reference data storage circuit, each of the search data stored in the search data storage circuit and the individual reference data stored in the reference data storage circuit A distance calculation circuit for calculating a partial distance of the dimension;
Each time new data is stored in the search data storage circuit and the reference data storage circuit, a dimension number expansion circuit that cumulatively adds the partial distances of each dimension calculated by the distance calculation circuit for each reference data. When,
After the E × M-dimensional search data and the R E × M-dimensional reference data are stored in the search data storage circuit and the reference data storage circuit in E times, respectively, for each reference data Then, the distances between the E × M dimensional search data and the individual E × M dimensional reference data are calculated by summing the partial distances cumulatively added by the dimensionality expansion circuit, and the number of clocks corresponding to the distance An associative memory comprising: a distance / clock number conversion circuit that outputs a timing signal indicating a timing at which counting is performed. The dimension extension circuit includes first and second multiplexers, a full adder, and first and second D flip-flops,
The first multiplexer has a first dimension partial distance calculated by the distance calculation circuit and an output of the first D flip-flop as first and second inputs, respectively, and a first control signal To selectively output one of the first and second inputs,
The second multiplexer is provided with a second dimension partial distance calculated by the distance calculation circuit and an output of the second D flip-flop as first and second inputs, respectively, and the first control. One of the first and second inputs is selectively output according to a signal;
The full adder fully adds the output of the first multiplexer and the output of the second multiplexer,
In the first D flip-flop, the output of the full adder is data-input, and storage of input data is controlled by a second control signal,
In the second D flip-flop, the output of the full adder is input as data, and storage of input data is controlled by a third control signal that is an inversion of the second control signal. The associative memory according to claim 1. The distance calculation circuit calculates, as the partial distance, a difference absolute value of each dimension between search data stored in the search data storage circuit and individual reference data stored in the reference data storage circuit. The associative memory according to claim 1 or 2. The distance calculation circuit calculates, as the partial distance, a difference square value of each dimension between search data stored in the search data storage circuit and individual reference data stored in the reference data storage circuit. The associative memory according to claim 1 or 2.