JP6205831B2 - Mask pattern generation method, mask pattern generation apparatus, and mask pattern generation program - Google Patents

Description

  The present invention relates to a mask pattern generation method, a mask pattern generation apparatus, and a mask pattern generation program.

  Along with the recent miniaturization of elements and multilayered wiring in semiconductor devices, in order to improve the manufacturing yield in the semiconductor manufacturing process, the substrate or conductor layer is coated with an oxide film after the etching process, and then CMP (Chemical Mechanical Polishing process is an essential process. In addition, it is known that in the CMP process, a dishing phenomenon in which the oxide film is excessively polished occurs when the pattern coverage in the planar region of the layer processed using the mask to be polished is different. Therefore, in the layout process of the semiconductor device, in order to make the mask pattern coverage uniform, a dummy pattern is formed in addition to the actual pattern necessary for the semiconductor element.

  In the layout process of the semiconductor device, the dummy pattern is arranged in an empty area after the semiconductor element to be arranged is arranged and the wiring is connected. Specifically, for example, dummy patterns having the same shape are arranged at equal intervals in an area other than the area where the actual pattern is arranged (see, for example, Patent Document 1). Thereafter, it is verified (density verification) whether or not the mask pattern coverage is uniform. As described above, the density verification of the mask pattern is generally performed after the placement of the semiconductor element, the wiring connection, and the generation of the dummy pattern.

JP 2010-102680 A

  However, if it is determined as an error as a result of the mask pattern density verification, it is necessary to repeat the process from the placement of the semiconductor elements and the wiring connections. As a result, every time an error occurs in density verification, a great amount of rework has occurred. In addition, since it is difficult to predict the mask pattern coverage at the stage of the semiconductor element arrangement and wiring connection process, the arrangement of the semiconductor element and the wiring connection process may be repeated many times.

  An object of the present invention is to provide a mask pattern generation method, a mask pattern generation apparatus, and a mask pattern generation program that efficiently set the mask pattern coverage to a reference range.

  A first aspect is a mask pattern generation method for a semiconductor device, wherein a boundary pattern region defining an element pattern formation region on a semiconductor substrate, and the mask pattern per verification region disposed around the boundary pattern region A reference process of library information having a plurality of library patterns having a density guarantee area for dummy pattern arrangement satisfying the minimum coverage ratio reference value, and a first arrangement for arranging a first library pattern extracted from the library information And after the first placement step, the second library pattern extracted from the library information is overlapped with the density guarantee region of the second library pattern and the boundary pattern region of the first library pattern. A second arrangement step of arranging the first and second library patterns An outer region of the serial boundary pattern region having a dummy pattern placement step of placing the dummy pattern in the region including the density security area.

  According to the first aspect, the present invention efficiently sets the mask pattern coverage to the reference range.

It is an example figure which shows the structure of the pattern production | generation apparatus of the semiconductor device in this Example. It is a flowchart figure which shows the outline | summary of the layout process of a semiconductor device. It is a figure explaining the coverage of a mask pattern. It is a figure explaining an example of a density guarantee area | region. It is a flowchart figure explaining the process which produces | generates a density guarantee area | region. It is an example figure which shows the boundary area | region of the element used as the generation object of a density guarantee area | region. It is a figure explaining the process of the flowchart figure of FIG. 5 based on a specific example. It is a figure which shows an example of the element library in this embodiment. It is a flowchart figure explaining the layout process of an element. It is a figure explaining the specific example of the layout of an element. It is a figure explaining another specific example of the layout of an element. It is a figure explaining the coverage of the mask pattern of a polysilicon. It is an example figure by which the element of arrangement | positioning object is arrange | positioned between the density guarantee area | regions of the arranged element. It is an example figure by which the element of arrangement | positioning object is arrange | positioned overlappingly in the inner part of the density guarantee area | region of the arranged element. It is an example figure by which the element of arrangement | positioning object is arrange | positioned overlappingly in the inner part of the several density guarantee area | region in the arranged element. It is an example figure by which the element of arrangement | positioning object is arrange | positioned overlappingly in the outer part of the density guarantee area | region in the arranged element. It is a figure which shows the minimum required area | region. It is a flowchart figure explaining the process which produces | generates the density guarantee area | region in the example of 3rd Embodiment. It is a figure explaining the 1st specific example of the minimum required area | region. It is a figure explaining the 2nd specific example of the minimum required area | region. It is a flowchart figure explaining the layout process of the element in the example of 3rd Embodiment. It is a 2nd flowchart figure explaining the layout process of the element in the example of 3rd Embodiment. It is a figure explaining the 1st specific example of a layout process. It is a figure explaining the 2nd specific example of a layout process.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the technical scope of the present invention is not limited to these embodiments, but extends to the matters described in the claims and equivalents thereof.

[Configuration of pattern generator]
FIG. 1 is an example diagram showing the configuration of a mask pattern generation device 1 for a semiconductor device according to the present embodiment. The mask pattern generation apparatus 1 shown in FIG. 1 is a computer equipped with a CAD system, for example. The mask pattern generation device 1 includes a processor 11, a memory 12, a processing unit 13, an output unit (display device) 14, an input unit 15, and the like. The processor 11 controls the entire mask pattern generation apparatus 1, and the processing unit 13 operates the CAD system in cooperation with the processor 11. The output unit 14 is a display device such as a display that displays output information on the CAD system. The input unit 15 is a mouse, a keyboard, or the like, and receives input to the CAD system. Each unit is connected to each other via a bus line 16.

  The memory 12 includes, for example, a check program PR, an element library d1, a design standard d2, and a layout database (DB) d3. The check program PR is a program for verifying the density of the mask pattern, and the element library d1 has information on semiconductor elements (hereinafter, elements) to be arranged in the layout target area. In addition, the design criteria d2 stores element arrangement, rules for wiring connection, prohibited items, and the like. The layout DBd3 stores element and dummy pattern arrangement information, wiring connection information, and the like, which are the results of element layout processing.

  Here, an outline of the layout process of the semiconductor device will be described. In the present embodiment, the element layout process is performed, for example, by the user operating the position information of the semiconductor element via the input unit 15 on the CAD system.

[Outline of layout process]
FIG. 2 is a flowchart showing an outline of the layout process of the semiconductor device. In the present embodiment, the element to be arranged is, for example, a polysilicon resistor composed of five polysilicon resistors, an MOM capacitor, a polysilicon capacitor, a PMOS, an NMOS, or the like. However, the present invention is not limited to this example, and the contents of elements to be arranged differ depending on the semiconductor device to be laid out.

  The element library d1 has a data identification name on the CAD system, layer information, size verification area size information, mask pattern coverage reference range information, and the like for each element to be arranged. The data identification name is a name for identifying an element in the CAD system, and the layer information indicates information of a layer in which the element is formed. The size information of the density verification region indicates size information of a region serving as a unit for density verification of the mask pattern. In the present embodiment, for example, the size of the density verification region is 10 um × 10 um. In the present embodiment, the reference range of the mask pattern coverage is, for example, 10% to 65%. That is, in the density verification, when the coverage of the mask pattern in the density verification region is other than 10 to 65%, it is determined as an error.

  In the flowchart of FIG. 2, the user arranges elements to be arranged in the layout target area. Specifically, the user selects and arranges elements with high priority one by one from the element library d1 (S11). When the arrangement is completed for all the elements (YES in S12), the wiring is connected (S13). Subsequently, the user places a dummy pattern in the empty area for each mask pattern (S14). Then, the check program PR verifies whether or not the coverage is within the reference range for each mask pattern with the density verification region as a unit (S15).

  Here, the density verification of the mask pattern will be described. As described above, in the present embodiment, the reference range of the mask pattern coverage is, for example, 10% to 65%. In the density verification process, it is verified whether the coverage is a value of 10% to 65% with the density verification frame Fr as a unit on the entire surface of the mask pattern.

[Mask pattern coverage]
FIG. 3 is a diagram for explaining the coverage of the mask pattern. In this example, two polysilicon resistance elements having five polysilicon resistors are arranged. In this example, the mask pattern is a pattern for masking the active region in the semiconductor substrate.

  The regions surrounded by the dotted lines are boundary pattern regions (hereinafter referred to as boundary regions) L1-1 and L1-2 that define the polysilicon formation region on the semiconductor substrate, and are regions where the placement of the dummy pattern dm is not permitted. In the case of a polysilicon resistor, a buried oxide film (inactive region) is generated below the boundary regions L1-1 and L1-2. In this example, the dummy pattern dm is a dummy pattern in the active region. The thick line indicates an example of the density verification frame Fr corresponding to the density verification area, and the area AC indicates the active area.

  (A-1) in FIG. 3 is an arrangement example of elements in which a mask pattern whose coverage is less than the reference range is generated. In the figure, the inactive regions are continuous because the boundary regions L1-1 and L1-2 of two polysilicon resistance elements are arranged adjacent to each other. When the density verification frame Fr corresponds as shown in the figure, the entire region in the density verification frame Fr becomes an inactive region. Therefore, the coverage of the mask pattern in the density verification frame Fr is 0%, resulting in a density error.

  (A-2) in FIG. 3 represents a cross-sectional view corresponding to the dotted line x1 in (A-1). In FIG. 6A-2, area E1 is a silicon substrate, area E2 is a stopper film, and area E3 is a buried oxide film. A dummy active region is formed in a region corresponding to the dummy pattern dm. As described above, when the boundary regions L1-1 and L1-2 of the two polysilicon resistance elements are adjacent to each other, the region E3 of the buried oxide film which is an inactive region becomes wide. In this case, the dishing phenomenon ER is likely to occur in the planarization process of the buried oxide film.

  On the other hand, (B-1) in FIG. 3 is an arrangement example of elements in which a mask pattern in which the coverage rate satisfies the reference range is generated. In the same figure, the boundary regions L1-1 and L1-2 are arranged at an interval where the dummy pattern dm can be arranged, so that the inactive layers corresponding to the boundary regions L1-1 and L1-2 are discontinuous. It becomes. Therefore, when the density verification frame Fr corresponds as shown in the figure, an active layer based on the dummy pattern dm is formed in the density verification frame Fr, and the coverage of the mask pattern in the density verification frame Fr is, for example, 15%. Succeeded in density verification.

  (B-2) in FIG. 3 represents a cross-sectional view corresponding to the dotted line x2 in (B-1). As described above, since there is a gap between the boundary regions L1-1 and L1-2 of the two polysilicon resistance elements, a dummy active region is formed between the buried oxide film formation area E3. In this case, the buried oxide film formation area E3 is narrowed and the dishing phenomenon is avoided.

  In this way, the dummy pattern dm is arranged in the region outside the boundary region in order to keep the coverage of the mask pattern within the reference range. However, the dummy pattern dm is arranged outside the boundary area after all the elements to be arranged are arranged and the corresponding boundary area is defined. Then, density verification is performed for each mask pattern, and when a density verification error occurs, re-starting from the element placement process occurs. As a result, a great amount of rework occurs.

  Therefore, in the pattern generation method of the semiconductor device in the present embodiment, the boundary pattern region that defines the element pattern formation region on the semiconductor substrate, and the coverage of the mask pattern per verification region that is arranged around the boundary pattern region An element library d1 having a plurality of library patterns having a density guarantee area for arranging dummy patterns that satisfy the minimum reference value is referred to. Then, the first library pattern extracted from the element library d1 is arranged, and the second library pattern does not overlap the density guaranteed area of the second library pattern with the boundary pattern area of the first library pattern. Be placed. A dummy pattern is arranged in an area outside the boundary pattern area of the first and second library patterns and including the density guarantee area.

  Thereby, each element can be arranged so that the coverage of the mask pattern satisfies the reference range in the element arranging step. That is, in the element arranging step, it is ensured that the coverage of each mask pattern falls within the reference range. For this reason, it is avoided that an error occurs in the density verification after the placement process of the dummy pattern dm, redoing from the element placement process is prevented, and rework is avoided.

  Next, the density guarantee area which is an area for dummy pattern placement will be described.

[Example of density guarantee area: (A-1) (A-2)]
FIG. 4 is a diagram illustrating an example of the density guarantee area. (A-1) in the figure will be described by exemplifying an element in which five vertically long polysilicon resistors are arranged in the horizontal direction in the same manner as in FIG. In the figure, a region L1-1 surrounded by a dotted line indicates a boundary region, and shaded regions dg1-1 to dg1-4 indicate density guaranteed regions.

  The density guarantee areas dg1-1 to dg1-4 are set with the vertices of the boundary area L1-1 as base points so as to be adjacent to the long side of the boundary area L1-1 as shown in FIG. Is done. The density guarantee areas dg1-1 to dg1-4 are areas for arranging the dummy patterns dm. Thus, in addition to the boundary region L1-1, the density guarantee regions dg1-1 to dg1-4 are set in advance for the elements to be arranged. In the present embodiment, the boundary area L1-1 is arranged based on the density guarantee areas dg1-1 to dg1-4, so that the coverage around the boundary area L1-1 in the mask pattern is the minimum reference value ( In this example, 10%) or more is guaranteed.

  (A-2) in FIG. 4 is a diagram for explaining an arrangement example of elements in which a density guarantee region is set. In this example, the density guarantee area dg1-3 of the boundary area L1-1 and the density guarantee area dg2-1 of the boundary area L2-1, the density guarantee area dg1-4 of the boundary area L1-1, and the density of the boundary area L2-1 The security areas dg2-2 are arranged so as to overlap each other. As a result, an interval for arranging a dummy pattern dm (not shown) for ensuring a coverage equal to or higher than the minimum reference value is secured between the boundary region L1-1 and the boundary region L1-2 based on the density guarantee region. Is done.

  The dummy pattern dm is arranged with respect to the inactive area outside the boundary areas L1-1 and L1-2 including the density guarantee areas dg1-1 to dg1-4 and dg2-1 to dg2-4. Therefore, for example, in the example of (A-2) in FIG. 4, when the density verification of the density verification frame Fr1 portion is performed, an active region that guarantees a coverage equal to or higher than the minimum reference value is included in the density verification frame Fr1. Because it is arranged, it succeeds in density verification. Similarly, when density verification is performed corresponding to the density verification frame Fr2, an active region that guarantees a coverage equal to or higher than the minimum reference value is arranged in the density verification frame Fr2. success.

[Example of density guarantee area: (B-1) (B-2)]
On the other hand, (B-1) in FIG. 4 will be described based on a polysilicon resistance element in which five horizontally long polysilicon resistors are aligned in the vertical direction. In the figure, a region L2-1 surrounded by a dotted line indicates a boundary region, and shaded regions dg2-1 to dg2-4 indicate density guaranteed regions. In the present embodiment, the density guarantee areas dg2-1 to dg2-4 are set so as to be adjacent to the long side of the boundary area L2-1. Details of the density guarantee area generation processing will be described later.

  In FIG. 4B-2, the density guarantee area dg2-3 of the boundary area L2-1, the density guarantee area dg2-1 of the boundary area L2-2, and the density guarantee area dg2-4 of the boundary area L2-1 The density guarantee areas dg2-4 of the area L2-2 are arranged so as to overlap each other. As a result, an interval for arranging a dummy pattern dm (not shown) for ensuring a coverage equal to or higher than the minimum reference value is secured between the boundary region L2-1 and the boundary region L2-2 based on the density guarantee region. Is done. Further, in the example of (B-2) in FIG. 4, when the density verification frame Fr3 portion is verified, the minimum reference value between the boundary regions L2-1 and L2-2 is determined based on the density guarantee region. Spaces for arranging dummy patterns are provided to ensure the above coverage. In the density verification frame Fr3, since the dummy pattern satisfying the coverage ratio equal to or higher than the minimum reference value is arranged, the density verification is successful.

  In this way, for each element to be arranged, a density guarantee area for dummy pattern arrangement is set in advance, which is adjacent to the long side of the boundary area and secures a coverage equal to or higher than the minimum reference value. Then, by arranging the boundary region based on the density guarantee region of the element, it is ensured that the coverage of the mask pattern satisfies the minimum reference value.

  Next, details of the density guarantee area generation processing will be described with reference to a flowchart.

[Density guarantee area generation processing]
FIG. 5 is a flowchart for explaining processing for generating a density guarantee area. First, the user inputs information on an element for which a density guarantee region is to be generated to the element library d1 (S21). The element information includes a data identification name on the CAD system, layer information, size verification area size information, and mask pattern coverage reference range information. Subsequently, the processing unit 13 of the mask pattern generation device 1 extracts a frame that defines the boundary region of the target element. As described above, the boundary region is a region that defines a conductive pattern formation region on the semiconductor substrate, and is a region that is required for element arrangement. For example, the boundary region indicates a region L1-1 indicated by a dotted line in the example of (A-1) in FIG.

  Next, the processing unit 13 determines whether or not the processing target element is a generation target of the density guarantee area. The element for which the density guarantee area is generated is an element whose boundary area is not included in the area of the density verification frame, and when the density verification frame and the boundary area are overlapped, the area excluding the boundary area in the density verification frame However, the element which can ensure the coverage more than the minimum reference value (10% in this example) is shown. Here, elements that are not targeted for generation of the density guarantee region will be described based on specific examples.

[Elements not subject to generation of density guarantee area]
FIG. 6 is an example diagram illustrating boundary regions L3 to L5 of elements that are not the generation target of the density guarantee region. First, the boundary region L3 shown in FIG. 5A is included in the region of the density verification frame Fr. In such a case, the coverage in the area of the density verification frame Fr needs to be calculated including other boundary areas arranged in the area within the density verification frame Fr. Therefore, in the flowchart of FIG. 5, an element whose boundary region is included in the density verification frame Fr is excluded from the generation of the density guarantee region.

  6B and 6C, when the density verification frame Fr and the boundary region overlap, the difference region excluding the boundary region in the density verification frame Fr is the minimum reference value. An example in which the above coverage cannot be secured will be shown. Specifically, the boundary region L4 shown in FIG. 6B includes a density verification frame Fr. For this reason, there is no difference area except for the boundary area L4 in the density verification frame Fr. In this case, since the coverage needs to be guaranteed within the boundary region L4, it is excluded from the generation of the density guaranteed region.

  Although the boundary region L5 shown in FIG. 6C does not include the density verification frame Fr, the boundary region L5 in the density verification frame Fr is high because the area ratio of the boundary region L5 in the density verification frame Fr is high. The difference area except for cannot cover the coverage more than the minimum reference value. Also in this case, since the coverage needs to be guaranteed within the boundary region L5, it is excluded from the generation of the density guaranteed region.

  As described above, the elements in the boundary regions L4 to L6 illustrated in FIG. 6 are excluded from the generation of the density guarantee region in the flowchart of FIG. As for the density guarantee region of the element in the boundary region L3 included in the density verification frame Fr as shown in FIG. 6A, for example, an element in which other elements arranged in the density verification frame Fr are combined. A boundary region of the group is generated, and a density guarantee region is generated for the boundary region. In addition, as shown in FIGS. 6B and 6C, for the element in which the difference area excluding the boundary area in the density verification frame Fr cannot secure the coverage that is equal to or higher than the minimum reference value, the coverage in the boundary area is previously set. Are generated to satisfy the reference range.

  Returning to the flowchart of FIG. 5, the processing unit 13 determines whether or not the target element is a target element for generating a density guarantee area. Specifically, the processing unit 13 first detects the size of the boundary region in the long side direction (S23). Then, the processing unit 13 determines whether or not the detected size in the long side direction is larger than the size in the same direction of the density verification frame Fr (S24). In this example, the density verification frame Fr is a square region. Therefore, when the size of the boundary region in the long side direction is equal to or smaller than the size of the density verification frame Fr (NO in S24), the case where the boundary region is included in the density verification frame Fr is shown ((A) in FIG. 6). ). For this reason, it is excluded from the generation of the density guarantee area.

  On the other hand, when the size in the long side direction of the target boundary region is larger than the size in the same direction of the density verification frame Fr (YES in S24), the processing unit 13 detects the size in the short side direction of the boundary region (S25). . Then, the processing unit 13 determines whether or not the detected size in the short side direction is smaller than the size in the same direction of the density verification frame Fr (S26). Since the density verification frame Fr is a square region, if the size of the boundary region in the short side direction is equal to or larger than the size of the density verification frame Fr in the same direction (NO in S26), the boundary region includes the density verification frame Fr. The case is shown ((B) of FIG. 6). For this reason, it is excluded from the generation of the density guarantee area.

  When the size in the short side direction of the boundary region is smaller than the size in the same direction of the density verification frame Fr (YES in S26), the boundary region is not included in the density verification frame Fr (YES in S24), and the boundary region is density The case where the verification frame Fr is not included (YES in S26) is shown. For elements that are excluded from the generation of the density guarantee region (NO in S24, NO in S26), as described above with reference to FIG. 6, the mask pattern coverage is within the reference range based on another method. Will be dealt with as follows.

  Subsequently, the processing unit 13 extracts the vertex coordinates of all the vertices in the boundary region (S27). In this example, since the boundary area is a rectangular area, the coordinates of four vertices are extracted. The coordinate indicates the relative position of each vertex. First, the processing unit 13 selects, for example, the coordinates of the lower left vertex of the boundary region as the first vertex of the boundary region (S28). Subsequently, the processing unit 13 sets a density guarantee area calculation frame (hereinafter, a calculation frame) having the same size as the density verification frame Fr for the boundary area. Specifically, the processing unit 13 sets the calculation frame by superimposing the lower left vertex of the boundary region and the lower left vertex of the calculation frame.

  And the process part 13 calculates the area | region except the boundary area | region in the set calculation frame as a difference figure according to a figure calculation process etc. (S30). Subsequently, the processing unit 13 calculates the area of the difference graphic (S31), and calculates the area of the dummy pattern dm that can be arranged in the area (S32). Specifically, the processing unit 13 calculates the area of the dummy pattern dm when the dummy pattern dm is averaged and arranged with respect to the area of the difference graphic. In this example, for example, the ratio of the area of the dummy pattern dm that can be arranged per unit area is about 60%. For this reason, the processing unit 13 calculates an area of 60% of the area of the differential graphic as the area of the maximum dummy pattern dm that can be generated in the differential graphic.

  Subsequently, the processing unit 13 determines that the ratio of the calculated area of the dummy pattern dm to the area of the calculation frame is the minimum value (in this example, 10% to 65%) in the reference range of the mask pattern coverage (in this example, 10% to 65%). , About 10%) or more is determined (S33). When the area ratio of the dummy pattern dm in the calculation frame is less than the coverage minimum reference value (NO in S33), the processing unit 13 excludes the target element from the generation of the density guarantee region. This corresponds to the example of FIG. 6C, and shows a case where the area of the difference graphic excluding the boundary area in the calculation frame (density verification frame Fr) cannot secure a coverage equal to or higher than the minimum reference value.

  On the other hand, when the ratio of the area in the calculation frame of the dummy pattern dm is equal to or greater than the coverage minimum reference value (YES in S33), the processing unit 13 determines that the area ratio in the calculation frame of the dummy pattern dm is the minimum reference value. That is, the minimum necessary area is calculated (S34). The minimum required area indicates a minimum area necessary for satisfying the reference range of the coverage ratio among the areas of the density guarantee region. In this example, the area where the ratio of the area in the calculation frame of the dummy pattern dm is 10% is calculated as the minimum required area. Then, the processing unit 13 sets the difference graphic as the density guarantee area, and stores the coordinate information of the density guarantee area and the information of the minimum necessary area in the element library d1 (S35).

  In this way, a density guarantee area corresponding to the first vertex of the boundary area is generated. When the density guarantee area has not been generated for all the vertices of the boundary area of the target element (NO in S36), the density guarantee area is then generated corresponding to the next vertex of the boundary area. When the density guarantee area is generated for all the vertices of the target element (YES in S36), the density guarantee area generation processing is performed for another element.

  As described above, for each vertex, an area excluding the boundary area in the calculation frame set so as to overlap with the boundary area is arranged as the density guarantee area. For this reason, as illustrated in (A-1) and (B-1) of FIG. 4, when the boundary region is a horizontally long region, the density guarantee region is set adjacent to the lateral side of the boundary region. . On the other hand, when the boundary region is a vertically long region, the density guarantee region is disposed adjacent to the vertical side of the boundary region. That is, the density guarantee area is arranged adjacent to the side in the long side direction of the boundary area.

  In this embodiment, the ratio of the area of the dummy pattern dm that can be arranged per unit area (60% in this example) is set in advance as a reference range of the mask pattern coverage (10% in this example). ˜65%) is set to a value equal to or less than the maximum value (65% in this example). Thereby, the coverage of the area where only the dummy pattern dm is arranged is kept within the reference range.

[Specific example of density guarantee area generation processing]
FIG. 7 is a diagram for explaining the processing of the flowchart in FIG. 5 based on a specific example. In this example, the generation of the guaranteed density region of the polysilicon resistance element illustrated in FIG. 3 is illustrated. The size of the calculation frame is 10 μm × 10 μm, and the area ratio of the dummy patterns dm that can be arranged per unit area is 60%.

  In the example of FIG. 7, the size of the boundary region L1-1 in the long side direction Y1 is larger than 10 μm (YES in S24 in FIG. 5), and the size in the short side direction Y2 (6.5 μm) is smaller than 10 μm (S26). YES) For this reason, the boundary region L1-1 is a generation target of the density guarantee region. Therefore, for the boundary region L1-1, the calculation frame Fr is set so that the corresponding vertices overlap with each other with the first vertex c1 as the base point (S28) (S29). Then, an area excluding the boundary area L1-1 in the calculation frame Fr is calculated as the difference graphic dg1-1 (S30).

  Subsequently, the area of the difference graphic dg1-1 is calculated (S31). Specifically, since the length of the short side of the boundary region L1-1 is 6.5 μm, the length of the short side of the differential graphic is 3.5 μm. For this reason, the area of the differential graphic is 35 square um (= 10 × 3.5). In this example, for example, four dummy patterns dm can be arranged in 60% of the area of the difference graphic. The area of the calculation frame is 100 square um (= 10 × 10), and the total area of the four dummy patterns dm is 21 square um (= 10 × 3.5 × 0.6) (S32). For this reason, the area ratio of the dummy pattern dm in the calculation frame is calculated as 21% (= 21 ÷ 100 × 100), which exceeds the minimum coverage standard value of 10% (YES in S33). Therefore, the difference graphic dg1-1 is set as the density guarantee area (S35). Similarly, subsequently, the density guarantee area dg1-2 is set for the second vertex c2 of the boundary area L1-1. The other density guarantee areas dg1-3 and dg1-4 are generated in the same manner.

  Further, the minimum required area in each density guarantee region dg1-1 to dg1-4 is calculated (S34). In this example, the ratio of the area of the dummy pattern dm that can be arranged per unit area is 60%. The minimum required area is an area where the ratio of the area of the dummy pattern to the area of the calculation frame is 10%. For this reason, the minimum area is calculated as about 17 square um (= 10 × 10 × 0.1 ÷ 0.6).

  In this way, a density guarantee area is preset for each element to be arranged and stored in the element library d1. The element library d1 also stores information on the minimum required area in addition to information on the density guarantee area.

[Example of element library d1]
FIG. 8 is a diagram showing an example of the element library d1 in the present embodiment. In the figure, coordinate information indicating the size of each side of the density verification frame Fr is stored as information areaV. Specifically, the coordinates X1-X2 indicate the size of the horizontal side of the density verification frame Fr, and the coordinates Y1-Y2 indicate the size of the vertical side of the density verification frame Fr. For each element, the size information of the density verification frame Fr, the coordinate information indicating the boundary area, the coordinate information indicating the density guarantee area, and the like are stored. In the figure, a specific example of information of the polysilicon resistance element is illustrated in the information Lib portion.

  Specifically, coordinate information indicating the boundary region of the polysilicon resistance element is stored as information diff-inhi. The coordinates x1-x2 indicate the horizontal side of the boundary area, and the coordinates y1-y2 indicate the size of the vertical side of the boundary area. And the coordinate information which shows a density guarantee area | region is memorize | stored as information areaA-areaD. For example, the coordinates x7-x8 in the information areaA indicate the horizontal sides of the density guarantee area, and the coordinates y7-y8 indicate the sizes of the vertical sides of the density guarantee area. Further, in the example of the figure, information on the minimum required area min and the maximum area max is described together as information on the density guarantee area. The maximum area max indicates the area of the dummy pattern that can be generated to the maximum in the density guarantee region.

  Similarly, boundary region information and density guarantee region information are also stored for elements other than polysilicon resistance elements (such as PMOS). Information of such an element library d1 is extracted as follows, and elements are arranged.

[Element layout process]
FIG. 9 is a flowchart illustrating element layout processing. As described above, the density guarantee region information is generated in advance for each element to be arranged and stored in the element library d1. First, the user selects and arranges one element to be arranged (S41). Subsequently, the user selects an element to be arranged next, and arranges the arranged element and the boundary region so as not to overlap each other (S42). At this time, the user may arrange the elements to be arranged so that they do not overlap with the arranged boundary area in the density guarantee area, or the coverage in the area excluding the arranged boundary area from the density guarantee area is You may arrange | position so that it may become more than the minimum reference value.

  Subsequently, the processing unit 13 determines whether or not the density guarantee area of the element to be arranged overlaps the density guarantee area of the arranged element or the boundary area (S43). When overlapping (YES in S43), the processing unit 13 calculates the area of the overlapping region (S44). Subsequently, the processing unit 13 determines, based on the overlapping region, whether or not the area of the density guarantee area in which the dummy pattern can be arranged (final density guarantee area) is equal to or larger than the minimum necessary area (S45). ). As described above, since the dummy pattern is not arranged in the boundary area, when the density guarantee area of the arrangement element to be arranged and the boundary area of the arranged element overlap, no dummy pattern is arranged in the overlap area.

  When the area of the final density guarantee region is not equal to or larger than the minimum necessary area (NO in S45), the user again arranges the target element (S42). On the other hand, when it is more than the minimum required area (YES in S45), the processing unit 13 determines whether or not all the elements to be arranged have been arranged (S46). When the arrangement of all the elements is completed (YES in S46), wiring is then connected based on the arranged elements. A dummy pattern dm is arranged in the empty area of each mask pattern.

  At this time, in the present embodiment, in the element arranging step, the area for arranging the dummy pattern dm that satisfies the minimum reference value of the mask pattern coverage is provided in advance, and the boundary area of each element is arranged. . In other words, at the element placement stage, elements are arranged based on the density guaranteed area for dummy pattern arrangement that satisfies the reference value of the mask pattern coverage, thereby avoiding mask pattern density errors. This eliminates the need for element re-arrangement processing and arrangement reconnection based on the mask pattern density error, thereby greatly reducing the time required for semiconductor element layout.

  In the element layout process, the density guarantee region may be visualized together with the boundary region, or only the coordinate information thereof may be displayed. In the element placement step, the user can place the boundary region so as to ensure a coverage equal to or higher than the minimum reference value by referring to the information of the density guarantee region in addition to the boundary region.

  Subsequently, the element layout process will be described based on a specific example.

[Specific example of element layout]
FIG. 10 is a diagram illustrating a specific example of the element layout. In (A-1) of the figure, the boundary region L1-2 of the element to be arranged overlaps the boundary region L1-1 and L1-2 of the arrangement target element with respect to the boundary region L1-1 of the arranged element. Instead, the density guarantee areas are arranged so as to overlap each other (YES in S42 and S43 in FIG. 9). In this example, the density guarantee areas dg2-1 and dg2-2 of the elements to be arranged overlap with the boundary area L1-1 of the arranged elements. The process for calculating the area of the overlapping region in this case (S44 in FIG. 9) and the process for comparing with the minimum area (S45 in FIG. 9) will be described focusing on the density guarantee region dg2-2 of the element to be arranged.

  (A-2) in FIG. 10 is an enlarged view of the peripheral portion of the density guarantee region dg2-2. In this example, the density guarantee area dg2-2 overlaps the boundary area L1-1 of the arranged elements by 1.5 μm in the vertical direction (YES in S43). For this reason, the area in which the overlapping area with the boundary area L1-1 is excluded from the density guarantee area dg2-2 is an area where the dummy pattern dm can be arranged in the density guarantee area dg2-2, that is, the final density guarantee area. dgx.

  Specifically, the area of the overlapping region between the density guarantee region dg2-2 and the boundary region L1-1 is 15 square um (= 1.5 um × 10 um) (S44). Since the area of the density guarantee area dg2-2 is 35 square um (= 3.5 um × 10 um), the area of the final density guarantee area dgx is calculated as 20 square um (= 35-15). In this example, the area of the final density guarantee region dgx may be calculated as 20 square um (= 2 × 10). In this case, the area of the final density guarantee region dgx exceeds the minimum required area (17 square um) (YES in S45). For this reason, by arranging the dummy pattern dm in the final density guarantee region dgx, a coverage ratio equal to or higher than the minimum reference value is guaranteed.

  On the other hand, in (B-1) of FIG. 10, the boundary region L1-2 of the element to be arranged is similarly arranged with respect to the boundary region L1-1 of the arranged element. (B-2) of FIG. 10 is an enlarged view of a peripheral portion of the density guarantee region dg2-2. In this example, the density guarantee region dg2-2 overlaps the boundary region L1-1 of the arranged elements by 3 μm in the vertical direction. For this reason, the area of the overlapping area between the density guarantee area dg2-2 and the boundary area L1-1 is calculated as 30 square um (= 3 um × 10 um). The area of the final density guarantee region dgx is calculated as 5 square um (= 35-30).

  In this case, the area of the final density guarantee region dgx is less than the minimum required area (17 square um). For this reason, even if the dummy pattern dm is arranged in the final density guarantee region dgx, the coverage of the minimum reference value cannot be obtained (NO in S45). For this reason, rearrangement is performed for the elements to be arranged (S42). This is a rearrangement targeting one element in the placement process. For this reason, an error occurs in the density verification after the arrangement of all the elements is completed, and the man-hour relating to the layout process is greatly reduced compared to the case where the arrangement is reviewed for all the arranged elements.

[Another specific example of element layout]
FIG. 11 is a diagram illustrating another specific example of the element layout. Similarly to the example of FIG. 10, in (A-1) of FIG. 10, the boundary region L1-2 of the element to be arranged is the mutual density guarantee region with respect to the boundary region L1-1 of the arranged element. Are arranged to overlap. However, in this example, the boundary area L1-1 and the boundary area L1-2 overlap each other with their density guarantee areas shifted in the horizontal direction.

  When the density guarantee areas overlap as shown in FIG. 11A-1, the area of the final density guarantee area is calculated by dividing it into a plurality of partial figures, for example. Specifically, as shown in FIG. 5B, the area of the final density guarantee area (brick pattern) is calculated as (m1 × n1) + (m2 × n2). When the area of the dummy pattern dm per unit area is 60%, the area of the dummy pattern dm that can be arranged in the final density guarantee region is {(m1 × n1) + (m2 × n2)} × 0.6. It is calculated as follows. And it is determined whether the calculated area is more than the minimum required area (S45).

  In addition, in the arrangement example of FIG. 11, the density guarantee area of the boundary area of the element is arranged so as to be shifted from the density guarantee area of the arranged boundary area in the long side direction of the boundary area instead of in series. In this case, as in the present embodiment, the area of the density guarantee region is set not to be the minimum coverage reference value but to a coverage that is larger than the minimum reference value within the reference range. Flexible placement processing is performed. This point will be specifically described.

  For example, when the density guarantee area is set corresponding to the minimum coverage ratio reference value, that is, when the area of the density guarantee area is the minimum required area, a new arrangement is made as shown in FIG. The element density guarantee area dg5-1 needs to be arranged so as not to overlap with the boundary area L1-4 of the arranged element. On the other hand, as shown in (A-1), when the density guarantee area is set to a coverage larger than the minimum coverage reference value, the density guarantee area dg2-1 of the element to be newly arranged is the density guarantee area. The boundary region is within a range in which the area of the final density guarantee region (brick pattern portion of 11 (B)) obtained by removing the overlapping region with the boundary region L1-1 of the arranged element from dg2-1 satisfies the minimum required area. It can be arranged overlapping with L1-1.

  As a result, the distance k between the boundary regions is set as shown in (A-1) as compared to the case where the density guarantee region is set corresponding to the minimum coverage reference value as shown in (A-2) of FIG. When the density guarantee area is set to a coverage ratio that is larger than the minimum coverage ratio reference value, the density guarantee area is set to be shorter. Thereby, a plurality of elements can be arranged in a narrower range, and more flexible element arrangement is possible.

  10 and 11, the area of the dummy pattern dm is calculated by multiplying the area of the final density guarantee region by the ratio of the dummy pattern dm that can be arranged per unit area (FIG. 10). 9 S44). However, the area of the dummy pattern dm may be calculated in units of meshes ME divided into predetermined unit areas as shown in FIG. In this case, for example, first, the number of meshes ME in which the dummy patterns dm are arranged is calculated. Then, the area of the dummy pattern dm is calculated by multiplying the number of meshes ME by the area ratio of the dummy pattern dm in the mesh ME. For example, when the dummy pattern dm is arranged in N meshes ME and the area ratio is 40%, the area of the dummy pattern dm is calculated as N × 0.4.

  As described above, the mask pattern generation apparatus 1 according to the present embodiment is arranged for each element around the boundary pattern area (boundary area) that defines the element pattern formation area on the semiconductor substrate and the boundary pattern area. And a library pattern having a density guarantee area for arranging dummy patterns satisfying the minimum coverage standard value of the mask pattern per verification area (density verification area). Then, after the arrangement of the first library pattern, the second library pattern is arranged so that the density guarantee area of the second library pattern does not overlap with the boundary area of the first library pattern.

  As a result, in the element arranging step, the elements to be arranged are arranged with an interval for dummy pattern arrangement ensuring the minimum coverage standard value of the arranged elements and the mask pattern. In the element arrangement process, elements can be arranged so that the minimum coverage standard value is ensured, so that it is possible to avoid an error in density verification after dummy pattern arrangement. Since the mask pattern density reference is ensured at the stage of the element placement process, re-replacement of the element placement and wiring connection based on the mask pattern density error does not occur, and rework is greatly reduced. This greatly improves the efficiency of the layout process of the semiconductor device.

  In the present embodiment, the mask pattern is a mask pattern of the active region in the semiconductor substrate. For some second library patterns, the density guarantee region of the second library pattern and the first library pattern are used. The mask pattern coverage in the region excluding the overlapping region with the boundary region of the boundary is arranged so as to satisfy the coverage minimum reference value. As a result, the minimum reference value of the mask pattern coverage is ensured, and the elements can be arranged in a narrower area range.

  In the present embodiment, the library information further includes minimum area information (minimum required area) at which the coverage is the minimum reference value. In the second library pattern, the area (final density guaranteed area) excluding the overlapping area between the density guaranteed area of the second library pattern and the boundary area of the first library pattern is equal to or larger than the minimum area. Be placed.

  As described above, since the density guarantee region has an area larger than the minimum required area, for example, in a case where the boundary regions of the elements are not arranged in series, more flexible element arrangement is possible. In this case, an area larger than the minimum required area is secured in the density guarantee region. For this reason, in the case where the elements are not arranged in series, the final density guarantee area obtained by removing the overlap area with the boundary area of the arranged element from the density guarantee area of the element to be arranged is within the range where the minimum required area is exceeded. Thus, it is possible to bring the element arrangement positions closer. As a result, it is possible to arrange the elements in a narrower area range, and also to allow more flexible arrangement.

  In this embodiment, the density verification frame is described as a square area, but the density verification frame does not necessarily have to be a square area. In the present embodiment, the density guarantee area is a boundary area in the density verification frame when any one of the vertices of the boundary area overlaps any one of the vertices of the density verification frame (verification area). Set as outside area. As a result, regardless of the shape of the density verification frame, by arranging the elements based on the density guarantee region, the elements can be arranged so that the minimum coverage standard value is guaranteed in the element arrangement process. It becomes possible. Further, the density guarantee area is generated around the vertex of the boundary area, thereby facilitating the adjustment of the distance between the boundary areas.

[Second Embodiment]
In the first embodiment, the pattern for masking the active region in the semiconductor substrate has been described as an example. However, the mask pattern is not limited to this example. The mask pattern may be a mask pattern of a conductive pattern formation region on the semiconductor substrate. In the second embodiment, a polysilicon mask pattern which is a conductive pattern will be described as an example. However, the conductive pattern is not limited to polysilicon, and is effective for other conductive patterns.

  FIG. 12 is a diagram for explaining the coverage of the polysilicon mask pattern. In the figure, as in the first embodiment, two polysilicon resistance elements are arranged. In this example, the mask pattern is a polysilicon mask pattern, and the dummy pattern dm is a polysilicon dummy pattern dmx. Polysilicon is generated in the polysilicon formation regions (for example, p1 and p2) in the boundary regions L1-1 and L1-2 and the formation region of the dummy pattern dmx.

  Similarly, with respect to the polysilicon mask pattern, if the interval between the regions where the polysilicon is formed is wide, a dishing phenomenon occurs in the CMP process. For this reason, the polysilicon dummy pattern dmx is arranged outside the boundary regions L1-1 and L1-2 so that the coverage with the density verification frame Fr as a unit falls within the reference range.

  In FIG. 12A, boundary regions L1-1 and L1-2 are arranged adjacent to each other. As shown in the figure, when the density verification frame Fr corresponds, the density verification frame Fr includes polysilicon formation regions p1 and p2. However, in this example, the coverage of the polysilicon mask pattern within the density verification frame Fr including the formation regions p1 and p2 is less than the minimum reference value. Therefore, as shown in FIG. 12B, a polysilicon dummy pattern dmx is arranged between the boundary regions L1-1 and L1-2. As a result, the polysilicon formation region in the density verification frame Fr is increased, and the coverage of the polysilicon mask pattern in the density verification frame Fr becomes a value equal to or greater than the minimum reference value, thereby succeeding in density verification.

  Therefore, also in the second embodiment, for each element, a density guarantee region (not shown) for arranging the dummy pattern dmx of polysilicon is generated so as to be adjacent to the boundary regions L1-1 and L1-2. Is done. The method of generating the density guarantee area is the same as that in the first embodiment. However, the calculation method of the area in the element arrangement process in the present embodiment is different from that in the first embodiment.

  In the second embodiment, polysilicon is also formed in the boundary regions L1-1 and L1-2. For this reason, in the comparison process with the minimum required area in the element arranging step of FIG. 10 (S45), the area of the dummy pattern dmx in the final density guarantee area (not shown) and the boundary area corresponding to the density verification frame Fr It is determined whether the area obtained by adding the areas of the polysilicon regions (for example, formation regions p1 and p2) is equal to or larger than the minimum required area. That is, the coverage indicated by the added area of the area of the dummy pattern dmx that can be arranged in the density guarantee area and the area of the polysilicon formed in the boundary area in the corresponding density verification frame Fr is greater than or equal to the minimum reference value. The elements are arranged as follows.

  As described above, the pattern generation method according to the present embodiment is also effective for a mask pattern in a conductive pattern formation region on a semiconductor substrate such as polysilicon. In the present embodiment, for some of the library patterns to be arranged, the area excluding the overlapping area between the density guaranteed area of the arrangement target library pattern and the boundary pattern area of the arranged library pattern, and the boundary in the verification area The mask pattern coverage in the total area with the area is arranged so as to satisfy the minimum coverage reference value.

  As a result, even in the process of generating the mask pattern of the conductive pattern, at the stage of the element arrangement process, the elements to be arranged are arranged for the arranged elements and the dummy pattern arrangement for ensuring the mask pattern coverage minimum reference value. By arranging the elements at intervals, the elements can be arranged so that the minimum reference value of the coverage is guaranteed. Therefore, rework from the element placement process based on the mask pattern density error is avoided, and the layout process of the semiconductor device is greatly improved in efficiency. Further, the minimum reference value of the mask pattern coverage is ensured, and the elements can be arranged in a narrower region.

  In the present embodiment, the case where the same elements are arranged next to each other is illustrated. However, it is not limited to this example. For example, the same applies to a case where a polysilicon resistance element and a PMOS element are arranged adjacent to each other.

  Further, in the present embodiment, the density guarantee area generation process and the element arrangement process are stored as a program in a computer-readable recording medium, and the program is read and executed by the computer. Also good. Further, the element placement process may be performed by referring to an element library that stores information on the boundary area and the density guarantee area for each element by the user.

[Third embodiment]
In the third embodiment, in contrast to the first and second embodiments, the element library d1 further includes the minimum necessary information for each element in addition to the coordinate information of the density guarantee region and the minimum necessary area information. Contains area width information. Since the element library d1 has the information on the minimum necessary area width, for example, even when the element to be arranged is arranged between the density guarantee areas in the arranged elements, the coverage more than the minimum reference value is obtained. It is possible to ensure a space for ensuring the dummy pattern arrangement.

  Here, based on the arrangement examples 1 to 3, the case where the element to be arranged is arranged between the density guarantee regions in the arranged elements will be described.

[Arrangement Example 1]
FIG. 13 is a diagram illustrating a case where the elements to be arranged are arranged between the density guarantee regions in the arranged elements. In FIG. 13, the boundary region L12 of the element to be arranged and the boundary region L11 of the arranged element are shown. In this example, the boundary region L12 of the element to be arranged is arranged between the density guaranteed areas dg11-1 and dg11-2 of the arranged elements, and the density guaranteed areas dg11-1 and dg11 of the arranged elements are arranged. -2 is not interfering.

  In the example of FIG. 13, based on the flowchart of FIG. 9, the processing unit 13 uses the density guarantee areas dg12-1 to dg12-4 of the elements to be arranged as the density guarantee areas dg11-1 to dg11 of the arranged elements. -4 or whether it overlaps with the boundary region L11 is determined (S43). Since there is no overlap (NO in S43), the processing unit 13 determines the arrangement position of the element to be arranged and places the next element to be arranged.

However, for example, as shown in FIG. 13, when the density verification frame Fr11 is set, the area of the final density guarantee area in the density verification frame Fr11 is smaller than the minimum required area (NO in S45 of FIG. 9). That is, in the density verification frame Fr11, the area of the dummy pattern that can be arranged in the non-overlapping area between the boundary area L11 of the arranged element and the boundary area L12 of the element to be arranged does not satisfy the minimum reference value of the coverage. Therefore, the area of the active layer based on the dummy pattern formed in the density verification frame Fr11 does not reach the coverage that is not less than the minimum reference value, and the density verification fails. Specifically, in the example of FIG. 13, the area can be arranged in the dummy pattern in the density verification frame FR11, for example, a 4 um ^2, does not satisfy the minimum required area 10um ^2.

  As described above, when the element to be arranged is arranged between the density guarantee areas dg11-1 and dg11-2 in the arranged element, the interval for dummy pattern arrangement is ensured based on the density guarantee area. There are cases where this is difficult. In the example of FIG. 13, for example, after the boundary region L11 of the arranged element is included at the maximum, the density guarantee region dg11-5 that includes the boundary region L12 of the element to be arranged is set to the first, A method of determining the arrangement position in the same manner as in the above embodiment is studied. However, according to this method, the amount of calculation related to the setting process of the density guarantee region dg11-5 corresponding to the arrangement position of the element to be arranged increases, and it becomes difficult to realize interactive element arrangement.

[Example 2]
FIG. 14 is a diagram showing a case where the elements to be arranged are arranged overlappingly inside the density guarantee region in the arranged elements. In FIG. 14, similarly to FIG. 13, the boundary region L12 of the element to be arranged and the boundary region L11 of the arranged element are shown. In this example, the boundary area L12 of the element to be arranged is between the density guarantee areas dg11-1 and dg11-2 of the arranged elements, and inside the one density guarantee area dg11-2 of the arranged elements. Interference with the short side D1. That is, the boundary region L12 of the element to be arranged overlaps with the inner portion of the density guarantee area dg11-2 in the arranged element.

  In the example of FIG. 14, based on the flowchart of FIG. 9, the processing unit 13 determines that the density guarantee areas dg12-1 to dg12-4 of the elements to be arranged are the density guarantee areas dg11-1 to dg11 of the arranged elements. -4 or whether it overlaps with the boundary region L11 is determined (S43). In this case, since they overlap (YES in S43), the processing unit 13 calculates the areas of the overlapping regions (S44), and sets the dummy pattern among the density guarantee regions dg11-1 to dg11-4 of the arranged elements. It is determined whether the area of the area (final density guarantee area) that can be arranged is equal to or larger than the minimum necessary area (S45). In this case, the area of the final density guarantee area in the arranged density guarantee area dg11-2 is equal to or larger than the minimum necessary area (YES in S45). For this reason, the processing unit 13 determines the arrangement position of the element to be arranged, and arranges the next element to be arranged.

  However, for example, when the density verification frame Fr12 is set, the area of the region where the dummy pattern can be arranged in the density verification frame Fr12 is smaller than the minimum required area (NO in S45 of FIG. 9). That is, in the density verification frame Fr12, the area of the dummy pattern that can be arranged in the non-overlapping area between the boundary area L11 of the arranged element and the boundary area L12 of the element to be arranged does not satisfy the minimum reference value of the coverage. Therefore, the area of the active layer based on the dummy pattern formed in the density verification frame Fr12 is less than the minimum reference value and the density verification fails.

[Arrangement Example 3]
FIG. 15 is a diagram showing a case where the elements to be arranged are arranged overlappingly inside a plurality of density guarantee regions. In FIG. 15, the boundary region L14 of the element to be arranged and the boundary region L13 of the arranged element are shown. In this example, the density guarantee areas dg14-2 and dg14-4 of the elements to be arranged interfere with the short sides D2 and D3 inside the density guarantee areas dg13-1 and dg13-2 of the arranged elements. That is, the boundary region L14 of the element to be arranged overlaps with the inner portions of the two density guarantee areas dg13-1 and dg13-2 in the arranged element.

  In the example of FIG. 15, based on the flowchart of FIG. 9, the density guarantee areas dg14-2 and dg14-4 of the elements to be arranged overlap with the density guarantee areas dg13-1 and dg13-2 of the arranged elements. (YES in S43). Therefore, the processing unit 13 calculates the area of the overlapping region (S44). Further, in the density guarantee areas dg13-1 and dg13-2 of the arranged elements, the area of the area where the dummy pattern can be placed (final density guarantee area) is equal to or larger than the minimum necessary area (YES in S45). For this reason, the processing unit 13 determines the arrangement position of the element to be arranged, and arranges the next element to be arranged.

  However, for example, when the density verification frame Fr13 is set, the area of the area where the dummy pattern can be arranged in the density verification frame Fr13 is smaller than the minimum necessary area in the same manner as in the examples of FIGS. NO of S45 in FIG. 9). Therefore, the area of the active layer based on the dummy pattern formed in the density verification frame Fr13 does not reach the coverage that is not less than the minimum reference value, and the density verification fails.

  As shown in FIGS. 14 and 15, even in the case where the elements to be arranged are arranged overlapping only inside the density guarantee area in the arranged elements, the dummy pattern placement interval is also based on the density guarantee area. There are cases where it is difficult to ensure. Also in the examples of FIGS. 14 and 15, for example, after the boundary region of the arranged element is included at the maximum, the density guarantee region that includes the boundary region of the element to be arranged is set to the maximum, A method of determining the arrangement position in the same manner as in the embodiment is studied. However, the amount of calculation related to the density guarantee region setting process according to the arrangement position of the element to be arranged increases, making it difficult to realize interactive element arrangement.

  At this time, for example, a method of expanding the size of the density guarantee area is considered. By expanding the size of the density guarantee region, it is possible to include a larger area in the element to be arranged in the density guarantee region. As a result, density verification errors in a wider range can be detected based on the density guarantee area. However, extending the density guarantee area indicates extending the area of the density verification frame, and is not appropriate.

  In recent years, with the miniaturization of process rules, the variation in the coverage ratio of an acceptable mask pattern is reduced, and the area of the density verification region (density verification frame) tends to be reduced. This is because the mask pattern coverage is calculated by “total pattern area / area of density verification region”. On the other hand, since the size of the element does not change greatly, the size of the density verification region with respect to the size of the element tends to be reduced. For this reason, the distance between the elements tends to be small, and as shown in FIGS. 13 to 15, the elements to be arranged overlap between the density guarantee areas in the arranged elements or inside the density guarantee area. The number of cases that are arranged tends to increase.

  Therefore, in the third embodiment, the element library d1 further includes information on the minimum necessary area width in addition to the coordinate information of the density guarantee area and the information on the minimum necessary area for each element. Then, the arrangement position of the element to be arranged is set based on the minimum necessary area based on the minimum necessary area width in the arranged elements. Thereby, for example, also in the cases as shown in FIGS. 13 to 15, it is possible to ensure a dummy pattern arrangement interval that ensures a coverage equal to or higher than the minimum reference value based on the minimum necessary area width.

  By the way, as shown in FIGS. 13 to 15, when it is difficult to secure an interval for dummy pattern placement that ensures a coverage equal to or higher than the minimum reference value based on the density guarantee region, for example, the boundary between elements to be placed The case where the region or the density guarantee region does not interfere with the short side outside the density guarantee region in the arranged element is shown.

  FIG. 16 is a diagram illustrating a case where the elements to be arranged are arranged overlapping the outer portion of the density guarantee region in the arranged elements. In FIG. 16, the boundary region L12 of the element to be arranged and the boundary region L11 of the arranged element are shown. In this example, the boundary area L12 of the element to be arranged interferes with the short side D4 outside the density guarantee area dg11-1 of the arranged element. That is, the boundary region L12 of the element to be arranged overlaps with the outer portion of the density guaranteed area dg11-1 of the arranged element.

  As described above, when the boundary area L12 of the element to be arranged interferes with the side D4 outside the density guarantee area in the arranged element, the boundary area L11 of the arranged element and the boundary area L12 of the element to be arranged are Indicates that the vertices of are approaching. For this reason, as shown in the first and second embodiments, the arrangement processing of the element to be arranged based on the density guarantee area set around the vertices of the boundary areas L11 and L12 of each element results in the minimum reference value or more. It is possible to secure an interval for arranging the dummy pattern that guarantees the coverage ratio.

  Here, the minimum necessary area width and the minimum necessary area will be described.

[Minimum required area width]
The minimum required area width is obtained by dividing the minimum required area (S45 in FIG. 9) described in the first and second embodiments by the length of the density verification frame in the same direction as the long side direction of the element boundary area. It is the value. Further, the minimum necessary area is set based on the minimum necessary area width. The minimum necessary area is an area adjacent to the long side of the boundary area of the arranged element and having the minimum necessary area width in the short side direction.

[Minimum required area]
FIG. 17 is a diagram illustrating the minimum necessary area. In FIG. 17, the minimum necessary area is an area e1. The minimum necessary area width is the width indicated by the arrow f1. As described above, the minimum required area e1 is adjacent to the long side of the boundary area L15 of the target element, and the minimum required area is calculated by dividing the minimum required area by the length of the density verification frame indicated by the arrow g1. It has a necessary area width f1. For this reason, as shown in the figure, when the dummy pattern dm is arranged on the entire surface of the minimum required area e1, the coverage that is equal to or higher than the minimum reference value is obtained regardless of the position of the density verification frame Fr15. Guaranteed. In other words, when the element to be placed is placed so that it does not overlap with the minimum required area width of the placed element, the coverage that is equal to or higher than the minimum reference value regardless of the position of the density verification frame Is guaranteed.

  In the third embodiment, the placement target element is placed based on the degree of overlap between the minimum required area of the placed element and the boundary area of the placement target element. As a result, even if the boundary area and the density guarantee area of the element to be arranged do not overlap with the short side outside the density guarantee area in the arranged element, in the element arrangement process, the coverage minimum reference value is Elements can be arranged to be guaranteed. This avoids an error occurring in the density verification after the dummy pattern placement.

  Next, details of the minimum required area width setting process will be described based on a flowchart of the density guarantee area generation process.

[Density guarantee area generation processing]
FIG. 18 is a flowchart for explaining processing for generating a density guarantee area in the third embodiment. The processes from steps S21 to S36 in the flowchart of FIG. 18 are the same as those in the first and second embodiments.

  In the flowchart of FIG. 18, when the density guarantee area is generated for all the vertices for the target element (YES in S36), the processing unit 13 continues along the long side of the boundary area of the target element. Then, the minimum necessary area width is set (S37). Specifically, the processing unit 13 sets a value obtained by dividing the minimum necessary area calculated in step S34 by the length in the same direction as the long side of the element boundary region in the density verification frame as the minimum necessary region width. . The calculated value of the minimum necessary area width is stored in the element library d1.

[Specific example of minimum required area]
FIG. 19 is a diagram illustrating a first specific example of the minimum necessary area e2. The element of FIG. 19 is the same as the element of FIG. In this example, for example, the size of the density verification frame Fr15 is 10 um × 10 um, and the minimum reference value of the coverage is 10%. Therefore, the minimum required area corresponding to the area 100um ² density verification frame Fr15 is 10um ^2. 19, region me1 is an area indicating the minimum necessary area 10um ^2. In this case, the minimum necessary region width f2 is the minimum necessary area 10um ^2, the long side in the same direction XX of the boundary region of the device, a value obtained by dividing the length 10um in density verification frame FR15 1um. Therefore, in the example of FIG. 19, the minimum necessary area width f2 is 1 μm.

  FIG. 20 is a diagram illustrating a second specific example of the minimum necessary area e3. Similarly in the example of FIG. 20, the size of the density verification frame Fr16 is 10 um × 10 um, and the minimum reference value of the coverage is 10%. However, in the example of FIG. 20, the active region aE is included in the boundary region L16 where the polysilicon resistance is formed.

Specifically, the boundary region L16, in the region corresponding to the density verification frame FR16, has four active regions aE (ax), the total area of the four active regions aE (ax) is 4 um ^2. Within the boundary region L16, since the active region is included 4 um ^2, the minimum area required in each density security area dg16-1~dg16-4 becomes 6 um ^2. That is, in the example of FIG. 20, the arrangement area of the dummy pattern may be smaller than the example of FIG. In Figure 20, region me2 is an area indicating the minimum necessary area 6 um ^2. In this example, the minimum required area width is 0.6 μm obtained by dividing the minimum required area 6 μm ² by the length 10 μm in the density verification frame Fr16 in the same direction XX as the long side of the boundary region L16. Therefore, in the example of FIG. 20, the minimum necessary region width f3 is 0.6 μm.

[Element Layout Process in Third Embodiment]
FIG. 21 is a flowchart for explaining element layout processing in the third embodiment. In the third embodiment, for each element to be arranged, in addition to the density guarantee area information, the minimum necessary area width is calculated in advance and stored in the element library d1. In the third embodiment, as in the first and second embodiments, the user selects and arranges one element to be arranged (S41). Subsequently, the user selects an element to be arranged next, and arranges the arranged element and the boundary region so as not to overlap each other (S42).

  Next, the processing unit 13 determines whether or not the density guarantee area of the element to be arranged overlaps the density guarantee area of the arranged element or the boundary area (S43). In the case of overlapping (YES in S43), the processing unit 13 in the third embodiment determines whether or not the boundary area of the element to be arranged does not overlap with the short side outside the density guaranteed area of the arranged element. Is determined (S51). In the case of overlapping (YES in S51), the processing unit 13 calculates the area of the overlapping region, similarly to the first and second embodiments (S44). This corresponds to the specific example of FIG. The subsequent steps S45 to S48 are the same as those in the first and second embodiments.

  On the other hand, when the boundary area of the element to be arranged does not overlap with the short side outside the density guarantee area of the arranged element (NO in S51), the processing unit 13 calculates a dummy pattern compensation area (S52). This corresponds to the specific examples of FIGS. The dummy pattern compensation area is an area that compensates for the dummy pattern generation area in the minimum necessary area, which is reduced by approaching the element to be arranged to the minimum necessary area of the arranged element. That is, the dummy pattern compensation area includes the boundary area of the arranged element at the maximum, and further, the boundary area of each element and the minimum necessary in the area of the density verification frame in the case of including the boundary area of the element to be arranged at the maximum. Indicates an area other than the area.

  For example, the long side direction of the boundary region of the arranged elements is the first direction, and the short side direction is the second direction. Specifically, for example, the processing unit 13 calculates the difference value X1 of the length between the density verification frame and the boundary region of the element to be arranged in the first direction. In addition, the processing unit 13 calculates a difference value Y1 of coordinates between the density guaranteed area and the minimum necessary area of the arranged elements in the second direction. The coordinates of the density guaranteed area and the minimum necessary area of the arranged element indicate the maximum value or the minimum value of the coordinates in the second direction. Then, the processing unit 13 calculates the multiplication value of the value X1 and the value Y1 as the area of the dummy pattern compensation region.

  Thus, the area of the dummy pattern filling region is the difference between the lengths of the verification region and the boundary region of the element to be arranged in the first direction, which is the long side direction of the boundary region of the arranged element, and It is calculated based on the multiplication value of the coordinate difference value between the density guaranteed area and the minimum necessary area of the arranged elements in the second direction orthogonal to the first direction. The length of each side of the boundary area and the density verification frame, the position of the density guarantee area and the minimum necessary area are detected in advance. For this reason, the processing unit 13 sets the area of the dummy pattern compensation region on the basis of the previously detected information without newly setting a density guarantee region corresponding to the position of the element to be arranged on the arranged element. Simple calculation is possible.

  Subsequently, the processing unit 13 calculates a dummy pattern reduction area (S53). The dummy pattern reduction area is an area eroded by the approach of the element to be arranged in the minimum necessary area of the arranged element for generating the dummy pattern. That is, the dummy pattern reduction area is an overlapping area between the boundary area of the element to be arranged and the minimum necessary area of the boundary area of the arranged element.

  Similarly, the long side direction of the boundary region of the arranged elements is the first direction, and the short side direction is the second direction. Specifically, the processing unit 13 calculates, for example, the length in the first direction of the boundary region of the element to be arranged as the value X2. Further, the processing unit 13 calculates a length value Y2 in the second direction that overlaps the boundary region of the element to be arranged in the minimum necessary region. Then, the processing unit 13 calculates a multiplication value of the value X2 and the value Y2 as a dummy pattern reduction area. As described above, the area of the dummy pattern reduction area can be simplified by calculating the area where the boundary area of the element to be arranged overlaps with the minimum necessary area without newly setting a density guarantee area for the arranged element. Can be calculated.

  Subsequently, the processing unit 13 determines whether or not the area of the dummy pattern compensation region calculated in step S52 is equal to or larger than the area of the dummy pattern reduction region calculated in step S53 (S54). When the area of the dummy pattern compensation region is equal to or larger than the area of the dummy pattern reduction region (YES in S54), the processing unit 13 stores the coordinates of the dummy pattern compensation region and the dummy pattern reduction region. At this time, the processing unit 13 may bring the element to be arranged closer to the arranged element in a range where the area of the dummy pattern filling area is equal to or larger than the area of the dummy pattern reduction area. Subsequently, the processing unit 13 determines whether or not all the elements to be arranged have been arranged (S46). Other elements are not arranged in the area of the dummy pattern filling region.

  On the other hand, when the area of the dummy pattern compensation region is smaller than the area of the dummy pattern reduction region (NO in S54), the processing unit 13 rearranges the elements to be arranged (S42). Similarly, the processing unit 13 determines whether the density guarantee area of the element to be arranged overlaps with the density guarantee area of the arranged element or the boundary area (S43). The subsequent processing is as described above.

  As described above, according to the processing unit 13 in the third embodiment, it is possible to easily calculate the areas of the dummy pattern compensation region and the dummy pattern reduction region based on information detected in advance. Then, the processing unit 13 can bring the element to be arranged closer to the arranged element while satisfying the condition “dummy pattern filling area ≧ dummy pattern reduction area”. As a result, even when the boundary area of the element to be arranged does not overlap with the short side outside the density guarantee area of the already arranged element, the density guarantee area is newly set according to the element to be arranged. However, it is possible to easily arrange the elements so that the minimum coverage reference value is guaranteed. That is, in the element arrangement process, the elements are arranged so that the minimum coverage reference value is guaranteed easily and at high speed without requiring complicated calculation processing.

[Element Layout Process in Third Embodiment]
FIG. 22 is a second flowchart for explaining the element layout processing in the third embodiment. The flowchart in FIG. 22 is different from the flowchart in FIG. 21 in that the contents of each process are the same, but the order of the processes is different. In the flowchart shown in FIG. 21, the step S44 is performed based on the result of the determination step (S51) as to whether or not the boundary region of the element to be arranged does not overlap with the short side outside the density guaranteed region of the arranged element. -S45 or process of process S52-S55 is performed.

  On the other hand, in the flowchart of FIG. 22, the processing unit 13 performs the processing of steps S44 to S45 and then performs the determination of step S51. Specifically, after the processes of steps S44 to S45, the processing unit 13 determines whether or not the boundary region of the element to be arranged does not overlap with the short side outside the density guaranteed area of the arranged element ( S51). And when it overlaps (YES of S51), the arrangement | positioning process of the next element is performed (S42). On the other hand, when there is no overlap (NO in S51), the processing unit 13 calculates a dummy pattern filling area (S52). Processing subsequent to step S52 is the same as the flowchart in FIG.

  As described above, the processing unit 13 may perform the element arrangement according to any procedure of the flowchart of FIG. 21 and the flowchart of FIG. 22. For example, as shown in the flowchart of FIG. 21, the processing unit 13 firstly, the boundary area of the element to be arranged overlaps the minimum necessary area of the arranged element, and the outside in the density guarantee area of the arranged element. It is determined whether or not it overlaps with the short side (S51). Then, the processing unit 13 performs either the placement process based on the density guarantee area (S44, S45) or the placement process based on the minimum necessary area (S52 to S55) based on the determination result. According to this method, when the boundary area of the element to be arranged overlaps with the minimum necessary area of the arranged element and overlaps with the outer short side in the density guarantee area of the arranged element (NO in S51), the density The placement process (S44, S45) based on the guaranteed area can be omitted.

  Or, for example, as shown in the flowchart of FIG. 22, the processing unit 13 performs the placement process (S44, S45) based on the density guarantee region, and then the boundary region of the placement target element is the position of the placed element. It is determined whether or not it overlaps with the minimum necessary area and does not overlap with the outer short side in the density guaranteed area of the arranged element. And the process part 13 performs the arrangement | positioning process (S52-S55) based on the minimum required area | region based on a determination result.

  Next, a specific example of the layout process in this embodiment will be described. A specific example will be described based on the flowchart of FIG.

[First Specific Example of Layout Process]
FIG. 23 is a diagram for explaining a first specific example of the layout process. In this example, the boundary area L12 of the elements to be arranged does not overlap with the short sides outside the density guarantee areas dg11-1 and dg11-2 of the arranged elements (NO in S51). Therefore, the processing unit 13 calculates the area of the dummy pattern filling area Z1a (S52). In this example, the horizontal direction XX corresponding to the long side direction of the boundary region L11 of the arranged elements is the first direction, and the vertical direction YY corresponding to the short side direction is the second direction.

First, in the horizontal direction (first direction) XX, the processing unit 13 determines a difference value 3 um (X1a, = 10) between the length 10 um of the density verification frame Fr17 and the length 7 um of the boundary region L12 of the element to be arranged. -7) is calculated. Further, the processing unit 13 calculates a difference value 2 um (Y1a) of the maximum coordinate values of the density guarantee areas dg11-1 and dg11-2 and the minimum necessary area e4 in the vertical direction (second direction) YY. Alternatively, the value Y1a is the difference between the added value 8um of the length 7um of the boundary region L11 of the arranged elements and the minimum required region width 1um (f4) and the length 10um of the density verification frame Fr17 in the vertical direction YY. May be calculated. Then, the processing unit 13, a multiplication value 6 um ² and the value X1a (3um) value Y1a (2um), is calculated as the area of the dummy pattern compensation region Z1a.

Subsequently, the processing unit 13 calculates the area of the dummy pattern reduction region Z2a (S53). First, the processing unit 13 calculates the length 7 um (X2a) of the boundary region L12 of the element to be arranged in the horizontal direction (first direction) XX. Further, the processing unit 13 calculates a value 0.6um (Y2a) of the distance that the boundary region L12 of the element to be arranged enters the minimum necessary region e4 in the vertical direction (second direction) YY. Then, the processing unit 13, a multiplication value 4.2Um ² between the value X2a (7 um) and the value Y2a (0.6 um), is calculated as the area of the dummy pattern reducing region Z2a.

In this case, the area 6 um ² dummy pattern compensation region Z1a is, (YES in S54) larger area 4.2Um ² dummy pattern reducing region Z2a. In other words, the area corresponding to the density verification frame Fr17 is outside the minimum necessary area where the dummy pattern can be generated, rather than the area of the dummy pattern generation area Z2a reduced by the entry of the element to be arranged into the minimum necessary area e4. The area of the region Z1a is larger. For this reason, in the arrangement example of FIG. 23, it becomes possible to secure an interval for dummy pattern arrangement that ensures a coverage equal to or greater than the minimum reference value. It should be noted that the boundary areas of other elements are not overlapped in the dummy pattern filling area Z1a.

[Second Specific Example of Layout Process]
FIG. 24 is a diagram for explaining a second specific example of the layout process. Also in the example of FIG. 24, as in the first specific example, the boundary region L12 of the elements to be arranged does not overlap with the short sides outside the density guarantee areas dg11-1 and dg11-2 of the arranged elements. (NO in S51). Therefore, the processing unit 13 calculates the area of the dummy pattern filling area Z1b (S52).

The area of the dummy pattern filling region Z1b is the same as that in the example of FIG. For the horizontal direction (first direction) XX, the processing unit 13 calculates a difference value 3 um (X1b, = 10-7) between the length 10 um of the density verification frame Fr18 and the length 7 um of the boundary region L12 of the element to be arranged. ) Is calculated. Further, the processing unit 13 calculates a difference value 2 um (Y1a) of the maximum coordinate values of the density guarantee areas dg11-1 and dg11-2 and the minimum necessary area e4 in the vertical direction (second direction) YY. Then, by the value X1a (3um) value Y1a (2um) is multiplied, the area 6 um ² dummy pattern compensation region Z1b is calculated.

Subsequently, the processing unit 13 calculates the area of the dummy pattern reduction region Z2b (S53). First, the processing unit 13 calculates the length 7 um (X2a) of the boundary region L12 of the element to be arranged in the horizontal direction (first direction) XX. Further, the processing unit 13 calculates a value 0.9 um (Y2b) of the distance that the boundary region L12 of the element to be arranged enters the minimum necessary region e4 in the vertical direction (second direction) YY. Then, the processing unit 13, a multiplication value 6.3Um ² between the value X2a (7 um) and the value Y2a (0.9um), is calculated as the area of the dummy pattern reducing region Z2b.

In this case, the area 6 um ² dummy pattern compensation region Z1b is, (NO in S54) the dummy pattern reducing region Z2a area 6.3Um ² smaller. That is, the area of the dummy pattern generation area Z2b reduced by the entry of the element to be arranged into the minimum necessary area e4 is an area outside the minimum necessary area where the dummy pattern can be generated in the area corresponding to the density verification frame Fr18. It is larger than the area of Z1b. For this reason, according to the arrangement example of FIG. 24, it is detected in advance that a density verification error occurs. Therefore, the elements to be arranged are rearranged so that the area of the dummy pattern deletion area Z2b due to the entry into the minimum necessary area e4 is within the area of the dummy pattern compensation area Z1b.

  As described above, according to the mask pattern generation method in the present embodiment, the second library pattern is adjacent to the long side of the first boundary pattern region of the first library pattern after the second placement step. The outer short side in the density guarantee region of the first library pattern overlaps with the minimum necessary region for dummy pattern placement having the minimum necessary region width that satisfies the minimum reference value of the mask pattern coverage per verification region in the short side direction. It is determined whether or not they overlap. If there is no overlap, the difference value between the lengths of the verification region and the second boundary pattern region in the first direction, which is the long side direction of the first boundary pattern region, and the first direction orthogonal to the first direction. In the direction of 2, the area of the dummy pattern compensation area is calculated based on the product of the coordinate difference value between the density guarantee area and the minimum necessary area of the first library pattern. Then, the second library pattern is rearranged so that the area of the dummy pattern compensation area is equal to or larger than the area of the dummy pattern reduction area where the second boundary pattern area and the minimum necessary area overlap. In the dummy pattern placement step, a dummy pattern is further placed in the dummy pattern compensation region.

  Alternatively, the mask pattern generation method according to the present embodiment includes a boundary pattern region (boundary region) that defines an element pattern formation region on a semiconductor substrate, and a verification region (density verification region) arranged around the boundary pattern region. And a reference step of library information having a plurality of library patterns each having a density guarantee area for arranging dummy patterns satisfying the minimum coverage standard value of the mask pattern. In addition, the mask pattern generation method includes a first arrangement step of arranging the first library pattern extracted from the library information, and second and third arrangement steps.

  In the second arrangement step, after the first arrangement step, the minimum necessary region width that is adjacent to the long side of the first boundary pattern region of the first library pattern and satisfies the mask pattern coverage minimum reference value per verification region It is determined whether or not a condition that does not overlap with the shortest outer side in the density guarantee region of the first library pattern overlaps with the minimum necessary region for dummy pattern placement having in the short side direction. If the condition is not met, the second library pattern extracted from the library information is arranged without overlapping the density guarantee area of the second library pattern with the boundary pattern area of the first library pattern.

  In the third arrangement step, after the first arrangement step, if the condition is satisfied, the verification region and the second boundary pattern region in the first direction which is the long side direction of the first boundary pattern region The dummy pattern filling area based on the product of the difference value of the length of the coordinate difference value of the density guarantee area and the minimum necessary area of the first library pattern in the second direction orthogonal to the first direction Is calculated. Then, the second library pattern is arranged so that the area of the dummy pattern compensation area is equal to or larger than the area of the dummy pattern reduction area where the second boundary pattern area and the minimum necessary area overlap. Then, in the dummy pattern placement step, dummy patterns are placed in a region outside the boundary pattern region of the first and second library patterns and including the density guarantee region, and a dummy pattern compensation region.

  Thereby, at the stage of the element arrangement process, even in the case where the element to be arranged is arranged between the density guarantee areas in the already arranged elements or inside the density guarantee area, the element to be arranged is Arrangement can be made with an interval for dummy pattern arrangement ensuring the minimum coverage standard value of the arranged elements and the mask pattern. Further, the area of the dummy pattern compensation region can be easily calculated based on information detected in advance without newly setting a density guarantee region in the arranged element. This makes it possible to arrange elements so that the minimum coverage reference value is guaranteed easily and at high speed without requiring complicated calculation processing.

  As described above, according to the mask pattern generation method in the present embodiment, the element placement process ensures that the minimum reference value of the coverage is ensured easily and at high speed without requiring complicated calculation processing. Can be placed. Further, since the elements can be arranged in the element arrangement process so that the minimum coverage reference value is ensured, it is possible to avoid an error in density verification after the dummy pattern arrangement. Since the mask pattern density reference is ensured at the stage of the element placement process, re-replacement of the element placement and wiring connection based on the mask pattern density error does not occur, and rework is greatly reduced. This greatly improves the efficiency of the layout process of the semiconductor device.

  In the present embodiment, the mask pattern is a mask pattern of the active region in the semiconductor substrate. For some second library patterns, the density guarantee region of the second library pattern and the first library pattern are used. The mask pattern coverage in the region excluding the overlapping region with the boundary region of the boundary is arranged so as to satisfy the coverage minimum reference value. As a result, the minimum reference value of the mask pattern coverage is ensured, and the elements can be arranged in a narrower area range.

  In the present embodiment, the mask pattern is a mask pattern in a conductive pattern formation region on a semiconductor substrate, and a part of the second library pattern has a density guarantee region in the second library pattern and a first pattern in the second library pattern. The mask pattern coverage in the total area of the region excluding the overlap region with the boundary pattern region of the library pattern and the boundary pattern formation region in the verification region is arranged so as to satisfy the coverage minimum reference value. As a result, the minimum reference value of the mask pattern coverage is ensured, and the elements can be arranged in a narrower area range.

  Further, in the present embodiment, the minimum width of the minimum necessary region is obtained by verifying the minimum area information in which the coverage is the minimum coverage reference value in the first direction which is the long side direction of the first boundary pattern region. The value divided by the length of the area. As a result, a coverage that is equal to or greater than the minimum reference value is guaranteed regardless of the position of the verification region.

  Further, in the present embodiment, the dummy pattern compensation area includes the first boundary pattern area at the maximum and further includes the second boundary pattern area of the second library pattern at the maximum in the verification area. It is an area other than the boundary pattern areas 1 and 2 and the minimum necessary area.

  As a result, the area of the dummy pattern compensation region can be easily calculated based on information detected in advance without newly setting a density guarantee region for the arranged elements. This makes it possible to arrange elements so that the minimum coverage reference value is guaranteed easily and at high speed without requiring complicated calculation processing.

  The above embodiment is summarized as follows.

(Appendix 1)
A mask pattern generation method for a semiconductor device, comprising:
A boundary pattern region for defining an element pattern formation region on a semiconductor substrate, and a density guarantee region for arranging a dummy pattern that is arranged around the boundary pattern region and satisfies the minimum coverage standard value of the mask pattern per verification region A library information reference step having a plurality of library patterns having
A first placement step of placing a first library pattern extracted from the library information;
After the first arrangement step, the second library pattern extracted from the library information is arranged without overlapping the density guarantee area of the second library pattern with the boundary pattern area of the first library pattern. A second placement step to
A dummy pattern placement step of placing the dummy pattern in a region outside the boundary pattern region of the first and second library patterns and including the density guarantee region;
A method for generating a mask pattern of a semiconductor device.

(Appendix 2)
In Appendix 1,
The mask pattern is a mask pattern of an active region in a semiconductor substrate,
In the second arrangement step, a part of the second library pattern is excluded in an area excluding an overlapping area between the density guarantee area of the second library pattern and the boundary pattern area of the first library pattern. A mask pattern generation method for a semiconductor device, wherein the mask pattern coverage is arranged so as to satisfy the minimum coverage reference value.

(Appendix 3)
In Appendix 1,
The mask pattern is a mask pattern of a conductive pattern formation region on a semiconductor substrate,
In the second arrangement step, a part of the second library pattern is an area excluding an overlapping area between the density guarantee area of the second library pattern and the boundary pattern area of the first library pattern; A mask pattern generation method for a semiconductor device, wherein the mask pattern coverage in a total area of the verification area and the boundary pattern formation area satisfies the minimum coverage reference value.

(Appendix 4)
In Appendix 2 or 3,
The library information further includes a mask pattern generation method for a semiconductor device having minimum area information in which the coverage is the minimum reference value of the coverage.

(Appendix 5)
In any one of supplementary notes 1 to 4,
The boundary pattern area and the verification area are rectangular areas,
The density guarantee region is a semiconductor indicating a region outside the boundary pattern region in the verification region when any one of the vertices of the boundary pattern region overlaps any one of the vertices of the verification region A mask pattern generation method for an apparatus.

(Appendix 6)
A mask pattern generation device for a semiconductor device,
A boundary pattern region for defining an element pattern formation region on a semiconductor substrate, and a density guarantee region for arranging a dummy pattern that is arranged around the boundary pattern region and satisfies the minimum coverage standard value of the mask pattern per verification region Means for referencing library information having a plurality of library patterns having
First placement means for placing a first library pattern extracted from the library information;
After the first arrangement means, the second library pattern extracted from the library information is arranged without overlapping the density guarantee area of the second library pattern with the boundary pattern area of the first library pattern. Second arrangement means for
Dummy pattern placement means for placing the dummy pattern in a region outside the boundary pattern region of the first and second library patterns and including the density guarantee region;
A mask pattern generation device for a semiconductor device having

(Appendix 7)
A computer-readable pattern generation program for causing a computer to execute mask pattern generation processing of a semiconductor device,
The pattern generation process includes:
A boundary pattern region for defining an element pattern formation region on a semiconductor substrate, and a density guarantee region for arranging a dummy pattern that is arranged around the boundary pattern region and satisfies the minimum coverage standard value of the mask pattern per verification region A library information reference step having a plurality of library patterns having
A first placement step of placing a first library pattern extracted from the library information;
After the first arrangement step, the second library pattern extracted from the library information is arranged without overlapping the density guarantee area of the second library pattern with the boundary pattern area of the first library pattern. A second placement step to
A dummy pattern placement step of placing the dummy pattern in a region outside the boundary pattern region of the first and second library patterns and including the density guarantee region;
A mask pattern generation program for a semiconductor device comprising:

(Appendix 8)
In Appendix 2 or 3,
After the second arrangement step, the second library pattern is adjacent to the long side of the first boundary pattern area of the first library pattern, and the mask pattern coverage minimum reference value per verification area is set. The first boundary when overlapping with the minimum necessary area for dummy pattern placement having a minimum necessary area width to satisfy in the short side direction and not overlapping with the outer short side in the density guarantee area of the first library pattern In the first direction which is the long side direction of the pattern region, the difference value between the lengths of the verification region and the second boundary pattern region, and the second direction orthogonal to the first direction, The area of the dummy pattern compensation area based on the product of the coordinate difference value between the density guarantee area of the first library pattern and the minimum necessary area is the second boundary pattern area. A third arrangement step of rearranging the second library patterns to be equal to or greater than the area of the dummy pattern reducing region and the minimum necessary area overlaps with,
In the dummy pattern arranging step, a mask pattern generation method for a semiconductor device, further comprising arranging the dummy pattern in the dummy pattern filling region.

(Appendix 9)
A mask pattern generation method for a semiconductor device, comprising:
A boundary pattern region for defining an element pattern formation region on a semiconductor substrate, and a density guarantee region for arranging a dummy pattern that is arranged around the boundary pattern region and satisfies the minimum coverage standard value of the mask pattern per verification region A library information reference step having a plurality of library patterns having
A first placement step of placing a first library pattern extracted from the library information;
After the first arrangement step, the minimum necessary area width that is adjacent to the long side of the first boundary pattern area of the first library pattern and that satisfies the minimum reference value of the coverage ratio of the mask pattern per verification area is the short side. A second pattern extracted from the library information if it does not satisfy the condition that overlaps with the minimum necessary area for dummy pattern placement in the direction and does not overlap with the outer short side of the density guarantee area of the first library pattern. A second arrangement step of arranging a library pattern without overlapping the density guarantee area of the second library pattern with the boundary pattern area of the first library pattern;
After the first arrangement step, when the condition is satisfied, the length of the verification region and the second boundary pattern region in the first direction which is the long side direction of the first boundary pattern region A dummy pattern filling area based on a product of a difference value of the first library pattern and a coordinate difference value between the minimum guaranteed area and the density guarantee area of the first library pattern in a second direction orthogonal to the first direction. A third arrangement step of arranging the second library pattern such that the area of the second library pattern is equal to or larger than the area of the dummy pattern reduction region where the second boundary pattern region overlaps the minimum necessary region;
A dummy pattern placement step of placing the dummy pattern in a region outside the boundary pattern region of the first and second library patterns and including the density guarantee region, and the dummy pattern compensation region;
A method for generating a mask pattern of a semiconductor device.

(Appendix 10)
In Appendix 9,
The mask pattern is a mask pattern of an active region in a semiconductor substrate,
In the second arrangement step, a part of the second library pattern is excluded in an area excluding an overlapping area between the density guarantee area of the second library pattern and the boundary pattern area of the first library pattern. A mask pattern generation method for a semiconductor device, wherein the mask pattern coverage is arranged so as to satisfy the minimum coverage reference value.

(Appendix 11)
In Appendix 9,
The mask pattern is a mask pattern of a conductive pattern formation region on a semiconductor substrate,
In the second arrangement step, a part of the second library pattern is an area excluding an overlapping area between the density guarantee area of the second library pattern and the boundary pattern area of the first library pattern; A mask pattern generation method for a semiconductor device, wherein the mask pattern coverage in a total area of the verification area and the boundary pattern formation area satisfies the minimum coverage reference value.

(Appendix 12)
In Appendix 8 or 10 or 11,
The minimum width of the minimum required area is the length of the verification area in the first direction, which is the long side direction of the first boundary pattern area, with the minimum area information in which the coverage is the minimum reference value of the coverage. A mask pattern generation method for a semiconductor device, which is a value divided by.

(Appendix 13)
In any one of appendices 8 to 12,
The dummy pattern compensation region includes the first boundary pattern region at the maximum and further includes the second boundary pattern region of the second library pattern at the maximum in the verification region. A mask pattern generation method for a semiconductor device which is an area other than a boundary pattern area and the minimum necessary area.

(Appendix 14)
A mask pattern generation device for a semiconductor device,
A boundary pattern region for defining an element pattern formation region on a semiconductor substrate, and a density guarantee region for arranging a dummy pattern that is arranged around the boundary pattern region and satisfies the minimum coverage standard value of the mask pattern per verification region Means for referencing library information having a plurality of library patterns having
First placement means for placing a first library pattern extracted from the library information;
After the first arrangement means, the shortest side is the minimum necessary region width that is adjacent to the long side of the first boundary pattern region of the first library pattern and satisfies the minimum reference value of the mask pattern coverage per verification region A second pattern extracted from the library information if it does not satisfy the condition that overlaps with the minimum necessary area for dummy pattern placement in the direction and does not overlap with the outer short side of the density guarantee area of the first library pattern. Second arrangement means for arranging a library pattern without overlapping the density guarantee area of the second library pattern with the boundary pattern area of the first library pattern;
The length of the verification region and the second boundary pattern region in the first direction that is the long side direction of the first boundary pattern region when the condition is satisfied after the first arrangement means A dummy pattern filling area based on a product of a difference value of the first library pattern and a coordinate difference value between the minimum guaranteed area and the density guarantee area of the first library pattern in a second direction orthogonal to the first direction. A third placement means for placing the second library pattern such that the area of the second library pattern is equal to or greater than the area of the dummy pattern reduction region where the second boundary pattern region and the minimum necessary region overlap.
Dummy pattern placement means for placing the dummy pattern in a region outside the boundary pattern region of the first and second library patterns and including the density guarantee region, and in the dummy pattern compensation region;
A mask pattern generation device for a semiconductor device having

(Appendix 15)
A computer-readable pattern generation program for causing a computer to execute mask pattern generation processing of a semiconductor device,
The pattern generation process includes:
A boundary pattern region for defining an element pattern formation region on a semiconductor substrate, and a density guarantee region for arranging a dummy pattern that is arranged around the boundary pattern region and satisfies the minimum coverage standard value of the mask pattern per verification region A library information reference step having a plurality of library patterns having
A first placement step of placing a first library pattern extracted from the library information;
After the first arrangement step, the minimum necessary area width that is adjacent to the long side of the first boundary pattern area of the first library pattern and that satisfies the minimum reference value of the coverage ratio of the mask pattern per verification area is the short side. A second pattern extracted from the library information if it does not satisfy the condition that overlaps with the minimum necessary area for dummy pattern placement in the direction and does not overlap with the outer short side of the density guarantee area of the first library pattern. A second arrangement step of arranging a library pattern without overlapping the density guarantee area of the second library pattern with the boundary pattern area of the first library pattern;
After the first arrangement step, when the condition is satisfied, the length of the verification region and the second boundary pattern region in the first direction which is the long side direction of the first boundary pattern region A dummy pattern filling area based on a product of a difference value of the first library pattern and a coordinate difference value between the minimum guaranteed area and the density guarantee area of the first library pattern in a second direction orthogonal to the first direction. A third arrangement step of arranging the second library pattern such that the area of the second library pattern is equal to or larger than the area of the dummy pattern reduction region where the second boundary pattern region overlaps the minimum necessary region;
A dummy pattern placement step of placing the dummy pattern in a region outside the boundary pattern region of the first and second library patterns and including the density guarantee region, and the dummy pattern compensation region;
A mask pattern generation program for a semiconductor device comprising:

1: mask pattern generation device, 11: processor, 12: memory, 13: processing unit, 14: output unit (display device), 15: input unit

Claims (7)

A mask pattern generation method executed by a computer,
The computer is
The boundary pattern region defining the element pattern formation region on the semi-conductor substrate, the density guarantee for the arrangement of the dummy pattern satisfying coverage minimum reference value of the mask pattern per verification region is disposed around the boundary pattern region With reference to library information having a plurality of library patterns having areas ,
Perform first arrangement step of arranging the first library pattern extracted from the previous SL library information,
Before SL after the first positioning step, the second library patterns extracted from the library information, the density security area of the second library pattern without overlap with the boundary pattern region of said first library patterns Performing a second placement step for placement ;
An outer region of the boundary pattern region before Symbol first and second library patterns, to place the dummy pattern in the region including the density security area
Mask pattern generation method of the semi-conductor device according to claim. In claim 1,
The mask pattern is a mask pattern of an active region in a semiconductor substrate,
In the second arrangement step, a part of the second library pattern is excluded in an area excluding an overlapping area between the density guarantee area of the second library pattern and the boundary pattern area of the first library pattern. A mask pattern generation method for a semiconductor device, wherein the mask pattern coverage is arranged so as to satisfy the minimum coverage reference value. In claim 1,
The mask pattern is a mask pattern of a conductive pattern formation region on a semiconductor substrate,
In the second arrangement step, a part of the second library pattern is an area excluding an overlapping area between the density guarantee area of the second library pattern and the boundary pattern area of the first library pattern; A mask pattern generation method for a semiconductor device, wherein the mask pattern coverage in a total area of the verification area and the boundary pattern formation area satisfies the minimum coverage reference value. In claim 2 or 3,
The library information further includes a mask pattern generation method for a semiconductor device having minimum area information in which the coverage is the minimum reference value of the coverage. In any one of Claims 1 thru | or 4,
The boundary pattern area and the verification area are rectangular areas,
The density guarantee region is a semiconductor indicating a region outside the boundary pattern region in the verification region when any one of the vertices of the boundary pattern region overlaps any one of the vertices of the verification region A mask pattern generation method for an apparatus. A mask pattern generation device for a semiconductor device,
A boundary pattern region for defining an element pattern formation region on a semiconductor substrate, and a density guarantee region for arranging a dummy pattern that is arranged around the boundary pattern region and satisfies the minimum coverage standard value of the mask pattern per verification region Means for referencing library information having a plurality of library patterns having
First placement means for placing a first library pattern extracted from the library information;
After the first arrangement means, the second library pattern extracted from the library information is arranged without overlapping the density guarantee area of the second library pattern with the boundary pattern area of the first library pattern. Second arrangement means for
Dummy pattern placement means for placing the dummy pattern in a region outside the boundary pattern region of the first and second library patterns and including the density guarantee region;
A mask pattern generation device for a semiconductor device having A computer-readable pattern generation program for causing a computer to execute mask pattern generation processing of a semiconductor device,
The pattern generation process includes:
A boundary pattern region for defining an element pattern formation region on a semiconductor substrate, and a density guarantee region for arranging a dummy pattern that is arranged around the boundary pattern region and satisfies the minimum coverage standard value of the mask pattern per verification region A library information reference step having a plurality of library patterns having
A first placement step of placing a first library pattern extracted from the library information;
After the first arrangement step, the second library pattern extracted from the library information is arranged without overlapping the density guarantee area of the second library pattern with the boundary pattern area of the first library pattern. A second placement step to
A dummy pattern placement step of placing the dummy pattern in a region outside the boundary pattern region of the first and second library patterns and including the density guarantee region;
A mask pattern generation program for a semiconductor device comprising:

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