JP6193189B2 - NAND background processing controller - Google Patents

Description

  Embodiments described herein relate generally to a NAND background processing control apparatus.

  NAND flash memory becomes fragmented as it is used, and the continuous area that can be used decreases, so NAND backgrounds such as garbage collection are separate from main processing such as writing and reading (usually called NAND processing or NAND access). It is necessary to perform processing.

  In a system configured with an existing real-time OS and NAND flash memory, it may be difficult to guarantee the response time of real-time tasks by executing NAND background processing.

  As a current solution to the above issues, in the eMMC standard, every time a real-time task execution on the HOST side is completed, the HOST side notifies the NAND device side of permission / prohibition of execution of NAND background processing, so that NAND background processing The execution timing is controlled. FIG. 1 is a diagram for explaining NAND background processing in the eMMC standard.

  However, there was a problem that the OS on the NAND device side affected the execution of the real-time task on the HOST side.

Embedded MultiMedia Card (e ・ MMC) e ・ MMC / Card Product Standard, High Capacity, including Reliable Write, Boot, Sleep Modes, Dual DataRate, Multiple Partitions Supports and Security Enhancement (MMCA, 4.4) JESD84-A44 MARCH 2009 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION

JP 2006-172494 A

  The problem to be solved by the present invention is to provide a NAND background processing control apparatus capable of proceeding NAND background processing by making maximum use of a gap time during which a real-time task does not access a NAND device.

  The NAND background processing control apparatus according to the embodiment includes a host device that has a real-time OS, periodically executes a real-time task, and is configured to be communicable with the host device, and has a NAND flash memory and a device-side OS. The memory device side OS sends information on the estimated execution time required for NAND background processing for garbage collection and the number of garbage collection target blocks to the OS on the host device side, while the host device side Since the OS does not affect the execution of the real-time task, the execution start time and the execution time of the NAND background process are transmitted to the memory device-side OS, and the memory device-side OS transmits the real-time task to the memory device In the gap time when the side is not accessed Te, the execution start enabled time, the only feasible time period for executing the NAND background processing.

It is a figure explaining the NAND background process in eMMC specification. It is a figure explaining the influence with respect to the real-time task by the presence or absence of NAND background processing. It is a figure explaining the NAND background process in this embodiment. 1 is a block diagram showing a schematic configuration of a NAND background processing control apparatus according to a first embodiment of the present invention. It is a flowchart which shows the flow of control of the NAND background process in the NAND background process control apparatus which concerns on 1st Embodiment. It is a figure explaining NAND background processing only for the executable time. It is a flowchart which shows the main flow of control of the NAND background process in the NAND background process control apparatus which concerns on 2nd Embodiment.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same portions are denoted by the same reference numerals, and redundant description is omitted.

  First, main terms used in the present embodiment will be described.

  “Real-time task” refers to a task whose processing must be completed by the end time (deadline). It starts at the scheduled start time and starts running immediately.

  “NAND processing” refers to main processing for writing / reading to / from a NAND device performed in response to a command from the HOST side, and “NAND background processing”.

  “NAND background processing” refers to processing for NAND block management that is performed separately from the main processing for the NAND device in response to a request from the HOST side. In the present embodiment, “garbage collection (GC)”, which will be described later, corresponds, and almost no involvement by the user is required. Since it is not the main process, it is required to have little influence on the real-time task executed on the HOST side. The NAND background processing is executed by switching tasks separately from the main processing requested from the HOST side. FIG. 2 is a diagram for explaining the influence on the real-time task due to the presence or absence of NAND background processing. In FIG. 2, a cycle A shows a situation without NAND background processing, a cycle B shows an example of NAND background processing by a conventional method, and a cycle C shows an example of NAND background processing according to the present embodiment described later. ing.

  “Garbage collection (GC)” refers to NAND background processing in the present embodiment. In writing to the NAND flash memory, it is necessary to erase the NAND flash memory before writing. In the NAND flash memory, the erasure unit is a block (for example, 512 KB) unit. Therefore, if a new erasable block (free block) that can be written cannot be secured, writing becomes impossible. Therefore, the valid data of the block containing invalid data is collected and rewritten to a free block to move the valid data, and the block to which the valid data is moved is erased as a block containing only invalid data. Garbage collection that generates free blocks.

  “Polling” refers to periodic inquiries.

  The “eMMC standard” is one of the standards for external storage devices for embedded devices that use flash memory. JEDEC (Joint Electron Device Engineering Council), an industry group that standardizes standards in the field of semiconductor components, is a standard for memory cards, combining NAND flash memory and control circuits in one package. It is connected to the outside via the same interface as MMC (multimedia card, the predecessor of SD card)

(First embodiment)
In this embodiment, from the OS on the NAND device side that is a memory device, information on the estimated execution time required for NAND background processing and the number of blocks to be garbage collected is sent to the OS on the HOST side that is the host device. The OS sends the execution start time and execution time to the NAND device-side OS so that the real-time task execution is not affected, and the NAND device-side OS executes in the gap time when the real-time task does not access the NAND device side. Execute NAND background processing for the executable time at the startable time. FIG. 3 is a diagram for explaining NAND background processing in the present embodiment. As shown in FIG. 3, in this embodiment, the NAND background process is executed by maximizing the “gap time” that the real-time task does not access the NAND device side.

  FIG. 4 is a block diagram showing a schematic configuration of the NAND background processing control apparatus according to the first embodiment of the present invention. This apparatus is realized using a general-purpose computer (for example, a personal computer (PC) or the like) and software operating on the computer. The computer includes an engineering workstation (EWS) suitable for CAD (Computer Aided Design) and CAE (Computer Aided Engineering). In this embodiment, in such a computer, the OS on the NAND device side sends information on the estimated execution time required for NAND background processing and the number of blocks to be garbage collected to the OS on the HOST side, while the OS on the HOST side is a real-time task. Since it does not affect execution, it can also be implemented as a program that transmits the execution start time and execution time of NAND background processing to the NAND device OS.

  As shown in FIG. 4, the NAND background processing control apparatus 1 according to the present embodiment includes a host device (hereinafter referred to as HOST side) 10 that periodically executes a real-time task, and a memory device including a NAND flash memory. (Hereinafter referred to as the NAND device side) 20, and the HOST side 10 and the NAND device side 20 are configured to be communicable. The NAND device side 20 executes main processing and NAND background processing serially, and these two processes are performed by switching execution tasks.

  The HOST side 10 includes a HOST side real-time OS 11. The HOST-side real-time OS 11 includes a real-time scheduler 111 that performs real-time task execution management, a task switching request receiving unit 112, and a first data holding unit 113.

  The task switching request receiving unit 112 receives a task switching request signal from the NAND device side 20 regarding switching of execution tasks on the NAND device side 20. The first data holding unit 113 does not affect the execution of the real-time task. The “execution startable time” of the NAND background processing and the “execution time that does not hinder the execution of the NAND background processing” It holds information on “possible time”.

  The NAND device side 20 includes a NAND device side OS 21. The NAND device-side OS 21 includes a block management unit 211, a task switching function unit 212, a read / write unit 213, a task switching request transmission unit 214, and a second data holding unit 215.

  The block management unit 211 can manage the block status on the NAND device side 20 and set a calculation rule (for example, a coefficient) for calculating “predicted execution time” required for garbage collection.

  The task switching function unit 212 controls switching between the main processing task and the NAND background processing task.

  The Read / Write unit 213 receives a command from the HOST side real-time OS 11 and controls writing to and reading from the NAND device.

  The task switching request transmission unit 214 transmits a task switching request signal to the HOST side 10 in order to ask whether or not execution tasks can be switched in the NAND device.

  The second data holding unit 215 holds information on the “garbage collection target number of blocks” and “predicted execution time” that are to be garbage collected.

  Next, a control flow of NAND background processing in the NAND background processing control device 1 configured as described above will be described.

  FIG. 5 is a flowchart showing a flow of control of NAND background processing in the NAND background processing control apparatus 1 according to the first embodiment.

  First, the NAND device side 20 transmits a task switching request from the main processing task to the NAND background processing task to the HOST side 10 (step S501). As a trigger for sending a task switching request, for example, a task switching permission notification is sent from the HOST side OS 11 to the NAND device side OS 21 by causing the current number of blocks to be garbage collected to correspond to a comparison result with a predetermined threshold. It may be triggered by what has been done. When transmitting a task switching request, the estimated execution time required for garbage collection calculated based on the current number of garbage collection target blocks is used as an argument.

  Next, the HOST side 10 receives a task switching request from the main processing task to the NAND background processing task using the predicted execution time as an argument (step S502).

  Next, the HOST side 10 calculates the execution start time of NAND background processing by taking into consideration the execution status of the real-time task by the real-time scheduler that manages the execution of the real-time task (step S503).

  Next, the HOST side 10 calculates an executable time that can be spent on NAND background processing on the NAND device side 20 (step S504).

  Subsequently, the HOST side 10 determines whether or not the predicted execution time is shorter than the executable time (step S505).

  Next, if the predicted execution time is shorter than the executable time (Yes in step S505), the HOST side 10 sets the predicted execution time to the time t at which the NAND background processing can actually be executed (step S506). The process proceeds to step S508. Here, the time t that may be executed is preferably determined in consideration of, for example, a free time from the current time until the next real-time task is activated.

  On the other hand, if the predicted execution time is not shorter than the executable time (No in step S505), the HOST side 10 sets the executable time as the time t at which the NAND background processing may actually be executed (step S507). .

Next, on the HOST side 10, a response to the task switching request from the NAND device side is transmitted to the NAND device side 20 with the execution startable time and the time t when the NAND background processing can actually be executed as arguments. S508).
Next, the NAND device side 20 receives a response from the HOST side 10 to the task switching request with the execution startable time and the time t at which the NAND background processing can actually be executed as arguments (step S509).

  Next, on the NAND device side 20, task switching is executed, and the NAND background processing task is executed for the executable time at the execution startable time (step S510), and then the control of the NAND background processing is ended. FIG. 6 is a diagram for explaining NAND background processing for the executable time.

  As described above, according to the present embodiment, NAND background processing can be smoothly executed without affecting the real-time task on the HOST side 10.

(Second Embodiment)
Next, a second embodiment will be described. The schematic configuration of the NAND background processing control apparatus according to the second embodiment is basically the same as the schematic configuration of the NAND background processing control apparatus according to the first embodiment. In the second embodiment, the block management unit 211 of the NAND device-side OS 21 sets a threshold value that reflects the importance (urgent level) of NAND background processing. The threshold value corresponds to the number of garbage collection target blocks. For example, it is preferable to set a two-level threshold value, that is, level 1 and level 2 which is more important (urgency level) than level 1.

  When the NAND background processing control device 1 is activated, the host-side real-time OS 11 transmits information such as a real-time task activation period, a deadline, and an average time until NAND access occurs to the NAND device-side OS 21. The real-time task activation cycle is information that a real-time task is activated every 50 msec, for example. The deadline is information indicating that the NAND background processing needs to be terminated within 30 msec after the real-time task is activated, for example. The average time until the NAND access occurs is, for example, information in a case where a prediction can be made in advance when a NAND access occurs about 20 msec after the real-time task is activated.

  The NAND device-side OS 21 calculates a two-level threshold for the number of blocks subject to garbage collection based on information received from the HOST side 10 such as the real-time task start cycle, deadline, and average time until NAND access occurs. The NAND device-side OS 21 is, for example, a system in which a real-time task is executed in very small increments depending on whether the real-time task is executed in a somewhat relaxed cycle or in a very small cycle. The number of blocks to be garbage collected at the threshold level 1 is set to a small value to reduce the number of blocks to be processed by one task switching request, and NAND background processing is performed in small steps in accordance with the execution of the real-time task. On the other hand, in a system in which a real-time task is executed at a somewhat relaxed period, the number of garbage collection target blocks with a threshold level of 1 is set to be large, and the number of blocks processed in one task switching request is increased.

  After setting the two-level threshold value, the NAND device-side OS 21 transmits a response indicating that the threshold value has been set to the HOST-side OS 11.

  When the current garbage collection target block count exceeds the threshold level 2, the NAND device-side OS 21 sends an execution request for NAND background processing to the HOST-side OS 11 with the predicted execution time and the threshold level 2 as arguments. .

  In the real-time mode, the HOST-side OS 11 periodically starts a real-time task, but the HOST-side host OS 11 that has received an execution request for the NAND background process with the threshold level 2 as an argument is the urgency of the NAND background process. Therefore, the real-time mode is immediately paused to deviate from the mode, and the NAND device side OS 21 is allowed to execute NAND background processing. After the NAND background processing is completed, the HOST side host OS 11 returns to the real time task mode again, and periodically starts and executes the real time task.

  FIG. 7 is a flowchart showing a main flow of control of NAND background processing in the NAND background processing control apparatus 1 according to the second embodiment. In the example shown in FIG. 7, a case where the threshold level is 1 or more and the threshold level 2 or less is shown.

  First, at the time of system startup of the NAND background processing control device 1, the HOST-side real-time OS 11 transmits information such as a real-time task start cycle, a deadline, and an average time until NAND access occurs to the NAND device-side OS 21. Based on the received information, the NAND device-side OS 21 calculates a two-level threshold for the number of garbage collection target blocks, and transmits a response.

  The HOST-side real-time OS 11 starts a real-time task, and when the real-time task ends, the HOST-side real-time OS 11 transmits a NAND background process execution permission to the NAND device-side OS 21.

  When receiving the NAND background process execution permission, the NAND device-side OS 21 determines whether or not the current number of garbage collection target blocks is greater than the threshold level 1 (step S701).

  If the number of garbage collection target blocks is larger than the threshold level 1 (Yes in step S701), the NAND device side 20 calculates the predicted execution time (step S702). The calculation of the predicted execution time is, for example, calculated from the number of garbage collection target blocks if the threshold level is 2 or less, and calculated from the number of garbage collection blocks set to the threshold level 1 if the threshold level is 1 or more and 2 or less. Either of these may be used.

  On the other hand, if the number of garbage collection target blocks is not greater than the threshold level 1 (No in step S701), the process returns to step S701 because NAND background processing is not necessary.

  Next, the NAND device side 20 transmits a task switching request from the main processing task to the NAND background processing task to the HOST side 10 (step S703). When transmitting a task switching request, the predicted execution time calculated in step S702 is used as an argument.

  Next, the HOST side 10 receives a task switching request from the main processing task to the NAND background processing task using the predicted execution time as an argument (step S704).

  Next, the HOST side 10 calculates the execution start time of NAND background processing by taking into consideration the execution status of the real-time task by the real-time scheduler that manages the execution of the real-time task (step S705).

  Next, the HOST side 10 calculates the executable time that can be spent on the NAND background processing on the NAND device side 20 (step S706).

  Subsequently, the HOST side 10 determines whether or not the predicted execution time is shorter than the executable time (step S707).

  Next, if the predicted execution time is shorter than the executable time (Yes in step S707), the HOST side 10 sets a time t at which the NAND background processing may actually be executed as the predicted execution time (step S708). The process proceeds to step S710.

  On the other hand, if the predicted execution time is not shorter than the executable time (No in step S707), the HOST side 10 sets the time t at which the NAND background processing can actually be executed as the executable time (step S709). .

Next, on the HOST side 10, a response to the task switching request from the NAND device side 20 is transmitted to the NAND device side 20 using the execution startable time and the time t when the NAND background processing can actually be executed as arguments. Step S710).
Next, the NAND device side 20 receives a response from the HOST side 10 to the task switching request with the execution startable time and the time t when the NAND background processing can actually be executed as arguments (step S711).

  Next, on the NAND device side 20, task switching is executed, a NAND background processing task is executed (step S712), and the control of the NAND background processing is ended.

  As described above, in the example illustrated in FIG. 6, the case where the threshold level is 1 or more and the threshold level 2 or less is described. However, when the threshold level 2 is also exceeded, It is preferable to handle as follows.

(1) Carry out garbage collection processing on all garbage collection target blocks, and calculate the estimated execution time based on the number of garbage collection target blocks.
(2) As a response to the task switching request notification received from the NAND device-side OS 21, the HOST-side OS 11 can pass the time t ₁ that may deviate from the real-time task mode as an argument, and pass this time t ₁ If, calculates the predicted execution time as treating the garbage collection object block within the range that can be processed in time t _1.

  According to the second embodiment, NAND background processing according to the degree of urgency reflecting the shortage of free blocks can be controlled.

(Third embodiment)
Next, a third embodiment will be described. The schematic configuration of the NAND background processing control apparatus according to the third embodiment is basically the same as the schematic configuration of the NAND background processing control apparatus 1 according to the second embodiment. In the third embodiment, the NAND device-side OS 21 divides and executes garbage collection according to the length of the executable time presented from the HOST-side OS 11. For example, NAND background processing is performed separately for each number of garbage collection target blocks set to threshold level 1.

  According to the third embodiment, the response delay to the HOST side 10 can be minimized.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1 ... NAND background processing control device 10 ... HOST side (host device)
11 ... HOST side real-time OS
111 ... Real-time scheduler 112 ... Task switching request receiving unit 113 ... First data holding unit 20 ... NAND device side (memory device)
21 ... NAND device side OS
211: Block management unit 212: Task switching function unit 213: Read / Write unit 214: Task switching request transmission unit 215: Second data holding unit

Claims (15)

A host device having a real-time OS and periodically executing a real-time task; and a memory device configured to be communicable with the host device and having a NAND flash memory and a device-side OS,
From the OS on the memory device side, while sending the information of the estimated execution time and the number of garbage collection target blocks required for NAND background processing for garbage collection to the OS on the host device side,
The OS on the host device side does not affect real-time task execution, and sends the execution start time and execution time of the NAND background process to the memory device side OS,
The memory device-side OS is a NAND background processing control device that executes the NAND background processing for the executable time at the execution startable time in a gap time during which a real-time task does not access the memory device. A host device having a real-time OS and periodically executing a real-time task; and a memory device configured to be communicable with the host device and having a NAND flash memory and a device-side OS,
The host device side real-time OS includes a task switching request receiving unit that receives a task switching request signal between a NAND background processing task and a main processing task that performs garbage collection on the memory device side, and the NAND A first data holding unit that holds information on an execution start time of a background process and an executable time that is a time that does not interfere with a real-time task even if the NAND background process is executed;
The OS on the memory device side manages the block status on the memory device side, and can calculate a predicted execution time required for the NAND background processing, the NAND background processing task, and the main processing task A task switching request transmission unit that transmits a task switching request signal to the host device side, and stores information on the number of blocks subject to garbage collection in the NAND background processing and the estimated execution time required for the NAND background processing. 2 data holding unit,
Prepared,
From the OS on the memory device side, the information on the predicted execution time and the number of blocks to be garbage collected is sent to the OS on the host device side, while the OS on the host device side does not affect real-time task execution. Send the execution startable time and executable time to the memory device side OS,
The memory device-side OS is a NAND background processing control device that executes the NAND background processing for the executable time at the execution startable time in a gap time during which a real-time task does not access the memory device.   The NAND background processing control device according to claim 2, wherein the block management unit can set a calculation rule for calculating the predicted execution time.   The transmission of the task switching request from the memory device side to the host device side is triggered by the current number of the garbage collection target blocks depending on a comparison result with a predetermined value. NAND background processing controller. The transmission from the memory device side of the task switching request to the host device side, claim 2 or claim that triggered said memory device side OS to the task switching permission notification from the host device side OS is sent Item 4. The NAND background processing control device according to Item 3 .   6. The NAND back according to claim 2, wherein when the task switching request is transmitted, an estimated execution time required for garbage collection calculated based on the current number of blocks to be garbage collected is used as an argument. Ground processing control device. On the host device side, if the predicted execution time is smaller than the executable time, the predicted execution time is set to a time t at which the NAND background process may actually be executed,
7. The executable time according to claim 1, wherein the executable time is set to a time t at which the NAND background processing may actually be executed if the predicted execution time is not smaller than the executable time. The NAND background processing control device described.   8. The NAND background processing control apparatus according to claim 7, wherein the time t is determined in consideration of a free time from the current time until the next real-time task is activated. A host device having a real-time OS and periodically executing a real-time task; and a memory device configured to be communicable with the host device and having a NAND flash memory and a device-side OS,
The OS memory device side, the threshold level 1 indicating the urgency of the NAND background processing for garbage collection, and set more two-stage threshold high threshold level 2 urgency,
When the number of garbage collection target blocks is threshold level 1 or more and threshold level 2 or less,
The OS on the memory device side sends the information on the estimated execution time and the number of blocks subject to garbage collection required for the NAND background processing to the OS on the host device side, while the OS on the host device side affects the real-time task execution. Send the execution start time and execution time to the memory device side OS so as not to reach,
The OS on the memory device side is a NAND background processing control device that executes NAND background processing for the executable time at the execution startable time in a gap time during which a real-time task does not access the memory device. The period of the real-time task to reduce the number of blocks to be processed by the task switching request once set smaller the number of garbage collection object block to be set to the threshold level 1 is smaller than a predetermined value,
Billing cycle before cut real-time task to increase the number of blocks to be processed by the task switching request of one degree and large set the number of garbage collection object block to be set to the threshold level 1 is larger than a predetermined value Item 10. The NAND background processing control device according to Item 9. If the number of blocks subject to garbage collection exceeds the threshold level 2, the real-time mode is immediately suspended to deviate from the mode, and the memory device OS is allowed to execute the NAND background processing. ,
10. The NAND background processing control apparatus according to claim 9, wherein after completion of the NAND background processing, the host device-side OS returns to the real-time task mode again and periodically starts and executes the real-time task. When the number of garbage collection target blocks exceeds the threshold level 2, the calculation of the predicted execution time on the memory device side is as follows:
(1) Carry out garbage collection on all garbage collection target blocks, and calculate based on the number of garbage collection target blocks.
(2) A time t ₁ that may deviate from the real-time task mode is received as an argument from the OS on the host device side, and is calculated based on the number of garbage collection target blocks within a range that can be processed within the time t ₁ .
The NAND background processing control device according to any one of claims 9 to 11, according to any one of the above. The NAND according to any one of claims 9 to 12 , wherein the memory device-side OS executes garbage collection in a divided manner according to the length of the executable time presented from the host device-side OS. Background processing controller. The NAND background processing control device according to claim 13 , wherein the NAND background processing is divided and executed for each number of garbage collection target blocks set to the threshold level 1. At the time of system startup, the host device side real-time OS provides the memory device side OS with a real-time task start cycle, a deadline indicating the time required to finish the NAND background processing after the real-time task start, real-time Send information on the average time from task activation to the occurrence of access to the memory device,
The memory device side OS, based on these information, NAND background processing control apparatus according to any one of claims 9 to 14 to calculate a two-level threshold of the garbage collection object blocks.

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