JP6177141B2 - Log likelihood ratio calculation device, log likelihood ratio calculation method, and log likelihood ratio calculation program - Google Patents

Log likelihood ratio calculation device, log likelihood ratio calculation method, and log likelihood ratio calculation program Download PDF

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JP6177141B2
JP6177141B2 JP2014002493A JP2014002493A JP6177141B2 JP 6177141 B2 JP6177141 B2 JP 6177141B2 JP 2014002493 A JP2014002493 A JP 2014002493A JP 2014002493 A JP2014002493 A JP 2014002493A JP 6177141 B2 JP6177141 B2 JP 6177141B2
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努 朝比奈
努 朝比奈
大介 新保
大介 新保
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Mitsubishi Electric Corp
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本発明は、誤り訂正符号化されたビット列が多値変調方式によって変調されて送信された信号が入力され、この信号からビット対数尤度比（Ｌｏｇ−Ｌｉｋｅｌｉｈｏｏｄ Ｒａｔｉｏ：ＬＬＲ）を算出する対数尤度比算出装置（以下「ＬＬＲ算出装置」とも言う。）、対数尤度比算出方法（以下「ＬＬＲ算出方法」とも言う。）、及び対数尤度比算出用プログラム（以下「ＬＬＲ算出用プログラム」とも言う。）に関するものである。   In the present invention, a logarithmic likelihood for calculating a bit log likelihood ratio (LLR) from a signal obtained by inputting a bit string that has been subjected to error correction coding and modulated by a multi-level modulation method is input. Ratio calculation device (hereinafter also referred to as “LLR calculation device”), log likelihood ratio calculation method (hereinafter also referred to as “LLR calculation method”), and log likelihood ratio calculation program (hereinafter referred to as “LLR calculation program”). Say.)

通信システムにおいては、送信装置側で情報ビットを符号化し、受信装置側で符号化情報ビットを復号することで、伝送路から受けるノイズなどによって発生する誤りの訂正を行う。送信装置側で行う符号化では、畳み込み符号（Ｃｏｎｖｏｌｕｔｉｏｎａｌ ｃｏｄｅ）、ターボ符号（Ｔｕｒｂｏ ｃｏｄｅ）、低密度パリティ検査（Ｌｏｗ−Ｄｅｎｓｉｔｙ Ｐａｒｉｔｙ−Ｃｈｅｃｋ：ＬＤＰＣ）符号などが用いられる。一般に、受信装置側で誤り訂正符号の復号を行う場合には、軟判定情報を用いた復号を行うことで、硬判定情報を用いた復号を行う場合よりも、ビット誤り率を改善することができる。軟判定情報は、送信ビットの信頼度を表すビット対数尤度比（ビットＬＬＲ）である。   In a communication system, an information bit is encoded on the transmission device side and an encoded information bit is decoded on the reception device side, thereby correcting an error caused by noise received from the transmission path. In the encoding performed on the transmission apparatus side, a convolutional code, a turbo code, a low-density parity-check (LDPC) code, or the like is used. In general, when decoding an error correction code on the receiving device side, the bit error rate can be improved by performing decoding using soft decision information as compared with decoding using hard decision information. it can. The soft decision information is a bit log likelihood ratio (bit LLR) representing the reliability of the transmission bit.

通信システムで用いられる変調方式が位相偏移変調（Ｐｈａｓｅ Ｓｈｉｆｔ Ｋｅｙｉｎｇ：ＰＳＫ）、振幅位相変調（Ａｍｐｌｉｔｕｄｅ Ｐｈａｓｅ Ｓｈｉｆｔ Ｋｅｙｉｎｇ：ＡＰＳＫ）、又は直交振幅変調（Ｑｕａｄｒａｔｕｒｅ Ａｍｐｌｉｔｕｄｅ Ｍｏｄｕｌａｔｉｏｎ：ＱＡＭ）などの多値変調方式である場合には、１つの送信シンボル点は複数のビットで構成される。１つの送信シンボル点を構成する複数のビットの内のｋビット目（ｋは正の整数）のビットのビットＬＬＲをＬｋと表記すると、ビットＬＬＲ（Ｌｋ）は次式（１）により算出できる。

Figure 0006177141
The modulation scheme used in the communication system is multi-level modulation such as phase shift keying (PSK), amplitude phase modulation (Amplitude Phase Shift Keying: APSK), or quadrature amplitude modulation (QAM). In some cases, one transmission symbol point is composed of a plurality of bits. When the bit LLR of the k-th bit (k is a positive integer) among a plurality of bits constituting one transmission symbol point is expressed as L k , the bit LLR (L k ) is calculated by the following equation (1). it can.
Figure 0006177141

式（１）において、ｒは、実軸（ｉｎ−ｐｈａｓｅ軸：Ｉ軸）と虚軸（ｑｕａｄｒａｔｕｒｅ軸：Ｑ軸）とを有する複素平面である位相平面上において受信信号を示す受信信号点の位置ベクトルを示し、ｓｉは、位相平面上における送信シンボル点の位置ベクトルを示す。また、Ｃｋ，０は、１つの送信シンボル点を構成する複数のビットの内のｋビット目のビットが０である送信シンボル点全体の集合（送信シンボル点群）を示し、Ｃｋ，１は、１つの送信シンボル点を構成する複数のビットの内のｋビット目のビットが１である送信シンボル点全体の集合（送信シンボル点群）を示す。また、σは、通信路のガウス雑音の標準偏差を示す。 In Expression (1), r is the position of a received signal point indicating a received signal on a phase plane that is a complex plane having a real axis (in-phase axis: I axis) and an imaginary axis (quadture axis: Q axis). S i indicates a position vector of a transmission symbol point on the phase plane. C k, 0 represents a set of all transmission symbol points (transmission symbol point group) in which the k-th bit among a plurality of bits constituting one transmission symbol point is 0, and C k, 1 Indicates a set (transmission symbol point group) of all transmission symbol points in which the k-th bit is 1 among a plurality of bits constituting one transmission symbol point. Further, σ represents the standard deviation of Gaussian noise on the communication path.

式（１）においてビットＬＬＲ（Ｌｋ）を算出するためには、式（１）の右辺の第１項の指数関数（ｅｘｐ）の値及び第２項の指数関数（ｅｘｐ）の値をそれぞれ計算し、第１項の指数関数の計算値の総和（集合Ｃｋ，０に属する送信シンボル点ｓｉについての計算値の総和）及び第２項の指数関数の計算値の総和（集合Ｃｋ，１に属する送信シンボル点ｓｉについての計算値の総和）のそれぞれに対する対数関数（ｌｎ）の値を計算しなければならない。このため、式（１）によるビットＬＬＲ（Ｌｋ）の算出には、膨大な演算量の計算処理が必要であり、このような計算処理を実行する回路をＬＬＲ算出装置に実装することは、回路規模の観点から現実的ではない。 In order to calculate the bit LLR (L k ) in the expression (1), the value of the exponential function (exp) of the first term and the value of the exponential function (exp) of the second term on the right side of the expression (1) are respectively calculated. And the sum of the calculated values of the exponential function of the first term (the sum of the calculated values of the transmission symbol points s i belonging to the set C k, 0 ) and the sum of the calculated values of the exponential function of the second term (set C k , 1 must be calculated for the logarithmic function (ln) for each of the transmission symbol points s i belonging to 1 , the sum of the calculated values. For this reason, calculation of the bit LLR (L k ) according to equation (1) requires a huge amount of calculation processing, and mounting a circuit for executing such calculation processing in the LLR calculation device It is not realistic from the viewpoint of circuit scale.

例えば、非特許文献１においては、式（１）の右辺の第１項の指数関数の計算値の内の最大値（ｍａｘ ｅｘｐ）と第２項の指数関数の計算値の内の最大値（ｍａｘ ｅｘｐ）とを用い、これら以外の指数関数の計算値を無視する近似手法が示されている。次式（２）は、この近似方法を表す式である。

Figure 0006177141
For example, in Non-Patent Document 1, the maximum value (max exp) among the calculated values of the exponential function of the first term on the right side of Equation (1) and the maximum value of the calculated values of the exponential function of the second term ( max exp) and an approximation method that ignores the calculated values of other exponential functions. The following equation (2) is an equation representing this approximation method.
Figure 0006177141

式（２）において、ｓｋ，０，ｍｉｎは、１つの送信シンボル点を構成する複数のビットの内のｋビット目のビットが０である送信シンボル点の内で、受信信号点ｒからの距離が最短である送信シンボル点の位置ベクトルを示す。また、ｓｋ，１，ｍｉｎは、１つの送信シンボル点を構成する複数のビットの内のｋビット目のビットが１である送信シンボル点の内で、受信信号点ｒからの距離が最短である送信シンボル点の位置ベクトルを示す。 In Expression (2), s k, 0, min is a value from the received signal point r within the transmission symbol points where the k-th bit among the plurality of bits constituting one transmission symbol point is 0. The position vector of the transmission symbol point with the shortest distance is shown. In addition, s k, 1, min is the shortest distance from the reception signal point r among the transmission symbol points where the k-th bit is 1 among the plurality of bits constituting one transmission symbol point. A position vector of a certain transmission symbol point is shown.

図１（ａ）から（ｅ）は、位相平面上に多値変調方式の１つである１６ＱＡＭにおける送信シンボル点を示す図である。図１（ａ）に示されるように、１６ＱＡＭでは、１つの送信シンボル点は４ビットｂ１ｂ２ｂ３ｂ４で構成され、４行４列に並ぶ丸印で示される送信シンボル点（送信シンボル点の候補）の数は１６個である。１６個の送信シンボル点は、４ビットｂ１ｂ２ｂ３ｂ４を構成する各ビットについて、ビット（ビットｂ１，ｂ２，ｂ３，ｂ４の各々）が０である複数の送信シンボル点から成る送信シンボル点群（図１（ｂ）から（ｅ）における白色領域）又はビット（ビットｂ１，ｂ２，ｂ３，ｂ４の各々）が１である複数の送信シンボル点から成る送信シンボル点群（図１（ｂ）から（ｅ）における斜線領域）に分類される。１６個の送信シンボル点の各々は、１ビット目のビットｂ１については、図１（ｂ）に白色領域で示されるｂ１＝０の送信シンボル点群（集合Ｃ１，０）及び斜線領域で示されるｂ１＝１の送信シンボル点群（集合Ｃ１，１）のいずれかに含まれる。また、１６個の送信シンボル点の各々は、２ビット目のビットｂ２については、図１（ｃ）に白色領域で示されるｂ２＝０の送信シンボル点群（集合Ｃ２，０）及び斜線領域で示されるｂ２＝１の送信シンボル点群（集合Ｃ２，１）のいずれかに含まれる。また、１６個の送信シンボル点の各々は、３ビット目のビットｂ３については、図１（ｄ）に白色領域で示されるｂ３＝０の送信シンボル点群（集合Ｃ３，０）及び斜線領域で示されるｂ３＝１の送信シンボル点群（集合Ｃ３，１）のいずれかに含まれる。また、１６個の送信シンボル点の各々は、４ビット目のビットｂ４については、図１（ｅ）に白色領域で示されるｂ４＝０の送信シンボル点群（集合Ｃ４，０）及び斜線領域で示されるｂ４＝１の送信シンボル点群（集合Ｃ４，１）のいずれかに含まれる。 FIGS. 1A to 1E are diagrams showing transmission symbol points in 16QAM, which is one of multilevel modulation schemes, on a phase plane. As shown in FIG. 1A, in 16QAM, one transmission symbol point is composed of 4 bits b 1 b 2 b 3 b 4 , and transmission symbol points (transmissions) indicated by circles arranged in 4 rows and 4 columns. The number of symbol point candidates) is 16. The 16 transmission symbol points are a plurality of transmission symbols whose bits (each of bits b 1 , b 2 , b 3 , and b 4 ) are 0 for each bit constituting 4 bits b 1 b 2 b 3 b 4. A transmission symbol point group consisting of points (white region in FIGS. 1B to 1E) or a plurality of transmission symbol points whose bits (each of bits b 1 , b 2 , b 3 , b 4 ) are 1 It is classified into a transmission symbol point group (shaded area in FIGS. 1B to 1E). Each of the 16 transmission symbols point 1 for the bit b 1 of bit, and FIG. 1 (b) to the transmission symbol point group of b 1 = 0 represented by the white areas (the set C 1, 0) and shaded region Are included in any of the transmission symbol point groups (set C 1,1 ) of b 1 = 1. Further, each of the 16 transmission symbol points, for the bit b 2 of the second bit, the transmission symbol point group (set C 2, 0) of b 2 = 0 represented by the white areas in FIG. 1 (c) and It is included in any of the b 2 = 1 transmission symbol point groups (set C 2,1 ) indicated by the hatched area. Further, each of the 16 transmission symbols point 3 for the bit b 3 of bit, 1 transmission symbol point group of b 3 = 0 represented by the white area (d) (collectively C 3, 0) and It is included in one of the b 3 = 1 transmission symbol point groups (set C 3,1 ) indicated by the hatched area. Further, each of the 16 transmission symbols point 4 for the bit b 4 of bit, 1 transmission symbol point group of b 4 = 0 as indicated by the white area (e) (set C 4, 0) and It is included in any of the transmission symbol point groups (set C 4,1 ) of b 4 = 1 indicated by the hatched area.

式（２）に基づいたＬＬＲ算出方法では、図２に示されるように、位相平面上において受信信号点ｒからの距離が最短である送信シンボル点である基準点ｓｋ，０，ｍｉｎと、基準点ｓｋ，０，ｍｉｎのビット反転基準点ｓ１，１，ｍｉｎ，ｓ２，１，ｍｉｎ，ｓ３，１，ｍｉｎ，ｓ４，１，ｍｉｎとを算出する。次に、基準点ｓｋ，０，ｍｉｎと受信信号点ｒとの間の距離の２乗Ａ０ ２と、ビット反転基準点ｓ１，１，ｍｉｎ，ｓ２，１，ｍｉｎ，ｓ３，１，ｍｉｎ，ｓ４，１，ｍｉｎのそれぞれと受信信号点ｒとの間の距離の２乗Ａ１ ２，Ａ２ ２，Ａ３ ２，Ａ４ ２とを算出する。次に、ビット反転基準点ｓ１，１，ｍｉｎ，ｓ２，１，ｍｉｎ，ｓ３，１，ｍｉｎ，ｓ４，１，ｍｉｎと受信信号点ｒとの間の距離の２乗Ａ１ ２，Ａ２ ２，Ａ３ ２，Ａ４ ２の各々から、基準点ｓｋ，０，ｍｉｎと受信信号点ｒとの間の距離の２乗Ａ０ ２を減算して、４つの減算結果である（Ａ１ ２−Ａ０ ２）、（Ａ２ ２−Ａ０ ２）、（Ａ３ ２−Ａ０ ２）、（Ａ４ ２−Ａ０ ２）を算出する。これら減算結果を、２σ２で除算することによって、１６ＱＡＭの１個の送信シンボル点を構成する４ビットの各々（ビットｂ１，ｂ２，ｂ３，ｂ４の各々）について、ビットＬＬＲ（Ｌｋ）を算出する。 In the LLR calculation method based on Equation (2), as shown in FIG. 2, a reference point s k, 0, min that is a transmission symbol point having the shortest distance from the reception signal point r on the phase plane; Bit inversion reference points s 1,1, min , s 2,1, min , s 3,1, min , s 4,1, min of the reference points s k, 0, min are calculated. Next, the square A 0 2 of the distance between the reference point s k, 0, min and the received signal point r, and the bit inversion reference points s 1,1, min , s 2,1, min , s 3, The squares A 1 2 , A 2 2 , A 3 2 , and A 4 2 of the distances between 1, min , s 4, 1 and min and the reception signal point r are calculated. Next, the square A 1 2 of the distance between the bit inversion reference point s 1,1, min , s 2,1, min , s 3,1, min , s 4,1, min and the received signal point r. , A 2 2 , A 3 2 , and A 4 2 , the square A 0 2 of the distance between the reference point sk, 0, min and the received signal point r is subtracted, and four subtraction results are obtained. Certain (A 1 2 -A 0 2 ), (A 2 2 -A 0 2 ), (A 3 2 -A 0 2 ), and (A 4 2 -A 0 2 ) are calculated. By dividing these subtraction results by 2σ 2 , for each of 4 bits (each of bits b 1 , b 2 , b 3 , b 4 ) constituting one transmission symbol point of 16QAM, bit LLR (L k ) is calculated.

Ｆ．Ｔｏｓａｔｏ及びＰ．Ｂｉｓａｇｌｉａ著、「Ｓｉｍｐｌｉｆｉｅｄ Ｓｏｆｔ−Ｏｕｔｐｕｔ ｄｅｍａｐｐｅｒ ｆｏｒ Ｂｉｎａｒｙ Ｉｎｔｅｒｌｅａｖｅｄ ＣＯＦＤＭ ｗｉｔｈ Ａｐｐｌｉｃａｔｉｏｎ ｔｏ ＨＩＰＥＲＬＡＮ／２」、 Ｃｏｍｍｕｎｉｃａｔｉｏｎｓ， ２００２． ＩＣＣ ２００２． ＩＥＥＥ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｃｏｎｆｅｒｅｎｃｅ ｏｎ， Ｖｏｌ．２， ＰＰ．６６４−６６８．F. Tosato and P.M. Bisagria, “Simplicated Soft-Output demapped for Binary Interleaved COFDM with Application to HIPERLAN / 2”, Communications, 2002. ICC 2002. IEEE International Conference on, Vol. 2, PP. 664-668.

しかしながら、非特許文献１のＬＬＲ算出方法においては、基準点と受信信号点との間の距離の２乗及びビット反転基準点と受信信号点との間の距離の２乗を計算することによって、各ビットのビットＬＬＲを算出しており、且つ、多値変調方式の多値数が増えるほど距離の２乗を計算する過程も増加する。このため、非特許文献１のＬＬＲ算出方法には、ビットＬＬＲを算出するための計算処理の演算量が膨大になるという問題があった。   However, in the LLR calculation method of Non-Patent Document 1, by calculating the square of the distance between the reference point and the reception signal point and the square of the distance between the bit inversion reference point and the reception signal point, The process of calculating the square of the distance increases as the bit LLR of each bit is calculated and the multi-level number of the multi-level modulation scheme increases. For this reason, the LLR calculation method of Non-Patent Document 1 has a problem that the amount of calculation processing for calculating the bit LLR is enormous.

そこで、本発明は、上記従来技術の課題を解決するためになされたものであり、ビットＬＬＲを算出するための計算処理の演算量を大幅に削減することができる対数尤度比算出装置、対数尤度比算出方法、及び対数尤度比算出用プログラムを提供することを目的とする。   Therefore, the present invention has been made to solve the above-described problems of the prior art, and a log likelihood ratio calculation apparatus, logarithm, and the like that can significantly reduce the amount of calculation processing for calculating the bit LLR. It is an object to provide a likelihood ratio calculation method and a log likelihood ratio calculation program.

本発明の一態様に係る対数尤度比算出装置は、所定数のビットで構成されたビット列を、実軸及び虚軸を有する複素平面上に予め決められた複数個の送信シンボル点に変調した放送信号を受信し、該受信した信号から前記ビット列の各々のビットに対して、ビット対数尤度比を算出する対数尤度比算出装置であって、前記受信した信号を前記複素平面上で示した受信信号点からの距離が最短となる送信シンボル点を基準点として検出する基準点検出回路と、前記ビット列の各々のビットに対して、前記ビット対数尤度比の算出対象となるビットの値が異なる任意の送信シンボル点をビット反転基準点として検出するビット反転基準点検出回路と、前記複素平面上の任意の直線を第１の軸として、前記受信信号点、前記基準点検出回路にて検出した基準点、及び前記ビット反転基準点検出回路にて検出したビット反転基準点を射影して、当該第１の軸に射影された前記受信信号点、前記基準点、及び前記ビット反転基準点の射影点を前記ビット列の各々のビットに対して取得する基準軸射影回路と、前記基準軸射影回路にて取得した基準点とビット反転基準点の射影点との中点を原点とするように、前記基準軸射影回路にて取得した受信信号点の射影点に対して差分の補正を、前記ビット列の各々のビットに対して行う軸内補正回路と、前記基準軸射影回路にて取得した基準点とビット反転基準点の射影点の距離に応じて、前記軸内補正回路で補正した射影点の前記ビット列の各々のビットに対して正規化するシンボル点間補正回路とを有することを特徴とする。 A log-likelihood ratio calculation apparatus according to an aspect of the present invention modulates a bit string composed of a predetermined number of bits into a plurality of predetermined transmission symbol points on a complex plane having a real axis and an imaginary axis . receiving a broadcast signal, for each of bits of the bit sequence from the received signal, a log-likelihood ratio calculating device for calculating a bit log likelihood ratio, the pre-Symbol received signal on the complex plane a reference point detecting circuit for detecting a reference point transmission symbol points the distance from the received signal point is shortest shown, for each of the bits before millet Tsu preparative column, the calculation target of the bit log likelihood ratio and the ruby Tsu preparative reversed reference point detection circuit to detect any transmission symbol points the value of the bits are different to be a bit inversion reference point, the arbitrary straight line on the complex plane as the first axis, the received signal point , detected by the reference point detection circuit Reference point, and by shadow morphism bit inversion reference point detected by said bit inversion reference point detection circuit, the received signal point, which is projected to the first axis, the reference point,及beauty before Symbol bit inversion midpoint of the criteria axial projection circuit you get the projection point of the reference point with respect to each bit of said bit sequence, and the projection point of the reference point and the bit inversion reference point acquired by the reference axis projection circuit the to the original point, the correction of the difference with respect morphism Kageten the received signal point acquired by the reference axis projection circuit, and the axis in the correction circuit performed on each bit of said bit sequence, the reference depending on the distance of the projection point of the reference point acquired in the axial projection circuit and bit inversion reference point, normal turn into that symbol point for each of bits of the bit sequence of projection points corrected by the shaft in the correction circuit and having a between correction circuit.

本発明の他の態様に係る対数尤度比算出装置は、所定数のビットで構成されたビット列を、実軸及び虚軸を有する複素平面上に予め決められた複数個の送信シンボル点に変調した放送信号を受信し、該受信した信号から前記ビット列の各々のビットに対して、ビット対数尤度比を算出する対数尤度比算出装置であって、前記受信した信号を前記複素平面上で示した受信信号点からの距離が最短となる送信シンボル点を基準点として検出する基準点検出回路と、前記ビット列の各々のビットに対して、前記ビット対数尤度比の算出対象となるビットの値が異なる任意の送信シンボル点をビット反転基準点として検出するビット反転基準点検出回路と、前記複素平面上の任意の直線を第１の軸及び該第１の軸に直交する直線を第２の軸として、前記第１の軸及び前記第２の軸に対して、前記受信信号点、前記基準点検出回路にて検出した基準点、及び前記ビット反転基準点検出回路にて検出したビット反転基準点を射影して、前記第１の軸及び前記第２の軸のそれぞれに射影された前記受信信号点、前記基準点、及び前記ビット反転基準点の射影点を前記ビット列の各々のビットに対して取得する基準軸射影回路と、前記基準軸射影回路にて取得した前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複すると判定した第１の場合は、前記第２の軸における基準点の射影点とビット反転基準点の射影点との中点を原点とするように前記第２の軸における前記受信信号点の射影点に対して差分の補正を行うことによって前記受信信号点の補正された射影点である第１の射影点を算出し、前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複せず前記第２の軸における基準点の射影点及びビット反転基準点の射影点が重複すると判定した第２の場合は、前記第１の軸における基準点の射影点とビット反転基準点の射影点との中点を原点とするように前記第１の軸における前記受信信号点の射影点に対して差分の補正を行うことによって前記受信信号点の補正された射影点である第２の射影点を算出し、前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複せず前記第２の軸における基準点の射影点及びビット反転基準点の射影点が重複しないと判定した第３の場合は、前記第１の射影点及び前記第２の射影点を算出する処理を、前記ビット列の各々のビットに対して行う軸内補正回路と、前記基準軸射影回路にて取得した基準点とビット反転基準点の射影点の距離に応じて、前記第１の場合では前記第１の射影点の前記ビット列の各々のビットに対して正規化処理を施し、前記正規化処理が施された前記第１の射影点の値をビット対数尤度比として出力し、前記第２の場合では前記第２の射影点の前記ビット列の各々のビットに対して正規化処理を施し、前記正規化処理が施された前記第２の射影点の値をビット対数尤度比として出力し、前記第３の場合では前記第１及び前記第２の射影点の前記ビット列の各々のビットに対する正規化処理と前記第１及び第２の射影点を均等に重み付け加算する処理とを行うことで得られた値をビット対数尤度比として出力する回路とを有することを特徴とする。 A log likelihood ratio calculation apparatus according to another aspect of the present invention modulates a bit string composed of a predetermined number of bits into a plurality of predetermined transmission symbol points on a complex plane having a real axis and an imaginary axis. A log likelihood ratio calculation device for calculating a bit log likelihood ratio for each bit of the bit string from the received signal, the received signal on the complex plane A reference point detection circuit that detects a transmission symbol point having the shortest distance from the received signal point as a reference point, and a bit log likelihood ratio calculation target bit for each bit of the bit string A bit inversion reference point detection circuit for detecting any transmission symbol point having a different value as a bit inversion reference point; a first straight line on the complex plane; a second straight line orthogonal to the first axis; as the axis, before For the first axis and the second axis, the received signal point, the reference point detected by the reference point detection circuit, and the bit inversion reference point detected by said bit inversion reference point detection circuit projected A reference for acquiring the reception signal point projected on each of the first axis and the second axis , the reference point, and the projection point of the bit inversion reference point for each bit of the bit string. In the first case where it is determined that the projection point of the reference point and the projection point of the bit reversal reference point in the first axis acquired by the axis projection circuit and the reference axis projection circuit overlap, in the second axis The received signal point is corrected by correcting a difference with respect to the projected point of the received signal point on the second axis so that the midpoint between the projected point of the reference point and the projected point of the bit inversion reference point is the origin. Is the corrected projection point of the first The projection point is calculated, and the projection point of the reference point and the bit inversion reference point on the first axis do not overlap, and the projection point of the reference point and the bit inversion reference point on the second axis overlap In the second case, the projection of the received signal point on the first axis so that the midpoint between the projection point of the reference point on the first axis and the projection point of the bit inversion reference point is the origin. Calculating a second projected point which is a corrected projected point of the received signal point by performing a difference correction on the point, and projecting a projected point of the reference point and a bit-reversed reference point on the first axis In the third case where it is determined that the projected point of the reference point and the projected point of the bit inversion reference point in the second axis do not overlap with each other, the first projected point and the second projected point are The calculation process is performed for each bit of the bit string. An in-axis correction circuit to perform, and according to the distance between the reference point acquired by the reference axis projection circuit and the projection point of the bit inversion reference point, in the first case, each of the bit strings of the first projection point Normalization processing is performed on the bits, and the value of the first projection point subjected to the normalization processing is output as a bit log likelihood ratio. In the second case, the value of the second projection point is A normalization process is performed on each bit of the bit string, and the value of the second projection point subjected to the normalization process is output as a bit log likelihood ratio. In the third case, the first and A value obtained by performing a normalization process on each bit of the bit sequence of the second projection point and a process of equally weighting and adding the first and second projection points is used as a bit log likelihood ratio. and having an you output circuits.

本発明においては、受信信号点と基準点とビット反転基準点とを予め決められた軸上に射影し、基準点の射影点とビット反転基準点の射影点との中点が原点となるようにする補正を行い、基準点の射影点とビット反転基準点の射影点との間の距離に応じて受信信号点の射影点を正規化する補正を行うことで、ビットＬＬＲを算出している。このように、本発明によれば、位相平面上における２つ点の距離の２乗を計算する必要がないので、ビットＬＬＲの算出過程の演算量を大幅に削減することができる。   In the present invention, the received signal point, the reference point, and the bit inversion reference point are projected onto a predetermined axis, and the midpoint between the projection point of the reference point and the projection point of the bit inversion reference point is the origin. The bit LLR is calculated by correcting the projection point of the reception signal point according to the distance between the projection point of the reference point and the projection point of the bit inversion reference point. . Thus, according to the present invention, since it is not necessary to calculate the square of the distance between two points on the phase plane, the amount of calculation in the bit LLR calculation process can be greatly reduced.

（ａ）から（ｅ）は、位相平面上に１６ＱＡＭにおける送信シンボル点を示す図である。(A)-(e) is a figure which shows the transmission symbol point in 16QAM on a phase plane. 従来のＬＬＲ算出方法を示す図である。It is a figure which shows the conventional LLR calculation method. 本発明の実施の形態１及び２に係る受信装置の構成を概略的に示すブロック図である。It is a block diagram which shows roughly the structure of the receiver which concerns on Embodiment 1 and 2 of this invention. 実施の形態１に係るＬＬＲ算出装置の構成を概略的に示すブロック図である。1 is a block diagram schematically showing a configuration of an LLR calculation apparatus according to Embodiment 1. FIG. （ａ）から（ｄ）は、実施の形態１に係るＬＬＲ算出方法の一例を示す図である。(A) to (d) are diagrams illustrating an example of an LLR calculation method according to the first embodiment. （ａ）から（ｄ）は、図５（ａ）の１ビット目のビットＬＬＲの算出処理を詳細に示す図である。(A) to (d) are diagrams showing in detail the calculation processing of the bit LLR of the first bit in FIG. 5 (a). （ａ）から（ｄ）は、図５（ｂ）の２ビット目のビットＬＬＲの算出処理を詳細に示す図である。(A) to (d) are diagrams showing in detail the calculation processing of the bit LLR of the second bit in FIG. 5 (b). （ａ）から（ｄ）は、図５（ｃ）の３ビット目のビットＬＬＲの算出処理を詳細に示す図である。(A) to (d) is a diagram showing in detail the calculation processing of the bit LLR of the third bit in FIG. 5 (c). （ａ）から（ｄ）は、図５（ｄ）の４ビット目のビットＬＬＲの算出処理を詳細に示す図である。(A) to (d) are diagrams showing in detail the calculation processing of the bit LLR of the fourth bit in FIG. 5 (d). 実施の形態１に係るＬＬＲ算出装置における処理を示すフローチャートである。4 is a flowchart showing processing in the LLR calculation apparatus according to Embodiment 1; 実施の形態２に係るＬＬＲ算出装置の構成を概略的に示すブロック図である。6 is a block diagram schematically showing a configuration of an LLR calculation apparatus according to Embodiment 2. FIG. 実施の形態２に係るＬＬＲ算出装置における処理を示すフローチャートである。10 is a flowchart illustrating processing in the LLR calculation apparatus according to the second embodiment.

以下に、本発明を適用した対数尤度比（ＬＬＲ）算出装置及びＬＬＲ算出方法を具体的に説明する。実施の形態１及び２においては、本発明を、欧州の地上デジタル放送規格であるグレイコード（Ｇｒａｙ ｃｏｄｅ）を用いた１６ＱＡＭ変調方式を採用した通信システムの受信装置に適用した例を説明する。ただし、本発明は、ＱＡＭ変調方式を採用した通信システムの受信装置だけでなく、ＰＳＫ又はＡＰＳＫなどのような他の多値変調方式を採用した通信システムの受信装置にも適用可能である   Hereinafter, a log likelihood ratio (LLR) calculation apparatus and an LLR calculation method to which the present invention is applied will be specifically described. In Embodiments 1 and 2, an example will be described in which the present invention is applied to a receiving apparatus of a communication system that adopts a 16QAM modulation scheme using a Gray code that is a European terrestrial digital broadcasting standard. However, the present invention can be applied not only to a receiving device of a communication system adopting the QAM modulation method but also to a receiving device of a communication system adopting another multilevel modulation method such as PSK or APSK.

図３は、本発明の実施の形態１及び２に係る受信装置の構成を概略的に示すブロック図である。図３に示される受信装置は、ＬＬＲ算出装置（実施の形態１における符号１又は実施の形態２における符号３）と、軟判定誤り訂正復号装置２とを有する。ＬＬＲ算出装置１（又は３）は、送信ビットを含む受信信号の位相平面上における受信信号点の位置（送信シンボル点の座標位置）から送信ビットの信頼性を表すビットＬＬＲを算出する。軟判定誤り訂正復号装置２は、ＬＬＲ算出装置１（又は３）で算出されたビットＬＬＲを用いて送信ビットの誤り訂正復号を行い、復号ビット列を算出する。   FIG. 3 is a block diagram schematically showing a configuration of the receiving apparatus according to Embodiments 1 and 2 of the present invention. The receiving apparatus illustrated in FIG. 3 includes an LLR calculation apparatus (reference numeral 1 in the first embodiment or reference numeral 3 in the second embodiment) and a soft decision error correction decoding apparatus 2. The LLR calculation device 1 (or 3) calculates a bit LLR representing the reliability of the transmission bit from the position of the reception signal point (coordinate position of the transmission symbol point) on the phase plane of the reception signal including the transmission bit. The soft decision error correction decoding device 2 performs error correction decoding of the transmission bits using the bit LLR calculated by the LLR calculation device 1 (or 3), and calculates a decoded bit string.

実施の形態１．
図４は、本発明の実施の形態１に係るＬＬＲ算出装置１の構成を概略的に示すブロック図である。ＬＬＲ算出装置１は、実施の形態１に係るＬＬＲ算出方法を実施することができる装置である。図４に示されるように、ＬＬＲ算出装置１は、基準点検出回路１０と、ビット反転基準点検出回路１１と、基準軸射影回路１２と、軸内補正回路１３と、シンボル点間補正回路１４と、各構成要素１１〜１４の動作を制御する制御部１５とを有する。ＬＬＲ算出装置１には、誤り訂正符号化された送信ビットのビット列が多値変調方式によって変調されて送信された信号が入力される。 Embodiment 1 FIG.
FIG. 4 is a block diagram schematically showing the configuration of the LLR calculation apparatus 1 according to Embodiment 1 of the present invention. The LLR calculation apparatus 1 is an apparatus that can perform the LLR calculation method according to the first embodiment. As shown in FIG. 4, the LLR calculation apparatus 1 includes a reference point detection circuit 10, a bit inversion reference point detection circuit 11, a reference axis projection circuit 12, an in-axis correction circuit 13, and an inter-symbol point correction circuit 14. And a control unit 15 that controls the operation of each of the constituent elements 11 to 14. The LLR calculation apparatus 1 receives a signal transmitted by modulating a bit string of transmission bits subjected to error correction coding by a multi-level modulation method.

図５（ａ）から（ｄ）は、実施の形態１に係るＬＬＲ算出装置１の動作の一例、すなわち、実施の形態１に係るＬＬＲ算出方法の一例を示す図である。また、図６（ａ）から（ｄ）は、図５（ａ）の１ビット目のビットＬＬＲの算出処理を詳細に示す図であり、図７（ａ）から（ｄ）は、図５（ｂ）の２ビット目のビットＬＬＲの算出処理を詳細に示す図であり、図８（ａ）から（ｄ）は、図５（ｃ）の３ビット目のビットＬＬＲの算出処理を詳細に示す図であり、図９（ａ）から（ｄ）は、図５（ｄ）の４ビット目のビットＬＬＲの算出処理を詳細に示す図である。   FIGS. 5A to 5D are diagrams illustrating an example of the operation of the LLR calculation apparatus 1 according to the first embodiment, that is, an example of the LLR calculation method according to the first embodiment. FIGS. 6A to 6D are diagrams showing in detail the calculation processing of the bit LLR of the first bit in FIG. 5A. FIGS. 7A to 7D are shown in FIG. FIG. 8 is a diagram illustrating in detail the calculation processing of the bit LLR of the second bit in b), and FIGS. 8A to 8D illustrate in detail the calculation processing of the bit LLR of the third bit in FIG. FIGS. 9A to 9D are diagrams illustrating in detail the calculation processing of the bit LLR of the fourth bit in FIG. 5D.

実施の形態１に係るＬＬＲ算出装置１は、誤り訂正符号化された４ビットのビット列ｂ１ｂ２ｂ３ｂ４が多値変調方式である１６ＱＡＭによって変調されて送信された信号が入力され、この受信信号からビットＬＬＲ（Ｌｋ）を算出する装置である。ただし、入力されるビット列のビット数は、４ビットに限定されない。また、受信信号の変調方式は、ＱＡＭ変調方式に限定されない。 The LLR calculation apparatus 1 according to the first embodiment receives a signal that is transmitted after the error correction encoded 4-bit bit string b 1 b 2 b 3 b 4 is modulated by 16QAM, which is a multi-level modulation scheme, This is a device for calculating the bit LLR (L k ) from this received signal. However, the number of bits of the input bit string is not limited to 4 bits. Further, the modulation method of the received signal is not limited to the QAM modulation method.

基準点検出回路１０は、誤り訂正符号化されたビット列が多値変調方式によって変調されて送信された信号を受信し、予め決められた個数の送信シンボル点の候補から受信信号点との位相平面上における距離が最短となる送信シンボル点を基準点として選択する。なお、位相平面上における予め決められた個数の「送信シンボル点の候補」を、単に「送信シンボル点」とも言う。基準点検出回路１０は、最短の距離が同じとなる送信シンボル点が複数ある場合は、その内の１つの送信シンボル点であれば、いずれの送信シンボル点を選択してもよい。例えば、基準点検出回路１０は、図５（ａ）から（ｄ）、図６（ａ）、図７（ａ）、図８（ａ）、図９（ａ）に示されるように、実軸（Ｉ軸）及び虚軸（Ｑ軸）を有する複素平面である位相平面上に配列された予め決められた個数（図６（ａ）、図７（ａ）、図８（ａ）、図９（ａ）に４行４列の丸印で示される１６個）の送信シンボル点の内、受信信号を示す受信信号点Ｒからの距離が最短となる送信シンボル点を基準点Ｓとして検出（選択）する。ただし、図６（ａ）、図７（ａ）、図８（ａ）、図９（ａ）に示される各処理は１つの受信信号点Ｒについて同じ処理であるため、例えば、図６（ａ）の処理のみを行い、処理結果を、例えば、制御部１５内の記憶部又は制御部１５に接続された記憶部に記憶するように構成すれば、図７（ａ）、図８（ａ）、図９（ａ）の処理を省略することができる。なお、実施の形態１においては、基準点を構成する４ビットｂ１ｂ２ｂ３ｂ４が“００００”である場合を説明する。 The reference point detection circuit 10 receives a signal that is transmitted by modulating a bit string that has been subjected to error correction coding by a multi-level modulation method, and a phase plane from a predetermined number of transmission symbol point candidates to a reception signal point. The transmission symbol point with the shortest distance is selected as a reference point. The predetermined number of “symbol transmission point candidates” on the phase plane is also simply referred to as “transmission symbol points”. When there are a plurality of transmission symbol points having the same shortest distance, the reference point detection circuit 10 may select any transmission symbol point as long as it is one of the transmission symbol points. For example, the reference point detection circuit 10 has a real axis as shown in FIGS. 5 (a) to 5 (d), FIG. 6 (a), FIG. 7 (a), FIG. 8 (a), and FIG. A predetermined number (FIGS. 6A, 7A, 8A, and 9) arranged on a phase plane that is a complex plane having (I axis) and imaginary axis (Q axis). The transmission symbol point having the shortest distance from the reception signal point R indicating the reception signal is detected (selected) as the reference point S among the 16 transmission symbol points indicated by circles in 4 rows and 4 columns in (a). ) However, each process shown in FIG. 6A, FIG. 7A, FIG. 8A, and FIG. 9A is the same process for one received signal point R. For example, FIG. 7), and the processing result is stored in the storage unit in the control unit 15 or a storage unit connected to the control unit 15, for example, FIG. 7 (a) and FIG. 8 (a). 9A can be omitted. In the first embodiment, the case where the 4 bits b 1 b 2 b 3 b 4 constituting the reference point are “0000” will be described.

次に、ビット反転基準点検出回路１１は、送信シンボル点の各々を構成するビット列ｂ１ｂ２ｂ３ｂ４の内の、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋ毎に（すなわち、ビットｂ１、ｂ２、ｂ３、ｂ４の各々について）、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋの値が異なる任意の送信シンボル点をビット反転基準点Ｉｋとして選択する処理を実行する。 Next, the bit inversion reference point detection circuit 11 (for each bit b k for which the bit LLR (L k ) of the bit string b 1 b 2 b 3 b 4 constituting each of the transmission symbol points is to be calculated ( That is, for each of bits b 1 , b 2 , b 3 , and b 4 ), an arbitrary transmission symbol point having a different value of bit b k for which bit LLR (L k ) is calculated is defined as bit inversion reference point I k. Execute the process to select.

例えば、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが１ビット目（ｋ＝１）のビットｂ１である場合には、ビット反転基準点検出回路１１は、図１（ｂ）、図５（ａ）及び図６（ｂ）に示されるように、ビットｂ１の値が基準点Ｓの１ビット目のビットの値“０”と異なる値“１”である送信シンボル点群（ｂ１＝１の斜線領域にある８つの送信シンボル点、すなわち、ビット反転基準点の候補）の中の任意の送信シンボル点をビット反転基準点Ｉｋ＝Ｉ１として選択する処理を実行する。 For example, the bit b k is 1 bit to be calculated subject to bit LLR (L k) (k = 1) if the bit b 1 is the bit inversion reference point detection circuit 11, FIG. 1 (b), the FIGS. 5 (a) and 6 (b) as shown in the bit b 1 of the first bit of the bit values of the reference point S "0" is different from the value "1" is transmission symbol point group ( A process of selecting an arbitrary transmission symbol point among eight transmission symbol points in the hatched region of b 1 = 1, that is, a bit inversion reference point candidate) as a bit inversion reference point I k = I 1 is executed.

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが２ビット目（ｋ＝２）のビットｂ２である場合には、ビット反転基準点検出回路１１は、図１（ｃ）、図５（ｂ）及び図７（ｂ）に示されるように、ビットｂ２の値が基準点Ｓの２ビット目のビットの値“０”と異なる値“１”である送信シンボル点群（ｂ２＝１の斜線領域にある８つの送信シンボル点、すなわち、ビット反転基準点の候補）の中の任意の送信シンボル点をビット反転基準点Ｉｋ＝Ｉ２として選択する処理を実行する。 When the bit b k for which the bit LLR (L k ) is to be calculated is the second bit (k = 2), the bit b 2 , the bit inversion reference point detection circuit 11 performs processing shown in FIG. As shown in FIG. 5B and FIG. 7B, the transmission symbol point group (the value of the bit b 2 is a value “1” different from the value “0” of the second bit of the reference point S) ( A process of selecting an arbitrary transmission symbol point among the eight transmission symbol points in the hatched region of b 2 = 1 (that is, a bit inversion reference point candidate) as the bit inversion reference point I k = I 2 is executed.

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが３ビット目（ｋ＝３）のビットｂ３である場合には、ビット反転基準点検出回路１１は、図１（ｄ）、図５（ｃ）及び図８（ｂ）に示されるように、ビットｂ３の値が基準点Ｓの３ビット目のビットの値“０”と異なる値“１”である送信シンボル点群（ｂ３＝１の斜線領域にある８つの送信シンボル点、すなわち、ビット反転基準点の候補）の中の任意の送信シンボル点をビット反転基準点Ｉｋ＝Ｉ３として選択する処理を実行する。 The bit b k is 3 bit to be calculated subject to bit LLR (L k) in the case (k = 3) is the bit b 3 of the bit inversion reference point detection circuit 11, FIG. 1 (d), the As shown in FIG. 5C and FIG. 8B, the transmission symbol point group (the value of the bit b 3 is a value “1” different from the value “0” of the third bit of the reference point S) ( A process of selecting an arbitrary transmission symbol point among eight transmission symbol points in the hatched region of b 3 = 1 (that is, a bit inversion reference point candidate) as a bit inversion reference point I k = I 3 is executed.

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが４ビット目（ｋ＝４）のビットｂ４である場合には、ビット反転基準点検出回路１１は、図１（ｅ）、図５（ｄ）及び図９（ｂ）に示されるように、ビットｂ４の値が基準点Ｓの４ビット目のビットの値“０”と異なる値“１”である送信シンボル点群（ｂ４＝１の斜線領域にある８つの送信シンボル点、すなわち、ビット反転基準点の候補）の中の任意の送信シンボル点をビット反転基準点Ｉｋ＝Ｉ４として選択する処理を実行する。 The bit b k is 4 bit to be calculated subject to bit LLR (L k) in the case (k = 4) is a bit b 4 of the bit inversion reference point detection circuit 11, FIG. 1 (e), the As shown in FIG. 5D and FIG. 9B, the value of bit b 4 has a value “1” different from the value “0” of the fourth bit of reference point S ( A process of selecting an arbitrary transmission symbol point among the eight transmission symbol points in the hatched region of b 4 = 1 (that is, a bit inversion reference point candidate) as the bit inversion reference point I k = I 4 is executed.

なお、ビット反転基準点検出回路１１において任意の送信シンボル点をビット反転基準点Ｉｋとして選択する処理は、基準点ＳからビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋ毎に、ビットＬＬＲ（Ｌｋ）の算出対象となるビット（ｂｋ）の値が異なり、且つ、位相平面上における受信信号点Ｒからの距離が最短となる送信シンボル点を、ｂｋ＝１の領域（図１（ｂ）から（ｅ）における斜線領域）にある８個の送信シンボル点（ビット反転基準点の候補）から選択する処理とすることができる。 Note that the process of selecting an arbitrary transmission symbol point as the bit inversion reference point I k in the bit inversion reference point detection circuit 11 is performed for each bit b k from which the bit LLR (L k ) is calculated from the reference point S. The transmission symbol point having the shortest distance from the reception signal point R on the phase plane and the value of the bit (b k ) from which the LLR (L k ) is to be calculated is the region of b k = 1 (see FIG. 1 (b) to (e) can be selected from eight transmission symbol points (bit inversion reference point candidates) in the hatched area).

また、ビット反転基準点検出回路１１において任意の送信シンボル点をビット反転基準点Ｉｋとして選択する処理は、基準点ＳからビットＬＬＲ（Ｌｋ）の算出対象となるビット（ｂｋ）毎に、ビットＬＬＲ（Ｌｋ）の算出対象となるビット（ｂｋ）だけを反転したビット列となる送信シンボル点を選択する処理としてもよい。ただし、この場合には、距離が最短となる送信シンボル点をビット反転基準点とした場合よりも、既に説明した式（２）が意図する近似よりも精度が低下するため、取得されたビットＬＬＲ（Ｌｋ）の信頼度は低くなるが、演算量が少なくなり、回路規模を小さくすることができる。 Further, the process of selecting an arbitrary transmission symbol point as the bit inversion reference point I k in the bit inversion reference point detection circuit 11 is performed for each bit (b k ) from which the bit LLR (L k ) is to be calculated from the reference point S. The transmission symbol point that is a bit string obtained by inverting only the bit (b k ) for which the bit LLR (L k ) is to be calculated may be selected. However, in this case, since the accuracy is lower than the approximation intended by Equation (2) described above, compared to the case where the transmission symbol point having the shortest distance is used as the bit inversion reference point, the obtained bit LLR is obtained. Although the reliability of (L k ) is lowered, the amount of calculation is reduced and the circuit scale can be reduced.

次に、基準軸射影回路１２は、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋ毎に、受信信号点Ｒ、基準点Ｓ、及びビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋのビット反転基準点Ｉｋを、予め決められた射影用の直線軸である第１の軸に射影して、第１の軸に射影された受信信号点の射影点（Ｒｉ，Ｒｑ）、基準点の射影点（Ｓｉ，Ｓｑ）、及びビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋのビット反転基準点の射影点（Ｉｋｉ，Ｉｋｑ）を求める処理を実行する。 Then, the reference axis projection circuit 12, for each bit b k as the calculation target bit LLR (L k), the bit b to be calculated subject to the received signal point R, the reference point S, and the bit LLR (L k) The k bit inversion reference point I k is projected onto a first axis which is a predetermined linear axis for projection, and the projection point (R i , R q ) of the received signal point projected onto the first axis. ), The projection point (S i , S q ) of the reference point, and the projection point (I ki , I kq ) of the bit inversion reference point of the bit b k to be calculated for the bit LLR (L k ) To do.

ここで、射影用の直線軸をＩ軸又はＱ軸とすることで、ビットＬＬＲ（Ｌｋ）を算出する際に、基準点及び各ビット反転基準点と受信信号点との間の距離の２乗を計算することなく、Ｉ軸成分又はＱ軸成分のいずれかのみを用いて加減算で計算するだけで済むため、ＬＬＲ算出過程の演算量を少なくすることができ、回路規模を小さくすることができる。 Here, by calculating the linear axis for projection as the I axis or the Q axis, when calculating the bit LLR (L k ), the reference point and the distance 2 between each bit inversion reference point and the received signal point Since only the I-axis component or the Q-axis component is used for the calculation without adding the power, the calculation amount in the LLR calculation process can be reduced and the circuit scale can be reduced. it can.

基準軸射影回路１２は、第１の軸を実軸（Ｉ軸）とすることができる。また、基準軸射影回路１２は、第１の軸を虚軸（Ｑ軸）とすることもできる。   The reference axis projection circuit 12 can set the first axis as a real axis (I axis). Further, the reference axis projection circuit 12 can also use the first axis as an imaginary axis (Q axis).

また、基準軸射影回路１２は、基準点の射影点（Ｓｉ，Ｓｑ）とビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋのビット反転基準点の射影点（Ｉｋｉ，Ｉｋｑ）とが、第１の軸上において重なる場合に、第１の軸と異なる第２の軸を新たな射影用の直線軸として選択するように構成してもよい。また、第２の軸として、第１の軸に直交する直線軸を選択してもよい。この場合、第１の軸を実軸（Ｉ軸）とし第２の軸を虚軸（Ｑ軸）としてもよく、逆に、第１の軸を虚軸（Ｑ軸）とし第２の軸を実軸（Ｉ軸）としてもよい。欧州の地上デジタル放送における変調方式においては、ビット列の各ビットに応じて一軸上（Ｉ軸又はＱ軸）に対応するように割り振られている（グレイマッピング法）場合は、各ビットに対応した軸とする。この場合には、選択した一軸上で射影点が重なる場合は、異なった軸、例えば、直交軸を選択するので、１つの軸上への射影点に基づいて処理する場合に比べて情報量が増え、ＬＬＲ算出結果であるビットＬＬＲ（Ｌｋ）の信頼度が向上する。 Further, the reference axis projection circuit 12 projects the projection point (I ki , I kq ) of the bit inversion reference point of the bit b k that is the calculation target of the projection point (S i , S q ) of the reference point and the bit LLR (L k ). ) Overlap on the first axis, a second axis different from the first axis may be selected as a new linear axis for projection. Further, a linear axis orthogonal to the first axis may be selected as the second axis. In this case, the first axis may be a real axis (I axis) and the second axis may be an imaginary axis (Q axis). Conversely, the first axis is an imaginary axis (Q axis) and the second axis is It may be a real axis (I axis). In the modulation system in terrestrial digital broadcasting in Europe, the axis corresponding to each bit when allocated so as to correspond to one axis (I axis or Q axis) according to each bit of the bit string (Gray mapping method) And In this case, if the projection points overlap on the selected one axis, a different axis, for example, an orthogonal axis is selected, so the amount of information is smaller than when processing is performed based on the projection point on one axis. As a result, the reliability of the bit LLR (L k ), which is the LLR calculation result, is improved.

さらに、基準軸射影回路１２は、第１の軸を基準点Ｓと各ビット反転基準点Ｉｋとを通る直線軸とすることもできる。この場合には、実軸及び虚軸の両方についての情報を併せて考慮することができるので、ＬＬＲ算出結果であるビットＬＬＲ（Ｌｋ）の信頼度が向上する。 Furthermore, the reference axis projection circuit 12 can also use the first axis as a linear axis passing through the reference point S and each bit inversion reference point Ik . In this case, since information about both the real axis and the imaginary axis can be considered together, the reliability of the bit LLR (L k ), which is the LLR calculation result, is improved.

例えば、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが１ビット目（ｋ＝１）のビットｂ１である場合には、基準軸射影回路１２は、図５（ａ）及び図６（ｃ）に示されるように、受信信号点Ｒ、基準点Ｓ、及びビットＬＬＲ（Ｌ１）の算出対象となるビットｂ１のビット反転基準点Ｉｋ＝Ｉ１をＩ軸に射影して、Ｉ軸に射影された受信信号点の射影点Ｒｉ、基準点の射影点Ｓｉ、及びビットｂ１のビット反転基準点の射影点Ｉ１ｉを求める処理を実行する。 For example, when the bit b k as the calculation target bit LLR (L k) is the bit b 1 of the first bit (k = 1), the reference axis projection circuit 12, FIG. 5 (a) and FIG. 6 As shown in (c), the received signal point R, the reference point S, and the bit inversion reference point I k = I 1 of the bit b 1 for which the bit LLR (L 1 ) is calculated are projected onto the I axis. Then, a process of obtaining a projection point R i of the received signal point projected onto the I axis, a projection point S i of the reference point, and a projection point I 1i of the bit inversion reference point of bit b 1 is executed.

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが２ビット目（ｋ＝２）のビットｂ２である場合には、基準軸射影回路１２は、図５（ｂ）及び図７（ｃ）に示されるように、受信信号点Ｒ、基準点Ｓ、及びビットＬＬＲ（Ｌ２）の算出対象となるビットｂ２のビット反転基準点Ｉｋ＝Ｉ２をＱ軸に射影して、Ｑ軸に射影された受信信号点の射影点Ｒｑ、基準点の射影点Ｓｑ、及びビットｂ２のビット反転基準点の射影点Ｉ２ｑを求める処理を実行する。 When the bit b k for which the bit LLR (L k ) is to be calculated is the second bit (k = 2), the bit b 2 , the reference axis projection circuit 12 performs the processing shown in FIGS. As shown in (c), the received signal point R, the reference point S, and the bit inversion reference point I k = I 2 of the bit b 2 for which the bit LLR (L 2 ) is calculated are projected onto the Q axis. Then, a process of obtaining a projection point R q of the received signal point projected onto the Q axis, a projection point S q of the reference point, and a projection point I 2q of the bit inversion reference point of bit b 2 is executed.

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが３ビット目（ｋ＝３）のビットｂ３である場合には、基準軸射影回路１２は、図５（ｃ）及び図８（ｃ）に示されるように、受信信号点Ｒ、基準点Ｓ、及びビットＬＬＲ（Ｌ３）の算出対象となるビットｂ３のビット反転基準点Ｉｋ＝Ｉ３をＩ軸に射影して、Ｉ軸に射影された受信信号点の射影点Ｒｉ、基準点の射影点Ｓｉ、及びビットｂ３のビット反転基準点の射影点Ｉ３ｉを求める処理を実行する。 Also, when the bit b k as the calculation target bit LLR (L k) is the bit b 3 of the third bit (k = 3), the reference axis projection circuit 12, and FIG. 5 (c) and 8 As shown in (c), the received signal point R, the reference point S, and the bit inversion reference point I k = I 3 of the bit b 3 for which the bit LLR (L 3 ) is calculated are projected onto the I axis. Then, a process of obtaining a projection point R i of the received signal point projected onto the I axis, a projection point S i of the reference point, and a projection point I 3i of the bit inversion reference point of bit b 3 is executed.

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが４ビット目（ｋ＝４）のビットｂ４である場合には、基準軸射影回路１２は、図５（ｄ）及び図９（ｃ）に示されるように、受信信号点Ｒ、基準点Ｓ、及びビットＬＬＲ（Ｌ４）の算出対象となるビットｂ４のビット反転基準点Ｉｋ＝Ｉ４をＱ軸に射影して、Ｑ軸に射影された受信信号点の射影点Ｒｑ、基準点の射影点Ｓｑ、及びビットｂ４のビット反転基準点の射影点Ｉ４ｑを求める処理を実行する。 Also, when the bit b k as the calculation target bit LLR (L k) is the bit b 4 to the fourth bit (k = 4) is the reference axis projection circuit 12, FIG. 5 (d) and 9 As shown in (c), the received signal point R, the reference point S, and the bit inversion reference point I k = I 4 of the bit b 4 to be calculated for the bit LLR (L 4 ) are projected onto the Q axis. Then, a process of obtaining a projection point R q of the received signal point projected onto the Q axis, a projection point S q of the reference point, and a projection point I 4q of the bit inversion reference point of bit b 4 is executed.

次に、軸内補正回路１３は、基準点の射影点（Ｓｉ，Ｓｑ）とビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋのビット反転基準点の射影点（Ｉｋｉ，Ｉｋｑ）との中点（Ｑ′，Ｉ′）を原点にする補正値Ｍを求め、受信信号点の射影点（Ｒｉ，Ｒｑ）を補正値Ｍに基づいて補正して、受信信号点の補正された射影点Ｌｋ′を算出する処理を実行する。具体的には、次式（３）の計算を行う。

Figure 0006177141
式（３）において、ｒ′は、受信信号点Ｒの射影点を示し、ｓ′ｋ，０，ｍｉｎ及びｓ′ｋ，１，ｍｉｎは、基準点及びビット反転基準点いずれかの射影点を示す。 Next, the in-axis correction circuit 13 projects the projection point (I ki , I q ) of the bit inversion reference point of the bit b k to be calculated as the projection point (S i , S q ) of the reference point and the bit LLR (L k ). kq ), a correction value M having a midpoint (Q ′, I ′) as the origin is obtained, the projection point (R i , R q ) of the reception signal point is corrected based on the correction value M, and the reception signal point The process of calculating the corrected projection point L k ′ is executed. Specifically, the following equation (3) is calculated.
Figure 0006177141
 In Equation (3), r ′ represents the projection point of the received signal point R, and s ′ k, 0, min and s ′ k, 1, min represent the projection point of either the reference point or the bit inversion reference point. Show.

例えば、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが１ビット目（ｋ＝１）のビットｂ１である場合には、軸内補正回路１３は、図５（ａ）及び図６（ｄ）に示されるように、基準点の射影点ＳｉとビットＬＬＲ（Ｌ１）の算出対象となるビットｂ１のビット反転基準点の射影点Ｉ１ｉとの中点Ｑ′を原点にする補正値Ｍを求め、受信信号点の射影点Ｒｉを補正値Ｍに基づいて補正して、受信信号点Ｒの補正された射影点Ｌｋ′＝Ｌ１′を算出する処理を実行する。 For example, when the bit b k as the calculation target bit LLR (L k) is the bit b 1 of the first bit (k = 1), the axis in the correction circuit 13, FIG. 5 (a) and FIG. 6 As shown in (d), the center point Q ′ between the projection point S i of the reference point and the projection point I 1i of the bit inversion reference point of the bit b 1 to be calculated of the bit LLR (L 1 ) is used as the origin. The correction value M to be obtained is obtained, the projection point R i of the reception signal point is corrected based on the correction value M, and the corrected projection point L k ′ = L 1 ′ of the reception signal point R is calculated. .

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが２ビット目（ｋ＝２）のビットｂ２である場合には、軸内補正回路１３は、図５（ｂ）及び図７（ｄ）に示されるように、基準点の射影点ＳｑとビットＬＬＲ（Ｌ２）の算出対象となるビットｂ２のビット反転基準点の射影点Ｉ２ｉとの中点Ｑ′を原点にする補正値Ｍを求め、受信信号点の射影点Ｒｑを補正値Ｍに基づいて補正して、受信信号点Ｒの補正された射影点Ｌｋ′＝Ｌ２′を算出する処理を実行する。 When the bit b k for which the bit LLR (L k ) is to be calculated is the second bit (k = 2), the bit b 2 , the in-axis correction circuit 13 performs the process shown in FIGS. As shown in (d), the center point Q ′ between the projection point S q of the reference point and the projection point I 2i of the bit inversion reference point of the bit b 2 to be calculated of the bit LLR (L 2 ) is used as the origin. The correction value M to be obtained is obtained, the projection point R q of the reception signal point is corrected based on the correction value M, and the corrected projection point L k ′ = L 2 ′ of the reception signal point R is calculated. .

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが３ビット目（ｋ＝３）のビットｂ３である場合には、軸内補正回路１３は、図５（ｃ）及び図８（ｄ）に示されるように、基準点の射影点ＳｉとビットＬＬＲ（Ｌ３）の算出対象となるビットｂ３のビット反転基準点の射影点Ｉ３ｉとの中点Ｑ′を原点にする補正値Ｍを求め、受信信号点の射影点Ｒｉを補正値Ｍに基づいて補正して、受信信号点Ｒの補正された射影点Ｌｋ′＝Ｌ３′を算出する処理を実行する。 Also, when the bit b k as the calculation target bit LLR (L k) is the bit b 3 of the third bit (k = 3) is in the correction circuit 13 axes, and FIG. 5 (c) and 8 As shown in (d), the midpoint Q ′ between the projection point S i of the reference point and the projection point I 3i of the bit inversion reference point of the bit b 3 to be calculated of the bit LLR (L 3 ) is used as the origin. The correction value M to be obtained is obtained, the projection point R i of the reception signal point is corrected based on the correction value M, and the corrected projection point L k ′ = L 3 ′ of the reception signal point R is calculated. .

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが４ビット目（ｋ＝４）のビットｂ４である場合には、軸内補正回路１３は、図５（ｂ）及び図９（ｄ）に示されるように、基準点の射影点ＳｑとビットＬＬＲ（Ｌ４）の算出対象となるビットｂ４のビット反転基準点の射影点Ｉ４ｑとの中点Ｑ′を原点にする補正値Ｍを求め、受信信号点の射影点Ｒｑを補正値Ｍに基づいて補正して、受信信号点Ｒの補正された射影点Ｌｋ′＝Ｌ４′を算出する処理を実行する。 In addition, when the bit b k for which the bit LLR (L k ) is to be calculated is the fourth bit (k = 4), the bit b 4 , the in-axis correction circuit 13 performs the process shown in FIGS. As shown in (d), the center point Q ′ between the projection point S q of the reference point and the projection point I 4q of the bit inversion reference point of the bit b 4 to be calculated of the bit LLR (L 4 ) is used as the origin. A correction value M to be obtained is obtained, the projection point R q of the reception signal point is corrected based on the correction value M, and a process of calculating the corrected projection point L k ′ = L 4 ′ of the reception signal point R is executed. .

次に、シンボル点間補正回路１４は、基準点の射影点（Ｓｉ，Ｓｑ）とビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋのビット反転基準点の射影点（Ｉｋｉ，Ｉｋｑ）との間の距離Ｑｋに応じて、軸内補正回路１３で算出された受信信号点の補正された射影点（Ｌｋ′）を正規化補正して（Ｑｍｉｎ／Ｑｋを乗算して）、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋのビットＬＬＲ（Ｌｋ）を算出する処理を実行する。具体的には、次式（４）の処理を実行する。

Figure 0006177141
式（４）において、Ｑｋは、基準点の射影点と各ビット反転基準点の射影点との間の距離を示し、Ｑｍｉｎは、送信シンボル点間の最小距離を示す。ここで、実装上の演算量を削減するために、Ｑｍｉｎ／Ｑｋを２のべき乗（ビットシフト演算）のみで近似してもよい。また、加算演算とビットシフト演算で除算を表現してもよい。さらに、外部から与えられるように構成してもよい。このような処理を行うことによって、高精度な誤り訂正を実行することができる。 Next, the inter-symbol point correction circuit 14 projects the reference point projection point (S i , S q ) and the bit inversion reference point projection point (I ki , I) of the bit b k to be calculated as the bit LLR (L k ). The corrected projection point (L k ′) of the received signal point calculated by the in-axis correction circuit 13 is normalized and corrected in accordance with the distance Q k between (I kq ) and (Q min / Q k multiplied with) executes a process of calculating the bit LLR (L k) calculated target bit b k of the bit LLR of (L k). Specifically, the processing of the following formula (4) is executed.
Figure 0006177141
 In Equation (4), Q k represents the distance between the projection point of the reference point and the projection point of each bit inversion reference point, and Q min represents the minimum distance between the transmission symbol points. Here, in order to reduce the amount of calculation in mounting, Q min / Q k may be approximated only by a power of 2 (bit shift calculation). Further, division may be expressed by addition operation and bit shift operation. Furthermore, it may be configured to be given from the outside. By performing such processing, highly accurate error correction can be performed.

例えば、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが１ビット目（ｋ＝１）のビットｂ１である場合には、シンボル点間補正回路１４は、図５（ａ）及び図６（ｄ）に示されるように、基準点の射影点Ｓｉとビットｂ１のビット反転基準点の射影点Ｉ１ｉとの間の距離Ｑｋ＝Ｑ１に応じて、軸内補正回路１３で算出された受信信号点の補正された射影点（Ｌ１′）を正規化補正して（Ｑｍｉｎ／Ｑ１を乗算して）、ビットｂ１のビットＬＬＲ（Ｌ１）を算出する処理を実行する。 For example, when the bit b k as the calculation target bit LLR (L k) is the bit b 1 of the first bit (k = 1), the inter-symbol point correction circuit 14, FIG. 5 (a) and FIG. As shown in FIG. 6 (d), the in-axis correction circuit 13 depends on the distance Q k = Q 1 between the projection point S i of the reference point and the projection point I 1i of the bit inversion reference point of bit b 1. in corrected projection point of the calculated received signal points (L 1 ') is normalized correction (by multiplying the Q min / Q 1), the process of calculating the bit b 1 of bit LLR (L 1) Execute.

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが２ビット目（ｋ＝２）のビットｂ２である場合には、シンボル点間補正回路１４は、図５（ｂ）及び図７（ｄ）に示されるように、基準点の射影点Ｓｑとビットｂ２のビット反転基準点の射影点Ｉ２ｑとの間の距離Ｑｋ＝Ｑ２に応じて、軸内補正回路１３で算出された受信信号点の補正された射影点（Ｌ２′）を正規化補正して（Ｑｍｉｎ／Ｑ２を乗算して）、ビットｂ２のビットＬＬＲ（Ｌ２）を算出する処理を実行する。 When the bit b k for which the bit LLR (L k ) is to be calculated is the second bit (k = 2), the bit b 2 , the inter-symbol point correction circuit 14 performs the processing shown in FIG. As shown in FIG. 7D , the in-axis correction circuit 13 corresponds to the distance Q k = Q 2 between the projection point S q of the reference point and the projection point I 2q of the bit inversion reference point of bit b 2. in corrected projection point of the calculated received signal point (L 2 ') is normalized correction (by multiplying the Q min / Q 2), the process of calculating the bit b 2 bit LLR (L 2) Execute.

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが３ビット目（ｋ＝３）のビットｂ３である場合には、シンボル点間補正回路１４は、図５（ｃ）及び図８（ｄ）に示されるように、基準点の射影点Ｓｉとビットｂ３のビット反転基準点の射影点Ｉ３ｉとの間の距離Ｑｋ＝Ｑ３に応じて、軸内補正回路１３で算出された受信信号点の補正された射影点（Ｌ３′）を正規化補正して（Ｑｍｉｎ／Ｑ３を乗算して）、ビットｂ３のビットＬＬＲ（Ｌ３）を算出する処理を実行する。 Also, when the bit b k as the calculation target bit LLR (L k) is the bit b 3 of the third bit (k = 3), the inter-symbol point correction circuit 14, and FIG. 5 (c) and FIG. As shown in FIG. 8 (d), the in-axis correction circuit 13 depends on the distance Q k = Q 3 between the projection point S i of the reference point and the projection point I 3i of the bit inversion reference point of bit b 3. in corrected projection point of the calculated received signal point (L 3 ') is normalized correction (by multiplying the Q min / Q 3), the process of calculating the bit LLR (L 3) of the bit b 3 Execute.

また、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋが４ビット目（ｋ＝４）のビットｂ４である場合には、シンボル点間補正回路１４は、図５（ｄ）及び図９（ｄ）に示されるように、基準点の射影点Ｓｑとビットｂ４のビット反転基準点の射影点Ｉ４ｑとの間の距離Ｑｋ＝Ｑ４に応じて、軸内補正回路１３で算出された受信信号点の補正された射影点（Ｌ４′）を正規化補正して（Ｑｍｉｎ／Ｑ４を乗算して）、ビットｂ４のビットＬＬＲ（Ｌ４）を算出する処理を実行する。 Also, when the bit b k as the calculation target bit LLR (L k) is the bit b 4 to the fourth bit (k = 4) is between the symbol point correction circuit 14, FIG. 5 (d) and FIG. As shown in FIG. 9 (d), the in-axis correction circuit 13 corresponds to the distance Q k = Q 4 between the projection point S q of the reference point and the projection point I 4q of the bit inversion reference point of bit b 4. Processing for calculating the bit LLR (L 4 ) of the bit b 4 by normalizing and correcting the corrected projection point (L 4 ′) of the received signal point calculated in ( 4 ) and multiplying by Q min / Q 4 Execute.

制御部１５は、ビット反転基準点検出回路１１がビット反転基準点Ｉｋを選択する処理、基準軸射影回路１２が前記受信信号点の射影点（Ｒｉ，Ｒｑ）、基準点の射影点（Ｓｉ，Ｓｑ）及びビット反転基準点の射影点（Ｉｋｉ，Ｉｋｑ）を求める処理、軸内補正回路１３が前記受信信号点の補正された射影点（Ｌｋ′）を算出する処理、並びに、シンボル点間補正回路１４がビットＬＬＲ（Ｌｋ）を算出する処理を、ビット列ｂ１ｂ２ｂ３ｂ４を構成する複数個のビットｂ１，ｂ２，ｂ３，ｂ４の各々について実行させる。 The control unit 15 is a process in which the bit inversion reference point detection circuit 11 selects the bit inversion reference point I k , the reference axis projection circuit 12 has a projection point (R i , R q ) of the received signal point, and a projection point of the reference point (S i , S q ) and the process of obtaining the projection point (I ki , I kq ) of the bit inversion reference point, the in-axis correction circuit 13 calculates the corrected projection point (L k ′) of the received signal point. process, as well as a process of symbol points between the correction circuit 14 calculates the bit LLR (L k), a plurality of bit b 1 constituting the bit sequence b 1 b 2 b 3 b 4 , b 2, b 3, b 4 For each of them.

図５（ａ）から（ｄ）に示される例では、４ビットのビット列ｂ１ｂ２ｂ３ｂ４の各ビットｂ１，ｂ２，ｂ３，ｂ４に対して基準点Ｓとビット反転基準点Ｉｋを検出後、基準点Ｓとビット反転基準点ＩｋをＩ軸又はＱ軸上に射影して、
基準点の射影点Ｓｉ＝＋３、
基準点の射影点Ｓｑ＝＋３、
ビット反転基準点Ｉｋの射影点Ｉ１ｉ＝Ｉ２ｑ＝−１、
ビット反転基準点Ｉｋの射影点Ｉ３ｉ＝Ｉ４ｑ＝＋１
を生成する。基準点の射影点（Ｓｉ，Ｓｑ）とビット反転基準点の射影点（Ｉ１ｉ，Ｉ２ｑ，Ｉ３ｉ，Ｉ４ｑ）との中点にＱ′軸又はＩ′軸があるものと仮定し、中点までの距離Ｍを算出すると、１ビット目及び２ビット目ではＭ＝＋１であり、３ビット目及び４ビット目ではＭ＝＋２である。この中点から受信信号点の射影点Ｒｉ又は受信信号点の射影点Ｒｑまでの距離をＬｋ′として算出する。その後、基準点の射影点（Ｓｉ，Ｓｑ）とビット反転基準点の射影点（Ｉ１ｉ，Ｉ２ｑ，Ｉ３ｉ，Ｉ４ｑ）との間の距離を送信シンボル点間の最小間隔で補正する。実施の形態１においては、補正値は、１ビット目及び２ビット目がＱｍｉｎ／Ｑｋ＝１／２であり、３ビット目及び４ビット目がＱｍｉｎ／Ｑｋ＝１である。以上より、ビットＬＬＲ（Ｌｋ）は、次式（５）で算出される。

Figure 0006177141
In the example shown in FIGS. 5A to 5D, the reference point S and bit inversion are performed for each bit b 1 , b 2 , b 3 , b 4 of the 4-bit bit string b 1 b 2 b 3 b 4. after detecting the reference point I k, the reference point S and the bit inversion reference point I k are projected on the I axis or Q axis,
Reference point projected point S i = + 3,
Reference point projection point S q = + 3,
Projection point I 1i = I 2q = −1 of bit inversion reference point I k
Projection point I 3i = I 4q = + 1 of bit inversion reference point I k
Is generated. It is assumed that there is a Q ′ axis or an I ′ axis at the midpoint between the projection point (S i , S q ) of the reference point and the projection point (I 1i , I 2q , I 3i , I 4q ) of the bit inversion reference point. When the distance M to the midpoint is calculated, M = + 1 for the first and second bits, and M = + 2 for the third and fourth bits. The distance from the midpoint to the projection point R i of the reception signal point or the projection point R q of the reception signal point is calculated as L k ′. After that, the distance between the projection point of the reference point (S i , S q ) and the projection point of the bit inversion reference point (I 1i , I 2q , I 3i , I 4q ) is corrected with the minimum interval between the transmission symbol points. To do. In the first embodiment, the correction value, first and second bits is Q min / Q k = 1/ 2, 3 bit and 4 bit is Q min / Q k = 1. As described above, the bit LLR (L k ) is calculated by the following equation (5).
Figure 0006177141

図６（ａ）から（ｄ）の場合には、式５は、次式６のようになる。

Figure 0006177141
In the case of FIG. 6A to FIG. 6D, the expression 5 becomes the following expression 6.
Figure 0006177141

式（６）における第１式及び第２式における値２による除算は、右方向に１ビットシフトで代用可能である。したがって、実施の形態１に係るＬＬＲ算出装置１及びＬＬＲ算出方法によれば、受信信号点Ｒと基準点Ｓとの間の距離の２乗と受信信号点Ｒと４ビットのビット反転基準点との間の距離の２乗の計算を、減算とビットシフトで実現することができ、よって、大幅に演算量を削減することができる。   The division by the value 2 in the first expression and the second expression in Expression (6) can be substituted by 1-bit shift in the right direction. Therefore, according to the LLR calculation apparatus 1 and the LLR calculation method according to Embodiment 1, the square of the distance between the reception signal point R and the reference point S, the reception signal point R, and the 4-bit bit inversion reference point The square of the distance between the two can be calculated by subtraction and bit shift, and the amount of calculation can be greatly reduced.

図１０は、実施の形態１に係るＬＬＲ算出装置１の動作を示すフローチャートである。図１０のフローチャートは、実施の形態１に係るＬＬＲ算出方法の一例でもある。図１０に示されるＬＬＲ算出方法は、誤り訂正符号化されたビット列が多値変調方式によって変調されて送信されたシンボル信号（１シンボルは複数個のビットｂ１ｂ２ｂ３ｂ４から構成される）を受信する毎に行われる。図１０に示されるＬＬＲ算出方法は、開始ステップＳＴ１と、基準点検出ステップＳＴ２と、初期設定ステップＳＴ３と、ビット反転基準点検出ステップＳＴ４と、基準軸射影ステップＳＴ５と、Ｉ軸方向射影シンボル点の重複確認ステップＳＴ６と、Ｉ軸方向射影シンボル点の重複がないときに実行されるＬＬＲ算出ステップＳＴ７と、Ｉ軸方向射影シンボル点の重複があるときに実行されるＬＬＲ算出ステップＳＴ８と、シンボル点間補正ステップＳＴ９と、ビット列最終反復確認ステップＳＴ１０と、カウントアップステップＳＴ１１と、終了ステップＳＴ１２とを有する。 FIG. 10 is a flowchart showing the operation of the LLR calculation apparatus 1 according to the first embodiment. The flowchart in FIG. 10 is also an example of the LLR calculation method according to the first embodiment. The LLR calculation method shown in FIG. 10 is a symbol signal (one symbol is composed of a plurality of bits b 1 b 2 b 3 b 4) in which a bit string that has been subjected to error correction coding is modulated by a multi-level modulation method. Every time it is received. The LLR calculation method shown in FIG. 10 includes a start step ST1, a reference point detection step ST2, an initial setting step ST3, a bit inversion reference point detection step ST4, a reference axis projection step ST5, and an I-axis direction projection symbol point. Duplication confirmation step ST6, LLR calculation step ST7 executed when there is no overlap of the I-axis direction projection symbol point, LLR calculation step ST8 executed when there is an overlap of the I-axis direction projection symbol point, It has a point correction step ST9, a bit string final repetition confirmation step ST10, a count-up step ST11, and an end step ST12.

開始ステップＳＴ１は、誤り訂正符号化されたビット列が多値変調方式によって変調されて送信されたシンボル信号を受信する毎に行われる。開始ステップＳＴ１の次に、処理は基準点検出ステップＳＴ２に進む。   The start step ST1 is performed every time a symbol signal is transmitted, in which a bit string that has been subjected to error correction coding is modulated by a multilevel modulation method. After the start step ST1, the process proceeds to a reference point detection step ST2.

基準点検出ステップＳＴ２において、基準点検出回路１０は、ＬＬＲ算出装置１に入力された受信信号に対応する位相平面上の点である受信信号点Ｒから、位相平面上における距離が最短である送信シンボル点を基準点Ｓとして検出する。基準点検出ステップＳＴ２の次に、処理は初期設定ステップＳＴ３に進む。   In the reference point detection step ST2, the reference point detection circuit 10 transmits the shortest distance on the phase plane from the reception signal point R that is a point on the phase plane corresponding to the reception signal input to the LLR calculation device 1. A symbol point is detected as a reference point S. After the reference point detection step ST2, the process proceeds to an initial setting step ST3.

初期設定ステップＳＴ３においては、制御部１５は、繰り返し変数ｋ（ｋは１以上の整数であって、１シンボルを構成する複数個のビットの内のビットの順番（ｋビット目）を示す。）を初期化して１にし、受信信号の多値変調ビット列数ｋｍａｘをビット列最終反復値（ｋの最大値であり、１シンボルが４ビットである場合には、ｋｍａｘは４である。）として、レジスタ又は記憶素子に設定し、記憶保持する。多値変調ビット列数ｋｍａｘを設定した後に、処理はビット反転基準点検出ステップＳＴ４に進む。なお、多値変調ビット列数ｋｍａｘは、予め設定され保持されていた値、又は、外部装置から若しくは入力装置からのユーザ操作によって与えられた値であってもよい。 In the initial setting step ST3, the control unit 15 repeats the variable k (k is an integer of 1 or more and indicates the order of bits (kth bit) among a plurality of bits constituting one symbol). Is set to 1 and the number k max of multi-value modulation bit strings of the received signal is set as a bit string final repetition value (k max is 4 when one symbol is 4 bits). , Set to a register or storage element and store and hold. After setting the multi-value modulation bit string number k max , the process proceeds to the bit inversion reference point detection step ST4. Note that the multi-value modulation bit string number k max may be a value set and held in advance, or a value given by a user operation from an external device or an input device.

ビット反転基準点検出ステップＳＴ４において、ビット反転基準点検出回路１１は、繰り返し変数ｋの示す値のビット（すなわち、１シンボルを構成するビット列の内のｋビット目のビット）をＬＬＲ算出対象として扱い、基準点Ｓを構成するビット列の内のｋビット目のビットを反転した送信シンボル点群（例えば、図１（ｂ）から（ｅ）の斜線領域）の中から１つをビット反転基準点として選択する。基準点Ｓを構成するビット列の内のｋビット目のビットを反転した送信シンボル点群の中から１つを選択する際に、ビット反転基準点検出回路１１は、対象シンボル点群で受信信号点との位相平面上における距離が最短である送信シンボル点を選択してもよいし、又は、基準点のビット列から該当ビットだけを反転した送信シンボル点を選択してもよい。ビット反転基準点検出後に、処理は基準軸射影ステップＳＴ５に進む。   In the bit inversion reference point detection step ST4, the bit inversion reference point detection circuit 11 treats the bit of the value indicated by the repetition variable k (that is, the kth bit in the bit string constituting one symbol) as an LLR calculation target. , One of the transmission symbol point groups (for example, hatched regions in FIGS. 1B to 1E) obtained by inverting the k-th bit in the bit string constituting the reference point S is used as a bit inversion reference point. select. When selecting one of the transmission symbol point groups obtained by inverting the k-th bit in the bit string constituting the reference point S, the bit inversion reference point detection circuit 11 uses the received symbol points in the target symbol point group. The transmission symbol point with the shortest distance on the phase plane may be selected, or the transmission symbol point obtained by inverting only the relevant bit from the bit string of the reference point may be selected. After the bit inversion reference point is detected, the process proceeds to reference axis projection step ST5.

基準軸射影ステップＳＴ５において、基準軸射影回路１２は、受信信号点Ｒと基準点Ｓとビット反転基準点を、ＬＬＲ算出対象であるビットに対応した軸上に射影する。この射影後に、処理はＩ軸方向射影シンボル点重複確認ステップＳＴ６に進む。ここで、受信信号点の射影点（Ｒｉ，Ｒｑ）と基準点の射影点（Ｓｉ，Ｓｑ）は、ＬＬＲ算出対象となるビットにかかわらず同じであるので、１回目の処理ステップ時に求めた値（Ｒｉ，Ｒｑ）及び（Ｓｉ，Ｓｑ）を、レジスタ又は記憶素子で記憶保持することで、演算量を削減するようにしてもよい。なお、ステップＳＴ５は、欧州の地上デジタル放送における変調方式（グレイマッピング法）を前提として、ビット列の各ビットに応じて一軸上（Ｉ軸又はＱ軸）に対応するように割り振られている場合の処理の一例として挙げて説明している。ただし、本発明は、Ｉ軸及びＱ軸以外の直線軸に射影してもよいし、また、基準点Ｓとビット反転基準点Ｉｋとを結ぶ直線軸に射影してもよい。 In the reference axis projection step ST5, the reference axis projection circuit 12 projects the reception signal point R, the reference point S, and the bit inversion reference point onto the axis corresponding to the bit that is the LLR calculation target. After this projection, the process proceeds to I-axis direction projection symbol point duplication confirmation step ST6. Here, the projection point (R i , R q ) of the received signal point and the projection point (S i , S q ) of the reference point are the same regardless of the bit that is the LLR calculation target, so that the first processing step The calculation amount may be reduced by storing and holding values (R i , R q ) and (S i , S q ) obtained at times in a register or a storage element. Note that step ST5 is based on the assumption that the modulation method (gray mapping method) in European terrestrial digital broadcasting is assigned to correspond to one axis (I axis or Q axis) according to each bit of the bit string. This is described as an example of processing. However, the present invention may be projected on the linear axis other than the I and Q axes, may also be projected onto the linear axis connecting the reference point S and the bit inversion reference point I k.

Ｉ軸方向射影シンボル点重複確認ステップＳＴ６において、制御部１５は、Ｉ軸上に射影された基準点の射影点Ｓｉとビット反転基準点の射影点Ｉｋｉが同じ点にあるかどうかを判定する。Ｉ軸方向射影シンボル点の重複が無いと判定したときは、処理はＬＬＲ算出ステップＳＴ７に進み、Ｉ軸方向射影シンボル点の重複が有ると判定であるときには、処理はＬＬＲ算出ステップＳＴ８に進む。 In the I-axis direction projected symbol point duplication confirmation step ST6, the control unit 15 determines whether the projected point S i of the reference point projected on the I axis and the projected point I ki of the bit inversion reference point are at the same point. To do. When it is determined that there is no overlap of the I-axis direction projection symbol point, the process proceeds to LLR calculation step ST7, and when it is determined that there is an overlap of the I-axis direction projection symbol point, the process proceeds to LLR calculation step ST8.

Ｉ軸方向射影シンボル点の重複が無いと判定したとき、軸内補正回路１３は、各々基準点の射影点（Ｓｉ，Ｓｑ）とビット反転基準点の射影点（Ｉｋｉ，Ｉｋｑ）の中点Ｍが原点となるように、受信信号点の射影点（Ｒｉ，Ｒｑ）と差分をとって前述の式（３）に示されるような補正を行う。 When it is determined that the I-axis direction projection symbol points do not overlap, the in-axis correction circuit 13 respectively projects the reference point projection points (S i , S q ) and the bit inversion reference point projection points (I ki , I kq ). The correction as shown in the above equation (3) is performed by taking the difference from the projection point (R i , R q ) of the received signal point so that the middle point M becomes the origin.

シンボル点間補正ステップＳＴ９において、シンボル点間補正回路１４は、ＬＬＲ算出ステップＳＴ７及びＳＴ８で算出した値に対して、基準点の射影点（Ｓｉ，Ｓｑ）とビット反転基準点の射影点（Ｉｋｉ，Ｉｋｑ）との間の距離に応じて受信信号点の射影点（Ｒｉ，Ｒｑ）を前述の式（４）に示されるように（Ｑｍｉｎ／Ｑｋ）を乗算することで正規化補正を行う。なお、シンボル点間補正回路１４は、演算量を削減するために、（Ｑｍｉｎ／Ｑｋ）を、２のべき乗（ビットシフト演算）のみで近似してもよい。また、シンボル点間補正回路１４は、加算演算とビットシフト演算を用いて演算量は増加するが２のべき乗のみで近似するよりも近似精度を向上するようにしてもよい。さらに、シンボル点間補正回路１４は、（Ｑｍｉｎ／Ｑｋ）の値を外部から受け取るように構成してもよい。正規化補正後に、処理はビット列最終反復確認ステップＳＴ１０に進む。 In the inter-symbol point correction step ST9, the inter-symbol point correction circuit 14 applies the projection point (S i , S q ) of the reference point and the projection point of the bit inversion reference point to the values calculated in the LLR calculation steps ST7 and ST8. The projected point (R i , R q ) of the received signal point is multiplied by (Q min / Q k ) as shown in the above equation (4) according to the distance between (I ki , I kq ). Normalization correction. Note that the inter-symbol point correction circuit 14 may approximate (Q min / Q k ) by only a power of 2 (bit shift calculation) in order to reduce the amount of calculation. Further, the inter-symbol point correction circuit 14 may improve the approximation accuracy rather than approximating only by a power of 2 using an addition operation and a bit shift operation. Furthermore, the inter-symbol point correction circuit 14 may be configured to receive the value of (Q min / Q k ) from the outside. After normalization correction, the process proceeds to the bit string final iteration confirmation step ST10.

ビット列最終反復確認ステップＳＴ１０において、制御部１５は、繰り返し変数ｋが初期設定ステップＳＴ３で設定されたビット列最終反復値ｋｍａｘに到達したかを判定する。繰り返し変数ｋが設定されたビット列最終反復値ｋｍａｘに到達していない場合は、処理はカウントアップステップＳＴ１１に進み、繰り返し変数ｋに１を加算（インクリメント）し、その後、処理はビット反転基準点検出ステップＳＴ４に進む。繰り返し変数ｋが設定されたビット列最終反復値ｋｍａｘに到達した場合は、処理は終了ステップＳＴ１２に進む。 In the bit string final repetition confirmation step ST10, the control unit 15 determines whether the repetition variable k has reached the bit string final repetition value k max set in the initial setting step ST3. If the repetition variable k has not reached the set bit string final repetition value k max , the process proceeds to the count-up step ST11, and 1 is added (incremented) to the repetition variable k. Proceed to exit step ST4. If the bit string final repetition value k max in which the repetition variable k is set is reached, the process proceeds to an end step ST12.

以上に説明したように、実施の形態１に係るＬＬＲ算出装置１及びＬＬＲ算出方法によれば、受信信号点Ｒと基準点Ｓと各ビット反転基準点Ｉｋを各々一軸上（Ｉ軸又はＱ軸）に射影し、基準点の射影点Ｓｉと各ビット反転基準点の射影点Ｉｋｉの中点が原点となるように受信信号点の射影点Ｒｉと当該射影点の中点Ｍとの差分をとる補正と、基準点の射影点Ｓｉと各ビット反転基準点の射影点Ｉｋｉとの間の距離に応じて受信信号点の射影点Ｒｉを正規化する補正とを行うことで、２点の間の距離の２乗の差分を計算する必要がなくなる。この結果、ＬＬＲ算出処理における演算量を大幅に削減することができる。 As described above, according to the LLR calculation apparatus 1 and the LLR calculation method according to the first embodiment, the reception signal point R, the reference point S, and each bit inversion reference point I k are each on one axis (I axis or Q axis). The projected point Ri of the received signal point and the midpoint M of the projected point so that the midpoint of the projected point S i of the reference point and the projected point I ki of each bit inversion reference point is the origin. By performing a correction for taking the difference and a correction for normalizing the projection point R i of the received signal point according to the distance between the projection point S i of the reference point and the projection point I ki of each bit inversion reference point There is no need to calculate the square difference of the distance between the two points. As a result, the calculation amount in the LLR calculation process can be greatly reduced.

実施の形態２．
図１１は、本発明の実施の形態２に係るＬＬＲ算出装置３の構成を概略的に示すブロック図である。ＬＬＲ算出装置３は、実施の形態２に係るＬＬＲ算出方法を実施することができる装置である。ＬＬＲ算出装置３は、誤り訂正符号化されたビット列ｂ１ｂ２ｂ３ｂ４が多値変調方式によって変調されて送信された信号である受信信号が入力され、該受信信号からビットＬＬＲ（Ｌｋ）を算出する装置である。図１１に示されるように、ＬＬＲ算出装置３は、基準点検出回路１０と、ビット反転基準点検出回路１１と、基準軸射影回路１２と、軸内補正回路１３と、シンボル点間補正回路１４と、２次元ＬＬＲ算出回路１６と、各構成要素１１〜１４及び１６の動作を制御する制御部１７とを有する。ＬＬＲ算出装置３には、誤り訂正符号化されたビット列が多値変調方式によって変調されて送信された信号が入力される。図１１において、図４に示されたＬＬＲ算出装置１の構成要素と同じ又は対応する構成要素には、図４の構成要素に付した符号と同じ符号を付与する。実施の形態２に係るＬＬＲ算出装置３は、シンボル点間補正回路１４の後段に２次元ＬＬＲ算出回路１６を有する点、及び、制御部１７による制御内容の点において、上記実施の形態１に係るＬＬＲ算出装置１と異なる。 Embodiment 2. FIG.
FIG. 11 is a block diagram schematically showing a configuration of the LLR calculation apparatus 3 according to Embodiment 2 of the present invention. The LLR calculation device 3 is a device that can perform the LLR calculation method according to the second embodiment. The LLR calculation device 3 receives a received signal that is a signal that is transmitted after the error correction-coded bit string b 1 b 2 b 3 b 4 is modulated by the multi-level modulation method, and receives the bit LLR (L k ). As shown in FIG. 11, the LLR calculation apparatus 3 includes a reference point detection circuit 10, a bit inversion reference point detection circuit 11, a reference axis projection circuit 12, an in-axis correction circuit 13, and a symbol point correction circuit 14. And a two-dimensional LLR calculation circuit 16 and a control unit 17 that controls the operations of the constituent elements 11 to 14 and 16. The LLR calculation device 3 is input with a signal obtained by modulating a bit string that has been subjected to error correction coding by a multi-level modulation method. In FIG. 11, the same reference numerals as the constituent elements in FIG. 4 are assigned to the same or corresponding constituent elements of the LLR calculation apparatus 1 shown in FIG. 4. The LLR calculation device 3 according to the second embodiment has the two-dimensional LLR calculation circuit 16 subsequent to the inter-symbol point correction circuit 14 and the control content by the control unit 17 according to the first embodiment. Different from the LLR calculation device 1.

ＬＬＲ算出装置３において、基準点検出回路１０は、位相平面上に配列された予め決められた個数の送信シンボル点の内、受信信号を示す受信信号点Ｒからの距離が最短となる送信シンボル点を基準点Ｓとして選択する。   In the LLR calculating device 3, the reference point detection circuit 10 transmits the transmission symbol point having the shortest distance from the reception signal point R indicating the reception signal among the predetermined number of transmission symbol points arranged on the phase plane. Is selected as the reference point S.

ビット反転基準点検出回路１１は、予め決められた複数個の送信シンボル点の各々を構成するビット列ｂ１ｂ２ｂ３ｂ４の内の、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋ毎に、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋの値が異なる任意の送信シンボル点をビット反転基準点Ｉｋとして選択する処理を実行する。 The bit inversion reference point detection circuit 11 calculates the bit LLR (L k ) of the bit string b 1 b 2 b 3 b 4 constituting each of a plurality of predetermined transmission symbol points. For each k , a process of selecting an arbitrary transmission symbol point having a different value of the bit b k for which the bit LLR (L k ) is to be calculated as the bit inversion reference point I k is executed.

基準軸射影回路１２は、ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋ毎に、受信信号点Ｒ、前記基準点Ｓ、及び前記ビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋのビット反転基準点Ｉｋを、予め決められた射影用の直線軸である第１の軸及び該第１の軸に直交する第２の軸の一方、若しくは、両方に射影して、第１の軸及び第２の軸の少なくとも一方に射影された受信信号点の射影点Ｒｉ，Ｒｑ、基準点の射影点Ｓｉ，Ｓｑ、及びビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋの前記ビット反転基準点の射影点（Ｉｋｉ，Ｉｋｑ）を取得する処理を実行する。 Reference axis projection circuit 12, for each bit b k as the calculation target bit LLR (L k), the bit b k as the calculation target of the received signal point R, the reference point S, and the bit LLR (L k) the bit inversion reference point I k, one of the second axis orthogonal to the first axis and the first axis is a predetermined linear axis for projection, or are projected both, first Bits for which the projection points R i and R q of the received signal points projected onto at least one of the axis of the second axis and the second axis, the projection points S i and S q of the reference point, and the bit LLR (L k ) A process of obtaining a projection point (I ki , I kq ) of the bit inversion reference point of b k is executed.

軸内補正回路１３は、基準点の射影点Ｓｉ，ＳｑとビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋのビット反転基準点の射影点Ｉｋｉ，Ｉｋｑとの中点Ｑ′，Ｉ′を原点にする補正値（Ｍ）を求め、受信信号点の射影点Ｒｉ，Ｒｑを前記補正値（Ｍ）に基づいて補正して、受信信号点の補正された射影点（Ｌｋ′）を算出する処理を実行する。 The in-axis correction circuit 13 generates a midpoint Q between the projection points S i and S q of the reference point and the projection points I ki and I kq of the bit inversion reference point of the bit b k to be calculated for the bit LLR (L k ). A correction value (M) with ′ and I ′ as the origin is obtained, and the projection points R i and R q of the reception signal point are corrected based on the correction value (M), thereby correcting the projection point of the reception signal point. A process of calculating (L k ′) is executed.

シンボル点間補正回路１４は、基準点の射影点Ｓｉ，ＳｑとビットＬＬＲ（Ｌｋ）の算出対象となるビットｂｋのビット反転基準点の射影点Ｉｋｉ，Ｉｋｑとの間の距離Ｑｋに応じて、軸内補正回路１３で算出された受信信号点の補正された射影点（Ｌｋ′）を正規化補正して（×Ｑｍｉｎ／Ｑｋ）、ビットＬＬＲ（Ｌｋ）の算出対象となる前記ビット（ｂｋ）のビットＬＬＲ（Ｌｋ）を算出する処理を実行する。 The inter-symbol point correction circuit 14 is used to calculate the projection points S i and S q of the reference point and the projection points I ki and I kq of the bit inversion reference point of the bit b k to be calculated of the bit LLR (L k ). According to the distance Q k , the corrected projection point (L k ′) of the received signal point calculated by the in-axis correction circuit 13 is normalized and corrected (× Q min / Q k ), and the bit LLR (L k the bit to be calculated subject to) (bit LLR (L k of b k)) executes processing for calculating.

２次元ＬＬＲ算出回路１６は、基準軸射影回路１２で射影した一軸で軸内補正回路１３とシンボル点間補正回路１４で補正した値と、基準軸射影回路１２で射影した一軸の直交軸に対して射影した各射影点から軸内補正回路１３とシンボル点間補正回路１４で補正した値とを入力とし、これら入力された２つの値を均等に重み付け加算した値をＬＬＲ算出結果（２次元ビットＬＬＲ）として出力する。具体的には、２次元ＬＬＲ算出回路１６は、シンボル点間補正回路１４で算出された、第１の軸上の受信信号点の補正された射影点（Ｒｉ−Ｍ）及び第２上の軸の前記受信信号点の補正された射影点（Ｒｑ−Ｍ）とを重み付け加算した値をビットＬＬＲ（Ｌｋ）（２次元ビットＬＬＲ）として出力する。 The two-dimensional LLR calculation circuit 16 calculates the value corrected by the in-axis correction circuit 13 and the inter-symbol point correction circuit 14 by one axis projected by the reference axis projection circuit 12 and the one axis orthogonal axis projected by the reference axis projection circuit 12. The values corrected by the in-axis correction circuit 13 and the inter-symbol point correction circuit 14 from each projected point are input, and a value obtained by equally weighting and adding these two values is obtained as an LLR calculation result (two-dimensional bit). LLR). Specifically, the two-dimensional LLR calculation circuit 16 calculates the corrected projection point (R i −M) of the reception signal point on the first axis calculated by the inter-symbol point correction circuit 14 and the second upper point. A value obtained by weighting and adding the corrected projection point (R q −M) of the reception signal point on the axis is output as a bit LLR (L k ) (two-dimensional bit LLR).

制御部１７は、ビット反転基準点検出回路１１がビット反転基準点の射影点Ｉｋｉ，Ｉｋｑを求める処理、軸内補正回路１３が受信信号点の補正された射影点（Ｌｋ′）を算出する処理、前記シンボル点間補正回路１４がビットＬＬＲ（Ｌｋ）を算出する処理、並びに、２次元ＬＬＲ算出回路１６を、ビット列ｂ１ｂ２ｂ３ｂ４を構成する複数個のビットｂｋの各々について実行させる。 In the control unit 17, the bit inversion reference point detection circuit 11 obtains the projection points I ki and I kq of the bit inversion reference point, and the in-axis correction circuit 13 calculates the corrected projection point (L k ′) of the reception signal point. A process of calculating, a process of calculating the bit LLR (L k ) by the inter-symbol point correction circuit 14, and a two-dimensional LLR calculation circuit 16 of a plurality of bits b constituting the bit string b 1 b 2 b 3 b 4 Run for each of k .

図１２は、実施の形態２に係るＬＬＲ算出装置３の動作を示すフローチャートである。図１２のフローチャートは、実施の形態２に係るＬＬＲ算出方法の一例でもある。図１２に示されるＬＬＲ算出方法は、誤り訂正符号化されたビット列が多値変調方式によって変調されて送信されたシンボル信号（１シンボルは複数個のビット、例えば、４個のビットｂ１ｂ２ｂ３ｂ４から構成される）を受信する毎に行われる。図１２において、図１０に示したＬＬＲ算出装置１の処理ステップと同じ又は対応する処理ステップには、図１０におけるステップ番号と同じステップ番号を付与する。 FIG. 12 is a flowchart showing the operation of the LLR calculation apparatus 3 according to the second embodiment. The flowchart of FIG. 12 is also an example of the LLR calculation method according to the second embodiment. In the LLR calculation method shown in FIG. 12, a symbol signal (one symbol is a plurality of bits, for example, 4 bits b 1 b 2 ), which is transmitted after the error correction coded bit string is modulated by the multi-level modulation method. b 3 b 4 ). In FIG. 12, the same step number as the step number in FIG. 10 is assigned to the same or corresponding processing step as the processing step of the LLR calculating apparatus 1 shown in FIG.

実施の形態２に係るＬＬＲ算出方法は、図１２のステップＳＴ２５においてＩ軸上の射影点Ｓｉ，Ｉｋｉ，ＲｉとＱ軸上の射影点Ｓｑ，Ｉｋｑ，Ｒｑの両方を取得する点が、図４のステップＳＴ５においてＩ軸上の射影点とＱ軸上の射影点の一方を取得する実施の形態１に係るＬＬＲ算出方法と異なる。ただし、射影点Ｓｉ，Ｒｉ，Ｓｑ，Ｒｑは、ｋ＝１，２，３，４の各々において同じ値であるので、制御部１７は、１ビット目（ｋ＝１）の処理において、射影点Ｓｉ，Ｒｉ，Ｓｑ，Ｒｑの値を、内蔵するレジスタなどの記憶部に記憶しておき、２ビット目（ｋ＝２）以降の処理において、Ｉ軸上の射影点ＩｋｉとＱ軸上の射影点Ｉｋｑのみを求めるようにしてもよい。 The LLR calculation method according to Embodiment 2 acquires both the projection points S i , I ki , R i on the I axis and the projection points S q , I kq , R q on the Q axis in step ST25 of FIG. This is different from the LLR calculation method according to the first embodiment in which one of the projection point on the I axis and the projection point on the Q axis is acquired in step ST5 of FIG. However, since the projection points S i , R i , S q , and R q have the same value in each of k = 1, 2, 3, and 4, the control unit 17 performs processing for the first bit (k = 1). , The values of the projection points S i , R i , S q , R q are stored in a storage unit such as a built-in register, and the projection on the I-axis is performed in the processing after the second bit (k = 2). Only the point I ki and the projection point I kq on the Q axis may be obtained.

また、実施の形態２に係るＬＬＲ算出方法は、図１２のステップＳＴ６におけるＩ軸上の基準点の射影点ＳｉとＩ軸上のビット反転基準点の射影点Ｉｋｉとが重なるか否かの判定だけでなく、図１２のステップＳＴ２７におけるＱ軸上の基準点の射影点ＳｑとＱ軸上のビット反転基準点の射影点Ｉｋｑとが重なるか否かの判定をも行う点において、図１２のステップＳＴ２７の処理を行わない実施の形態１に係るＬＬＲ算出方法と異なる。 Also, the LLR calculation method according to Embodiment 2 determines whether or not the projection point S i of the reference point on the I axis and the projection point I ki of the bit reversal reference point on the I axis overlap in step ST6 of FIG. determination as well, in that also performs determination of whether or not the projected point I kq bits inversion reference point on the projection point S q and Q-axis of the reference point on the Q-axis in step ST27 in FIG. 12 overlap This differs from the LLR calculation method according to the first embodiment in which the process of step ST27 in FIG. 12 is not performed.

さらに、実施の形態２に係るＬＬＲ算出方法は、ＬＬＲ算出装置３が、ステップＳＴ６とＳＴ２７の両方において、基準点の射影点Ｓｉ，Ｓｑとビット反転基準点の射影点Ｉｋｉ，Ｉｋｑとにシンボル点の重複が無いと判定されたときに、ＬＬＲ算出ステップＳＴ２８を行う点において、実施の形態１に係るＬＬＲ算出方法と異なる。図１２に示されるように、Ｑ軸方向射影シンボル点重複確認ステップＳＴ２７において、制御部１７は、Ｉ軸方向射影シンボル点重複確認ステップＳＴ６においてＩ軸上に射影された基準点の射影点Ｓｉとビット反転基準点の射影点Ｉｋｉが同じ点にないと判定された後に、Ｑ軸上に射影された基準点の射影点Ｓｑとビット反転基準点の射影点Ｉｋｑが同じ点にあるかどうかを判定する。制御部１７がＱ軸方向射影シンボル点の重複が無いと判定したときは、処理はＬＬＲ算出ステップＳＴ２８に進み、制御部１７がＱ軸方向射影シンボル点の重複が有りと判定したときは、処理はＬＬＲ算出ステップＳＴ７に進む。 Further, in the LLR calculation method according to the second embodiment, the LLR calculation device 3 causes the projection points S i and S q of the reference point and the projection points I ki and I kq of the bit inversion reference point in both steps ST6 and ST27. Are different from the LLR calculation method according to the first embodiment in that the LLR calculation step ST28 is performed when it is determined that there is no symbol point overlap. As shown in FIG. 12, in the Q-axis direction projection symbol point duplication confirmation step ST27, the control unit 17 projects the reference point projection point S i projected on the I-axis in the I-axis direction projection symbol point duplication confirmation step ST6. after projection point I ki bit inversion reference point is not determined to be in the same point as the projection point I kq of the projection point S q and bit inversion reference point of the projected reference points on the Q axis are in the same point Determine whether or not. When the control unit 17 determines that there are no overlapping Q-axis direction projection symbol points, the process proceeds to LLR calculation step ST28, and when the control unit 17 determines that there is an overlap between Q-axis direction projection symbol points, Advances to LLR calculation step ST7.

Ｉ軸上及びＱ軸上の両方において、基準点の射影点Ｓｉ，Ｓｑとビット反転基準点の射影点Ｉｋｉ，Ｉｋｑとにシンボル点の重複が無いと判定されたときのＬＬＲ算出ステップＳＴ２８は、Ｉ軸への射影点ＳｉとＩｋｉの中点と受信信号点の射影点Ｒｉとの差分をとって式（３）に示される補正を行って得られた第１の値と、Ｑ軸への射影点ＳｑとＩｋｑの中点と受信信号点の射影点Ｒｑと差分をとって式（３）に示される補正を行って得られた第２の値とを、均等に重み付けして加算した値Ｌｋ′を、ＬＬＲ算出結果とする。ステップＳＴ２８のＬＬＲ算出方法は、次式（７）で表される。

Figure 0006177141
LLR calculation when it is determined that there is no symbol point overlap between the projected points S i and S q of the reference point and the projected points I ki and I kq of the bit inversion reference point on both the I axis and the Q axis Step ST28 is the first obtained by performing the correction shown in equation (3) by taking the difference between the midpoint of the projected points S i and I ki on the I axis and the projected point R i of the received signal point. And the second value obtained by performing the correction shown in the equation (3) by taking the difference between the value and the midpoint of the projection points S q and I kq on the Q axis and the projection point R q of the received signal point A value Lk ′ obtained by equally weighting and adding is used as an LLR calculation result. The LLR calculation method in step ST28 is expressed by the following equation (7).
Figure 0006177141

上記処理をすることで、２次元の情報を考慮するため、一軸上の１次元の情報だけを扱う手法に比べＬＬＲ算出結果の信頼性の精度が向上する。ただし、実施の形態２に係るＬＬＲ算出方法は、実施の形態１で説明したような欧州の地上デジタル放送における変調方式で適用しているグレイマッピング法（変調ビット列の各ビットに応じて一軸上（Ｉ軸又はＱ軸）に対応するように割り振られている）における実施の形態１以上の信頼性の精度の向上は期待できない。   By performing the above processing, since the two-dimensional information is taken into account, the accuracy of the reliability of the LLR calculation result is improved as compared with a method that handles only one-dimensional information on one axis. However, the LLR calculation method according to the second embodiment is a gray mapping method (one axis corresponding to each bit of the modulation bit string) applied in the modulation method in European terrestrial digital broadcasting as described in the first embodiment ( (I-axis or Q-axis) is assigned so as to correspond to the first embodiment), and improvement in the reliability accuracy of the first embodiment or higher cannot be expected.

以上に説明したように、実施の形態２に係るＬＬＲ算出装置３及びＬＬＲ算出方法によれば、２次元の情報を考慮することで一軸だけではなく、その直交軸の情報量も加えることができるので、ＬＬＲ算出結果の精度を向上させることができる。   As described above, according to the LLR calculation device 3 and the LLR calculation method according to the second embodiment, it is possible to add not only one axis but also the amount of information on the orthogonal axis by considering two-dimensional information. Therefore, the accuracy of the LLR calculation result can be improved.

変形例．
上記実施の形態１及び２に係るＬＬＲ算出装置及びＬＬＲ算出方法の機能の一部は、ハードウェア構成で実現されてもよいし、或いは、ＣＰＵを含むマイクロプロセッサにより実行されるコンピュータプログラムで実現されてもよい。当該機能の一部がコンピュータプログラムで実現される場合には、マイクロプロセッサは、コンピュータ読み取り可能な記録媒体（例えば、光ディスク、磁気記録媒体又はフラッシュメモリ）から当該コンピュータプログラムをロードして実行することによって当該機能の一部を実現することができる。 Modified example.
A part of the functions of the LLR calculation apparatus and the LLR calculation method according to the first and second embodiments may be realized by a hardware configuration or a computer program executed by a microprocessor including a CPU. May be. When a part of the function is realized by a computer program, the microprocessor loads and executes the computer program from a computer-readable recording medium (for example, an optical disk, a magnetic recording medium, or a flash memory). Part of the function can be realized.

例えば、実施の形態１に係るＬＬＲ算出方法をコンピュータで実行可能なプログラムで実現する場合には、対数尤度比算出用プログラムは、コンピュータに、
実軸及び虚軸を有する複素平面である位相平面上に配列された予め決められた個数の送信シンボル点の内、前記受信信号を示す受信信号点からの距離が最短となる送信シンボル点を基準点として選択する基準点検出機能と、
前記予め決められた複数個の送信シンボル点の各々を構成するビット列の内の、前記ビット対数尤度比の算出対象となるビット毎に、前記ビット対数尤度比の算出対象となるビットの値が異なる任意の送信シンボル点をビット反転基準点として選択する処理を実行するビット反転基準点検出機能と、
前記ビット対数尤度比の算出対象となる前記ビット毎に、前記受信信号点、前記基準点、及び前記ビット対数尤度比の算出対象となる前記ビットの前記ビット反転基準点を、予め決められた射影用の直線軸である第１の軸に射影して、前記第１の軸に射影された前記受信信号点の射影点、前記基準点の射影点、及び前記ビット対数尤度比の算出対象となる前記ビットの前記ビット反転基準点の射影点を取得する処理を実行する基準軸射影機能と、
前記基準点の射影点と前記ビット対数尤度比の算出対象となる前記ビットの前記ビット反転基準点の射影点との中点を原点にする補正値を求め、前記受信信号点の射影点を前記補正値に基づいて補正して、前記受信信号点の補正された射影点を算出する処理を実行する軸内補正機能と、
前記基準点の射影点と前記ビット対数尤度比の算出対象となる前記ビットの前記ビット反転基準点の射影点との間の距離に応じて、前記軸内補正機能によって算出された前記受信信号点の前記補正された射影点を正規化補正して、前記ビット対数尤度比の算出対象となる前記ビットのビット対数尤度比を算出する処理を実行するシンボル点間補正機能と、
前記ビット反転基準点検出機能によって前記ビット反転基準点の射影点を求める処理、前記軸内補正機能によって前記受信信号点の補正された射影点を算出する処理、並びに、前記シンボル点間補正機能によって前記ビット対数尤度比を算出する処理を、前記ビット列を構成する複数個のビットの各々について実行させる機能とを、
実現させるプログラムである。 For example, when the LLR calculation method according to Embodiment 1 is realized by a computer-executable program, the log likelihood ratio calculation program is stored in the computer.
Of a predetermined number of transmission symbol points arranged on a phase plane that is a complex plane having a real axis and an imaginary axis, a transmission symbol point having the shortest distance from the reception signal point indicating the reception signal is used as a reference. A reference point detection function to select as a point;
The value of the bit for which the bit log likelihood ratio is to be calculated for each bit that is to be calculated for the bit log likelihood ratio in the bit string constituting each of the predetermined plurality of transmission symbol points A bit inversion reference point detection function for executing processing for selecting any transmission symbol point having a different bit reference reference point,
The received signal point, the reference point, and the bit inversion reference point of the bit for which the bit log likelihood ratio is to be calculated are determined in advance for each of the bits for which the bit log likelihood ratio is to be calculated. Projecting to the first axis that is the linear axis for projection, calculating the projected point of the received signal point projected to the first axis, the projected point of the reference point, and the bit log likelihood ratio A reference axis projection function for executing a process of acquiring a projection point of the bit reversal reference point of the target bit;
A correction value having a midpoint between a projection point of the reference point and a projection point of the bit inversion reference point of the bit to be calculated for the bit log likelihood ratio is obtained, and a projection point of the reception signal point is obtained. An in-axis correction function that performs processing based on the correction value to calculate a corrected projection point of the received signal point;
The received signal calculated by the in-axis correction function according to the distance between the projected point of the reference point and the projected point of the bit inversion reference point of the bit to be calculated for the bit log likelihood ratio A symbol inter-point correction function for performing a process of calculating the bit log likelihood ratio of the bit to be calculated by normalizing and correcting the corrected projection point of the point;
By the process of obtaining the projection point of the bit inversion reference point by the bit inversion reference point detection function, the process of calculating the corrected projection point of the reception signal point by the in-axis correction function, and the correction function between symbol points A function of executing the process of calculating the bit log likelihood ratio for each of a plurality of bits constituting the bit string,
This is a program to be realized.

また、実施の形態２に係るＬＬＲ算出方法をコンピュータで実行可能なプログラムで実現する場合には、対数尤度比算出用プログラムは、コンピュータに、
実軸及び虚軸を有する複素平面である位相平面上に配列された予め決められた個数の送信シンボル点の内、前記受信信号を示す受信信号点からの距離が最短となる送信シンボル点を基準点として選択する基準点検出機能と、
前記予め決められた複数個の送信シンボル点の各々を構成するビット列の内の、前記ビット対数尤度比の算出対象となるビット毎に、前記ビット対数尤度比の算出対象となるビットの値が異なる任意の送信シンボル点をビット反転基準点として選択する処理を実行するビット反転基準点検出機能と、
前記ビット対数尤度比の算出対象となる前記ビット毎に、前記受信信号点、前記基準点、及び前記ビット対数尤度比の算出対象となる前記ビットの前記ビット反転基準点を、予め決められた射影用の直線軸である第１の軸及び該第１の軸に直交する第２の軸の少なくとも一方に射影して、前記第１の軸及び前記第２の軸の少なくとも一方に射影された前記受信信号点の射影点、前記基準点の射影点、及び前記ビット対数尤度比の算出対象となる前記ビットの前記ビット反転基準点の射影点を取得する処理を実行する基準軸射影機能と、
前記基準点の射影点と前記ビット対数尤度比の算出対象となる前記ビットの前記ビット反転基準点の射影点との中点を原点にする補正値を求め、前記受信信号点の射影点を前記補正値に基づいて補正して、前記受信信号点の補正された射影点を算出する処理を実行する軸内補正機能と、
前記基準点の射影点と前記ビット対数尤度比の算出対象となる前記ビットの前記ビット反転基準点の射影点との間の距離に応じて、前記軸内補正機能によって算出された前記受信信号点の前記補正された射影点を正規化補正して、前記ビット対数尤度比の算出対象となる前記ビットのビット対数尤度比を算出する処理を実行するシンボル点間補正機能と、
前記シンボル点間補正機能によって算出された、前記第１の軸上の前記受信信号点の補正された射影点及び前記第２上の軸の前記受信信号点の補正された射影点とを重み付け加算した値をビット対数尤度比として出力する２次元対数尤度比算出機能と、
前記ビット反転基準点検出機能によって前記ビット反転基準点の射影点を求める処理、前記軸内補正機能によって前記受信信号点の補正された射影点を算出する処理、前記シンボル点間補正機能によって前記ビット対数尤度比を算出する処理、並びに、前記２次元対数尤度比算出機能による処理を、前記ビット列を構成する複数個のビットの各々について実行させる機能と
を実現させるプログラムである。 When the LLR calculation method according to the second embodiment is realized by a computer-executable program, the log likelihood ratio calculation program is stored in the computer.
Of a predetermined number of transmission symbol points arranged on a phase plane that is a complex plane having a real axis and an imaginary axis, a transmission symbol point having the shortest distance from the reception signal point indicating the reception signal is used as a reference. A reference point detection function to select as a point;
The value of the bit for which the bit log likelihood ratio is to be calculated for each bit that is to be calculated for the bit log likelihood ratio in the bit string constituting each of the predetermined plurality of transmission symbol points A bit inversion reference point detection function for executing processing for selecting any transmission symbol point having a different bit reference reference point,
The received signal point, the reference point, and the bit inversion reference point of the bit for which the bit log likelihood ratio is to be calculated are determined in advance for each of the bits for which the bit log likelihood ratio is to be calculated. Projection is performed on at least one of the first axis that is the linear axis for projection and the second axis that is orthogonal to the first axis, and is projected onto at least one of the first axis and the second axis. A reference axis projection function for executing a process for obtaining a projection point of the received signal point, a projection point of the reference point, and a projection point of the bit inversion reference point of the bit to be calculated for the bit log likelihood ratio When,
A correction value having a midpoint between a projection point of the reference point and a projection point of the bit inversion reference point of the bit to be calculated for the bit log likelihood ratio is obtained, and a projection point of the reception signal point is obtained. An in-axis correction function that performs processing based on the correction value to calculate a corrected projection point of the received signal point;
The received signal calculated by the in-axis correction function according to the distance between the projected point of the reference point and the projected point of the bit inversion reference point of the bit to be calculated for the bit log likelihood ratio A symbol inter-point correction function for performing a process of calculating the bit log likelihood ratio of the bit to be calculated by normalizing and correcting the corrected projection point of the point;
Weighted addition of the corrected projected point of the received signal point on the first axis and the corrected projected point of the received signal point on the second axis calculated by the inter-symbol point correction function A two-dimensional log-likelihood ratio calculation function for outputting the obtained value as a bit log-likelihood ratio;
Processing for obtaining a projection point of the bit inversion reference point by the bit inversion reference point detection function, processing for calculating a projection point of the reception signal point corrected by the in-axis correction function, and the bit by the symbol point correction function And a function for executing a process of calculating a log likelihood ratio and a process of the two-dimensional log likelihood ratio calculation function for each of a plurality of bits constituting the bit string.

また、上記実施の形態１及び２に係るＬＬＲ算出装置及びＬＬＲ算出方法を実現する構成の一部は、ＦＰＧＡ（Ｆｉｅｌｄ−Ｐｒｏｇｒａｍｍａｂｌｅ Ｇａｔｅ Ａｒｒａｙ）又はＡＳＩＣ（Ａｐｐｌｉｃａｔｉｏｎ Ｓｐｅｃｉｆｉｃ Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）などのＬＳＩ（Ｌａｒｇｅ ｓｃａｌｅ ｉｎｔｅｇｒａｔｅｄ ｃｉｒｃｕｉｔ）により実現されてもよい。   Further, part of the configuration for realizing the LLR calculation apparatus and the LLR calculation method according to the first and second embodiments is an LSI (Large scale scale) such as an FPGA (Field-Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit). circuit).

なお、上記した実施の形態は例示にすぎず、本発明は、上記実施の形態の説明内容に制限されるものではない。   The above-described embodiment is merely an example, and the present invention is not limited to the description of the above-described embodiment.

本発明が適用されたＬＬＲ算出装置及びＬＬＲ算出方法は、デジタル放送（テレビ、ラジオ）受信装置、受信機能を備えたパーソナルコンピュータ、受信機能を備えたカーナビゲーションシステムなどの車載機器、スマートフォンなどの携帯情報端末などの各種機器に適用可能である。   An LLR calculation device and an LLR calculation method to which the present invention is applied include a digital broadcast (TV, radio) reception device, a personal computer having a reception function, an in-vehicle device such as a car navigation system having a reception function, and a portable device such as a smartphone. It can be applied to various devices such as information terminals.

１，３ ＬＬＲ算出装置、 ２ 軟判定誤り訂正復号装置、 １０ 基準点検出回路、 １１ ビット反転基準点検出回路、 １２ 基準軸射影回路、 １３ 軸内補正回路、 １４ シンボル点間補正回路、 １５，１７ 制御部、 １６ ２次元ＬＬＲ算出回路。   1, 3 LLR calculation device, 2 soft decision error correction decoding device, 10 reference point detection circuit, 11 bit inversion reference point detection circuit, 12 reference axis projection circuit, 13 in-axis correction circuit, 14 symbol point correction circuit, 17 control part, 16 two-dimensional LLR calculation circuit.

Claims (20)

所定数のビットで構成されたビット列を、実軸及び虚軸を有する複素平面上に予め決められた複数個の送信シンボル点に変調した放送信号を受信し、該受信した信号から前記ビット列の各々のビットに対して、ビット対数尤度比を算出する対数尤度比算出装置であって、
前記受信した信号を前記複素平面上で示した受信信号点からの距離が最短となる送信シンボル点を基準点として検出する基準点検出回路と、
前記ビット列の各々のビットに対して、前記ビット対数尤度比の算出対象となるビットの値が異なる任意の送信シンボル点をビット反転基準点として検出するビット反転基準点検出回路と、
前記複素平面上の任意の直線を第１の軸として、前記受信信号点、前記基準点検出回路にて検出した基準点、及び前記ビット反転基準点検出回路にて検出したビット反転基準点を射影して、当該第１の軸に射影された前記受信信号点、前記基準点、及び前記ビット反転基準点の射影点を前記ビット列の各々のビットに対して取得する基準軸射影回路と、
前記基準軸射影回路にて取得した基準点とビット反転基準点の射影点との中点を原点とするように、前記基準軸射影回路にて取得した受信信号点の射影点に対して差分の補正を、前記ビット列の各々のビットに対して行う軸内補正回路と、
前記基準軸射影回路にて取得した基準点とビット反転基準点の射影点の距離に応じて、前記軸内補正回路で補正した射影点の前記ビット列の各々のビットに対して正規化するシンボル点間補正回路と
を有することを特徴とする対数尤度比算出装置。 A broadcast signal obtained by modulating a bit string composed of a predetermined number of bits into a plurality of predetermined transmission symbol points on a complex plane having a real axis and an imaginary axis is received, and each of the bit strings is received from the received signal. A log likelihood ratio calculation device for calculating a bit log likelihood ratio for the bits of
A reference point detection circuit for detecting, as a reference point, a transmission symbol point having the shortest distance from the reception signal point indicating the received signal on the complex plane;
A bit inversion reference point detection circuit for detecting, as a bit inversion reference point, any transmission symbol point having a different bit value for which the bit log likelihood ratio is to be calculated for each bit of the bit string;
Using the arbitrary straight line on the complex plane as the first axis, the received signal point, the reference point detected by the reference point detection circuit, and the bit inversion reference point detected by the bit inversion reference point detection circuit are projected. A reference axis projection circuit that obtains a projection point of the reception signal point, the reference point, and the bit inversion reference point projected onto the first axis for each bit of the bit string;
The difference between the reference point acquired by the reference axis projection circuit and the projection point of the received signal point acquired by the reference axis projection circuit so that the origin is the midpoint between the reference point acquired by the reference axis projection circuit and the projection point of the bit inversion reference point. An in-axis correction circuit that performs correction on each bit of the bit string;
A symbol point to be normalized with respect to each bit of the bit string of the projection point corrected by the in-axis correction circuit according to the distance between the reference point acquired by the reference axis projection circuit and the projection point of the bit inversion reference point A log-likelihood ratio calculation apparatus comprising: an inter-correction circuit. 前記ビット反転基準点検出回路は、前記基準点検出回路にて検出した基準点に対して、前記ビット対数尤度比の算出対象となるビットの値が異なる前記複数個の送信シンボル点の内、前記受信信号点からの距離が最短となる送信シンボル点をビット反転基準点として検出することを特徴とする請求項１に記載の対数尤度比算出装置。   The bit inversion reference point detection circuit is different from the reference point detected by the reference point detection circuit in the plurality of transmission symbol points having different bit values for which the bit log likelihood ratio is calculated, The log likelihood ratio calculation apparatus according to claim 1, wherein a transmission symbol point having a shortest distance from the reception signal point is detected as a bit inversion reference point. 前記ビット反転基準点検出回路は、前記基準点検出回路にて検出した基準点を構成するビット列に対して、前記ビット対数尤度比の算出対象となるビットだけを反転したビット列となる送信シンボル点をビット反転基準点として検出することを特徴とする請求項１に記載の対数尤度比算出装置。   The bit inversion reference point detection circuit is a transmission symbol point that is a bit string obtained by inverting only the bit for which the bit log likelihood ratio is to be calculated with respect to the bit string constituting the reference point detected by the reference point detection circuit. The log likelihood ratio calculation apparatus according to claim 1, wherein: is detected as a bit inversion reference point. 前記基準軸射影回路は、前記第１の軸を前記実軸とすることを特徴とする請求項１から３のいずれか１項に記載の対数尤度比算出装置。   4. The log likelihood ratio calculation apparatus according to claim 1, wherein the reference axis projection circuit uses the first axis as the real axis. 5. 前記基準軸射影回路は、前記第１の軸を前記虚軸とすることを特徴とする請求項１から３のいずれか１項に記載の対数尤度比算出装置。   4. The log likelihood ratio calculation apparatus according to claim 1, wherein the reference axis projection circuit uses the first axis as the imaginary axis. 5. 前記基準軸射影回路は、前記基準点と前記ビット反転基準点の射影点とが、前記第１の軸上において重なる場合に、前記第１の軸と異なる前記複素平面上の任意の直線を第２の軸として、前記受信信号点、前記基準点、及び前記ビット反転基準点を射影して、当該第２の軸に射影された前記受信信号点、前記基準点、及び前記ビット反転基準点の射影点を、前記ビット列の各々のビットに対して取得することを特徴とする請求項４又は５に記載の対数尤度比算出装置。   The reference axis projection circuit calculates an arbitrary straight line on the complex plane different from the first axis when the reference point and the projection point of the bit inversion reference point overlap on the first axis. The reception signal point, the reference point, and the bit inversion reference point projected onto the second axis by projecting the reception signal point, the reference point, and the bit inversion reference point as two axes. 6. The log likelihood ratio calculation apparatus according to claim 4, wherein a projection point is acquired for each bit of the bit string. 前記基準軸射影回路は、前記第２の軸を、前記第１の軸に直交する直線軸とすることを特徴とする請求項６に記載の対数尤度比算出装置。   The log likelihood ratio calculation apparatus according to claim 6, wherein the reference axis projection circuit sets the second axis as a linear axis orthogonal to the first axis. 前記基準軸射影回路は、前記第１の軸を前記基準点と前記各ビット反転基準点とを通る直線軸とし、前記ビット列の各々のビットに対して実施することを特徴とする請求項１から３のいずれか１項に記載の対数尤度比算出装置。   2. The reference axis projecting circuit is implemented for each bit of the bit string with the first axis as a linear axis passing through the reference point and each bit inversion reference point. 4. The log likelihood ratio calculation apparatus according to any one of 3 above. 所定数のビットで構成されたビット列を、実軸及び虚軸を有する複素平面上に予め決められた複数個の送信シンボル点に変調した放送信号を受信し、該受信した信号から前記ビット列の各々のビットに対して、ビット対数尤度比を算出する対数尤度比算出装置であって、
前記受信した信号を前記複素平面上で示した受信信号点からの距離が最短となる送信シンボル点を基準点として検出する基準点検出回路と、
前記ビット列の各々のビットに対して、前記ビット対数尤度比の算出対象となるビットの値が異なる任意の送信シンボル点をビット反転基準点として検出するビット反転基準点検出回路と、
前記複素平面上の任意の直線を第１の軸及び該第１の軸に直交する直線を第２の軸として、前記第１の軸及び前記第２の軸に対して、前記受信信号点、前記基準点検出回路にて検出した基準点、及び前記ビット反転基準点検出回路にて検出したビット反転基準点を射影して、前記第１の軸及び前記第２の軸のそれぞれに射影された前記受信信号点、前記基準点、及び前記ビット反転基準点の射影点を前記ビット列の各々のビットに対して取得する基準軸射影回路と、
前記基準軸射影回路にて取得した前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複すると判定した第１の場合は、前記第２の軸における基準点の射影点とビット反転基準点の射影点との中点を原点とするように前記第２の軸における前記受信信号点の射影点に対して差分の補正を行うことによって前記受信信号点の補正された射影点である第１の射影点を算出し、
前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複せず前記第２の軸における基準点の射影点及びビット反転基準点の射影点が重複すると判定した第２の場合は、前記第１の軸における基準点の射影点とビット反転基準点の射影点との中点を原点とするように前記第１の軸における前記受信信号点の射影点に対して差分の補正を行うことによって前記受信信号点の補正された射影点である第２の射影点を算出し、
前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複せず前記第２の軸における基準点の射影点及びビット反転基準点の射影点が重複しないと判定した第３の場合は、前記第１の射影点及び前記第２の射影点を算出する
処理を、前記ビット列の各々のビットに対して行う軸内補正回路と、
前記基準軸射影回路にて取得した基準点とビット反転基準点の射影点の距離に応じて、前記第１の場合では前記第１の射影点の前記ビット列の各々のビットに対して正規化処理を施し、前記正規化処理が施された前記第１の射影点の値をビット対数尤度比として出力し、前記第２の場合では前記第２の射影点の前記ビット列の各々のビットに対して正規化処理を施し、前記正規化処理が施された前記第２の射影点の値をビット対数尤度比として出力し、前記第３の場合では前記第１及び前記第２の射影点の前記ビット列の各々のビットに対する正規化処理と前記第１及び第２の射影点を均等に重み付け加算する処理とを行うことで得られた値をビット対数尤度比として出力する回路と
を有することを特徴とする対数尤度比算出装置。 A broadcast signal obtained by modulating a bit string composed of a predetermined number of bits into a plurality of predetermined transmission symbol points on a complex plane having a real axis and an imaginary axis is received, and each of the bit strings is received from the received signal. A log likelihood ratio calculation device for calculating a bit log likelihood ratio for the bits of
A reference point detection circuit for detecting, as a reference point, a transmission symbol point having the shortest distance from the reception signal point indicating the received signal on the complex plane;
A bit inversion reference point detection circuit for detecting, as a bit inversion reference point, any transmission symbol point having a different bit value for which the bit log likelihood ratio is to be calculated for each bit of the bit string;
Wherein any line on the complex plane a straight line perpendicular to the first axis and the first axis as a second axis, against the first axis and the second axis, the received signal point, reference point detected by the reference point detection circuit, and by projecting a bit inversion reference point detected by said bit inversion reference point detection circuit, which is projected to each of the first axis and the second axis A reference axis projection circuit for obtaining a projection point of the received signal point, the reference point, and the bit inversion reference point for each bit of the bit string;
In the first case where it is determined that the projection point of the reference point and the projection point of the bit reversal reference point in the first axis obtained by the reference axis projection circuit overlap, the projection point of the reference point in the second axis And the projection of the received signal point by correcting the difference with respect to the projected point of the received signal point in the second axis so that the origin is the midpoint of the projected point of the bit reversal reference point Calculate a first projection point that is a point,
The second determination point that the projection point of the reference point and the projection point of the bit inversion reference point on the first axis do not overlap and the projection point of the reference point and the projection point of the bit inversion reference point on the second axis overlap. The difference between the projected point of the received signal point on the first axis and the midpoint between the projected point of the reference point on the first axis and the projected point of the bit-reversed reference point on the first axis. Calculating a second projected point that is a corrected projected point of the received signal point by performing correction;
It is determined that the projection point of the reference point and the projection point of the bit inversion reference point on the first axis do not overlap, and the projection point of the reference point and the projection point of the bit inversion reference point on the second axis do not overlap. In the case of the above, the first projection point and the second projection point are calculated.
An in- axis correction circuit that performs processing on each bit of the bit string;
In accordance with the distance between the reference point acquired by the reference axis projection circuit and the projection point of the bit inversion reference point, in the first case, normalization processing is performed on each bit of the bit string of the first projection point And outputting the value of the first projection point subjected to the normalization processing as a bit log likelihood ratio, and in the second case, for each bit of the bit string of the second projection point The normalization process is performed, and the value of the second projection point subjected to the normalization process is output as a bit log likelihood ratio, and in the third case, the first and second projection points are output. a normalization process and the first and circuits you output a value obtained by the second to perform the processing for weighted addition evenly projection point as the bit log likelihood ratio for each bit of the bit sequence A log-likelihood ratio calculation apparatus characterized by comprising: 所定数のビットで構成されたビット列を、実軸及び虚軸を有する複素平面上に予め決められた複数個の送信シンボル点に変調した放送信号を受信し、該受信した信号から前記ビット列の各々のビットに対して、ビット対数尤度比を算出する対数尤度比算出方法であって、
前記受信した信号を前記複素平面上で示した受信信号点からの距離が最短となる送信シンボル点を基準点として検出する基準点検出ステップと、
前記ビット列の各々のビットに対して、前記ビット対数尤度比の算出対象となるビットの値が異なる任意の送信シンボル点をビット反転基準点として検出するビット反転基準点検出ステップと、
前記複素平面上の任意の直線を第１の軸として、前記受信信号点、前記基準点検出ステップにて検出した基準点、及び前記ビット反転基準点検出ステップにて検出したビット反転基準点を射影して、当該第１の軸に射影された前記受信信号点、前記基準点、及び前記ビット反転基準点の射影点を前記ビット列の各々のビットに対して取得する基準軸射影ステップと、
前記基準軸射影ステップにて取得した基準点とビット反転基準点の射影点との中点を原点とするように、前記基準軸射影ステップにて取得した受信信号点の射影点に対して差分の補正を、前記ビット列の各々のビットに対して行う軸内補正ステップと、
前記基準軸射影ステップにて取得した基準点とビット反転基準点の射影点の距離に応じて、前記軸内補正ステップで補正した射影点の前記ビット列の各々のビットに対して正規化するシンボル点間補正ステップと
を有することを特徴とする対数尤度比算出方法。 A broadcast signal obtained by modulating a bit string composed of a predetermined number of bits into a plurality of predetermined transmission symbol points on a complex plane having a real axis and an imaginary axis is received, and each of the bit strings is received from the received signal. A log likelihood ratio calculation method for calculating a bit log likelihood ratio for a bit of
A reference point detection step of detecting, as a reference point, a transmission symbol point having the shortest distance from a reception signal point indicating the received signal on the complex plane;
A bit inversion reference point detecting step for detecting, as a bit inversion reference point, any transmission symbol point having a different bit value for which the bit log likelihood ratio is to be calculated for each bit of the bit string;
Projecting the received signal point, the reference point detected in the reference point detection step, and the bit inversion reference point detected in the bit inversion reference point using the arbitrary straight line on the complex plane as the first axis Then, a reference axis projection step of obtaining the projection point of the reception signal point, the reference point, and the bit inversion reference point projected onto the first axis for each bit of the bit string,
The difference between the reference point obtained in the reference axis projection step and the projection point of the received signal point obtained in the reference axis projection step is set so that the midpoint between the reference point obtained in the reference axis projection step and the projection point of the bit inversion reference point is the origin. An in-axis correction step for performing correction on each bit of the bit string;
A symbol point that is normalized with respect to each bit of the bit string of the projection point corrected in the in-axis correction step according to the distance between the reference point acquired in the reference axis projection step and the projection point of the bit inversion reference point A log likelihood ratio calculation method comprising: an inter-step correction step. 前記ビット反転基準点検出ステップでは、前記基準点検出ステップにて検出した基準点に対して、前記ビット対数尤度比の算出対象となるビットの値が異なる前記複数個の送信シンボル点の内、前記受信信号点からの距離が最短となる送信シンボル点をビット反転基準点として検出することを特徴とする請求項１０に記載の対数尤度比算出方法。   In the bit inversion reference point detection step, among the plurality of transmission symbol points having different bit values for which the bit log likelihood ratio is calculated with respect to the reference point detected in the reference point detection step, The log likelihood ratio calculation method according to claim 10, wherein a transmission symbol point having the shortest distance from the reception signal point is detected as a bit inversion reference point. 前記ビット反転基準点検出ステップでは、前記基準点検出ステップにて検出した基準点を構成するビット列に対して、前記ビット対数尤度比の算出対象となるビットだけを反転したビット列となる送信シンボル点をビット反転基準点として検出することを特徴とする請求項１０に記載の対数尤度比算出方法。   In the bit inversion reference point detection step, a transmission symbol point that becomes a bit string obtained by inverting only the bit for which the bit log likelihood ratio is calculated with respect to the bit string constituting the reference point detected in the reference point detection step The log-likelihood ratio calculation method according to claim 10, wherein: is detected as a bit inversion reference point. 前記基準軸射影ステップにおいて、前記第１の軸を前記実軸とすることを特徴とする請求項１０から１２のいずれか１項に記載の対数尤度比算出方法。   The log likelihood ratio calculation method according to any one of claims 10 to 12, wherein, in the reference axis projecting step, the first axis is the real axis. 前記基準軸射影ステップにおいて、前記第１の軸を前記虚軸とすることを特徴とする請求項１０から１２のいずれか１項に記載の対数尤度比算出方法。   The log likelihood ratio calculation method according to any one of claims 10 to 12, wherein, in the reference axis projection step, the first axis is the imaginary axis. 前記基準軸射影ステップにおいて、前記基準点と前記ビット反転基準点の射影点とが、前記第１の軸上において重なる場合に、前記第１の軸と異なる前記複素平面上の任意の直線を第２の軸として、前記受信信号点、前記基準点、及び前記ビット反転基準点を射影して、当該第２の軸に射影された前記受信信号点、前記基準点、及び前記ビット反転基準点の射影点を、前記ビット列の各々のビットに対して取得することを特徴とする請求項１３又は１４に記載の対数尤度比算出方法。   In the reference axis projecting step, when the reference point and the projected point of the bit inversion reference point overlap on the first axis, an arbitrary straight line on the complex plane different from the first axis is defined as a first line. The reception signal point, the reference point, and the bit inversion reference point projected onto the second axis by projecting the reception signal point, the reference point, and the bit inversion reference point as two axes. The log likelihood ratio calculation method according to claim 13 or 14, wherein a projection point is acquired for each bit of the bit string. 前記基準軸射影ステップは、前記第２の軸を、前記第１の軸に直交する直線軸とすることを特徴とする請求項１５に記載の対数尤度比算出方法。   The log likelihood ratio calculation method according to claim 15, wherein the reference axis projecting step sets the second axis as a linear axis orthogonal to the first axis. 前記基準軸射影ステップは、前記第１の軸を前記基準点と前記各ビット反転基準点とを通る直線軸とすることを特徴とする請求項１０から１２のいずれか１項に記載の対数尤度比算出方法。   The logarithmic likelihood according to any one of claims 10 to 12, wherein in the reference axis projecting step, the first axis is a linear axis passing through the reference point and each bit inversion reference point. Degree ratio calculation method. 所定数のビットで構成されたビット列を、実軸及び虚軸を有する複素平面上に予め決められた複数個の送信シンボル点に変調した放送信号を受信し、該受信した信号から前記ビット列の各々のビットに対して、ビット対数尤度比を算出する対数尤度比算出方法であって、
前記受信した信号を前記複素平面上で示した受信信号点からの距離が最短となる送信シンボル点を基準点として検出する基準点検出ステップと、
前記ビット列の各々のビットに対して、前記ビット対数尤度比の算出対象となるビットの値が異なる任意の送信シンボル点をビット反転基準点として検出するビット反転基準点検出ステップと、
前記複素平面上の任意の直線を第１の軸及び該第１の軸に直交する直線を第２の軸として、前記第１の軸及び前記第２の軸に対して、前記受信信号点、前記基準点検出ステップにて検出した基準点、及び前記ビット反転基準点検出ステップにて検出したビット反転基準点を射影して、前記第１の軸及び前記第２の軸のそれぞれに射影された前記受信信号点、前記基準点、及び前記ビット反転基準点の射影点を前記ビット列の各々のビットに対して取得する基準軸射影ステップと、
前記基準軸射影ステップにて取得した前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複すると判定した第１の場合は、前記第２の軸における基準点の射影点とビット反転基準点の射影点との中点を原点とするように前記第２の軸における前記受信信号点の射影点に対して差分の補正を行うことによって前記受信信号点の補正された射影点である第１の射影点を算出し、
前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複せず前記第２の軸における基準点の射影点及びビット反転基準点の射影点が重複すると判定した第２の場合は、前記第１の軸における基準点の射影点とビット反転基準点の射影点との中点を原点とするように前記第１の軸における前記受信信号点の射影点に対して差分の補正を行うことによって前記受信信号点の補正された射影点である第２の射影点を算出し、
前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複せず前記第２の軸における基準点の射影点及びビット反転基準点の射影点が重複しないと判定した第３の場合は、前記第１の射影点及び前記第２の射影点を算出する
処理を、前記ビット列の各々のビットに対して行う軸内補正ステップと、
前記基準軸射影ステップにて取得した基準点とビット反転基準点の射影点の距離に応じて、前記第１の場合では前記第１の射影点の前記ビット列の各々のビットに対して正規化処理を施し、前記正規化処理が施された前記第１の射影点の値をビット対数尤度比として出力し、前記第２の場合では前記第２の射影点の前記ビット列の各々のビットに対して正規化処理を施し、前記正規化処理が施された前記第２の射影点の値をビット対数尤度比として出力し、前記第３の場合では前記第１及び前記第２の射影点の前記ビット列の各々のビットに対する正規化処理と前記第１及び第２の射影点を均等に重み付け加算する処理とを行うことで得られた値をビット対数尤度比として出力するステップと
を有することを特徴とする対数尤度比算出方法。 A broadcast signal obtained by modulating a bit string composed of a predetermined number of bits into a plurality of predetermined transmission symbol points on a complex plane having a real axis and an imaginary axis is received, and each of the bit strings is received from the received signal. A log likelihood ratio calculation method for calculating a bit log likelihood ratio for a bit of
A reference point detection step of detecting, as a reference point, a transmission symbol point having the shortest distance from a reception signal point indicating the received signal on the complex plane;
A bit inversion reference point detecting step for detecting, as a bit inversion reference point, any transmission symbol point having a different bit value for which the bit log likelihood ratio is to be calculated for each bit of the bit string;
Wherein any line on the complex plane a straight line perpendicular to the first axis and the first axis as a second axis, against the first axis and the second axis, the received signal point, reference point detected by the reference point detection step, and by projecting a bit inversion reference point detected by said bit inversion reference point detection step, which is projected to each of the first axis and the second axis A reference axis projection step of obtaining a projection point of the received signal point, the reference point, and the bit inversion reference point for each bit of the bit string;
In the first case where it is determined that the projected point of the reference point and the projected point of the bit reversal reference point in the first axis acquired in the reference axis projecting step overlap, the projected point of the reference point in the second axis And the projection of the received signal point by correcting the difference with respect to the projected point of the received signal point in the second axis so that the origin is the midpoint of the projected point of the bit reversal reference point Calculate a first projection point that is a point,
The second determination point that the projection point of the reference point and the projection point of the bit inversion reference point on the first axis do not overlap and the projection point of the reference point and the projection point of the bit inversion reference point on the second axis overlap. The difference between the projected point of the received signal point on the first axis and the midpoint between the projected point of the reference point on the first axis and the projected point of the bit-reversed reference point on the first axis. Calculating a second projected point that is a corrected projected point of the received signal point by performing correction;
It is determined that the projection point of the reference point and the projection point of the bit inversion reference point on the first axis do not overlap, and the projection point of the reference point and the projection point of the bit inversion reference point on the second axis do not overlap. In the case of the above, the first projection point and the second projection point are calculated.
An in- axis correction step for performing processing on each bit of the bit string;
In accordance with the distance between the reference point acquired in the reference axis projection step and the projection point of the bit inversion reference point, in the first case, normalization processing is performed on each bit of the bit string of the first projection point And outputting the value of the first projection point subjected to the normalization processing as a bit log likelihood ratio, and in the second case, for each bit of the bit string of the second projection point The normalization process is performed, and the value of the second projection point subjected to the normalization process is output as a bit log likelihood ratio, and in the third case, the first and second projection points are output. and a step you output a normalization process and the first and second values obtained by performing a process of equally weighted addition of projection points for each bit of the bit string as a bit log likelihood ratio A log likelihood ratio calculation method characterized by the above. 所定数のビットで構成されたビット列を、実軸及び虚軸を有する複素平面上に予め決められた複数個の送信シンボル点に変調した放送信号を受信し、該受信した信号から前記ビット列の各々のビットに対して、ビット対数尤度比を算出するための対数尤度比算出用プログラムであって、
コンピュータに、
前記受信した信号を前記複素平面上で示した受信信号点からの距離が最短となる送信シンボル点を基準点として検出する基準点検出機能と、
前記ビット列の各々のビットに対して、前記ビット対数尤度比の算出対象となるビットの値が異なる任意の送信シンボル点をビット反転基準点として検出するビット反転基準点検出機能と、
前記複素平面上の任意の直線を第１の軸として、前記受信信号点、前記基準点検出機能によって検出した基準点、及び前記ビット反転基準点検出機能によって検出したビット反転基準点を射影して、当該第１の軸に射影された前記受信信号点、前記基準点、及び前記ビット反転基準点の射影点を前記ビット列の各々のビットに対して取得する基準軸射影機能と、
前記基準軸射影機能によって取得した基準点とビット反転基準点の射影点との中点を原点とするように、前記基準軸射影機能によって取得した受信信号点の射影点に対して差分の補正を、前記ビット列の各々のビットに対して行う軸内補正機能と、
前記基準軸射影機能によって取得した基準点とビット反転基準点の射影点の距離に応じて、前記軸内補正機能によって補正した射影点の前記ビット列の各々のビットに対して正規化するシンボル点間補正機能と
を実現させる対数尤度比算出用プログラム。 A broadcast signal obtained by modulating a bit string composed of a predetermined number of bits into a plurality of predetermined transmission symbol points on a complex plane having a real axis and an imaginary axis is received, and each of the bit strings is received from the received signal. A log likelihood ratio calculation program for calculating a bit log likelihood ratio for the bits of
On the computer,
A reference point detection function for detecting, as a reference point, a transmission symbol point having the shortest distance from the reception signal point indicating the received signal on the complex plane;
A bit inversion reference point detection function for detecting, as a bit inversion reference point, any transmission symbol point having a different bit value for which the bit log likelihood ratio is calculated for each bit of the bit string;
Using the arbitrary straight line on the complex plane as the first axis, the received signal point, the reference point detected by the reference point detection function, and the bit inversion reference point detected by the bit inversion reference point detection function are projected. A reference axis projection function that obtains a projection point of the received signal point, the reference point, and the bit inversion reference point projected onto the first axis for each bit of the bit string;
Difference correction is performed on the projection point of the received signal point acquired by the reference axis projection function so that the midpoint between the reference point acquired by the reference axis projection function and the projection point of the bit inversion reference point is the origin. , An in-axis correction function for each bit of the bit string,
Between symbol points to be normalized with respect to each bit of the bit string of the projection point corrected by the in-axis correction function according to the distance between the reference point acquired by the reference axis projection function and the projection point of the bit inversion reference point A log likelihood ratio calculation program that realizes a correction function. 所定数のビットで構成されたビット列を、実軸及び虚軸を有する複素平面上に予め決められた複数個の送信シンボル点に変調した放送信号を受信し、該受信した信号から前記ビット列の各々のビットに対して、ビット対数尤度比を算出するための対数尤度比算出用プログラムであって、
コンピュータに、
前記受信した信号を前記複素平面上で示した受信信号点からの距離が最短となる送信シンボル点を基準点として検出する基準点検出機能と、
前記ビット列の各々のビットに対して、前記ビット対数尤度比の算出対象となるビットの値が異なる任意の送信シンボル点をビット反転基準点として検出するビット反転基準点検出機能と、
前記複素平面上の任意の直線を第１の軸及び該第１の軸に直交する直線を第２の軸として、前記第１の軸及び前記第２の軸に対して、前記受信信号点、前記基準点検出機能にて検出した基準点、及び前記ビット反転基準点検出機能によって検出したビット反転基準点を射影して、前記第１の軸及び前記第２の軸のそれぞれに射影された前記受信信号点、前記基準点、及び前記ビット反転基準点の射影点を前記ビット列の各々のビットに対して取得する基準軸射影機能と、
前記基準軸射影機能によって取得した前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複すると判定した第１の場合は、前記第２の軸における基準点の射影点とビット反転基準点の射影点との中点を原点とするように前記第２の軸における前記受信信号点の射影点に対して差分の補正を行うことによって前記受信信号点の補正された射影点である第１の射影点を算出し、
前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複せず前記第２の軸における基準点の射影点及びビット反転基準点の射影点が重複すると判定した第２の場合は、前記第１の軸における基準点の射影点とビット反転基準点の射影点との中点を原点とするように前記第１の軸における前記受信信号点の射影点に対して差分の補正を行うことによって前記受信信号点の補正された射影点である第２の射影点を算出し、
前記第１の軸における基準点の射影点及びビット反転基準点の射影点が重複せず前記第２の軸における基準点の射影点及びビット反転基準点の射影点が重複しないと判定した第３の場合は、前記第１の射影点及び前記第２の射影点を算出する
処理を、前記ビット列の各々のビットに対して行う軸内補正機能と、
前記基準軸射影機能によって取得した基準点とビット反転基準点の射影点の距離に応じて、前記第１の場合では前記第１の射影点の前記ビット列の各々のビットに対して正規化処理を施し、前記正規化処理が施された前記第１の射影点の値をビット対数尤度比として出力し、前記第２の場合では前記第２の射影点の前記ビット列の各々のビットに対して正規化処理を施し、前記正規化処理が施された前記第２の射影点の値をビット対数尤度比として出力し、前記第３の場合では前記第１及び前記第２の射影点の前記ビット列の各々のビットに対する正規化処理と前記第１及び第２の射影点を均等に重み付け加算する処理とを行うことで得られた値をビット対数尤度比として出力する機能と
を実現させる対数尤度比算出用プログラム。 A broadcast signal obtained by modulating a bit string composed of a predetermined number of bits into a plurality of predetermined transmission symbol points on a complex plane having a real axis and an imaginary axis is received, and each of the bit strings is received from the received signal. A log likelihood ratio calculation program for calculating a bit log likelihood ratio for the bits of
On the computer,
A reference point detection function for detecting, as a reference point, a transmission symbol point having the shortest distance from the reception signal point indicating the received signal on the complex plane;
A bit inversion reference point detection function for detecting, as a bit inversion reference point, any transmission symbol point having a different bit value for which the bit log likelihood ratio is calculated for each bit of the bit string;
Wherein any line on the complex plane a straight line perpendicular to the first axis and the first axis as a second axis, against the first axis and the second axis, the received signal point, The reference point detected by the reference point detection function and the bit inversion reference point detected by the bit inversion reference point detection function are projected onto the first axis and the second axis, respectively. A reference axis projection function for obtaining a projection point of the received signal point, the reference point, and the bit inversion reference point for each bit of the bit string;
In the first case where it is determined that the projection point of the reference point and the projection point of the bit reversal reference point in the first axis obtained by the reference axis projection function overlap, the projection point of the reference point in the second axis The corrected projected point of the received signal point by correcting the difference with respect to the projected point of the received signal point on the second axis so that the midpoint of the projected point of the bit reversal reference point is the origin. Calculate a first projection point that is
The second determination point that the projection point of the reference point and the projection point of the bit inversion reference point on the first axis do not overlap and the projection point of the reference point and the projection point of the bit inversion reference point on the second axis overlap. The difference between the projected point of the received signal point on the first axis and the midpoint between the projected point of the reference point on the first axis and the projected point of the bit-reversed reference point on the first axis. Calculating a second projected point that is a corrected projected point of the received signal point by performing correction;
It is determined that the projection point of the reference point and the projection point of the bit inversion reference point on the first axis do not overlap, and the projection point of the reference point and the projection point of the bit inversion reference point on the second axis do not overlap. In the case of the above, the first projection point and the second projection point are calculated.
An in- axis correction function for performing processing on each bit of the bit string;
In accordance with the distance between the reference point acquired by the reference axis projection function and the projection point of the bit reversal reference point, in the first case, normalization processing is performed on each bit of the bit string of the first projection point. And output the value of the first projection point subjected to the normalization processing as a bit log likelihood ratio, and in the second case, for each bit of the bit string of the second projection point The normalization process is performed, and the value of the second projection point subjected to the normalization process is output as a bit log likelihood ratio. In the third case, the values of the first and second projection points are output. realizing functions and you output a value obtained by performing a process of equally weighted addition the normalization processing with respect to each bit of said first and second projected point of the bit string as a bit log likelihood ratio Log likelihood ratio calculation program.
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