JP6176044B2 - Block structure determination circuit and information compression circuit - Google Patents

Description

  The present invention relates to a block structure determination circuit that determines the structure of a block without increasing the circuit scale in an encoding apparatus, and an information compression circuit that performs orthogonal transformation without increasing the circuit scale.

  Non-Patent Document 1 describes HEVC (High Efficiency Video Coding), which is a video encoding system based on the ITU-T recommendation H.265 standard.

  In HEVC, each frame of a digitized video is divided into coding tree units (CTUs), and each CTU is coded in raster scan order. Each CTU has a quad-tree structure and is encoded by being divided into coding units (CU: Coding Unit). Each CU is predicted by being divided into prediction units (PUs). Further, the prediction error of each CU is divided into transform units (TU: Transform Unit) in a quad-tree structure, and is subjected to frequency conversion. The largest CU is called a maximum CU (LCU: Largest Coding Unit), and the smallest CU is called a smallest CU (SCU: Smallest Coding Unit).

  The CU is predictively encoded by intra prediction or inter-frame prediction (inter prediction).

  FIG. 7 is an explanatory diagram showing an example of CU division when the CTU size is 64 × 64 (64 pixels × 64 pixels). FIG. 7A shows an example of a divided shape (hereinafter also referred to as a block structure), and FIG. 7B shows a CU quadtree structure corresponding to the divided shape shown in FIG. It is shown.

  The CU is divided into TUs in a quadtree structure. The way of division is the same as in the case of CU division shown in FIG. Note that the hierarchy (depth) described in FIG. 7B is a hierarchy focused on TU partitioning.

  When division is performed when encoding is performed by intra prediction, the TU is sequentially divided starting from a PU that is a block having the same size as the CU or a block obtained by dividing the CU into four. When encoding is performed by inter prediction, the TU is sequentially divided starting from the CU. In HEVC, it is possible to set the maximum size of the TU used for encoding.

  With reference to FIG. 8, the configuration and operation of a general video encoding apparatus that outputs a bit stream using each CU of each frame of a digitized video as an input image will be described.

  FIG. 8 is a block diagram illustrating an example of a general video encoding device. The video encoding apparatus illustrated in FIG. 8 includes a transform unit 301, a quantization unit 302, an entropy coding unit 303, an inverse transform / inverse quantization unit 304, a buffer 305, a prediction unit 306, and a block structure determination unit 307.

  The block structure determination unit 307 determines the CU quadtree structure / PU partition shape / TU quadtree structure for each CTU so as to increase the coding efficiency in accordance with the feature of the image.

  The prediction unit 306 generates a prediction signal for the input image signal of the CU based on the CU quadtree structure and the PU partition shape determined by the block structure determination unit 307. The prediction signal is generated based on intra prediction or inter prediction.

  Based on the TU quadtree structure determined by the block structure determination unit 307, the conversion unit 301 performs frequency conversion on the prediction error image (prediction error signal) obtained by subtracting the prediction signal from the input image signal. The transform unit 301 uses orthogonal transform of 4 × 4, 8 × 8, 16 × 16, or 32 × 32 block size based on frequency transform in transform coding of the prediction error signal. Specifically, DST (Discrete Sine Transform) (integer precision) approximated by integer arithmetic is used for 4 × 4 TU of the luminance component of CU (intra CU) to be intra-coded. For other TUs, use DCT (Discrete Cosine Transform) (integer precision) approximated by integer arithmetic corresponding to the block size.

  Hereinafter, the discrete cosine transform process and the discrete sine transform process executed by the transform unit 301 are collectively referred to as “orthogonal transform process”.

  The quantization unit 302 quantizes the transform coefficient (orthogonal transform coefficient) supplied from the transform unit 301. The inverse quantization / inverse transform unit 304 inversely quantizes the transform coefficient. Further, the inverse quantization / inverse transform unit 304 inversely transforms the inversely quantized transform coefficient. A prediction signal is added to the inversely transformed prediction error image, and the prediction error image is supplied to the buffer 305. The buffer 305 stores the image as a reference image.

ITU-T recommendation H.265 High efficiency video coding, April 2013

  The amount of calculation in the conversion process executed by the conversion unit 301 increases as the block size increases. In addition, since the transform unit 301 is configured to be able to execute orthogonal transform processing for a large block size, when the transform unit 301 is configured by a hardware circuit, the circuit scale of the transform unit 301 becomes large and the hardware Cost increases. Further, the block structure determination unit 307 evaluates the coding cost of other types of TU quadtree structures in order to determine an appropriate TU quadtree structure. For this reason, the circuit scale of the block structure determination unit 307 is increased and the hardware cost is increased. Further, in HEVC, the maximum size of the TU is set to be smaller than the standard maximum size of 32 × 32, thereby limiting the amount of computation in the conversion processing executed by the conversion unit 301 and the block structure determination unit 307. Increase can be prevented. For example, it is possible not to evaluate and convert a 32 × 32 block size. However, in the case of a method that suppresses an increase in calculation amount and hardware cost due to such a limitation, encoding efficiency is reduced in any image in which a 32 × 32 block size is suitable.

  Accordingly, the present invention provides a block structure determination circuit and a block structure determination method capable of determining a block structure without increasing the circuit scale while suppressing a decrease in encoding efficiency, and an increase in circuit scale while suppressing a decrease in encoding efficiency. It is an object of the present invention to provide an information compression circuit and an information compression method that can perform orthogonal transformation processing without using the information.

A block structure determination circuit according to the present invention is a block structure determination circuit that determines one or more block structures from a plurality of block structures that are different from each other in a block structure including units formed by hierarchically dividing a block. A plurality of types of sizes are defined as unit sizes, a block structure enumeration unit that enumerates a plurality of block structures, and a size less than a predetermined size are provided, and orthogonal transformation is performed for units of the corresponding size. An orthogonal transform unit that outputs a transform coefficient and a simplified value output unit that outputs a simplified value as a transform coefficient for a unit having a size larger than a predetermined size , and the simplified value output unit outputs 0 as a simplified value It is characterized by.

The block structure determination method according to the present invention is a block structure determination method for determining one or more block structures from a plurality of block structures having different division methods, the block structure including units formed by dividing blocks hierarchically. A plurality of types of sizes are defined as unit sizes, a plurality of block structures are listed, orthogonal transform is performed on each unit having a size less than a predetermined size, and a transform coefficient is output. A simplified value is output as a conversion coefficient for the unit, and the simplified value is 0 .

An information compression circuit according to the present invention is an information compression circuit that compresses the information amount of each unit in a block formed by hierarchically divided units, and a plurality of types of sizes are defined as unit sizes. An orthogonal transform unit that is provided corresponding to each of a size less than a predetermined size, performs orthogonal transform on a unit of the corresponding size and outputs a transform coefficient, and outputs a simplified value as a transform coefficient for a unit of a size larger than the predetermined size. A simplified value output unit, and the simplified value output unit outputs 0 as a simplified value .

An information compression method according to the present invention is an information compression method for compressing the amount of information of each unit in a block formed by hierarchically divided units, and a plurality of types of sizes are defined as unit sizes, It is provided corresponding to each of the sizes less than the predetermined size, performs orthogonal transform for the unit of the corresponding size and outputs a conversion coefficient, outputs a simple value as a conversion coefficient for the unit of the size larger than the predetermined size , and the simple value is It is 0 .

  According to the present invention, it is possible to obtain a block structure determination circuit and an information compression circuit that suppress both of a decrease in coding efficiency and an increase in the amount of computation and reduce the circuit scale.

It is a conceptual diagram which shows the structural example of the apparatus containing a block structure determination means and a compression process means. It is a block diagram which shows the structural example of a block structure determination part and an information compression part. It is a flowchart which shows operation | movement of a block structure determination part. It is a block diagram which shows the other structural example of a block structure determination part and an information compression part. It is a block diagram which shows the principal part of the block structure determination circuit by this invention. It is a block diagram which shows the principal part of the information compression circuit by this invention. It is explanatory drawing which shows the example of a division | segmentation of CU. It is explanatory drawing which shows the structure of a general video coding apparatus.

  FIG. 1 is a conceptual diagram showing a configuration example of an apparatus including a block structure determining unit and a compression processing unit according to the present invention.

  The block structure determining means 10 determines a TU quadtree structure (block structure) with a low coding cost using a predetermined cost evaluation formula. When the block structure is expressed two-dimensionally, it is as shown in FIG. However, the block size is 32 × 32.

  The compression processing unit 20 performs orthogonal transform processing for each TU included in the CU having the block structure determined by the block structure determination unit 10.

  The block structure determining means 10 and the compression processing means 20 shown in FIG. 1 can be applied to the video encoding apparatus shown in FIG. 8, and when applied to the video encoding apparatus, the block structure determining means 10 Is applied to the block structure determination unit 307, and the compression processing means 20 is applied to the conversion unit 301.

Embodiment 1. FIG.
FIG. 2 is a block diagram showing configurations of a block structure determining unit 110 and an information compressing unit 210, which are specific configuration examples of the block structure determining unit 10 and the compression processing unit 20 shown in FIG.

  The block structure determining unit 110 includes a block structure listing unit 111, a 4 × 4 orthogonal transform unit 112, an 8 × 8 orthogonal transform unit 113, a 16 × 16 orthogonal transform unit 114, a DC component output unit 115, and a block structure evaluation unit 117. .

  The information compression unit 210 includes a 4 × 4 orthogonal transform unit 212, an 8 × 8 orthogonal transform unit 213, a 16 × 16 orthogonal transform unit 214, and a DC component output unit 215.

  In the block structure determination unit 110, the block structure enumeration unit 111 lists all the block structures that can be used based on the input image. An example is shown in FIG. 7 (however, in this case, the maximum block size is 32 × 32), but the block structure is a combination of 4 × 4, 8 × 8, and 16 × 16 TUs. Or one TU of 32 × 32.

  The block structure enumeration unit 111 may enumerate all combinations (all block structures) that can be divided starting from a 32 × 32 CU, but the encoding cost is less than a predetermined value based on the input image. Some block structures may be mentioned.

  The 4 × 4 orthogonal transform unit 112 performs 4 × 4 TU orthogonal transform (specifically, integer precision DCT: where DST is integer precision in the case of intra prediction). The 8 × 8 orthogonal transform unit 113 performs 8 × 8 TU orthogonal transform (specifically, DCT with integer precision). The 16 × 16 orthogonal transform unit 114 performs 16 × 16 TU orthogonal transform (specifically, DCT with integer precision).

  The DC component output unit 115 outputs only a component having a frequency of 0 (DC component) in orthogonal transform. That is, all AC components are treated as 0.

  FIG. 3 is a flowchart showing the operation of the block structure determination unit 110. The operation of the block structure determination unit 110 will be described with reference to FIG.

  The block structure enumeration unit 111 enumerates (lists up) block structures (step S101). Then, the number of listed block structures is set to a variable n (step S102).

  Next, the block structure enumeration unit 111 sequentially converts the TUs constituting the nth block structure into 4 × 4 orthogonal transform unit 112, 8 × 8 orthogonal transform unit 113, 16 × 16 orthogonal transform unit 114, or DC component output. It supplies to the part 115 (step S103). Then, the value of n is decreased by 1 (step S104).

  In the process of step S103, the block structure listing unit 111 outputs the TU to the orthogonal transform unit corresponding to the size of the TU. That is, if the TU size is 4 × 4, the TU is output to the 4 × 4 orthogonal transform unit 112. If the TU size is 8 × 8, the TU is output to the 8 × 8 orthogonal transform unit 113. If the TU size is 16 × 16, the TU is output to the 16 × 16 orthogonal transform unit 114.

  When the TU size is 32 × 32, the block structure listing unit 111 outputs the TU to the DC component output unit 115.

  Each transform unit performs orthogonal transform (for example, DCT with integer precision) and outputs transform coefficients to the block structure evaluation unit 117 (step S105). However, the DC component output unit 115 outputs the DC component to the block structure evaluation unit 117.

  The block structure evaluation unit 117 calculates the coding cost of the CU including a plurality of TUs (step S106). The encoding cost reflects a value related to the code amount and encoding distortion (correlated with image quality). As an example, the block structure evaluation unit 117 uses the following RD (Rate Distortion) cost.

  Cost = D + λ ・ R

  D is the coding distortion, R is the amount of code including the transform coefficient, and λ is the Lagrange multiplier.

  If n = 0 is not satisfied, the block structure evaluation unit 117 executes the processes of steps S103 to S106 again (step S107). That is, the transform coefficient (or only the DC component) is calculated for the next block structure, and the coding cost is calculated.

  When n = 0, the block structure evaluation unit 117 compares the calculated coding costs of the respective block structures, and shows a predetermined number of block structures with low coding costs (indicating the division state of the CU). For example, data indicating a block structure having a minimum encoding cost (in this case, the predetermined number is 1) is output (step S108).

  In the present embodiment, when the TU size is 32 × 32 (maximum TU size), the block structure determination unit 110 does not perform the orthogonal transform operation. The block structure determination unit 110 only outputs a direct current component of orthogonal transformation. Therefore, an increase in the calculation amount of the block structure determining unit 110 is suppressed, and the circuit scale of the block structure determining unit 110 is reduced.

  Next, the operation of the information compression unit 210 will be described. In the information compression unit 210, the TU constituting the CU is input to the orthogonal transform unit corresponding to the size of the TU. That is, if the size of the TU is 4 × 4, the TU is input to the 4 × 4 orthogonal transform unit 212. If the TU size is 8 × 8, the TU is input to the 8 × 8 orthogonal transform unit 213. If the TU size is 16 × 16, the TU is input to the 16 × 16 orthogonal transform unit 214.

  When the TU size is 32 × 32, the TU is input to the DC component output unit 215.

  Each transform unit performs orthogonal transform (for example, DCT with integer precision) and outputs transform coefficients. However, the DC component output unit 215 outputs a DC component.

  In the present embodiment, when the TU size is 32 × 32 (maximum TU size), the information compression unit 210 does not perform an orthogonal transform operation. The information compression unit 210 only outputs a direct current component of orthogonal transformation. Therefore, an increase in the calculation amount of the information compression unit 210 is suppressed, and the circuit scale of the information compression unit 210 is reduced.

  In the present embodiment, when the block structure determination unit 110 and the information compression unit 210 do not perform the orthogonal transformation operation on the maximum TU size and output the DC component of the orthogonal transformation, the inverse quantization / inverse transformation unit 304 is used. (Refer to FIG. 8) may be configured such that the inverse orthogonal transform operation is not performed on the maximum TU size, and only the direct current component is inversely orthogonal transformed and the result is output. That is, in the present embodiment, an increase in the amount of computation of the inverse quantization / inverse transform unit 304 is suppressed, and the circuit scale can be reduced.

  In the present embodiment, the block structure determination unit 110 and the information compression unit 210 output the DC component in the orthogonal transform without performing the orthogonal transform operation only for the maximum TU size, but the smaller size (for example, 16 × 16) A DC component may be output as a conversion coefficient for a TU having the above size. In that case, the image quality may be reduced, but the effect of reducing the amount of calculation and the circuit scale is further increased.

  In the present embodiment, the block structure determination unit 110 and the information compression unit 210 output the direct current component in the orthogonal transform as a transform coefficient, but output a predetermined low frequency component in addition to the direct current component. It may be. The predetermined low frequency component is, for example, “three” low frequency components adjacent to the direct current component. Note that “three” is merely an example, and the number thereof may be increased.

Embodiment 2. FIG.
FIG. 4 is a block diagram showing configurations of a block structure determining unit 120 and an information compressing unit 220 which are other examples of the block structure determining unit 10 and the compression processing unit 20 shown in FIG.

  The block structure determination unit 120 includes a block structure enumeration unit 111, a 4 × 4 orthogonal transform unit 112, an 8 × 8 orthogonal transform unit 113, a 16 × 16 orthogonal transform unit 114, a zero output unit 116, and a block structure evaluation unit 117.

  The information compression unit 220 includes a 4 × 4 orthogonal transform unit 212, an 8 × 8 orthogonal transform unit 213, a 16 × 16 orthogonal transform unit 214, and a zero output unit 216.

  In the block structure determining unit 120, the block structure listing unit 111, 4 × 4 orthogonal transform unit 112, 8 × 8 orthogonal transform unit 113, 16 × 16 orthogonal transform unit 114, and block structure evaluation unit 117 are the same as those in the first embodiment. The same operation as that in the block structure determination unit 110 is performed.

  In the present embodiment, when the TU size is 32 × 32, the block structure listing unit 111 outputs the TU to the zero output unit 216. The zero output unit 116 always outputs zero (0) as the conversion coefficient.

  That is, when the TU size is 32 × 32 (maximum TU size), the block structure determination unit 120 does not perform the orthogonal transform operation. The block structure determination unit 120 only outputs 0. Therefore, an increase in the calculation amount of the block structure determining unit 120 is suppressed, and the circuit scale of the block structure determining unit 110 is reduced.

  Next, the operation of the information compression unit 220 will be described. In the information compression unit 220, the 4 × 4 orthogonal transform unit 212, the 8 × 8 orthogonal transform unit 213, and the 16 × 16 orthogonal transform unit 214 operate in the same manner as those in the information compression unit 210 of the first embodiment.

  In the present embodiment, when the size of the TU is 32 × 32, the TU is input to the zero output unit 216. The zero output unit 216 always outputs zero (0) as the conversion coefficient.

  That is, when the size of the TU is 32 × 32 (maximum TU size), the information compression unit 220 does not perform the orthogonal transform operation. The information compression unit 220 always outputs 0 only. Therefore, an increase in the calculation amount of the information compression unit 220 is suppressed, and the circuit scale of the information compression unit 220 is reduced.

  In the present embodiment, the block structure determination unit 120 and the information compression unit 220 do not perform orthogonal transformation only for the maximum TU size and output 0 as a transform coefficient, but a smaller size (for example, 16 × 16) 0 may be output as a conversion coefficient for a TU of the above size. In that case, the image quality may be reduced, but the effect of reducing the amount of calculation and the circuit scale is further increased.

  In the present embodiment, when the block structure determining unit 120 and the information compressing unit 220 do not perform the orthogonal transform operation on the maximum TU size and output 0 as the transform coefficient, the inverse quantization / inverse transform unit 304 ( 8) may be configured to output 0 without executing the inverse orthogonal transform operation for the maximum TU size. That is, in the present embodiment, an increase in the amount of computation of the inverse quantization / inverse transform unit 304 is suppressed, and the circuit scale can be reduced.

  In HEVC, the CTU is composed of a luminance component coding block (CTB: Coding Tree Block) and a corresponding color difference component CTB. Also, in the current HEVC, the resolution of the color difference component is defined as 4: 2: 0 (the number of pixels of the U component and V component is 1/2 of the number of pixels of the luminance component Y in the horizontal direction and the vertical direction). ing. Therefore, with respect to the color difference component, the TU size can be reduced to ½ of the TU size related to the luminance component.

  Accordingly, even when the orthogonal transformation operation is not executed for the 32 × 32 TU, the orthogonal transformation operation can be executed for all block sizes in the TU relating to the color difference component.

FIG. 5 is a block diagram showing the main part of the block structure determining circuit according to the present invention. As shown in FIG. 5, the block structure determination circuit 1 includes a block structure enumeration unit 2 that enumerates a plurality of block structures (for example, realized by the block structure enumeration unit 111 shown in FIGS. 2 and 4), and a predetermined structure. Orthogonal transformation units 3 _{1 to} 3 _N (for example, FIG. 2 and FIG. 2) provided corresponding to each of sizes smaller than the size (for example, 32 × 32), performing orthogonal transformation on the corresponding size unit and outputting transformation coefficients. 4 × 4 orthogonal transform unit 112, 8 × 8 orthogonal transform unit 113, and 16 × 16 orthogonal transform unit 114 shown in FIG. 4) and simple values (for example, DC component, low-frequency component, 0) simplified value output section for outputting the transform coefficients 3 _{N + 1 (for} example, implemented by the zero output portion 116 shown in the DC component output unit 115 or FIG. 4 is shown in FIG. 2.) and Bei the That.

FIG. 6 is a block diagram showing the main part of the information compression circuit according to the present invention. As shown in FIG. 6, the information compression circuit 6 is provided corresponding to each of a size smaller than a predetermined size (for example, 32 × 32), and performs orthogonal transformation on the unit of the corresponding size and outputs a transformation coefficient. Transformers 7 _{1 to} 7 _N (for example, realized by 4 × 4 orthogonal transform unit 212, 8 × 8 orthogonal transform unit 213, and 16 × 16 orthogonal transform unit 214 shown in FIGS. 2 and 4) and a predetermined size Simplified value output unit 7 _{N + 1} (for example, DC component output unit 215 shown in FIG. 2 or zero shown in FIG. 4) outputs a simple value (for example, DC component, low frequency component, 0) as a conversion coefficient for the unit of the above size. It is realized by the output unit 216).

1 block structure determination circuit 2 block structure listing unit 3 ₁ to 3 _N orthogonal transform unit 3 _{N + 1} simplified value output unit 6 information compression circuit 7 ₁ to _7-N orthogonal transformation section 7 _{N + 1} simplified value output section 10 block structure determination unit 20 compression Means 110, 120 Block structure determination unit 111 Block structure enumeration unit 112 4 × 4 orthogonal transform unit 113 8 × 8 orthogonal transform unit 114 16 × 16 orthogonal transform unit 115 DC component output unit 116 Zero output unit 117 Block structure evaluation unit 210, 220 Information compression unit 212 4 × 4 orthogonal transform unit 213 8 × 8 orthogonal transform unit 214 16 × 16 orthogonal transform unit 215 DC component output unit 216 Zero output unit

Claims (10)

A block structure determination circuit for determining one or more block structures from a plurality of block structures having a block structure including units formed by hierarchically dividing blocks and having different division methods,
Multiple types of sizes are defined as unit sizes,
A block structure enumeration unit for enumerating the plurality of block structures;
An orthogonal transform unit that is provided corresponding to each of a size less than a predetermined size, performs orthogonal transform on a unit of the corresponding size, and outputs a transform coefficient;
A simplified value output unit that outputs a simplified value as a conversion coefficient for a unit of a size larger than a predetermined size ,
The simplified value output unit outputs 0 as the simplified value . Wherein the predetermined size, block structure determination circuit according to claim 1, wherein the maximum unit size. A block structure determination circuit mounted on an encoding device,
Using the conversion coefficient and a predetermined cost evaluation formula to calculate the coding cost for each block structure further comprises claim 1 or claim block structure evaluation section coding cost identify one or more block structure in ascending order 3. The block structure determining circuit according to 2. A block structure determining method for determining one or more block structures from a plurality of block structures having a block structure including units formed by hierarchically dividing blocks and having different dividing methods,
Multiple types of sizes are defined as unit sizes,
Enumerate the plurality of block structures;
Perform orthogonal transform on each unit of size less than the predetermined size and output transform coefficient,
A simple value is output as a conversion coefficient for units of a size larger than the specified size .
The block structure determining method , wherein the simplified value is 0 . The block structure determination method according to claim 4 , wherein the predetermined size is a maximum unit size. A block structure determination method applied to an encoding device, comprising:
The block structure determination method according to claim 4 or 5 , wherein an encoding cost for each block structure is calculated using a transform coefficient and a predetermined cost evaluation formula, and one or more block structures are specified in order of increasing encoding cost. . An information compression circuit for compressing the amount of information of each unit in a block formed by hierarchically divided units,
Multiple types of sizes are defined as unit sizes,
An orthogonal transform unit that is provided corresponding to each of a size less than a predetermined size, performs orthogonal transform on a unit of the corresponding size, and outputs a transform coefficient;
A simplified value output unit that outputs a simplified value as a conversion coefficient for a unit of a size larger than a predetermined size ,
The simplified value output unit outputs 0 as the simplified value . The information compression circuit according to claim 7 , wherein the predetermined size is a maximum unit size. An information compression method for compressing the amount of information of each unit in a block formed of hierarchically divided units,
Multiple types of sizes are defined as unit sizes,
It is provided corresponding to each of the sizes less than the predetermined size, performs orthogonal transformation on the unit of the corresponding size, and outputs a transform coefficient,
A simple value is output as a conversion coefficient for units of a size larger than the specified size .
The information compression method , wherein the simplified value is 0 . The information compression method according to claim 9 , wherein the predetermined size is a maximum unit size.

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