JP6175637B2 - Power estimation support program, power estimation support device, and power estimation support method - Google Patents

Description

  The present invention relates to a power estimation support program, a power estimation support apparatus, and a power estimation support method.

  Conventionally, there is a demand for estimating the power of a circuit by ESL (Electronic System Level). ESL is a high-level concept having a higher level of abstraction than RTL (Register Transfer Level). In the ESL, for example, a functional block, a memory, and a bus are defined, and a data flow between functional blocks or between functional blocks / memory is described.

  As a related prior art, for example, there is one that analyzes a power consumption tendency for a large-scale circuit. Specifically, for example, the power estimation device obtains an average value of the number of signal changes per unit time in each circuit range, calculates a power coefficient for each circuit range, or calculates the signal per unit time. The power coefficient for each circuit range when the average value of the number of changes is 1 is calculated. Next, the power estimation device calculates the average value of the number of changes per unit time of the signal of each signal line included in the circuit range with respect to the average value of the number of changes per unit time of the signal at the observation point specified in the circuit range. The ratio is calculated as a correction coefficient. The power estimation apparatus calculates a power value for each circuit range based on the correction coefficient and the power coefficient for each circuit range.

  There is also a technique for shortening the time required for power consumption analysis of a semiconductor integrated circuit. Specifically, for example, the power consumption analysis apparatus analyzes design circuit information and extracts a measurement target circuit that defines an operation mode in a circuit block having a common operation mode, and characteristic information thereof. Next, the power consumption analysis apparatus groups the extracted measurement target circuits based on the grouping policy. The power consumption analyzer measures the number of operations for each grouped measurement group, and calculates the operation rate of each measurement target circuit based on the measurement result.

JP2012-104091A JP 2009-053747 A

  However, the conventional technique has a problem that it is difficult to estimate the power of the circuit by ESL. For example, a primitive power model for estimating the power of a circuit is a model of a gate level cell. In ESL, for example, the flow of data between functional blocks or between functional blocks / memory is described, and it is difficult to establish a relationship with a gate.

  In one aspect, an object of the present invention is to provide a power estimation support program, a power estimation support apparatus, and a power estimation support method that can support circuit power estimation.

  According to one aspect of the present invention, the amount of data input to and output from a partial circuit via a bus in the circuit measured by a simulation for estimating the power consumption of the circuit and a unit time in the partial circuit. A measurement result representing the number of signal changes in association with each other is read from the storage unit, and based on the measurement result, the data amount is set as an independent variable, and regression analysis is performed using the change number as a dependent variable. A power estimation support program, a power estimation support apparatus, and a power estimation support method for creating a toggle rate estimation function for obtaining the number of changes from a quantity are proposed.

  According to one embodiment of the present invention, circuit power estimation can be supported.

FIG. 1 is an explanatory diagram of an example of a power estimation support method according to the embodiment. FIG. 2 is a block diagram illustrating a hardware configuration example of the power estimation support apparatus 101. FIG. 3A is an explanatory diagram (part 1) of a specific example of measurement result data. FIG. 3B is an explanatory diagram (part 2) illustrating a specific example of measurement result data. FIG. 4 is a block diagram illustrating a functional configuration example of the power estimation support apparatus 101. FIG. 5 is an explanatory diagram showing a measurement result and an estimation result of the average toggle rate. FIG. 6 is an explanatory diagram showing the power measurement result and the estimation result. FIG. 7 is a flowchart illustrating an example of the power estimation support processing procedure of the power estimation support apparatus 101. FIG. 8 is an explanatory diagram illustrating an example of the clock tree unit. FIG. 9 is an explanatory diagram illustrating an example of a non-clock tree unit. FIG. 10 is a Gantt chart showing the operation status of the block A. FIG. 11 is an explanatory diagram showing state data of the block A. FIG. 12 is an explanatory diagram (part 1) illustrating a simulation result of emulation power estimation. FIG. 13 is an explanatory diagram (part 2) of the simulation result of the emulation power estimation. FIG. 14 is an explanatory diagram (part 1) illustrating the correlation between the toggle rate of the non-clock tree and the flow rate. FIG. 15 is an explanatory diagram (part 2) illustrating the correlation between the toggle rate of the non-clock tree and the flow rate. FIG. 16 is an explanatory diagram (part 1) showing the correlation between the power of the RAM / ROM and the flow rate. FIG. 17 is an explanatory diagram (part 2) illustrating the correlation between the power of the RAM / ROM and the flow rate. FIG. 18 is an explanatory diagram (part 1) showing the correlation between the power of the FF clock and the flow rate. FIG. 19 is an explanatory diagram (part 2) illustrating the correlation between the power of the FF clock and the flow rate. FIG. 20 is an explanatory diagram (part 1) illustrating the correlation between the power of the clock tree and the flow rate. FIG. 21 is an explanatory diagram (part 2) illustrating the correlation between the power of the clock tree and the flow rate. FIG. 22 is an explanatory diagram (part 3) illustrating the correlation between the power of the FF clock and the flow rate. FIG. 23 is an explanatory diagram (part 4) illustrating the correlation between the power of the FF clock and the flow rate. FIG. 24 is an explanatory diagram (part 5) illustrating the correlation between the power of the FF clock and the flow rate. FIG. 25 is an explanatory diagram (part 3) illustrating the correlation between the power of the clock tree and the flow rate. FIG. 26 is an explanatory diagram (part 4) illustrating the correlation between the power of the clock tree and the flow rate. FIG. 27 is an explanatory diagram (part 5) illustrating the correlation between the power of the clock tree and the flow rate. FIG. 28 is an explanatory diagram showing an example of a multifunction. FIG. 29 is an explanatory diagram (part 1) illustrating the correlation of the clock tree with the sample data 2. FIG. 30 is an explanatory diagram (part 2) of the correlation of the clock tree with the sample data 2. FIG. 31 is an explanatory diagram (part 3) illustrating the correlation of the clock tree with the sample data 2. FIG. 32 is an explanatory diagram (part 4) illustrating the correlation of the clock tree with the sample data 2. FIG. 33 is an explanatory diagram (part 1) illustrating the correlation between the clock tree power estimation based on the flow rate and the waiting time. FIG. 34 is an explanatory diagram (part 2) showing the correlation between the clock tree power estimation based on the flow rate and the waiting time. FIG. 35 is an explanatory diagram (part 1) illustrating the correlation between the FF clock power estimation based on the flow rate and the waiting time. FIG. 36 is an explanatory diagram (part 2) illustrating the correlation of the FF clock power estimation based on the flow rate and the waiting time. FIG. 37 is an explanatory diagram (part 1) illustrating a correlation between the clock tree power estimation based on the flow rate and the waiting time in the Run state. FIG. 38 is an explanatory diagram (part 2) of the correlation between the clock tree power estimation based on the flow rate and the waiting time in the Run state. FIG. 39 is an explanatory diagram (part 1) illustrating the correlation between the flow rate in the Run state and the FF clock power estimation based on the waiting time. FIG. 40 is an explanatory diagram (part 2) of the correlation between the FF clock power estimation based on the flow rate and the waiting time in the Run state. FIG. 41 is an explanatory diagram (part 1) illustrating the correlation of the clock tree power estimation based on the flow rate in the Run state. FIG. 42 is an explanatory diagram (part 2) illustrating the correlation of the clock tree power estimation based on the flow rate in the Run state. FIG. 43 is an explanatory diagram (part 1) illustrating the correlation of the FF clock power estimation based on the flow rate in the Run state. FIG. 44 is an explanatory diagram (part 2) illustrating the correlation of the FF clock power estimation based on the flow rate in the Run state. FIG. 45A is an explanatory diagram (part 1) of a description example of the power estimation support apparatus 101. FIG. 45B is an explanatory diagram (part 2) illustrating a description example of the power estimation support apparatus 101. FIG. 45C is an explanatory diagram (part 3) of a description example of the power estimation support apparatus 101. FIG. 46 is an explanatory diagram of an example of the estimation target block N.

  Exemplary embodiments of a power estimation support program, a power estimation support apparatus, and a power estimation support method according to the present invention will be described below in detail with reference to the accompanying drawings.

(One example of power estimation support method)
FIG. 1 is an explanatory diagram of an example of a power estimation support method according to the embodiment. In FIG. 1, a power estimation support apparatus 101 is a computer that supports estimation of power consumption of a circuit. The circuit for which the power consumption is estimated is, for example, a semiconductor integrated circuit such as an LSI (Large Scale Integrated Circuit).

  Here, the primitive power model for estimating the power consumption of the circuit is, for example, a model of a gate level cell. RTL design data can be dropped into gate level design data by logical synthesis. Therefore, it is relatively easy to estimate the power consumption of the circuit from the RTL design data.

  On the other hand, ESL design data with a higher abstraction level than RTL, for example, describes the flow of data between functional blocks or between functional blocks / memory, and has relations with gates. Is difficult. Also, it may be difficult to drop ESL design data into RTL design data.

  Therefore, in this embodiment, the power estimation support apparatus 101 assumes that there is a correlation between the data amount (bus flow rate) input / output to / from the partial circuit via the bus in the circuit and the toggle rate of the partial circuit. Create a model formula that estimates the toggle rate from the bus flow to the circuit. As a result, it is possible to estimate the power in the ESL where only information about the bus flow rate to the partial circuit can be obtained. Hereinafter, an embodiment of the power estimation support process of the power estimation support apparatus 101 will be described.

  (1) The power estimation support apparatus 101 acquires a measurement result of a power estimation simulation that estimates the power consumption of a certain circuit. Here, the measurement result is information indicating, for example, the bus flow rate and the toggle rate that are measured in a unit of a predetermined period during the simulation for the partial circuits in the circuit.

  The partial circuit is a circuit block including a plurality of cells and signal lines, for example. The cell is a circuit element such as a NOT gate, an AND gate, a buffer, INV (inverter), and FF (flip-flop). Specifically, for example, the partial circuit is an IP (Intellectual Property) used as partial circuit information for forming a semiconductor integrated circuit such as an LSI, and is summarized in a form that can be reused in units of functional blocks. Design assets.

  The bus flow rate is the amount of data input / output to / from the partial circuit via the bus in the circuit per unit time. The unit of the bus flow rate may be, for example, [byte / sec] or [bit / sec]. When the bus width in the circuit is fixed, the number of cycles / sec may be used as a unit of bus flow rate. Further, when the data amount of a certain period during simulation is acquired and the period is fixed, the period may be regarded as a unit time and the data amount may be simply identified with the flow rate. In this case, the unit of the bus flow rate may be [byte], [bit], or the number of cycles. In the following description, the bus flow rate may be simply expressed as “flow rate”.

  The toggle rate represents the number of signal changes per unit time in the partial circuit. Specifically, for example, the toggle rate represents the average value of the toggle rate of each cell in the partial circuit (average toggle rate), that is, the average value of the number of signal changes per unit time in each cell. May be.

  In the example of FIG. 1, for the partial circuit X in the circuit, the bus flow rate (for example, bus flow rate x1) and the toggle rate (for example, toggle rate y1) measured for each period (for example, the period T1) during simulation. The measurement result 110 representing the above in association with each other is acquired.

  (2) The power estimation support apparatus 101 creates a toggle rate estimation function for obtaining the toggle rate of the partial circuit from the bus flow rate of the partial circuit based on the acquired measurement result. Specifically, for example, the power estimation support apparatus 101 performs a toggle analysis based on the measurement result 110 to obtain a toggle rate from the bus flow rate by performing regression analysis with the bus flow rate as an independent variable and the toggle rate as a dependent variable. Create an estimation function.

  Here, the power coefficient PC of the cell can be expressed using the following equation (1). The power coefficient PC represents, for example, the power of a cell consumed per signal change. Where C is the capacitance [pF] of the cell. V is the cell voltage [V].

PC = (1/2) * C * V ² (1)

In addition, the power of a circuit including n cells can be expressed using, for example, the following formula (2). Here, PC _m is the power coefficient PC of the m-th cell of n cells. TR _m is the toggle rate TR [toggle / ns] of the m-th cell of n cells.

  Further, assuming that the variation of the cell power coefficient PC is small, the power of a circuit including n cells can be expressed using, for example, the following equation (3).

  Further, assuming that there is a strong correlation between the bus flow rate and the average toggle rate, the average toggle rate of the partial circuit (IP) can be expressed using, for example, the following equation (4).

In other words, the power estimation support apparatus 101 performs regression analysis by substituting the bus flow rate and toggle rate (average toggle rate) for each period specified from the measurement result 110 into the above equation (4), whereby the partial circuit X A toggle rate estimation function can be created. More specifically, for example, the power estimation support apparatus 101 creates the toggle rate estimation function of the partial circuit X by obtaining the coefficients Coeff _X and Coff _C of the above equation (4) by the least square method.

  (3) The power estimation support apparatus 101 outputs the generated toggle rate estimation function in association with the partial circuit. Specifically, for example, the power estimation support apparatus 101 registers the created toggle rate estimation function of the partial circuit X in the library 120 in association with the identification information of the partial circuit X (for example, the IP name of the partial circuit X). You may decide.

  As described above, according to the power estimation support apparatus 101, it is assumed that there is a correlation between the bus flow rate to the partial circuit and the toggle rate, and the toggle rate estimation function (model equation) for estimating the toggle rate of the partial circuit from the bus flow rate. Can be created. As a result, the toggle rate of the partial circuit of the same type as the existing IP (for example, the partial circuit that realizes the same function as the existing IP) can be calculated from the bus flow rate even if the details of the circuit to be estimated for power consumption are not determined Can be estimated.

  Further, according to the power estimation support apparatus 101, for example, by substituting the toggle rate estimated from the bus flow rate to the partial circuit into the above equation (3), the power of the partial circuit can be obtained. The power can be estimated. In addition, as the power coefficient of the partial circuit (the value obtained by multiplying the average value of the power coefficient of the cell by the number n of cells, that is, the total value of the power coefficient of the cell), for example, The power coefficient of the existing IP can be used.

  Further, according to the power estimation support apparatus 101, the toggle rate estimation function can be registered in the library 120 in association with the identification information (for example, IP name) of the partial circuit. Thereby, a model formula for estimating the toggle rate of the partial circuit from the bus flow rate can be provided as a power library.

(Example of hardware configuration of power estimation support apparatus 101)
FIG. 2 is a block diagram illustrating a hardware configuration example of the power estimation support apparatus 101. In FIG. 2, a power estimation support apparatus 101 includes a CPU (Central Processing Unit) 201, a ROM (Read-Only Memory) 202, a RAM (Random Access Memory) 203, a magnetic disk drive 204, a magnetic disk 205, An optical disk drive 206, an optical disk 207, an I / F (Interface) 208, a display 209, a keyboard 210, and a mouse 211 are included. Each component is connected by a bus 200.

  Here, the CPU 201 governs overall control of the power estimation support apparatus 101. The ROM 202 stores a program such as a boot program. The RAM 203 is used as a work area for the CPU 201. The magnetic disk drive 204 controls reading / writing of data with respect to the magnetic disk 205 according to the control of the CPU 201. The magnetic disk 205 stores data written under the control of the magnetic disk drive 204.

  The optical disk drive 206 controls reading / writing of data with respect to the optical disk 207 according to the control of the CPU 201. The optical disk 207 stores data written under the control of the optical disk drive 206, or causes the computer to read data stored on the optical disk 207.

  The I / F 208 is connected to a network 212 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and is connected to other devices via the network 212. The I / F 208 controls an internal interface with the network 212 and controls input / output of data from an external device. For example, a modem or a LAN adapter may be employed as the I / F 208.

  A display 209 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As the display 209, for example, a CRT, a TFT liquid crystal display, a plasma display, or the like can be adopted.

  The keyboard 210 includes keys for inputting characters, numbers, various instructions, and the like, and inputs data. Moreover, a touch panel type input pad or a numeric keypad may be used. The mouse 211 performs cursor movement, range selection, window movement, size change, and the like. Note that the power estimation support apparatus 101 may not include, for example, the optical disk drive 206, the optical disk 207, the display 209, the keyboard 210, and the mouse 211 among the components described above.

(Specific example of measurement result data)
Next, a specific example of measurement result data of a power estimation simulation for estimating the power consumption of a circuit including a certain partial circuit IP will be described.

  3A and 3B are explanatory diagrams showing specific examples of measurement result data. In FIG. 3A and FIG. 3B, the measurement result data 300 correlates the flow rate, the execution rate, the average toggle rate, and the power measured for each partial circuit IP in the circuit during a predetermined period (Interval). It is the information including the measurement results 300-1 to 300-38.

  Here, the flow rate is the amount of data input / output to / from the partial circuit IP via the bus in the circuit measured in a predetermined period unit (for example, one cycle) during the simulation. The execution rate is a ratio of a period in which the partial circuit IP is in a state from when the partial circuit IP can execute the process requested by the processor in the circuit until the execution of the process is completed. The average toggle rate is an average value of the number of signal changes per unit time in each cell in the partial circuit IP. The power is an estimation result of power consumed by the partial circuit IP in a predetermined period.

  The measurement result data 300 corresponds to, for example, the measurement result 110 illustrated in FIG. Specifically, the flow rate of the measurement result data 300 corresponds to the bus flow rate of the measurement result 110, and the average toggle rate of the measurement result data 300 corresponds to the toggle rate of the measurement result 110.

(Functional configuration example of power estimation support apparatus 101)
FIG. 4 is a block diagram illustrating a functional configuration example of the power estimation support apparatus 101. In FIG. 4, the power estimation support apparatus 101 includes an acquisition unit 401, a creation unit 402, a calculation unit 403, and an output unit 404. The acquisition unit 401 to the output unit 404 are functions as a control unit. Specifically, for example, a program stored in a storage device such as the ROM 202, the RAM 203, the magnetic disk 205, and the optical disk 207 illustrated in FIG. The function is realized by executing or by the I / F 208. The processing result of each functional unit is stored in a storage device such as the RAM 203, the magnetic disk 205, and the optical disk 207, for example.

  The acquisition unit 401 has a function of acquiring measurement result data of a simulation for estimating the power consumption of a circuit including the partial circuit IP. Specifically, for example, the acquisition unit 401 receives the input measurement result data 300 (see FIG. 3) from a storage device such as the RAM 203 by a user operation input using the keyboard 210 and the mouse 211 illustrated in FIG. 2. You may decide to read.

  In addition, the acquisition unit 401 may acquire the measurement result data 300 by performing a power estimation simulation that estimates the power consumption of the circuit, for example. Note that the power estimation support apparatus 101 can execute a power estimation simulation based on, for example, gate level design data (for example, a net list) of a circuit including the partial circuit IP.

  The creation unit 402 obtains the average toggle rate from the flow rate by performing regression analysis using the flow rate of the partial circuit IP as an independent variable and the average toggle rate of the partial circuit IP as a dependent variable based on the acquired measurement result data. It has a function to create a toggle rate estimation function.

Specifically, for example, first, the creation unit 402 sets the above equation (4) as a regression equation. Next, the creation unit 402 calculates, for example, the measured value of the independent variable, the measured value of the dependent variable, and the estimated value of the independent variable using the regression equation based on the measurement result data 300 by the least square method. The coefficients Coeff _X and Coff _C are obtained so that the mean square of the difference is minimized. Thereby, the toggle rate estimation function which calculates | requires an average toggle rate from flow volume can be created.

  Further, the creation unit 402 performs an average from the flow rate by performing multiple regression analysis using the flow rate and execution rate of the partial circuit IP as independent variables and the average toggle rate of the partial circuit IP as a dependent variable based on the measurement result data. A toggle rate estimation function for obtaining the toggle rate may be created. The execution rate is a ratio of a period in which the partial circuit IP is in a state (execution state) until the execution of the process is completed after the partial circuit IP can execute the process requested by the processor in a predetermined period during the simulation.

Specifically, for example, first, the creation unit 402 sets the following equation (5) as a regression equation. Here, RunRatic is the execution rate of the partial circuit IP. Coeff _Y is a coefficient.

Next, the creation unit 402 calculates, for example, the measured value of the independent variable, the measured value of the dependent variable, and the estimated value of the independent variable using the regression equation based on the measurement result data 300 by the least square method. The coefficients Coeff _X , Coeff _Y , and Coff _C are obtained so that the mean square of the difference is minimized. Thereby, a toggle rate estimation function for obtaining an average toggle rate from the flow rate and the execution rate can be created.

  More specifically, for example, based on the measurement result data 300, the creation unit 402 performs multiple regression analysis using the flow rate and execution rate of the partial circuit IP as independent variables and the average toggle rate of the partial circuit IP as a dependent variable. Thus, the toggle rate estimation function of the following equation (6) can be created.

  Further, the creation unit 402 obtains the power (power consumption) of the partial circuit IP by using the toggle rate estimation function of the created partial circuit IP and the power value of the partial circuit IP consumed per signal change. A function of generating a power estimation function;

  For example, when the toggle rate estimation function is a function using only the flow rate of the partial circuit IP as a parameter, the creation unit 402 creates a power estimation function for obtaining the power of the partial circuit IP from the flow rate. When the toggle rate estimation function is a function using the flow rate and execution rate of the partial circuit IP as parameters, the creation unit 402 creates a power estimation function for obtaining the power of the partial circuit IP from the flow rate and execution rate. .

  Here, the power value of the partial circuit IP consumed per change of the signal is a value obtained by multiplying the number n of cells in the partial circuit IP and the average value of the power coefficient PC of the cell, that is, in the partial circuit IP. (It is assumed that the variation of the power coefficient PC of the cell is small). For the sake of explanation, the power value of the partial circuit IP consumed per signal change may be expressed as “power value (n * PC)”.

  The power estimation support apparatus 101 can obtain the power value (n * PC) of the partial circuit IP by, for example, estimating the power of the partial circuit IP at one toggle rate using an existing power estimation tool. it can. Further, the power estimation support apparatus 101 divides the average value of the power of the partial circuit IP by the average value of the average toggle rate based on the measurement result data 300, for example, to thereby determine the power value (n * PC) of the partial circuit IP. ) May be requested.

  Specifically, for example, the creation unit 402 substitutes the created toggle rate estimation function of the partial circuit IP and the power value (n * PC) of the partial circuit IP into the above equation (3), thereby obtaining a partial flow rate. A power estimation function for obtaining the power of the circuit IP is created. Thereby, a power estimation function for obtaining the power of the partial circuit IP from the flow rate of the partial circuit IP can be created.

  More specifically, for example, the creation unit 402 substitutes the toggle rate estimation function of the above equation (6) and the power value (n * PC) of the partial circuit IP into the above equation (3), thereby obtaining the following equation: The power estimation function of (7) can be created. However, the power value (n * PC) of the partial circuit IP is “10.4”.

  The calculation unit 403 has a function of calculating the estimated power consumption of the partial circuit IP in the circuit to be estimated using the power estimation function of the created partial circuit IP. For example, assume that the power estimation function is a function using only the flow rate of the partial circuit IP as a parameter. In this case, the calculation unit 403 calculates the estimated power consumption of the partial circuit IP by substituting the data amount (flow rate) input / output to / from the partial circuit IP via the bus in the circuit into the power estimation function.

  Further, it is assumed that the power estimation function is a function using the flow rate and execution rate of the partial circuit IP as parameters. In this case, the calculation unit 403 substitutes the data amount input / output to / from the partial circuit IP via the bus in the circuit in the predetermined period and the execution rate of the partial circuit IP into the power estimation function, thereby The estimated power consumption of the circuit IP is calculated.

  Note that the amount of data input to and output from the partial circuit IP via the bus in the circuit substituted for the power estimation function and the execution rate of the partial circuit IP are directly input to the power estimation support apparatus 101 by, for example, a user operation input. It may be input. Further, the power estimation support apparatus 101 obtains the amount of data input to and output from the partial circuit IP via the bus and the execution rate of the partial circuit IP by performing a simulation of an architecture simulation model that is a power estimation target. May be.

  The output unit 404 has a function of outputting the generated toggle rate estimation function in association with the partial circuit IP. Specifically, for example, the output unit 404 may register the toggle rate estimation function of the partial circuit IP in the library 120 (see FIG. 1) in association with the IP name of the partial circuit IP. The library 120 is realized by a storage device such as the RAM 203, the magnetic disk 205, and the optical disk 207, for example.

  Thereby, a model formula (toggle rate estimation function) for estimating the toggle rate of the partial circuit IP from the bus flow rate and the execution rate can be provided as a power library.

  The output unit 404 may output the generated power estimation function in association with the partial circuit IP. Specifically, for example, the output unit 404 may register the power estimation function of the partial circuit IP in the library 120 in association with the IP name of the partial circuit IP.

  Thereby, a model formula (power estimation function) for estimating the power of the partial circuit IP from the bus flow rate and the execution rate can be provided as a power library.

  The output unit 404 may output the calculated estimated power consumption of the partial circuit IP. As an output format of the output unit 404, for example, storage in a storage area such as the RAM 203, the magnetic disk 205, and the optical disk 207, display on the display 209, print output to a printer (not shown), and output to an external device by the I / F 208 There is transmission.

  Further, the calculation unit 403 may calculate the estimated power consumption of the circuit to be power estimated by accumulating the estimated power consumption for each partial circuit IP in the circuit to be power estimated, for example. In this case, the output unit 404 may output the estimated power consumption of the calculated circuit to be estimated.

(Example of average toggle rate estimation)
Next, an example of estimating the average toggle rate of the partial circuit IP estimated using the toggle rate estimation function created by the creation unit 402 will be described.

  FIG. 5 is an explanatory diagram showing a measurement result and an estimation result of the average toggle rate. In FIG. 5, a graph 501 represents a time-series change in the average toggle rate of the partial circuit IP estimated by substituting the flow rate and execution rate of the measurement result data 300 into the above equation (6). A graph 502 represents a time-series change in the average toggle rate of the measurement result data 300.

  According to the graphs 501 and 502, it can be seen that the measurement result and the estimation result of the average toggle rate of the partial circuit IP have similar time series changes.

(Example of power estimation)
Next, an example of estimating the power of the partial circuit IP estimated using the power estimation function created by the creation unit 402 will be described.

  FIG. 6 is an explanatory diagram showing the power measurement result and the estimation result. In FIG. 6, a graph 601 represents a time-series change in power of the partial circuit IP estimated by substituting the flow rate and execution rate of the measurement result data 300 into the above equation (7). A graph 602 represents a time-series change in power of the measurement result data 300.

  According to the graphs 601 and 602, it can be seen that the measurement result and the estimation result of the power (power consumption) of the partial circuit IP have the same time series change.

(Power estimation support processing procedure of power estimation support apparatus 101)
Next, the power estimation support processing procedure of the power estimation support apparatus 101 will be described.

  FIG. 7 is a flowchart illustrating an example of the power estimation support processing procedure of the power estimation support apparatus 101. In the flowchart of FIG. 7, first, the power estimation support apparatus 101 determines whether measurement result data of a simulation for estimating the power consumption of a circuit including the partial circuit IP has been acquired (step S701). The measurement result data is, for example, the measurement result data 300 illustrated in FIG.

  Here, the power estimation support apparatus 101 waits for acquisition of measurement result data (step S701: No). When the power estimation support apparatus 101 acquires the measurement result data (step S701: Yes), the power estimation support apparatus 101 sets a regression equation for calculating the dependent variable representing the average toggle rate of the partial circuit IP with the independent variable (step S702).

  The regression equation is, for example, the above equation (4) or the above equation (5). The regression equation is stored in a storage device such as the ROM 202, for example. The regression equation to be set may be determined in advance, and in step S702, the power estimation support apparatus 101 may accept selection of the regression equation to be set by a user operation input.

  Next, the power estimation support apparatus 101 calculates the value of the coefficient included in the set regression equation by the least square method based on the acquired measurement result data (step S703). Then, the power estimation support apparatus 101 creates a toggle rate estimation function of the partial circuit IP by substituting the calculated coefficient value into the regression equation (step S704).

  Next, the power estimation support apparatus 101 calculates the power value of the partial circuit IP at one toggle rate based on the acquired measurement result data (step S705). The power estimation support apparatus 101 substitutes the generated toggle rate estimation function of the partial circuit IP and the power value of the partial circuit IP at the time of 1 toggle rate into the above formula (3), thereby estimating the power of the partial circuit IP. A function is created (step S706).

  Next, the power estimation support apparatus 101 registers the generated toggle rate estimation function and power estimation function of the partial circuit IP in the library 120 in association with the IP name of the partial circuit IP (step S707). A series of processing ends.

  As described above, according to the power estimation support apparatus 101 according to the embodiment, assuming that there is a correlation between the bus flow rate to the partial circuit IP and the toggle rate, the toggle rate of the partial circuit IP is estimated from the bus flow rate. A toggle rate estimation function can be created. Specifically, for example, according to the power estimation support apparatus 101, toggle analysis is performed by performing regression analysis using the above equation (4) based on the measurement result data of the power estimation simulation of the circuit including the partial circuit IP. A rate estimation function can be created.

  Further, according to the power estimation support apparatus 101, it is assumed that there is a correlation between the bus flow rate and execution rate to the partial circuit IP and the toggle rate, and the toggle rate for estimating the toggle rate of the partial circuit IP from the bus flow rate and execution rate. A rate estimation function can be created. Specifically, for example, according to the power estimation support apparatus 101, toggle analysis is performed by performing regression analysis using the above equation (5) based on the measurement result data of the power estimation simulation of the circuit including the partial circuit IP. A rate estimation function can be created.

  As a result, the toggle rate of the partial circuit IP of the same type as the existing IP can be estimated from the bus flow rate and the execution rate, even if the details of the circuit to be estimated for power consumption are not determined.

  Further, according to the power estimation support apparatus 101, the power estimation function for estimating the power of the partial circuit IP is obtained using the toggle rate estimation function of the partial circuit IP and the power value of the partial circuit IP per one average toggle rate. Can be created. As a result, the power of the partial circuit IP of the same type as that of the existing IP can be estimated from the bus flow rate and the execution rate even if the details inside the circuit to be estimated for power consumption are not determined.

  Further, according to the power estimation support apparatus 101, a toggle rate estimation function can be registered in the library 120 in association with identification information (for example, IP name) of the partial circuit IP. Thereby, a model formula for estimating the toggle rate of the partial circuit IP from the bus flow rate and the execution rate can be provided as a power library. Further, step 707 may be performed at the time of use, and data necessary for the calculation in step 707 may be described in the library. In this way, after correcting the power value per toggle at the time of use, step 707 can be executed to use the power estimation function. In this way, it is possible to perform power estimation considering the difference between the technology library at the time of creating the power library and the technology library at the time of power estimation.

  Further, according to the power estimation support apparatus 101, the power estimation function can be registered in the library 120 in association with the identification information (for example, IP name) of the partial circuit IP. As a result, a model formula for estimating the power of the partial circuit IP from the bus flow rate and the execution rate can be provided as a power library.

  In the above description, the case where the execution state of the partial circuit IP is one has been described. However, the present invention is not limited to this. For example, when there are a plurality of execution states of the partial circuit IP, the power estimation support apparatus 101 acquires an execution rate in a predetermined period unit for each execution state, and performs a regression analysis using each execution rate as an independent variable. Thus, a toggle rate estimation function may be created. The bus flow rate for each execution state may be an independent variable.

(Example)
Examples will be described below. First, classification of power elements will be described. In the present embodiment, it is assumed that power estimation is performed by dividing a circuit by four attributes (power elements) of an FF clock unit, a clock tree unit, a non-clock tree unit, and a RAM / ROM unit.

  The FF clock unit is a set of FFs (FF clock terminals) included in the clock tree. The clock tree portion is a set of non-FF cells having output terminals that can be traced from a clock source. Note that a non-FF is a cell that is not an FF. The non-clock tree part is a set of cells not included in the clock tree. The RAM / ROM unit is a RAM or a ROM connected to a clock tree.

  The FF clock part and the clock tree part are power elements related to the power consumption tendency related to the clock tree for the unit cell. FF has about 15 times the number of non-FF elements in the clock tree in the leaf part of the clock tree. May also change.

  On the other hand, the clock tree has a tree structure, and there are many CGICs near the leaves. Further, the complexity of the trunk portion is determined by the layout matter rather than the FF number. For these reasons, there is a possibility that the power consumption tendency is different between the FF clock unit and the clock tree unit. Therefore, in this embodiment, the FF clock part and the clock tree part are handled separately.

  The non-clock tree part is divided into a first non-clock tree, a second non-clock tree, and a third non-clock tree. The first non-clock tree is a set of FFs connected to the clock tree. The second non-clock tree is a set of FFs not connected to the clock tree. The third non-clock tree is a set of non-FFs that are not connected to the clock tree. In the present embodiment, these first, second and third non-clock trees are handled as one group (non-clock tree portion).

  Regarding the RAM / ROM portion, first, when the unit cell 1 cell is compared with the RAM / ROM 1 macro, the difference in power consumption per unit is large. Further, power saving is often performed by stopping the clock inside and outside the RAM, and if the RAM control fails, the loss of the power saving effect increases. The number of RAM / ROMs in the circuit can be estimated to be about 1000, which is a small number compared with unit cells (for example, 2.6 million). Therefore, in this embodiment, the RAM / ROM is handled as one group (RAM / ROM unit).

(Power factor abstraction)
Next, abstraction of power coefficients when a circuit is divided by four attributes (power elements) of an FF clock unit, a clock tree unit, a non-clock tree unit, and a RAM / ROM unit will be described. In the following description, “partial circuit IP” may be simply expressed as “IP”. Further, the IP state from when the processing requested by the processor can be executed until the execution of the processing is completed is expressed as “Run state”, and the IP state other than the Run state is expressed as “Idle state”. There is a case.

  FIG. 8 is an explanatory diagram illustrating an example of the clock tree unit. In FIG. 8, an example of a clock tree inside the block 800 is shown. In the example of FIG. 8, there are three partial circuits of a partial clock tree A, a partial clock tree B, and a grouping unit grouped by the partial clock tree. The partial clock tree is a portion including a group of cells that are guaranteed to have the same toggle rate in the clock tree.

  The result of grouping and estimation is equivalent to dividing the clock tree into three. Further, since the partial clock tree A is always ON, it is a fixed consumption (a factor included in the intercept if graphed). Although the partial clock tree B is controlled by the hand-held CGIC, when considering that the hand-held CGIC controls the entire block, the IP is controlled in either Run / Idle state, with a large granularity. It is thought that it is the control in.

  Therefore, when only the Run state is viewed, the partial clock tree B has a fixed consumption. The grouping unit is controlled by automatic insertion CGIC, and this part depends on the operation of the circuit. However, there is not much problem in power estimation even when grouping. Therefore, if the Idle state is estimated separately and a Run state power model is created, it is possible to think that there is no need to separate the partial clock tree A, the partial clock tree B, and the grouping unit.

  Similarly, for the FF, first, the FF connected to the partial clock tree A is the same as the toggle rate of the clock tree A. The FF connected to the partial clock tree B is the same as the toggle rate of the clock tree B. Moreover, it can be said that the FF controlled by the automatic placement CGIC may use the average toggle rate of the grouping unit.

  Therefore, it can be said that the clock tree portion is the same as the clock tree portion, the clock component of the FF connected to the partial clock tree A is fixed consumption, and the clock portion connected to the partial clock tree B is fixed consumption in the Run state. . Further, the grouped part is considered to be a part depending on the operation of the circuit. For this reason, if a certain degree of accuracy is obtained by the grouping, it is considered that one power coefficient may be used for the block with respect to the clock tree and the FF clock.

  That is, the portion where the automatic placement CGIC is driven is a portion which may have a correlation with the bus flow rate, and the manual placement CGIC portion is usually a portion where ON / OFF is determined by a set value from the CPU (processor). This is the part that is considered to depend on the state value of. The portion without CGIC corresponds to a fixed value portion (intercept portion) that consumes power in a fixed manner. Next, the non-clock tree part will be described.

  FIG. 9 is an explanatory diagram illustrating an example of a non-clock tree unit. In FIG. 9, the non-clock tree unit 900 determines whether or not the circuit can move depending on the presence or absence of input data. In the non-clock tree unit 900, the data acquisition interval expands and contracts depending on the number of loops, etc., but measurement is often performed under conditions where power or performance is the most severe.

  Assuming that throughput and latency are close to a constant value under such severe conditions, the bus flow rate and the calculation amount are proportional, and the calculation amount and the toggle rate are proportional. Therefore, the bus flow rate and the toggle rate are proportional. I can guess it will be a relationship.

  Note that the IP power value may change depending on the number of loops. For this reason, for example, in the case of an IP for moving image processing, a description such as “the power value is based on the measured value of the Nth standard image” may be appended to the power value of the IP.

  The RAM / ROM is a circuit in which the number contained in one instance is small and the number of accesses depends on the operation of the circuit portion. For this reason, in consideration of the fact that access can be expected as described in the circuit, it can be expected that a certain degree of estimation accuracy can be obtained as a RAM / ROM component.

(Power modeling considering IP status)
Here, power modeling considering the IP state (Run state, Idle state) will be described. Hereinafter, one block will be described as a theme. This block is temporarily referred to as “block A”. Here, the period from the start assert to the IP to the done assert during the simulation period of the emulation power estimation is set to the Run state, and the other periods are set to the Idle state.

  FIG. 10 is a Gantt chart showing the operation status of the block A. In FIG. 10, a Gantt chart 1000 shows an operation state (Run state, Idle state) of block A that changes with the lapse of simulation time. Note that the horizontal axis represents the simulation time.

  FIG. 11 is an explanatory diagram showing state data of the block A. In FIG. 11, the status data 1100 indicates the detailed operation status of the block A corresponding to the Gantt chart 1000 shown in FIG. According to the state data 1100, it can be said that the operation state of the block A is in the Run state from 281 [ms] onward.

  12 and 13 are explanatory diagrams showing simulation results of emulation power estimation. In FIG. 12, a graph 1200 shows the power of the clock tree portion, the FF clock portion, and the RAM / ROM portion that change with the lapse of the simulation time. In FIG. 13, a graph 1300 indicates the number of toggles of the FF input terminal of the non-clock tree portion that changes with the lapse of the simulation time.

  For example, according to the Gantt chart 1000, the state is almost 100 [%] Run from 281 [ms] to 2.5 [s]. On the other hand, according to the graph 1200, significant increases and decreases in the power of the clock tree unit, the FF clock unit, and the RAM / ROM unit occur in a time that cannot be ignored. Further, according to the graph 1300, a significant increase / decrease in the number of toggles in the non-clock tree portion occurs in a time that cannot be ignored. That is, it is difficult to estimate power with high accuracy by power modeling considering only the Run / Idle state.

(Power modeling considering flow rate)
Next, power modeling considering the flow rate (bus flow rate) will be described. Assuming that there is a proportional relationship between the IP flow rate and the IP calculation amount, and that there is a proportional relationship between the IP calculation amount and the IP power, there is a proportional relationship between the IP flow rate and the toggle rate. I can guess. Hereinafter, the experimental results of power modeling considering the flow rate will be described with reference to FIGS.

  FIG. 14 is an explanatory diagram (part 1) illustrating the correlation between the toggle rate of the non-clock tree and the flow rate. In FIG. 14, a graph 1400 represents a time-series change in the number of toggles of the FF input data terminal and the flow rate.

  FIG. 15 is an explanatory diagram (part 2) illustrating the correlation between the toggle rate of the non-clock tree and the flow rate. 15, a scatter diagram 1500 of the number of toggles of the FF input data terminal and the flow rate of each sample of the graph 1400 shown in FIG. 14 is shown. The determination coefficient of the scatter diagram 1500 is “0.98”, and it can be said that a sufficient correlation is observed.

  The determination coefficient is an index indicating how much an independent variable (explanatory variable) can explain a dependent variable (explained variable). The coefficient of determination is used as a measure of the goodness of fit of a regression equation obtained from a sample value, for example. The determination coefficient represents, for example, how similar the change of the variable of x and the change of the variable of y are (x and y are, for example, flow rate).

  FIG. 16 is an explanatory diagram (part 1) showing the correlation between the power of the RAM / ROM and the flow rate. In FIG. 16, a graph 1600 represents a time-series change in the power and flow rate of the RAM / ROM.

  FIG. 17 is an explanatory diagram (part 2) illustrating the correlation between the power of the RAM / ROM and the flow rate. 17, a scatter diagram 1700 of the power and flow rate of each sample of the graph 1600 shown in FIG. 16 is shown. The determination coefficient of the scatter diagram 1700 is “0.91”, and it can be said that a sufficient correlation is observed.

  FIG. 18 is an explanatory diagram (part 1) showing the correlation between the power of the FF clock and the flow rate. In FIG. 18, a graph 1800 represents a time-series change in the power and flow rate of the clock terminal component of the FF.

  FIG. 19 is an explanatory diagram (part 2) illustrating the correlation between the power of the FF clock and the flow rate. 19, a scatter diagram 1900 of the power and flow rate of the FF clock terminal component of each sample of the graph 1800 shown in FIG. 18 is shown. The determination coefficient of the scatter diagram 1900 is “0.18”, and it can be said that no correlation is observed.

  FIG. 20 is an explanatory diagram (part 1) illustrating the correlation between the power of the clock tree and the flow rate. In FIG. 20, a graph 2000 represents a time-series change in power and flow rate of the clock tree.

  FIG. 21 is an explanatory diagram (part 2) illustrating the correlation between the power of the clock tree and the flow rate. In FIG. 21, a scatter diagram 2100 of the power and flow rate of the clock tree of each sample of the graph 2000 shown in FIG. 20 is shown. The determination coefficient of the scatter diagram 2100 is “0.51”, and it can be said that a sufficient correlation has not been observed.

  Thus, although it can be said that there is a correlation with the flow rate for the non-clock tree portion and the RAM / ROM portion, it can be said that some improvement measures are necessary for the clock tree portion and the FF clock portion. That is, it is difficult to estimate power with high accuracy by power modeling considering only the flow rate.

(Power modeling considering flow rate and IP status)
Next, power modeling considering the flow rate and the IP state will be described. According to the power modeling considering the flow rate, the tendency is divided between the clock system, the non-clock system, and the RAM. Although the RAM is a clock system, there is a possibility that the correlation is strong because the clock gating of the RAM can be performed with a large granularity by the chip enable signal.

  It can be assumed that the clock system also has a correlation in the part of the automatic insertion CGIC. The RAM / ROM and the non-clock tree have a strong correlation between the calculation amount and the power amount, and the Idle state and the Run state show the same tendency when the calculation amount is very small. Even when the amount of calculation in the state is extremely small, a different tendency may be shown.

  That is, the clock tree and the FF clock have power consumption due to IP control factors, and since this power consumption cannot be measured from the flow rate, it can be assumed that there is no power. Therefore, in the following description, an experimental result in the case of performing modeling that has “Idle state and Run state, and the Run state has a correlation with the flow rate” will be described with reference to FIGS.

  FIG. 22 is an explanatory diagram (part 3) illustrating the correlation between the power of the FF clock and the flow rate. In FIG. 22, a graph 2200 represents a time-series change in the power value and flow rate of the FF clock terminal component only in the RUN state. Note that the vicinity of 0 [ms] to 300 [ms] is excluded because of the idle state.

  FIG. 23 is an explanatory diagram (part 4) illustrating the correlation between the power of the FF clock and the flow rate. FIG. 23 shows a scatter diagram 2300 of the power value and flow rate of the FF clock terminal component of each sample of the graph 2200 shown in FIG. The coefficient of determination in the scatter diagram 2300 is “0.75”, which is a significant improvement over the experimental results shown in FIG.

  FIG. 24 is an explanatory diagram (part 5) illustrating the correlation between the power of the FF clock and the flow rate. 24, a graph 2400 is a time series change of the predicted power value and the actual power value (FFCLK in FIG. 24) estimated from the flow rate using the equation obtained by the regression analysis in the example shown in FIG. Represents. According to the graph 2400, it can be seen that the predicted power value matches the actual power value.

  FIG. 25 is an explanatory diagram (part 3) illustrating the correlation between the power of the clock tree and the flow rate. In FIG. 25, a graph 2500 represents a time-series change in the power value and flow rate of the clock tree only in the RUN state. Note that the vicinity of 0 [ms] to 300 [ms] is excluded because of the idle state.

  FIG. 26 is an explanatory diagram (part 4) illustrating the correlation between the power of the clock tree and the flow rate. In FIG. 26, a scatter diagram 2600 of the power value and flow rate of the clock tree of each sample of the graph 2500 shown in FIG. 25 is shown. The coefficient of determination in the scatter diagram 2600 is “0.74”, which is a significant improvement over the experimental results shown in FIG.

  FIG. 27 is an explanatory diagram (part 5) illustrating the correlation between the power of the clock tree and the flow rate. In FIG. 27, a graph 2700 is a time series of the predicted power value estimated from the flow rate and the actual power value (clock tree in FIG. 27) using the equation obtained by regression analysis in the example shown in FIG. It represents a change. According to the graph 2700, it can be seen that the predicted power value matches the actual power value.

  As described above, regarding the FF clock and the clock tree, it is understood that the determination coefficient is greatly increased by considering the Run state, and the accuracy of the power estimation can be improved.

  Moreover, as shown in FIG. 24 and FIG. 27, the shape of the waveform is very similar. This is considered to depend on the circuit structure. For example, if there is the circuit shown in FIG. 8, in the idle state, it is considered that the manual placement CGIC is stopped and the partial clock tree B is completely stopped.

  In the Run state, the manual placement CGIC is ON, and the portion of the partial clock tree B seems to be operating at all times, so the fixed consumption increases. On the other hand, the automatic placement CGIC is turned on only when necessary for calculation. Therefore, it is considered that there is some dependency on the calculation amount. That is, it can be said that a proportional relationship is established between the amount of calculation of IP and the toggle rate.

  It can be presumed that the reason why the determination coefficient is increased by classifying the IP state by Run / Idle is that there is a manual insertion CGIC having a strong correlation with Run / Idle. Therefore, it is desirable to identify and define IP states that correlate with CGIC that can stop a wide range of clock trees, and to perform regression analysis for each state. In addition, as shown in FIG. 28, there may be a case where a plurality of major components exist.

  FIG. 28 is an explanatory diagram showing an example of a multifunction. In FIG. 28, for example, if the power difference between sub-block A and sub-block B is large and the power of the common sub-block portion is small, it becomes important whether the signal passes through sub-block A or sub-block B. come.

  In this case, for example, it is desirable to set the value of the setting register as the state. Since the bus access portion is common, the flow rate and the power of the non-clock tree portion are greatly different. The FF clock and clock part are also affected. On the other hand, if the power difference between sub-block A and sub-block B is small, the power of the common sub-block portion is large, and the multipath portion is small, there is no need to deal with it.

  That is, in power modeling, it is desirable to take into account parameters correlated with manual insertion CGIC that affects a wide range (including designs that are expected to obtain the same effect using PowerPro or the like). And it can be said that the safety degree of power model creation by regression analysis is increased by considering a parameter correlated with manual insertion CGIC.

(Power modeling considering flow rate and waiting time)
Next, power modeling considering flow rate and waiting time will be described. Looking at the power of the clock tree and the FF clock in the example described in the power modeling considering the flow rate described above, the calculation amount is increased where it should be reduced. There is a change that has a correlation.

  This is considered to be an event in which power is wasted somehow. Also, considering that the power modeling decision coefficient considering the flow rate is a good value to some extent, it can be estimated that an event caused by the bus is occurring. Therefore, assuming that the time spent waiting for the right to use the bus is a negative factor, the case where the waiting time is added to the power modeling element in addition to the bus flow rate will be described.

  The waiting time is the time spent waiting for the right to use the bus, that is, the accumulated time from when a request is sent to the arbiter until the bus is allowed to be used. In the experiment, for the sample with waiting time data and the sample with power, the data acquisition condition is about 1 [ms] for the former, and about 6 [ms] for the latter, and the start time It was found that there was a gap.

  Therefore, in this experiment, in accordance with the waiting time data, the power value including the time of the sampling point is taken from the latter data and collected into one data (hereinafter referred to as “sample data 2”). "). The waiting time is generated for each port.

  Hereinafter, an example in which multiple regression analysis is performed using only the flow rate in the sample data 2 will be described with reference to FIGS. 29 to 32. Note that sample data 2 has a transaction history of two read ports and one write port.

  FIG. 29 is an explanatory diagram (part 1) illustrating the correlation of the clock tree with the sample data 2. In FIG. 29, a graph 2900 represents a time-series change between the predicted value and the observed value from the flow rate in this data set regarding the power of the clock tree.

  FIG. 30 is an explanatory diagram (part 2) of the correlation of the clock tree with the sample data 2. FIG. 30 shows a scatter diagram 3000 of predicted values and observed values from the flow rate in this data set regarding the power of the clock tree. The determination coefficient of the scatter diagram 3000 is “0.47”, which is equivalent to the determination coefficient “0.51” of FIG.

  FIG. 31 is an explanatory diagram (part 3) illustrating the correlation of the clock tree with the sample data 2. In FIG. 31, a graph 3100 represents a time-series change between the predicted value and the observed value from the flow rate in this data set regarding the power of the FF clock terminal component.

  FIG. 32 is an explanatory diagram (part 4) illustrating the correlation of the clock tree with the sample data 2. FIG. 32 shows a scatter diagram 3200 of predicted values and observed values from the flow rate in this data set regarding the power of the FF clock terminal component. The determination coefficient of the scatter diagram 3200 is “0.15”, which is equivalent to the determination coefficient “0.18” of FIG.

  From these facts, it can be seen that the same accuracy is obtained even in the data sets having different time granularities, and it is not necessary to consider the factor that the number of ports is increased. Therefore, it can be said that the sample data 2 has the same quality as the data used up to (power modeling considering the flow rate and the IP state). Therefore, sample data 2 is used in the regression analysis experiment using the waiting time.

(Regression analysis result using flow rate and waiting time)
Next, the regression analysis results using the flow rate and the waiting time will be described with reference to FIGS.

  FIG. 33 is an explanatory diagram (part 1) illustrating the correlation between the clock tree power estimation based on the flow rate and the waiting time. In FIG. 33, a graph 3300 represents a time-series change between the predicted value and the observed value of the clock tree power according to the flow rate and the waiting time.

  FIG. 34 is an explanatory diagram (part 2) showing the correlation between the clock tree power estimation based on the flow rate and the waiting time. 34 shows a scatter diagram 3400 of predicted values and observed values of the graph 3300 shown in FIG. The determination coefficient of the scatter diagram 3400 is “0.97”, and it can be said that a sufficient correlation is observed.

  FIG. 35 is an explanatory diagram (part 1) illustrating the correlation between the FF clock power estimation based on the flow rate and the waiting time. In FIG. 35, a graph 3500 represents a time-series change between the predicted value and the observed value of the power of the FF clock terminal component according to the flow rate and the waiting time.

  FIG. 36 is an explanatory diagram (part 2) illustrating the correlation of the FF clock power estimation based on the flow rate and the waiting time. 36 shows a scatter diagram 3600 of predicted values and observed values of the graph 3500 shown in FIG. The determination coefficient of the scatter diagram 3600 is “0.89”, and it can be said that a sufficient correlation is observed.

  Thus, by considering the flow rate and the waiting time, a sufficient correlation can be seen in terms of the determination coefficient without considering the state. However, as can be seen from the graph 3300 shown in FIG. 33 and the graph 3500 shown in FIG. 35, the amplitude is large and an error is observed.

(Regression analysis result using flow rate, waiting time and status)
Next, regression analysis results using the flow rate, the waiting time, and the state will be described with reference to FIGS.

  FIG. 37 is an explanatory diagram (part 1) illustrating a correlation between the clock tree power estimation based on the flow rate and the waiting time in the Run state. In FIG. 37, a graph 3700 represents a time-series change between the predicted value and the observed value of the clock tree power due to the flow rate and the waiting time focusing only on the Run state.

  FIG. 38 is an explanatory diagram (part 2) of the correlation between the clock tree power estimation based on the flow rate and the waiting time in the Run state. FIG. 38 shows a scatter diagram 3800 of predicted values and observed values of the graph 3700 shown in FIG. The determination coefficient of the scatter diagram 3800 is “0.76”, and it can be said that a correlation is observed. In addition, although the coefficient of determination is smaller than that in FIG. 34, it can be seen from the graph 3300 in FIG. 33 and the graph 3700 in FIG. 37 that the amplitude is small and the error is small.

  FIG. 39 is an explanatory diagram (part 1) illustrating the correlation between the flow rate in the Run state and the FF clock power estimation based on the waiting time. In FIG. 39, a graph 3900 represents a time-series change in the predicted value and the observed value of the power of the FF clock terminal component due to the flow rate and waiting time focusing only on the Run state.

  FIG. 40 is an explanatory diagram (part 2) of the correlation between the FF clock power estimation based on the flow rate and the waiting time in the Run state. In FIG. 40, a scatter diagram 4000 of predicted values and observed values of the graph 3900 shown in FIG. 39 is shown. The determination coefficient of the scatter diagram 4000 is “0.77”, and it can be said that the correlation is observed. In addition, although the coefficient of determination is smaller than that in FIG. 36, it can be seen from the graph 3500 in FIG. 35 and the graph 3900 in FIG. 39 that the amplitude is small and the error is small.

  Thus, estimation errors can be suppressed by considering the state according to the flow rate and the waiting time.

(Regression analysis result using flow rate and condition)
Next, with reference to FIGS. 41 to 44, the regression analysis results using the flow rate in the Run state will be described using the analysis results used instead of the data used until the power modeling considering the flow rate and the IP state. .

  FIG. 41 is an explanatory diagram (part 1) illustrating the correlation of the clock tree power estimation based on the flow rate in the Run state. In FIG. 41, a graph 4100 represents a time-series change between the predicted value and the observed value of the clock tree power due to the flow rate focusing only on the Run state.

  FIG. 42 is an explanatory diagram (part 2) illustrating the correlation of the clock tree power estimation based on the flow rate in the Run state. In FIG. 42, a scatter diagram 4200 of predicted values and observed values of the graph 4100 shown in FIG. 41 is shown. The determination coefficient of the scatter diagram 4200 is “0.74”, and it can be said that the correlation is observed as in the example shown in FIG.

  FIG. 43 is an explanatory diagram (part 1) illustrating the correlation of the FF clock power estimation based on the flow rate in the Run state. In FIG. 43, a graph 4300 represents a time series change between the predicted value and the observed value of the power of the FF clock terminal component due to the flow rate focusing only on the Run state.

  FIG. 44 is an explanatory diagram (part 2) illustrating the correlation of the FF clock power estimation based on the flow rate in the Run state. 44, a scatter diagram 4400 of the predicted values and observed values of the graph 4300 shown in FIG. 43 is shown. The determination coefficient of the scatter diagram 4400 is “0.75”, and it can be said that the correlation is observed as in the example shown in FIG.

(Description example of the power estimation support apparatus 101)
45A, 45B, and 45C are explanatory diagrams illustrating a description example of the power estimation support apparatus 101. FIG. According to the description example 4500 shown in FIGS. 45A, 45B, and 45C, the occupation of each state included in the section in which the power is estimated using the toggle rate value, the bus information, and the IP state history used for the power estimation. The rate can be determined.

  Further, according to the description example 4500, it is possible to perform a regression analysis with the calculation formula of each state * the sum of the occupation ratios and output an estimation formula. Note that the counter prepares the number of IP states * the number of parameters, and outputs the counter value of the state A parameter a. Further, the period / unit time of the state is also output.

(Example of block N for estimation)
Next, an example of the estimation target block N will be described. Here, the estimation target block N (partial circuit IP) classified into the circuit ranges of the clock tree portion, the non-clock tree portion, and the RAM / ROM portion will be described.

  FIG. 46 is an explanatory diagram of an example of the estimation target block N. In FIG. 46, the estimation target block N is classified into circuit ranges of a clock tree portion, a non-clock tree portion, and a RAM / ROM portion. In this case, if the flow rate (Trans) and the state (State) are parameters (independent variables) used in the regression analysis, the value to be observed in order to estimate the power of the estimation target block N is the flow rate for the estimation target block N ( (Trans) and state (State).

Flow rate (Trans) and state parameters (State) respectively X _ntrans, When X _NState, power estimation function estimates the target block N is, for example, the following equation (8). Incidentally, X _ntrans, units of X _NState are the same units as when performing a regression analysis.

  As described above, according to the power estimation support apparatus 101, for example, a power library for each clock tree unit, FF clock unit, non-clock tree unit, and RAM / ROM unit can be provided. For example, when the partial circuit IP is classified into the circuit ranges of the clock tree unit, the non-clock tree unit, and the RAM / ROM unit, the power estimation support apparatus 101 acquires measurement result data of each circuit range, A toggle rate estimation function for the circuit range can be created.

  The power estimation support apparatus 101 can create a power estimation function for each circuit range using the toggle rate estimation function for each circuit range and the power value (n * PC) for each circuit range. This makes it possible to estimate power consumption by category such as a clock tree portion, a non-clock tree portion, and a RAM / ROM portion.

  The power estimation support method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. The power estimation support program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The power estimation support program may be distributed via a network such as the Internet.

  In addition, the power estimation support apparatus 101 described in the present embodiment is a PLD (hereinafter simply referred to as “ASIC”) such as a standard cell or a structured specific integrated circuit (ASIC) (hereinafter simply referred to as “ASIC”) or a PLD (such as an FPGA). It can also be realized by Programmable Logic Device). Specifically, for example, the function (acquisition unit 401 to output unit 404) of the power estimation support apparatus 101 described above is defined by HDL description, and the HDL description is logically synthesized and given to the ASIC or PLD. The estimate support apparatus 101 can be manufactured.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary note 1)
Associating the amount of data input / output to / from a partial circuit via a bus in the circuit measured in a predetermined unit of time by simulation for estimating the power consumption of the circuit and the number of signal changes per unit time in the partial circuit Reading out the measurement results expressed as
Based on the measurement result, the data amount is an independent variable, and a regression analysis is performed using the number of changes as a dependent variable, thereby creating a toggle rate estimation function for obtaining the number of changes from the data amount.
A power estimation support program characterized by causing processing to be executed.

(Supplementary note 2)
Using the generated toggle rate estimation function and the power value of the partial circuit consumed per change of the signal, a process for generating a power estimation function for determining the power of the partial circuit from the data amount is executed. The power estimation support program according to supplementary note 1, wherein the program is executed.

(Supplementary Note 3) The measurement result is associated with the data amount and the number of changes, and the execution of the process is completed after the partial circuit can execute the requested process in the predetermined period. Represents the percentage of the period that is in state,
The process of creating the toggle rate estimation function is as follows:
Based on the measurement result, toggle rate estimation for obtaining the number of changes from the data amount and the ratio by performing multiple regression analysis with the data amount and the ratio as independent variables and the number of changes as a dependent variable. The power estimation support program according to attachment 2, wherein the function is created.

(Supplementary Note 4) The process of creating the power estimation function is as follows:
Using the generated toggle rate estimation function and the power value of the partial circuit consumed per change of the signal, a power estimation function for determining the power of the partial circuit from the data amount and the ratio is generated The power estimation support program according to appendix 2 or 3, characterized in that:

(Supplementary note 5)
The power estimation support program according to any one of appendices 2 to 4, wherein a process of outputting the generated toggle rate estimation function in association with the partial circuit is executed.

(Appendix 6)
The power estimation support program according to any one of appendices 2 to 5, wherein a process of outputting the generated power estimation function in association with the partial circuit is executed.

(Appendix 7)
Associating the amount of data input / output to / from a partial circuit via a bus in the circuit measured in a predetermined unit of time by simulation for estimating the power consumption of the circuit and the number of signal changes per unit time in the partial circuit Reading out the measurement results expressed as
Based on the measurement result, the data amount is an independent variable, and a regression analysis is performed using the number of changes as a dependent variable, thereby creating a toggle rate estimation function for obtaining the number of changes from the data amount.
A computer-readable recording medium in which a power estimation support program for executing processing is recorded.

(Supplementary note 8) The amount of data input to and output from the partial circuit via the bus in the circuit measured by a simulation for estimating the power consumption of the circuit and the number of signal changes per unit time in the partial circuit An acquisition unit for acquiring a measurement result in association with
Based on the measurement result acquired by the acquisition unit, a toggle rate estimation function for obtaining the number of changes from the data amount by performing regression analysis with the data amount as an independent variable and the number of changes as a dependent variable. A creation section to create,
A power estimation support apparatus comprising:

(Supplementary note 9) Amount of data input / output to / from a partial circuit via a bus in the circuit measured by a simulation for estimating power consumption of the circuit and a number of signal changes per unit time in the partial circuit An acquisition unit for acquiring a measurement result in association with
Based on the measurement result acquired by the acquisition unit, a toggle rate estimation function for obtaining the number of changes from the data amount by performing regression analysis with the data amount as an independent variable and the number of changes as a dependent variable. A creation section to create,
A power estimation support apparatus comprising: a computer having:

(Supplementary note 10)
Associating the amount of data input / output to / from a partial circuit via a bus in the circuit measured in a predetermined unit of time by simulation for estimating the power consumption of the circuit and the number of signal changes per unit time in the partial circuit Reading out the measurement results expressed as
Based on the measurement result, the data amount is an independent variable, and a regression analysis is performed using the number of changes as a dependent variable, thereby creating a toggle rate estimation function for obtaining the number of changes from the data amount.
A power estimation support method characterized by executing processing.

101 Power Estimation Support Device 401 Acquisition Unit 402 Creation Unit 403 Calculation Unit 404 Output Unit

Claims (9)

On the computer,
In association with the number of changes in the circuit data amount signal per unit time in the partial circuit is input to the partial circuit via the bus in the circuit that is measured in a predetermined period unit by simulation to estimate the power consumption of , Reading a measurement result representing a ratio of a period in which the partial circuit can execute the requested process in the predetermined period until the execution of the process is completed from the storage unit,
Based on the measurement result, toggle rate estimation for obtaining the number of changes from the data amount and the ratio by performing multiple regression analysis with the data amount and the ratio as independent variables and the number of changes as a dependent variable. Create a function,
A power estimation support program characterized by causing processing to be executed. In the computer,
Using the generated toggle rate estimation function and the power value of the partial circuit consumed per change of the signal, a power estimation function for determining the power of the partial circuit from the data amount and the ratio is generated The power estimation support program according to claim 1, wherein the power estimation support program is executed.   In the computer,
  The power estimation support program according to claim 1, wherein a process for outputting the generated toggle rate estimation function in association with the partial circuit is executed.   In the computer,
  The power estimation support program according to claim 2, wherein a process of outputting the generated power estimation function in association with the partial circuit is executed.   Corresponding to the amount of data input / output to / from the partial circuit via the bus in the circuit measured by a simulation for estimating the power consumption of the circuit and the number of signal changes per unit time in the partial circuit An acquisition unit that acquires a measurement result representing a ratio of a period in which the partial circuit can execute the requested process in the predetermined period until the execution of the process is completed;
  Based on the measurement result acquired by the acquisition unit, the data amount and the ratio are set as independent variables, and multiple regression analysis is performed using the number of changes as a dependent variable. A creation unit for creating a toggle rate estimation function for obtaining the number of changes;
  A power estimation support apparatus comprising:   Computer
  Corresponding to the amount of data input / output to / from the partial circuit via the bus in the circuit measured by a simulation for estimating the power consumption of the circuit and the number of signal changes per unit time in the partial circuit , Reading a measurement result representing a ratio of a period in which the partial circuit can execute the requested process in the predetermined period until the execution of the process is completed from the storage unit,
  Based on the measurement result, toggle rate estimation for obtaining the number of changes from the data amount and the ratio by performing multiple regression analysis with the data amount and the ratio as independent variables and the number of changes as a dependent variable. Create a function,
  A power estimation support method characterized by executing processing.   On the computer,
  Corresponding to the amount of data input / output to / from the partial circuit via the bus in the circuit measured by a simulation for estimating the power consumption of the circuit and the number of signal changes per unit time in the partial circuit , Reading a measurement result representing a ratio of a period in which the partial circuit can execute the requested process in the predetermined period until the execution of the process is completed from the storage unit,
  Based on the measurement result, toggle rate estimation for obtaining the number of changes from the data amount and the ratio by performing multiple regression analysis with the data amount and the ratio as independent variables and the number of changes as a dependent variable. Create a function
  Using the created toggle rate estimation function and the power value of the partial circuit consumed per change of the signal, a power estimation function for determining the power of the partial circuit from the data amount is created.
  A power estimation support program characterized by causing processing to be executed. The process of creating the power estimation function includes:
Using the generated toggle rate estimation function and the power value of the partial circuit consumed per change of the signal, a power estimation function for determining the power of the partial circuit from the data amount and the ratio is generated The power estimation support program according to claim 7 , wherein:   Computer
  Corresponding to the amount of data input / output to / from the partial circuit via the bus in the circuit measured by a simulation for estimating the power consumption of the circuit and the number of signal changes per unit time in the partial circuit , Reading a measurement result representing a ratio of a period in which the partial circuit can execute the requested process in the predetermined period until the execution of the process is completed from the storage unit,
  Based on the measurement result, toggle rate estimation for obtaining the number of changes from the data amount and the ratio by performing multiple regression analysis with the data amount and the ratio as independent variables and the number of changes as a dependent variable. Create a function
  Using the created toggle rate estimation function and the power value of the partial circuit consumed per change of the signal, a power estimation function for determining the power of the partial circuit from the data amount is created.
  A power estimation support method characterized by executing processing.

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