JP6169436B2 - Dual system verification device - Google Patents

Description

  The present invention relates to a dual system verification apparatus, and more particularly to a dual system verification apparatus that can ensure fail-safety with a simple circuit without using a processing circuit such as a CPU.

  Conventionally, for example, in a control system that requires high safety and high reliability, such as a railway signal security device and an industrial robot, a double-system arithmetic device is often used.

  As such a dual system verification device, conventionally, for example, an A system arithmetic processing circuit, a B system arithmetic processing circuit, a verification circuit, and a reset circuit are provided, and an A system arithmetic processing circuit and a B system arithmetic processing circuit are provided. Data is exchanged between the systems, and it is judged whether the data matches or does not match between the systems, and whether the data matching results match between the systems, and the data matching results do not match Until the number of times reaches the threshold value, output of the signal indicating that the result of the data matching is different to the verification circuit is stopped, and then the A-system arithmetic processing circuit and the B-system arithmetic processing circuit are reset. When it reaches, let's output a signal indicating that the result of data verification is different to the verification circuit, stop reset, and maintain the output of the verification circuit at high level or low level to drop the safety relay Techniques have been disclosed (e.g., see Patent Document 1.).

JP 2012-038026 A

  However, the conventional technique requires a collation circuit independent of the two arithmetic processing circuits, and the two arithmetic processing circuits perform clock synchronization, so that the circuit becomes complicated and large. There is a problem that it is necessary to perform processing using an arithmetic circuit such as a CPU.

  In recent years, it has been desired to achieve SLI4 level safety based on the international standard IEC62425. In order to achieve SLI4 level safety in this way, the clock of each arithmetic processing circuit is ensured independence. Therefore, the conventional technique has a problem that the number of components such as a CPU is large and it is extremely difficult to make the clock independent. Therefore, there has been a demand for a dual collation apparatus that can ensure fail-safety with a simple circuit without using a processing circuit such as a CPU.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a dual system verification device that can ensure fail-safety with a simple circuit without using a processing circuit such as a CPU. To do.

In order to achieve the above object, according to the present invention, the dual system verification device according to the first aspect of the present invention sets the count value in advance when the count value counted based on a predetermined input signal reaches a target value. First and second output counters that are respectively replaced with different arbitrary set values;
The count values of the first and second output counters are compared, and if a mismatch is detected, each count value is collated with the corresponding arbitrary set value, and the count value and the arbitrary set value are counted. A verification circuit that determines that the operation is normal;
It is characterized by providing.

An invention according to a second aspect includes the first collation device and the second collation device each including the first and second output counters according to the first aspect,
The first and second output counters perform counting based on the input signal and a signal to which the input signal is input via a detector,
The first verification unit and the second verification device, a phase comparator circuit for detecting a phase difference and sends the first and second output counter with signal input via the input signal and the detector It is characterized by having each.

According to a third aspect of the present invention, in the second aspect, the first verification device and the second verification device receive the phase difference sent from the phase comparison circuit and convert it into a frequency signal corresponding to the phase difference. And a conversion circuit for sending to the first and second output counters.

According to a fourth aspect of the present invention, in any one of the first to third aspects, the arbitrary set value is a value that cannot be generated in a normal count by the first and second output counters. It is characterized by that.
According to a fifth aspect of the present invention, in the verification circuit according to any one of the first to fourth aspects, the difference between the count values of the first and second output counters exceeds a preset allowable value. Then, it is collated with the arbitrary set value.

According to the first aspect of the present invention, when the count value reaches the target value by the first and second output counters, the count value is replaced with a preset arbitrary set value. The collation circuit compares the count values of the first and second output counters. When a mismatch is detected, each count value is collated with the corresponding arbitrary set value, and the count value and the arbitrary set value are obtained. If they match, the count operation is determined to be normal. As described above, fail-safety can be secured with a simple circuit without using a processing circuit such as a CPU.

According to the second aspect of the present invention, the phase difference between the input signal and the signal input via the detector is inputted to the first collation device and the second collation device each having the first and second output counters. Since a phase comparison circuit for detecting and sending to the first and second output counters is provided, the phase comparison circuit detects the phase difference between the signal and the signal input via the detector . Can be sent to the first and second output counters.

According to the third aspect of the present invention, the phase difference sent from the phase comparison circuit is input to the first collation device and the second collation device, and the first and second collation devices are converted into frequency signals corresponding to the phase difference . Since a conversion circuit for sending to the second output counter is further provided, the conversion circuit can convert the frequency signal corresponding to the phase difference and send it to the first and second output counters . the second output counter, it is possible to perform counting.

According to the fourth aspect of the present invention, the arbitrary set value is a value that cannot be generated in the normal counts by the first and second output counters . The counter values of the two output counters can be properly verified.

It is a schematic block diagram which shows embodiment of the double type | system | group collation apparatus which concerns on this invention. It is a flowchart which shows the operation | movement by the phase adjustment circuit, phase comparison circuit, and phase / frequency conversion table in embodiment of the double type | system | group collation apparatus which concerns on this invention. It is a flowchart which shows the operation | movement by the output counter in embodiment of the double type | system | group collation apparatus which concerns on this invention. It is a flowchart which shows the operation | movement by the collation circuit in embodiment of the double system collation apparatus which concerns on this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic configuration diagram showing an embodiment of a dual system verification device according to the present invention. In FIG. 1, the dual system verification device of this embodiment is a first system for converting the phase of a signal into a frequency. 1 collation device 1 and 2nd collation device 2 are comprised. Since the first verification device 1 and the second verification device 2 have the same configuration, the first verification device 1 will be described below.

  The first verification device 1 includes a phase adjustment circuit 3, a phase comparison circuit 4, a phase / frequency conversion table 5 as a conversion circuit, an output counter 6, a verification circuit 7, and an output generation circuit 8. ing.

  The phase adjustment circuit 3 is configured to receive a signal f1 (TX) sent from a transmission unit (not shown). The phase adjustment circuit 3 receives the signal f1 (TX) based on a predetermined shift setting value. It is configured to adjust the time lag of the phase.

  The phase comparison circuit 4 is configured to receive a signal f1 (RX) from which a signal f1 is sent from a transmission unit via a detector (not shown). The phase comparison circuit 4 is configured by a counter or the like. Has been. The phase comparison circuit 4 starts the phase difference count when the signal f1 (TX) is sent from the phase adjustment circuit 3, and this phase difference count is the rising timing of the operation clock of the first verification device 1. And is configured to count. Then, when f1 (RX) is input, the phase comparison circuit 4 stops counting the phase difference of the signal f1 (TX) and counts the phase difference between the signal f1 (TX) and the signal f1RX. It is configured. That is, the phase difference between the signal f1 (TX) and the signal f1 (RX) is counted by the number of pulses of the operation clock.

  In the phase / frequency conversion table 5, the frequency to be converted with respect to the phase difference is set in advance, and the phase comparison circuit 4 counts the phase difference between the signal f1 (TX) and the signal f1 (RX). In such a case, the phase / frequency conversion table 5 converts the count value of the phase difference into a frequency, replaces it with an output target value, and outputs it to the output counter 6. When the target value is output, the phase comparison circuit 4 is configured to reset the phase difference counter and wait until the next signal is input.

  The output counter 6 is configured to set a target value and start counting when an output target value is input. The output counter 6 is configured to replace the counter value of the counter with an arbitrarily set value when the count value reaches the target value, and at the same time, configured to send an instruction to replace the counter value with the arbitrarily set value to another system. ing. Here, the arbitrarily set value is a predetermined value, and is set to a different value between the first verification device 1 and the second verification device 2, and is a value that cannot be generated by a normal count.

  In addition, the output counter 6 of the second collation device 2 sets the first collation device 1 when the count value of the second collation device 2 reaches the target value before the count value of the first collation device 1. The output counter 6 of the first verification device 1 is configured to send an instruction to replace it with an arbitrary set value. When the output counter 6 of the first collating device 1 receives an instruction to replace the arbitrary set value, the count value reaches the target value. Even if not, it is configured to replace the count value with an arbitrarily set value. However, in this case, the output counter 6 replaces the count value with an arbitrarily set value when the count value is within the predetermined error range with the target value. If not, the count is stopped as abnormal.

  The collation circuit 7 is configured to always compare the count values of the first collation device 1 and the second collation device 2 and determine whether or not the difference exceeds a predetermined allowable value. Here, since the first verification device 1 and the second verification device 2 are not completely synchronized, the count values of the first verification device 1 and the second verification device 2 are completely identical. Since it is not limited, an allowable range of about several counts is set, and when it is within this allowable range, the first verification device 1 and the second verification device 2 are handled as being coincident.

  And the collation circuit 7 is comprised so that a count may be continued when the count value of the 1st collation apparatus 1 and the 2nd collation apparatus 2 corresponds. When the count values of the first verification device 1 and the second verification device 2 exceed the tolerance and do not match, the verification circuit 7 compares the count value with the arbitrarily set value, and the count value becomes the arbitrarily set value. If they match, an instruction to invert the output is sent to the output generation circuit 8. On the other hand, when the count value does not match the arbitrarily set value, it is determined that the count value is not normal, and the count operation is stopped. The collation between the count value and the arbitrarily set value also serves as confirmation of normal operation. When the count value matches the arbitrarily set value, the matching circuit 7 is configured to reset the count and wait until the output target value is input from the phase / frequency conversion table 5. .

  The output generation circuit 8 is configured to generate and output a target frequency pulse by inverting the output when an instruction to invert the output is sent from the collation circuit 7. When the count value does not match the arbitrarily set value and the count operation is stopped, the inversion instruction for the output is not sent from the collating circuit 7, so that the target frequency pulse is not output.

  In the present embodiment, the first verification device 1 and the second verification device 2 include a similar circuit to which the signal f2 is input in addition to the circuit to which the signal f1 is input. The phase can be converted into a frequency. In this case, in this embodiment, the output of the first collation device 1 and the second collation device 2 suffices with one system, and therefore the output generation circuit 8 is configured to be provided only in the first collation device 1. ing.

  Next, the operation of this embodiment will be described.

  First, operations by the phase adjustment circuit 3, the phase comparison circuit 4, and the phase / frequency conversion table 5 will be described with reference to the flowchart shown in FIG.

  When the signal f1 (TX) is input from the transmission unit to the phase adjustment circuit 3 (ST1), the phase adjustment circuit 3 causes the phase shift of the phase of the signal f1 (TX) based on a predetermined shift setting value. Is adjusted (ST2).

  When the signal f1 (TX) is sent from the phase adjustment circuit 3 to the phase comparison circuit 4, the phase difference count is started (ST3), and when f1 (RX) is input to the phase comparison circuit 4. (ST4: YES), the phase difference counting of the signal f1 (TX) is stopped (ST5), and the phase difference between the signal f1 (TX) and the signal f1 (RX) is counted (ST6).

  Thereafter, the phase / frequency conversion table 5 converts the count value of the phase difference between the signal f1 (TX) and the signal f1 (RX) into a frequency, replaces it with the output target value, and outputs it to the output counter 6 ( ST7). When the target value is output, the phase comparison circuit 4 resets the phase difference counter (ST8), and waits until the next signal is input.

  Next, the operation of the output counter 6 will be described with reference to the flowchart shown in FIG. The operation of the output counter 6 will be described mainly with respect to the operation of the first verification device 1.

  In the present embodiment, when a target value is input to the output counter 6, the target value is set (ST10) and counting is started (ST11). And when the instruction | indication which replaces with an arbitrary setting value is not sent from the 2nd collation apparatus 2 (ST12: NO), if a count value reaches target value (ST13: YES), the count value of a counter will be replaced with an arbitrary setting value. (ST14). Then, an instruction to replace the arbitrarily set value is sent to the second verification device 2 (ST15).

  On the other hand, when an instruction to replace with an arbitrary set value is sent from another verification device (ST12: YES), when the count value is within an error range (ST16: YES), the counter value of the counter is set to an arbitrary set value. (ST14), and if the count value and the target value do not coincide with each other beyond the error range (ST16: NO), the count is stopped as being abnormal (ST17).

  Next, the operation of the verification circuit 7 will be described with reference to the flowchart shown in FIG.

  In this embodiment, the collation circuit 7 always collates the count values of the first collation device 1 and the second collation device 2 (ST20), and determines whether or not the difference exceeds a predetermined allowable value. . And when it is judged that the count value of the 1st collation apparatus 1 and the 2nd collation apparatus 2 has not exceeded the allowable value and is in agreement (ST21: YES), the count is continued and the first collation apparatus 1 When the count value of the second verification device 2 exceeds the tolerance and does not match (ST21: NO), the count value is checked against the arbitrarily set value (ST22), and the count value matches the arbitrarily set value (ST23: YES), an instruction to invert the output is sent to the output generation circuit 8 (ST24). If the count value matches the arbitrarily set value, the output count is reset (ST25), and the process waits until the output target value is input from the phase / frequency conversion table 5.

  On the other hand, if the count value does not match the arbitrarily set value (ST23: NO), it is determined that the count value is not normal, and the count operation is stopped (ST26).

  As described above, in this embodiment, the output counter 6 counts up to a predetermined target value, and when this count value reaches the target value, the count value is replaced with an arbitrarily set value, and the collating circuit 7 The count values of the first verification device 1 and the second verification device 2 are compared, and when the difference exceeds a preset allowable value and a mismatch is detected, the result is compared with the arbitrarily set value and the two match. In this case, since it is determined that the operation is normal, an independent verification circuit 7 is not required without using a processing circuit such as a CPU, and fail-safety can be ensured with a simple circuit.

  Also, when the count value reaches the target value by one output counter 6, the counter value is replaced with an arbitrarily set value, and an instruction to replace the other set value with an arbitrarily set value is sent to the other output counter 6. The other output counter 6 can process the count value when it reaches the target value, and can synchronize the output counter 6 of the first verification device 1 and the second verification device 2.

  Furthermore, since the arbitrary set value is set to a value that cannot be generated by a normal count, the counter value of the output counter 6 of the first verification device 1 and the second verification device 2 is verified by using the arbitrary set value. It can be done properly.

  In addition, this invention is not limited to the said embodiment, A various deformation | transformation is possible based on the meaning of this invention.

DESCRIPTION OF SYMBOLS 1 1st collation apparatus 2 2nd collation apparatus 3 Phase adjustment circuit 4 Phase comparison circuit 5 Phase / frequency conversion table 6 Output counter 7 Collation circuit 8 Output generation circuit

Claims (5)

First and second output counters that replace the count value with a preset arbitrary set value when the count value counted based on a predetermined input signal reaches a target value;
The count values of the first and second output counters are compared, and if a mismatch is detected, each count value is collated with the corresponding arbitrary set value, and the count value and the arbitrary set value are counted. A verification circuit that determines that the operation is normal;
A double system verification apparatus comprising: A first collation device and a second collation device each comprising the first and second output counters;
The first and second output counters perform counting based on the input signal and a signal to which the input signal is input via a detector,
The first verification device and the second verification device each include a phase comparison circuit that detects a phase difference between the input signal and a signal input through the detector and sends the phase difference to the first and second output counters. The dual system verification device according to claim 1, wherein each of the dual system verification devices is provided.   The first collation device and the second collation device receive the phase difference sent from the phase comparison circuit, convert it into a frequency signal corresponding to this phase difference, and send it to the first and second output counters. The dual system verification apparatus according to claim 2, further comprising a conversion circuit.   4. The double according to claim 1, wherein the arbitrary set value is a value that cannot be generated in a normal count by the first and second output counters. 5. System verification device.   5. The verification circuit according to claim 1, wherein when the difference between the count values of the first and second output counters exceeds a preset allowable value, the verification circuit performs verification with the arbitrary set value. The double system verification device according to any one of the above.

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