JP6168595B2 - Data compressor and data decompressor - Google Patents

Description

  The present invention relates to a data compressor and a data decompressor.

In an environment where a data stream flows over a network in recent years, in order to perform real-time processing on the stream data forming the data stream, it is required to shorten the data transmission time between various entities that transmit and receive the stream data. The entity is, for example, various communication devices (terminal device, relay device) connected to the network. Data streams flow between electronic circuit chips that perform processing on various stream data such as processors, LSIs (Large Scale Integrated Circuits), and FPGAs (Field Programmable Gate Arrays) mounted in communication devices. An electronic circuit chip is also an entity, and communication between entities includes not only communication between communication devices but also communication between electronic circuit chips inside the communication device (so-called internal communication).

  In recent years, the amount of stream data tends to increase. As a method for efficiently transmitting a certain amount of stream data from the transmission side to the reception side, increasing the frequency of the transmission path connecting the entities (widening the transmission band), connecting the entities with a plurality of transmission paths, It is conceivable to transmit stream data in parallel. However, these methods are considered to have physical and frequency limitations.

  Therefore, it is considered to improve the efficiency of data transmission by shortening the data transmission time associated with a decrease in the amount of transmission data by compressing the stream data at the transmission side entity. For example, in a communication device, transmission data is connected to a compression device (including a plurality of compression algorithms such as LZW and RLE), and each data size of the original transmission data and data processed by each of the plurality of compression algorithms There is a technique for sending the smallest data from a communication device (for example, Patent Document 1).

JP 2007-65828 A Japanese Patent No. 3748003

J. Ziv and A. Lempel, "A universal algorithm for sequential data compression." IEEE Transactions on Information Theory, Vol. IT-23, No.3, May 1977, p.337-343 T. Welch, "A technique for high-performance data compression." IEEE Computer. 1984, p. 8-19

  However, for example, the technique (prior art) in Patent Document 1 described above presupposes application of an existing lossless compression algorithm by software processing. For this reason, there were the following problems.

In the existing compression algorithm, for example, when a compression process is performed on a data symbol (abcd ...) string (hereinafter simply referred to as “symbol”), a lookup table for the symbol “a” is first used. Is searched. If “a” is hit, then the lookup table is searched for “ab”. When “ab” does not hit, the data string “a” is converted into predetermined compressed data (for example, “x”), while a conversion entry for “ab” (for example, “ab” → “y” ") Is newly registered in the lookup table.

  In the above method, the lookup table search is repeated until the search target does not hit. Accordingly, the processing steps for one compression process are variable according to the number of lookup table searches. In the stream data, the number of processing steps depends on the tendency of the data string (the appearance frequency of a certain convertible symbol string). For this reason, the time required for one compression process is not constant. This is the first problem.

  In the above method, the number of compressible symbol sequences is increased by updating the lookup table. On the other hand, if the table entry for decompression processing (“y” → “ab”) is not sent to the decompression side, It cannot be thawed. At this time, if the total size of the compressed data and the decompression data is equal to or exceeds the size of the original data, it does not contribute to a reduction in the amount of data on the transmission path. This is the second problem.

  Furthermore, in the above method, the number of symbols forming the symbol sequence to be compressed is not constant in the lookup table, and any length (number) of symbol sequences can be registered. This is the third problem.

  The compression processing is inserted as one of a plurality of steps (steps) executed before the transmitting entity transmits stream data at the receiving entity. At this time, it should be avoided that the compression process becomes a bottleneck. In addition, the occurrence of fluctuation (jitter) in the compression process should be avoided in view of the influence on the process located in the subsequent stage. From these viewpoints, the conventional technique including the first problem and the third problem in which the number of processing steps (processing delay) is not constant cannot be adopted, and the conventional technique is also adopted in view of the second problem. I can't.

  Furthermore, it is considered that the compression processing is preferably performed by hardware processing rather than software processing from the viewpoint of processing speed. At this time, when trying to form a digital circuit that performs compression processing (algorithm) performed in the prior art, since the processing is complicated, various delays for timing adjustment are required to be inserted into the circuit. As a result, the circuit However, there is a risk that the circuit scale increases.

  In order to decompress the compressed data, a process opposite to the compression process is performed on the reception side as the decompression process. For this reason, the above-described problem relating to the compression process is directly raised as a problem relating to the decompression process.

  The present invention has been made in view of the above circumstances, and provides a technique that enables efficient data transmission between transmission and reception using compression and decompression processing with a fixed processing delay. With the goal.

  In the data compressor according to one aspect of the present invention, when two or more consecutive symbols included in an input data sequence including a plurality of fixed-length symbols are registered, the two or more symbols are converted into one symbol. A conversion unit for conversion, and an output unit for outputting one or more symbols when two or more symbols are converted into one symbol by the conversion unit, and an output unit for outputting two or more symbols otherwise.

  In addition, the data decompressor according to another aspect of the present invention, when a fixed-length symbol included in an input data string is registered as a symbol converted from two or more symbols in the compression processing, the symbol is 2 A conversion unit that converts the above symbols, and an output that outputs two or more symbols when the conversion unit converts the symbols into two or more symbols, and outputs a symbol included in the input data string otherwise. Part.

  According to the present invention, it is possible to provide a technology that enables efficient data transmission between transmission and reception using compression and decompression processing with a fixed processing delay.

It is a figure which shows the structure of a compression / decompression machine. It is a functional block diagram which shows an example of a data compressor. It is a figure which shows an example of the entry registered into a lookup table. It is a circuit block diagram which shows an example of a data compressor. It is a circuit block diagram which shows an example of a data decompressor. It is a figure for demonstrating the specific example of a compression process and a decompression | decompression process. 6 is a functional block diagram illustrating an example of a data compressor according to Embodiment 2. FIG. FIG. 6 is a circuit configuration diagram illustrating an example of a data compressor according to a second embodiment. FIG. 6 is a circuit configuration diagram illustrating an example of a data decompressor according to a second embodiment. FIG. 9 is a diagram for explaining processing of a data compression apparatus according to a third embodiment. FIG. 10 is a functional block diagram illustrating an example of a data compressor according to a third embodiment. It is a figure for demonstrating the process of the data decompression | decompression apparatus which concerns on Embodiment 3. FIG. FIG. 6 is a circuit configuration diagram illustrating an example of a data decompressor according to a third embodiment. It is a functional block diagram which shows an example of the data compressor which concerns on Embodiment 4. FIG. 10 is a circuit configuration diagram illustrating an example of a delimiter position determination unit according to a fourth embodiment. It is a figure for demonstrating the input / output of an encoder. It is a figure explaining the process which determines a delimiter position. FIG. 6 is a circuit configuration diagram illustrating an example of a compression unit according to a fourth embodiment. It is a figure for demonstrating an example of the format of the data transmitted / received between a data compressor and a data decompressor.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiment is an example of the present invention, and the configuration of the present invention is not limited to the following example.

Embodiment 1
FIG. 1 is a diagram schematically showing a data compression / decompression system. In FIG. 1, the data compression / decompression system includes a data compressor 10 and a data decompressor 20.

  The data compressor 10 performs a compression process on data (for example, stream data) to be transmitted from a transmitting entity (not shown) to a receiving entity (not shown), and outputs the compressed data. The compressed data reaches the data decompressor 20 through the transmission path 3. The data decompressor 20 restores the compressed data to the original data by decompression processing. The original data is then supplied to the receiving entity. When the compression process is not performed, the amount of data sent to the transmission path 3 is reduced by the compression process, so that the time until the data having a certain size is received from the transmission side entity to the reception side entity is reduced. It can be shortened in comparison.

The data compression / decompression system may be applied to communication between communication devices, or may be applied to communication (so-called internal communication) between components (electronic circuit chips) in the communication device. For communication between communication devices, the data compressor 10 can be mounted on a transmission-side communication device, and the data decompressor 20 can be mounted on a reception-side communication device. For internal communication, the data compressor 10 and the data decompressor 20 can be mounted as one of components in a communication device or various information processing apparatuses (computers).

  When the communication device performs two-way communication, the data compressor 10 and the data decompressor 20 are installed in each of the communication device on the transmission side and the reception side, and data compression is performed in each of the upstream communication and the downstream communication. A configuration in which decompression / decompression is performed is applicable.

<Data compressor>
FIG. 2 is a block diagram showing an example of the data compressor 10 shown in FIG. For example, the data compressor 10 performs a lossless compression process (also referred to as an encoding process) on stream data input from a transmission side entity (transmission side apparatus), and outputs the stream data subjected to the lossless compression process. The data compressor 10 performs static encoding using so-called grammar compression as a lossless compression technique. Specifically, the data compressor 10 has a lookup table that defines a conversion rule for a predetermined symbol sequence included in the stream data, and the predetermined data symbol sequence is sized from the symbol sequence in accordance with the lookup table. Is compressed (encoded) into one symbol (also referred to as a compressed symbol).

<< Lookup Table >>
FIG. 3 shows an example of a lookup table provided in the data compressor 10. In the lookup table, correspondence between two symbols (referred to as symbol pairs) of “input (before compression)” and one symbol of “output (after compression)” converted by compression (encoding) processing is registered. Multiple entries. The number of entries is a finite value corresponding to the storage capacity of the memory 101 that stores the lookup table.

  In FIG. 3, one English character means one data symbol. The size of one symbol is a fixed size (fixed length). For example, the size of one symbol is 1 byte (8 bits). However, the symbol size is not limited to 1 byte, and a predetermined size can be adopted.

  In the lookup table shown in FIG. 3, the symbol after compression is represented by an alphabetic character for the sake of convenience, but in Embodiment 1, a value that cannot exist in the symbol before compression is used as the value of the symbol after compression. Is registered. In other words, the symbol after compression is a value that does not belong to a set of values that the symbol before compression can take. As a result, the data decompressor 20 can perform a decompression process that distinguishes between compressed symbols and uncompressed symbols.

  For example, when the stream data is text data in which predetermined character codes are arranged in series, a pair of two characters is registered as a symbol before compression, and an unused bit string in the character code as a symbol after compression Is registered. For example, when the stream data is gene data (nucleic acid coding sequences of “A”, “G”, “T”, and “C”), “A” is used as two symbols before compression of the lookup table. , “G”, “T” and “C” are registered permutations, and values other than “A”, “G”, “T” and “C” are registered as one symbol after compression Is done.

The data compressor 10 and the data decompressor 20 according to the embodiment are provided with a lookup table that stores a statically created entry group (symbol pair list) having the same contents. “Statically” means that the registered content of the lookup table is not dynamically changed (updated) according to the search result. However, the registered contents of the lookup table can be changed by, for example, maintenance work at any time or periodic update work. Also, symbol pairs are registered in order of appearance rate in stream data (in order of so-called likelihood).

<< Configuration of data compressor >>
Returning to FIG. 2, the data compressor 10 is based on the configuration of the above-described lookup table (hereinafter sometimes simply referred to as “table”), and is used to specify a symbol pair to be searched in the table. Depending on the configuration, the configuration for converting the symbol pair to one corresponding symbol (referred to as “compressed symbol”) when the symbol pair is registered in the table, and whether or not the symbol pair in the table is hit And a configuration for outputting one of the original symbol pair and the compressed symbol.

  Specifically, the data compressor 10 includes a latch 110 that holds input data such as stream data, a memory 101 (including a read / write circuit) corresponding to a conversion unit that stores a lookup table, and symbols in the order of input. A serializer (multiplexer: MUX) 102 for outputting, a selector (multiplexer) 103 corresponding to an output unit for outputting a compressed symbol or an original symbol pair, and a latch 120 for holding output data, which are signal lines Connected with.

  The latch 110 has a buffer function for temporarily holding the input stream data. The stream data is a finite-length bit string, and is handled by the data compressor 10 in units of symbols of a fixed size (1 byte). The latch 110 outputs two adjacent symbols (symbol 1 and symbol 2) forming a symbol pair in parallel at a predetermined timing in order from the head of the stream data. The symbol pair is input to the memory 101 and the serializer 102.

  In the memory 101, the input symbol pair is retrieved from the table. The search is executed by matching the symbol pair of “input (before compression)” registered in each entry of the table (FIG. 3) with the input symbol pair. If an entry that matches (matches) the input symbol pair is found (hit), the search is a hit with the “output (compressed)” symbol (compressed symbol) registered in the entry. A match signal indicating that this has occurred is output. The compressed symbol is input to the selector 12, and the match signal is input to the selector 103 as a control signal for the selector 103.

  For example, an associative memory (CAM (Content Addressable Memory)) can be applied as the memory 101. The CAM is a computer memory for high-speed search that can output an address corresponding to an input data word (data word). When CAM is applied, a symbol pair as a data word is input to the CAM, and when an entry hits, the CAM outputs a compressed symbol as an address corresponding to the data word and is true. The True signal is used as the above-mentioned match signal, whereas if the entry does not hit, the output of the address (compressed symbol) from the CAM is not performed. A false signal (“0” signal) is output.

The serializer (multiplexer) 102 can output the input symbol pairs to the selector 103 in a predetermined order (symbol 1, symbol 2). The selector 103 outputs a compressed symbol out of the original symbol pair and the compressed symbol when a match signal is input (true input). On the other hand, when no match signal is input (False input), the original symbol pair output from the serializer 102 is output. The output of the selector 103 is temporarily held in the latch 120. By repeating such processing in order from the beginning of the stream data, the latch 120 accumulates compressed data obtained by compressing the original stream data. The compressed data is latched 12 at an appropriate timing.
The data is output from 0 and sent to the data decompressor 20 via the transmission path 3.

  The memory 101 may be a combination of CAM and RAM (Random Access Memory). In this case, the compressed symbol is stored at the RAM address output by the CAM, and the compressed symbol at the address is supplied to the selector 12. The RAM may be a DRAM or an SRAM, but it is preferable to select one that can operate at high speed in consideration of the linkage with the CAM.

  In the data compressor 10 shown in FIG. 2, the operation in the memory 101 is a sequential process of “table search → hit determination → compressed symbol output → True / False signal output”. The table search is a one-time matching between the symbol pair and the symbol pair stored in each entry, and the search process is performed again after changing the search target (input symbol string) as in the prior art. I will not. In other words, when an entry hits in the first search, the next symbol is not obtained from the latch 110 and the search is not performed again. Therefore, the time required for the table search (processing delay) is within the time required for matching the symbol pair and the symbol pair of all entries at the longest.

  The processing delay for hit determination, compressed symbol output, and True / False signal output is almost fixed. Therefore, the processing delay in the memory 101 (CAM) is fixed. Therefore, the output timing of the compressed symbol and True / False signal from the memory 101 can be fixed. Further, the processing start timing in the serializer 102 and the selector 103 depends on the output timing of the compressed symbol and True / False signal from the memory 101.

  By fixing the output timing of the compressed symbol and the True / False signal, the processing start timing of the serializer 102 and the selector 103 can also be fixed. The processing delay of the serializer 102 and the selector 103 is almost constant. Therefore, the required time (processing delay) from when a symbol pair is output from the latch 110 to when the compressed symbol or the original symbol pair is input to the latch 120 can be fixed.

  This facilitates timing adjustment when the data compressor 10 shown in FIG. 2 is realized (implemented) by hardware (digital circuit), and simplification of the digital circuit can be achieved.

  FIG. 4 shows an example of the case where the digital compressor of the data compressor 10 shown in FIG. 2 is used. The data compressor 10 includes a CAM 101 that stores a look-up table, D-FFs (D-type flip-flops) 111 to D-FF 113 that hold stream data in symbol units and transmit according to a clock signal, a selector 103, and a selector 103 And a D-FF 121 for holding the symbol output to 103. A common clock signal is supplied to each of these components, and an operation synchronized with the timing according to the clock signal is performed.

  Stream data is input to the D-FF 111 in symbol units. Each time the next symbol is input to the D-FF 111, the previously input symbol proceeds to the D-FF 112 or D-FF 113 in the next stage.

  On the other hand, an enable (validation) signal or a disable (invalidation) signal is alternately and regularly input to the CAM 101. For example, the enable signal is input to the CAM 101 at the timing when the first symbol is output from the D-FF 112 and the second symbol is output from the D-FF 111. Based on the enable signal, the CAM 101 searches the look-up table using the first and second symbol pairs (ie, tries to compress).

Next, the disable signal is input to the CAM 101 at the timing when the second symbol is output from the D-FF 112 and the third symbol is output from the D-FF 111. CAM 101 does not attempt compression for the second and third symbol pairs. Further, at the timing when the third symbol is output from the D-FF 112 and the fourth symbol is output from the D-FF 111, an enable signal is input to the CAM 101, and compression is performed using the third and fourth symbol pairs. Try. In the first embodiment, two symbols are paired in order from the beginning of the stream data, and compression is attempted.

  In the selector 103, while the first symbol is held in the D-FF 113, a compressed symbol is input (when hit) and a match signal is input. When a match signal is input, a compressed symbol for the D-FF 121 is input from the selector 103 to the D-FF 121. On the other hand, when no match signal is input, the selector 103 inputs the first symbol and the second symbol to the D-FF 121 at a predetermined timing.

  Thereafter, the operations described for the first and second symbols are repeated for the third and fourth, fifth and sixth symbol pairs. In this manner, a simple circuit configuration in which compression processing (conversion to compressed symbols) by CAM is performed while each symbol progresses on a plurality of D-FFs connected in series can be employed.

  In addition, although the parallel path | route and serializer 102 which transmit the adjacent symbol (symbol pair) shown in FIG. 2 were illustrated, the multistage circuit of D-FF which transmits a symbol pair serially as shown in FIG. By adopting, the same (equivalent) configuration as when the parallel path and the serializer 102 are provided can be adopted.

  According to the data compressor 10 as described above, the amount of data flowing through the transmission line 3 can be reduced by the amount corresponding to the replacement of the symbol pair with one compressed symbol. Further, by making the symbol (that is, the data size of the processing unit) a fixed length, etc., the compression processing in the data compressor 10 is simplified, and the processing delay is fixed, so that significant delay and fluctuation are caused. It can be avoided. In this way, efficient data transmission can be performed. Furthermore, for example, hardware for performing pipeline processing as shown in FIG. 4 can be easily formed.

<Data decompressor>
Next, the data decompressor 20 shown in FIG. 1 will be described. FIG. 5 is a block diagram illustrating an example of the data decompressor 20. The data decompressor 20 includes a memory 201 (including a read / write circuit) that stores a compressed symbol and an uncompressed (original) symbol pair in association with each other, and a separator (decoder) that separates the uncompressed symbol pair into two symbols. (Multiplexer: DMUX) 202, serializer 203 that outputs two symbols in the order of the original stream data, 1-bit counter 204 that outputs a signal for controlling the serializer 203, and a symbol or decoding input to the data decompressor 20 And a selector 205 that selectively outputs the symbol pairs thus selected, and these are connected by signal lines. The data decompressor 20 performs a synchronized operation according to a predetermined clock.

  First, stream data (symbol string) input from the transmission path 3 to the data decompressor 20 is temporarily held by the latch 200 and output for each symbol at a predetermined timing. The output symbol is input to the memory 201 and the selector 205 of the data decompressor 20.

The memory 201 is a storage device such as a RAM. A combination of symbols corresponding to the memory 101 of the data compressor 10 is registered in the memory 201. That is, the memory 201 stores a lookup table as shown in FIG. However, the memory 20
In the lookup table stored in 1, an entry in which the input value and the output value of the lookup table stored in the memory 101 are exchanged is registered. For example, an address output from the CAM of the data compressor 10 is registered in the input value of the lookup table stored in the memory 201.

  In addition, when an entry including a symbol input in the input field of the table is registered in the memory 201 (that is, when the input symbol is a compressed symbol), the original ( Replace with the symbol pair before compression and output to the separator 202.

  The separator 202 divides the symbol pair into two symbols and supplies it to the serializer 203. The serializer 203 outputs two symbols (symbol 1 and symbol 2) forming a symbol pair to the selector 205 in the original arrangement order. The data decompressor 20 has a 1-bit counter 204 that outputs “1” or “0” at a predetermined timing. For example, when the 1-bit counter 204 outputs “1”, the symbol 1 is output from the serializer 203. On the other hand, the symbol 2 is output from the serializer 203 when the 1-bit counter 204 outputs “0”. The correspondence between the counter value and the symbol may be reversed. The path between the memories 201 and 205 can be replaced with a D-FF series circuit as shown in FIG.

The selector 205 outputs one of the symbol pair input from the memory 201 or the symbol output from the latch. In the example illustrated in FIG. 5, the data decompressor 20 includes a detection circuit 205 </ b> A that detects data output from the memory 201 to the separator 202. The detection circuit 205A monitors a signal line of data read from the memory 201, and controls the selector 205 to output a symbol pair from the serializer 203 when data read is detected at a predetermined monitoring timing. A signal (corresponding to a True signal) is supplied to the selector 205. On the other hand, when no data output is detected at a predetermined monitoring timing, the selector 205 gives a control signal (corresponding to a False signal) for outputting a symbol from the latch 200 to the selector 205.

  With the above configuration, the data decompressor 20 can convert (restore) a compressed symbol into an original symbol pair using a lookup table. The processing delay of the decompression process can be fixed.

<Operation of data compression / decompression system>
The entire compression process and decompression process will be described with reference to FIG. In FIG. 6, the data compression / decompression system includes a transmission side device 1 as a transmission side entity, a data compressor 10, a reception side device 2 as a reception side entity, and a data decompression unit 20. Each of the transmission-side device 1 and the reception-side device 2 is, for example, a communication device (terminal device, relay device) having a communication function, and the data compression / decompression system performs communication between communication devices (“inter-device communication”). The data to be transferred is compressed and decompressed.

  The transmission side device 1 and the reception side device 2 are electronic circuit chips such as a processor, LSI, ASIC, and programmable logic device (PLD (eg, FPGA)) mounted on a communication device, for example, and data compression / decompression. The system compresses and decompresses data transmitted by communication between chips (so-called internal communication). The transmission path 3 is a communication line that connects devices in a wired or wireless manner in the case of communication between devices, and a signal line that connects chips in internal communication.

In the memory 101, a lookup table as shown in FIG.
1 is a table in which the input / output values are reversed. First, stream data to be transmitted is output from the transmission-side apparatus 1 to the data compressor 10. Here, it is assumed that the stream data includes a symbol string such as “abdaabaa” (the right side is the top).

  The data compressor 10 replaces the uncompressed symbol pair registered in the memory 101 with a compressed symbol, and outputs it to the transmission path 3. The symbol string in the stream data is converted into compressed data “TdaTS” based on a lookup table. On the other hand, the data decompressor 20 converts the compressed symbols in the stream data arriving via the transmission path 3 into symbol pairs before compression. In the example of FIG. 6, the memory 201 stores a table as shown in the figure, and the decompression process in the data decompressor 20 converts the compressed data “TdaTS” in the stream to the original “abdaabaa” (restoration). Is done.

[Embodiment 2]
Hereinafter, Embodiment 2 of the present invention will be described. Since the second embodiment includes a configuration that is common to the first embodiment, the common configuration is denoted by the same reference numeral, description thereof is omitted, and differences are mainly described.

  In the first embodiment, as a symbol after conversion, a value that does not belong to a set of values that can be taken by the symbol before conversion is registered in the lookup table. However, if the symbol before conversion can take any bit string as in the case where the stream data is binary data, it cannot be guaranteed that the value of the symbol converted as a compressed symbol is not included in the stream data. That is, the symbol value included in the stream data may be the same as the compressed symbol value.

  In the second embodiment, a flag (identifier) indicating whether a symbol is a compressed symbol is set for each symbol. The data compressor outputs a symbol and a flag corresponding to the symbol, and the data decompressor replaces the corresponding symbol with the symbol before conversion when the flag indicates that the corresponding symbol is a compressed symbol. The flag is, for example, 1-bit data (also referred to as an “additional bit” in the meaning of an identifier bit added to a symbol). For example, a bit value “1” indicates a compression symbol, and a bit value “0” indicates an uncompressed symbol.

  Note that each of the symbols and the flags is naturally associated with processing from the top by maintaining the order in the stream data. In this way, it is possible to perform the decompression process by distinguishing the symbols compressed and uncompressed in the data decompressor.

  FIG. 7 is a block diagram illustrating an example of the data compressor (data compressor 10a) according to the second embodiment. The difference from the data compressor 10 shown in FIG. 2 is that the match signal output from the memory 101a is treated as a flag. That is, the memory 101a outputs a flag “1” when the symbol pair hits in the table, and outputs a flag “0” when it does not hit. A signal indicating the flag “1” is used for operation control of the selector 103 as a match signal in the first embodiment.

FIG. 8 shows an example of a digital circuit configuration for realizing the function of the data compressor 10a. 4 differs from the data compressor 10 shown in FIG. 4 in that it includes a D-FF 122 that latches the True / False signal output from the CAM 101a, and the output value from the D-FF 122 is output as a flag (additional bit). The

FIG. 9 is a block diagram illustrating an example of a data decompressor (data decompressor 20a) according to the second embodiment. The difference from the data decompressor 20 shown in FIG. 5 is that a flag (additional bit) received from the data compressor 10 a side is used as a control signal for the selector 205. Each additional bit (flag) generated by the data compressor 20a is transmitted to the data decompressor 20a as a bit string having the number of bits corresponding to the number of symbols. In the data decompressor 20 a, a corresponding flag (additional bit) is input to the selector 205 in accordance with the symbol output from the latch 200. As a result, when the flag value is “1”, the restored symbol pair output from the memory 201 can be output from the selector 205. Conversely, when the flag value is “0”, the symbol output from the latch 200 can be output from the selector 205.

  As described above, in the second embodiment, the data compressor 10a generates a bit (flag) indicating compression / non-compression for each symbol and transmits it to the data decompressor 20a. Thereby, the data decompressor 20a can execute the decompression process according to the flag value. Therefore, for example, even when binary data is compressed, the data decompressor 20a can execute a decompression process that distinguishes between compressed symbols and uncompressed symbols. The compression / decompression process according to the second embodiment is more general than the first embodiment in that the attribute of the data to be compressed is not questioned.

[Embodiment 3]
Hereinafter, Embodiment 3 of the present invention will be described. Since the third embodiment includes a configuration that is common to the first and second embodiments, the common configuration is denoted by the same reference numeral, description thereof is omitted, and differences are mainly described.

  In the third embodiment, an example in which the compression rate is increased by connecting the data compressor 10a and the data decompressor 20a described in the second embodiment in a plurality of stages in series is shown. FIG. 10 shows an example of an apparatus (also referred to as a data compression apparatus) in which the data compressor 10b is connected in multiple stages. The data compression apparatus shown in FIG. 10 is formed from four data compressors 10b connected in series. However, the number of data compressors forming the data compression apparatus can be selected as appropriate.

  The plurality of data compressors 10b1 to 10b4 included in the data compression apparatus are referred to as a first stage, a second stage,. The first-stage data compressor 10b1 includes a data string (compressed data (1)) including compressed symbols obtained as a result of compression processing, and flags (additional bits) corresponding to the symbols forming the compressed data (1). ) Are output in a sequence that matches the symbol sequence (referred to as a first flag sequence).

  In the second-stage data compressor 10b2, the compressed data (compressed data (2)) obtained by the compression processing on the compressed data (1) from the data compressor 10b1 and a flag group corresponding to the compressed data (2). The formed bit string (referred to as a second flag string) and the first flag string are output.

  In the third-stage data compressor 10b3, the compressed data (compressed data (3)) obtained by the compression process on the compressed data (2) from the data compressor 10b2 and a flag group corresponding to the compressed data (3) are used. The formed bit string (referred to as the third flag string), the first flag string, and the second flag string are output.

  In the data compressor 10b4 at the fourth stage (the last stage in the example of FIG. 10), the compressed data (compressed data (4)) obtained by the compression processing on the compressed data (3) from the data compressor 10b3, and the compressed data A bit string (referred to as a fourth flag string) formed by a flag group corresponding to (4) and the first to third flag strings are output. These compressed data (4) and the first to fourth flag strings are transmitted to the data decompressor side via the transmission path.

  FIG. 11 is an explanatory diagram of a configuration example of the data compressors 10b2 to 10b4 illustrated in FIG. Since the data compressor 10b1 has the same configuration as the data compressor 10a (FIG. 7) described in the second embodiment, the description thereof is omitted. The configuration illustrated in FIG. 11 is a configuration included in the data compressor 10b4 in the final stage (fourth stage).

  In FIG. 11, the data compressor 10b4 includes three signal lines 131 to 133 that connect the input port and the output port of the data compressor 10b4 in addition to the configuration of the data compressor 10a. The signal line 131 is used for transmission of the first flag string, the signal line 132 is used for transmission of the second flag string, and the signal line 133 is used for transmission of the third flag string. . A fourth flag string is output to the signal line 134.

  The third-stage data compressor 10b3 has a configuration obtained by modifying the configuration of FIG. 11 as follows. That is, the signal line 133 illustrated in FIG. 11 is omitted. The signal line 134 illustrated in FIG. 11 functions as the signal line 133. Further, in the second stage data compressor 10b2, the signal lines 133 and 132 shown in FIG. 11 are omitted. Then, the signal line 134 is treated as the signal line 132. Regarding the data compressor 10 b 1, the signal line for outputting the additional bits shown in FIG. 7 corresponds to the signal line 131.

  FIG. 12 shows an example of a data decompression apparatus in which a plurality of data decompressors 20b are connected. The data decompression apparatus shown in FIG. 12 corresponds to the data compression apparatus shown in FIG. 10, and is formed of a four-stage data decompressor 20b. The first, second,..., N (n = 4, n is a natural number) stage in order of increasing distance from the transmission path 3.

  The fourth-stage data decompressor 20b4 receives the compressed data (4) and the first to fourth flag strings via the transmission path 3. Also in the example of FIG. 12, symbol paths are indicated by thick arrows, and additional bits (flag strings) are indicated by thin arrows. The data decompressor 20b4 executes decompression processing of the compressed data (4) based on the fourth flag string, and outputs the compressed data (3) and the first to third flag strings. The data decompressor 20b3 executes decompression processing of the compressed data (3) based on the third flag string, and outputs the compressed data (2) and the first and second flag strings. The data decompressor 20b2 executes decompression processing of the compressed data (2) based on the second flag string, and outputs the compressed data (1) and the first flag string. Finally, the data decompressor 20b1 executes decompression processing of the compressed data (2) based on the first flag string. As a result, the original stream data is output from the data decompressor 20b1 (data decompression device).

  FIG. 13 is a block diagram illustrating a configuration example of the data decompressor 20b (20b2 to 20b4) according to the third embodiment. The configuration of the data decompressor 20b shown in FIG. 13 shows the configuration of the data decompressor 20b4 located in the first stage of the data decompressing apparatus shown in FIG. The data decompressor 20b4 adds the first to third flag sequences output from the data compressor 10b1 to the data compressor 10b3 to the data decompressor 20b1 to the data decompressor 20b3 in addition to the configuration of the data decompressor 20b (FIG. 9). It has signal lines 211 to 213 for transmission. The compressed data (4) is input to the latch 200, and the fourth flag string is input to the signal line 214.

  The data decompressor 20b3 has a configuration in which the signal line 213 is omitted from the configuration illustrated in FIG. The data decompressor 20b2 has a configuration in which the signal lines 213 and 212 are omitted from the configuration illustrated in FIG. The data decompressor 20b1 has the same configuration as in FIG. 9, and the first flag string is input as an additional bit. As described above, since the compressed symbol compressed by the data compressor at a certain stage is decompressed by the data decompressor at the corresponding stage, it is possible to decode the original data while reducing the amount of data transmitted to the transmission line. it can.

  In addition, since the output of the data compressor at the previous stage is further compressed by the data compressor at the subsequent stage, the transfer data output to the transmission line 3 through the data compressor at the plurality of stages uses a single-stage data compressor. The compression rate is higher than the case. For example, in the case of the second embodiment, even if all the symbol pairs are replaced with compressed symbols, the data increases by the number of additional bits (flags), so the compression rate cannot be 50% or less. When a multi-stage data compressor is used, the compression rate can be improved every time one stage is increased in terms of data size. Further, since pipeline processing can be performed over a plurality of stages of data compressors or data decompressors, it is advantageous in terms of processing speed.

  In the third embodiment, the data compressor 10a and the data decompressor 20a of the second embodiment are connected in a plurality of stages, respectively, but the data compressor 10 and the data decompressor 20 shown in the first embodiment are connected in a plurality of stages. You may do it.

[Embodiment 4]
Embodiment 4 of the present invention will be described below. Since the fourth embodiment includes a configuration that is common to the first to third embodiments, the common configuration is denoted by the same reference numeral, description thereof is omitted, and differences are mainly described.

  In the first to third embodiments, it is determined whether or not to compress a pair of two symbols in order from the top of the stream data. Here, when the data stream is viewed in a unit of a certain length longer than two symbols, even if a symbol string having the same certain length appears at a different position in the data stream, the symbol pair is separated. If the eyes are shifted back and forth, they are processed as a sequence of different symbol pairs.

  Here, for example, there is a limit to the number of entries that can be registered in the lookup table stored in the CAM. However, if the same symbol string can be divided into the same symbol pairs based on some rule, the number of entries can be reduced. The same symbol string of a certain length can be compressed. That is, an improvement in the compression rate can be expected as a whole. In the fourth embodiment, using a data compressor including a circuit for determining a delimiter position between symbols, two symbols from the beginning of each determined delimiter position are combined into a symbol pair.

  FIG. 14 shows a block diagram of a data compressor 10c according to the present embodiment. The data compressor 10c in FIG. 14 includes a latch 105 that temporarily stores stream data as input data, a memory 101a, a serializer 102, a selector 103, and a delimiter position determination circuit 104, which are signals. Connected with wires. The data compressor 10c is configured by adding a delimiter position determination circuit 104 to the data compressor 10b shown in FIG. Here, it demonstrates centering on the difference with the data compressor 10b shown in FIG.

  The delimiter position determination circuit 104 receives an input of a symbol string and determines a delimiter position between symbols based on a predetermined condition. In the fourth embodiment, four adjacent symbols are compared based on a predetermined priority, and a delimiter position is determined. The delimiter position determination circuit 104 outputs symbols in the order of the input symbol string and outputs a signal indicating the delimiter position. The serializer 13 outputs the symbol pairs in the same order as the input symbol string. In the fourth embodiment, for the sake of convenience, the part up to the separation position determination circuit 104 is referred to as a separation position determination unit, and the subsequent part is referred to as a compression unit. The compression unit has the same configuration as that of the data compressor 10b.

In the fourth embodiment, the delimiter position determination circuit 104 determines a delimiter position between symbols based on a predetermined priority relationship between two symbols to be connected, for example, using the magnitude relationship between the values indicated by the symbols. To do. Specifically, the delimiter position determination circuit 104 treats the bit string indicated by the symbol as a numerical value, and compares the size of two adjacent symbols. Then, a monotonically increasing interval in which the numerical value continues to increase (also referred to as “increasing column”), a monotonically decreasing interval in which the numerical value continues to decrease (also referred to as “decreasing column”), or an interval in which the numerical values are equal (“equivalent column”) Also, the boundary of the section is set as the delimiting position. At this time, for example, priorities may be determined in the order of “equivalent column”, “increasing column”, and “decreasing column”, and symbols positioned at the boundary of the interval may be incorporated into the interval with higher priority. When only one symbol is included in the section, it may be incorporated into the preceding and following sections based on the same priority, for example.

In summary, in the present embodiment, the following two rules are set in advance.
(1) Character size relationship: a <b <c <d...
(2) Priority level of section: Equivalent column> Increasing column> Decreasing column

  According to such a rule, a delimiter position can be determined by comparing four adjacent symbols. In other words, the delimiter position determination process can be executed only by holding four symbols before and after. For this reason, an increase in circuit configuration can be suppressed.

  Next, an implementation example of a data compressor including the delimiter position determination circuit 104 and a data decompressor corresponding thereto will be described. FIG. 15 is a circuit configuration diagram showing an example of the delimiter position determining circuit 104 shown in FIG. The delimiter position determination circuit 104 shown in FIG. 15 holds the stream data in symbol units and transmits the D-FFs 141a to 141c according to the clock signal, the comparators 142a to 142c for comparing the magnitude relationship between the two symbols, and the comparison results. Q-FFs 143a to 143d to be held, and an encoder 144 that outputs a signal indicating the timing for enabling the CAM 101 of the compression unit based on the comparison result (that is, the timing for searching the lookup table).

  The D-FF 141a, D-FF 141b, and D-FF 141c connect the compression unit and the transmission side device 1 in series, and transmit the stream data output from the transmission side device 1 to the compression unit in units of symbols. The comparator 142a receives the output of the D-FF 141a and the output of the D-FF 141b (that is, the first and second symbols adjacent to each other in the stream data at a certain time point), and increases the relationship between the numerical values indicated by the symbols. (<) ”,“ Equivalent (=) ”, or“ decrease (>) ”. For example, identifiers such as “1”, “2”, and “3” are output as signals indicating “increase”, “equivalent”, or “decrease”, respectively. Similarly, the comparator 142b receives the output of the D-FF 141b and the output of the D-FF 141c (similarly, the second and third symbols adjacent to each other), and is either “increase”, “equivalent”, or “decrease”. Is output. The comparator 142c receives the output of the D-FF 141c and the new input to the delimiter position determination unit (similarly, the third and fourth symbols adjacent to each other), and receives “increase”, “equivalent”, or “ "Decrease" is output. Note that a section having a length of one symbol may be incorporated into any one of the front and rear sections.

  The outputs of the comparators 142a to 142c are held in the Q-FF 143a to Q-FF 143c, respectively. Further, values held in Q-FF 143a to Q-FF 143c and values held in Q-FF 143d described later are input to encoder 144. The input of the Q-FF 143d is connected to the output of the encoder 144, and the signal output from the encoder 144 one clock before is held. At the timing when the output of the encoder 144 is “TRUE”, the compression unit described later searches the memory for a symbol pair and attempts compression.

FIG. 16 shows combinations of input and output of the encoder 144. The table in FIG. 16 includes an “input” column (“1 · 2”, “2 · 3”, “3 · 4” and “previous output”) and an “output” column. Yes. Each column of inputs shows the magnitude relationship in the comparator that compares the corresponding symbols. The “first and second” columns correspond to the magnitude relationship held in the Q-FF 143a. The “second and third” columns correspond to the magnitude relationship held in the Q-FF 143b. The “third and fourth” columns correspond to the magnitude relationship held in the Q-FF 143c. Then, the encoder 144 outputs a signal described in the “output” column of the record in which the magnitude relationship in each comparator matches.

  In the first row, when the two symbols input to the comparator 142b are equal and the output from the encoder 144 one clock before is FALSE, the output from the encoder 144 at that clock is TRUE regardless of the preceding and following symbols. Represents that It should be noted that “ANY” described in “1st, 2nd” and “3rd, 4th” in the input string indicates that any of “<”, “>”, and “=” may be used. The second and third lines are a monotonically increasing section and a monotonically decreasing section, respectively. When the output one clock before from the encoder 144 is FALSE, the output from the encoder 144 at that clock is TRUE. Represents that. That is, in the equivalent interval, the monotone increase interval, and the monotone decrease interval, the output of the encoder 144 repeats TRUE and FALSE for each symbol, and the second and third symbols in the delimiter position determination unit are used as symbol pairs in the compression unit. Search the lookup table and try conversion. In the fourth line, two symbols input to the comparator 142b correspond to the end of the monotonically increasing section. When the output from the encoder 144 one clock before is FALSE, the output from the encoder 144 at the clock is Represents becoming TRUE. In the fifth line, two symbols input to the comparator 142b correspond to the beginning of a monotonically increasing section, and when the output from the encoder 144 one clock before is FALSE, the output from the encoder 144 at that clock is TRUE. Represents that The sixth line corresponds to a monotonically increasing section having a length of 2 symbols, in which the two symbols input to the comparator 142b are located at the boundary between two monotonically decreasing sections, and the output from the encoder 144 one clock before is In the case of FALSE, it indicates that the output from the encoder 144 at the clock is TRUE.

  In the example of FIG. 16, the destination for incorporating the symbol corresponding to the break is determined based on the priority order of “equivalent column> increase column> decrease column”. That is, as can be seen from the first row, the equivalent columns are connected most preferentially to form a section regardless of the size of the preceding and following symbols. Further, as can be seen from the 4th to 6th rows, the increasing column is connected with priority over the decreasing column to form a section. Such a rule is an example, and the same symbol string can be divided into the same symbol pair by determining the dividing position according to a predetermined rule.

  With reference to FIG. 17, a process for determining a break position will be described. For example, a case where the symbol string 1 in FIG. 17 is compressed using the lookup table shown in FIG. 3 will be described.

  The symbol string 1 includes two long symbol strings “bcdeacbdddbcdaaaadc” (FIG. 17: underlined portion of the symbol string 1). In the fourth embodiment, first, the lookup table is searched by using the beginning of the symbol string as the first delimiter position and using two symbols from the beginning of the symbol string as a symbol pair (FIG. 17: step S1). Here, as shown in S1, if no symbol pair is registered in the lookup table, no conversion is performed. If there is a delimiter position that is a boundary of a section, the lookup table is searched using two symbols as a symbol pair from the next of the delimiter position (FIG. 17: S2). Here, as shown in S2, if a symbol pair is registered in the lookup table, it is replaced with a converted symbol. Note that “cc” in FIG. 17 is an equivalent section, and “bcde” is an increasing section, and these boundaries serve as delimiting positions. Similarly, symbol pairs are converted from the beginning of each section while detecting the break position (FIG. 17: S3). In FIG. 17, the description of the subsequent processing is omitted.

Symbol string 1 is in a state in which a delimiter as shown in symbol string 2 in FIG. 17 is inserted by the processing of S1 to S3. When the symbol string 2 is converted based on the look-up table having the contents shown in FIG. 3, the compressed data is as shown by the symbol string 3 in FIG. In FIG. 17, delimiters are described for convenience, but symbols or bits indicating delimiters are not added to the stream data.

  The two “bcdeacbdddabcdaadac” included in the symbol column 1 in the symbol column 3 are “VZ | U | b | Yd | TW | Sa | X” and “TWe | Ub | Yd | TW | Sa | X”, respectively. Has been converted. As described above, when the symbol strings match over a plurality of sections, the same symbol pair is generated except for the sections at both ends among the plurality of sections with the matching symbol strings. In the example of FIG. 17, in the two symbol strings in the symbol string 2, the symbol strings in the first section are “cc” and “abcde”, respectively, and are different from each other. Similarly, the symbol strings in the last section are “dca” and “dcc”, respectively, which are different. On the other hand, the symbol sequence (refer to the italicized symbol 2) in the section sandwiched between these first and last symbol sequences matches. Therefore, the sandwiched section is converted by the same logic (see the italicized symbol 3).

  On the other hand, when the symbol sequence 1 is compressed as a symbol pair by two symbols from the top using the lookup table shown in FIG. 3 (that is, in the case of Embodiments 1 to 3), the symbol sequence 4 in FIG. 17 is obtained. .

  The symbol sequence 4 has a data amount larger by 3 symbols than the symbol sequence 3, that is, the compression rate is poor. In other words, more entries are needed in the look-up table to achieve comparable compression ratios. As described above, according to the fourth embodiment, since the same long symbol string can be compressed with a smaller number of entries, the overall compression rate can be improved.

  As the circuit configuration of the compression unit in the fourth embodiment, those shown in FIGS. 4 and 8 can be employed. More specifically, as shown in FIG. 18, the output of the encoder (signal for enabling the CAM) is input to the CAM via the timing matching delay circuits (D-FF 114 to D-FF 116). In the fourth embodiment, for example, a data decompressor similar to that shown in FIGS. 5, 9, and 13 can be employed.

  The data compressor and the data decompressor shown in the fourth embodiment can be combined with at least a part of the first to third embodiments. That is, without using the additional bit (flag), a value that cannot be taken by the symbol before compression may be registered in the lookup table as a symbol after compression. Further, a plurality of stages of data compressors and data decompressors shown in the fourth embodiment may be connected.

  Further, the method of determining the break position is not limited to the above method. For example, by using an algorithm called LCA (Lowest Common Ancestor), an efficient symbol pair may be identified and a delimiter position may be determined, or other methods may be used.

<Modification>
In the above embodiment, two symbols are compressed into one symbol, but the combination of symbols before compression is not limited to two. If the configuration replaces a plurality of symbols with a smaller number of symbols, it functions as a data compressor. However, from the viewpoint of improving the coincidence rate between the lookup table entry and the stream data symbol pair, and from the viewpoint of reducing the data storage capacity, it is preferable to compress the two symbols into one symbol. I can say that.

In the above embodiment, when the symbol pair of the first symbol and the second symbol is not registered in the lookup table, the next processing target is the third symbol and the fourth symbol, and these symbols It was determined whether the pair was registered in the lookup table. Here, when the symbol pair of the first symbol and the second symbol is not registered in the lookup table, the next processing target may be the symbol pair of the second symbol and the third symbol. In this way, an improvement in compression rate can be expected.

  The entry of the lookup table may be changed based on the appearance likelihood of the symbol in the compression target data. For example, the memory may calculate the matching rate between the symbol pair and the entry, and when the matching rate falls below a predetermined threshold, the entry in the lookup table may be updated. At this time, the entries in the lookup table may be distributed by a management apparatus connected to the transmission side apparatus 1 and the reception side apparatus 2. For example, when the compression target data is a so-called miniblog timeline, the topic to be posted changes with the passage of time, and the symbol pair preferable as the compression target also changes accordingly. When the matching rate between the symbol pair and the entry is less than or equal to a predetermined threshold, the compression rate can be prevented from decreasing by updating the lookup table entry.

For example, the data compressor and the data decompressor according to the present invention may be provided in a network interface (network card) of a computer connected to a network, or may be provided between two points of a bus connecting a plurality of processors. Good. When the network interface is provided, for example, it is provided at a stage before being divided (fragmented) into frames (MTU: Max Transmission Unit, also referred to as a packet) in Ethernet (registered trademark).
For example, an identifier that can identify each of a symbol string (compressed data) and an additional bit string (flag string) at each stage may be added to the frame. The identifier includes information that makes it possible to separate the compressed data and the flag string multiplexed on the receiving side, such as the position information when the compressed data and each flag string are mapped on the frame.

  The data compressor and the data decompressor according to the present invention may be applied to so-called big data transfer or may be applied to data backup between specific devices. Further, for example, when the computer virus pattern data and the data flowing through the network are compared in a compressed state, an improvement in processing speed can be expected.

  By the way, in the second embodiment described above, the data compressor outputs two data series of a symbol string (compressed data) and a flag string. In the third embodiment, in addition to the symbol string (compressed data), two or more flag strings corresponding to the number of stages of the data compressor are output. The compressed data output from the data compressor is transmitted to the data decompressor via the transmission path 3 as described above. At this time, when a configuration is adopted in which the data compressor and the data decompressor are connected by a parallel dedicated line, the output (each data series) from each output port provided in the data compressor is the data decompressor. Can be connected to an input port corresponding to each data series.

  On the other hand, the output from the data compressor may be mapped to a predetermined transmission medium (for example, a MAC frame) and transmitted on the transmission path 3. At this time, the mapping of the compressed data and the flag string to the transmission medium follows a protocol of a layer positioned lower than the data compressor. As a result, the lower layer on the data decompressor side may deliver the data string in which the compressed data and the flag string are connected in series to the layer where the data decompressor is located (referred to as “decompression layer”). In this case, in the decompression layer, the compressed data and the flag string are required to be separated (separated) in order to connect the compressed data and the flag string to the input port of an appropriate data decompressor. For this reason, for example, the following configuration is adopted.

FIG. 19 shows an example of a data format in which a data string (bit string) in which compressed data and a flag string are connected in series can be separated for each data series in a data decompressor. The data compressor 10b and the data decompressor 20b shown in FIGS. 11 and 13 will be described as an example. The compressed data (4) output from the data compressor 10d and the five data sequences of the first to fourth flag sequences are as follows. For example, a parallel / serial converter (not shown) converts the data into one serial data string having a predetermined order (for example, compressed data, first flag string, second flag string, third flag string, fourth flag string). Is done. A data string is handled as one data block. Further, the number of bits of each data series is counted by a counter (not shown), and a header based on the counting result is generated. The header includes, for example, at least the header size and the size of each data series in the data block. The header size in the header and the size of the data series are expressed by, for example, fixed-length bits (the header size becomes a fixed length. When the header size is fixed length (known on the decompression side), Including the header size in the header can be omitted). Such a header is set in the preceding stage of the data block and passed to the lower layer. The header may store an offset (start position of each data series) and a data block size instead of the data size.

  On the data decompressor 20b (FIG. 14) side, a header analysis circuit (not shown) is placed in front of the data decompressor. The header analysis circuit receives a data string (FIG. 19) composed of a header and a data block from the lower layer, and refers to information (header size, size of each data series) stored in the header to convert the data block into five data Separate into series. In the example of FIG. 19, the header has a fixed length, and the start position of the data block following the header is determined. Also, the start position of the first flag string is behind the compressed data size from the beginning of the data block. Similarly, the start positions of the second to fourth flag sequences can also be obtained using the size of the compressed data and the sizes of the first to third flag sequences. The size of the entire data block is the sum of the size of the compressed data and the sizes of the first to fourth flag columns. In this way, the data decompressor side can determine the offset and size of each data series, and can separate the data block into each data series. One of the separated data series (compressed data (4)) is input (connected) to the latch 200. The fourth flag string is stored in a buffer (not shown) for supplying a flag value to the selector 205a at an appropriate timing. The first to third flag strings are sent to another data decompressor located in the subsequent stage. As described above, a protocol for separating a plurality of data series on the decompression side is determined between the compression side and the decompression side.

  The configurations of Embodiments 1 to 4 described above can be combined as appropriate.

10, 10a, 10b Data compressor 101, 101a Memory (CAM)
102 Serializer (Multiplexer)
103 selector (multiplexer)
104 Separation position determination circuit 20, 20a, 20b Data decompressor 201 Memory 202 Separator (demultiplexer)
203, 205 Selector 204 1-bit counter 3 Transmission path

Claims (12)

A data compressor mounted on a communication device on a transmission side that transmits stream data to a communication device on a reception side,
A latch for receiving an input data string that is the stream data composed of a plurality of fixed-length symbols, and holding and outputting the input data string in symbol units;
A memory in which a plurality of entries each representing one conversion destination symbol corresponding to two or more symbols having a fixed number of symbols is registered, and corresponds to two or more consecutive symbols output from the latch The process of searching for one symbol from the plurality of entries is performed once, and when one symbol corresponding to the two or more consecutive symbols is hit, the one hit symbol is output and the hit one A memory that outputs a signal indicating the output of two symbols;
And two or more symbols the continuous output from the latch, and can input and the signal with one symbol mentioned above hit output from the memory, on the basis of the said signal outputted from said memory latch A selector that outputs one of the two or more consecutive symbols output from the one of the hit symbols output from the memory;
Only including,
The processing delay in the memory is substantially fixed, the processing delay of the selector is substantially constant, and the selector outputs the two or more consecutive symbols after the two or more consecutive symbols are output from the latch. A data compressor in which a processing delay until one of the one symbols output from the memory is output is fixed . A delimiter position determining circuit that determines a delimiter position between the symbols included in the input data sequence based on a magnitude relationship between the symbols included in the input data sequence;
The memory outputs one symbol corresponding to a predetermined number of symbols output from the latch and based on the delimiter position, and outputs the one symbol. The data compressor according to claim 1, wherein a signal indicating is output. 3. The data compressor according to claim 1, wherein an output of the selector when the two or more symbols are converted into one symbol is a value that cannot be obtained otherwise. The data compressor according to any one of claims 1 to 3, wherein the memory is a CAM (Content Addressable Memory). The data compressor according to any one of claims 1 to 4, wherein the memory outputs one symbol corresponding to two consecutive symbols output from the latch. The latch includes first to third flip-flops that operate according to a predetermined clock signal,
The first flip-flop holds the input symbol and outputs the held symbol according to the clock signal to the second flip-flop and the memory;
The second flip-flop holds the symbol output from the first flip-flop and outputs the symbol held according to the clock signal to the third flip-flop and the memory,
The third flip-flop holds the symbol output from the second flip-flop and outputs the symbol held according to the clock signal to the selector.
At the first timing, when two consecutive symbols held in the first flip-flop and the second flip-flop are respectively output to the subsequent flip-flop and the memory,
In the second timing, when the memory outputs a signal indicating the output of the one symbol, the selector outputs one symbol output from the memory,
When the memory does not output a signal indicating the output of the one symbol at the second timing, the selector holds the second flip-flop and the third flip-flop at the second timing. The data compressor according to claim 5, wherein two consecutive symbols are sequentially output. The data compressor according to any one of claims 1 to 6, wherein a signal indicating the output of the one symbol is also output to a signal line connected to a data decompressor that decompresses a symbol output from the selector. . A plurality of data compressors according to claim 7 are connected in series,
A data compression device for inputting a symbol output from the selector of a preceding data compressor as the input data string to a subsequent data compressor,
A data compression apparatus in which a symbol replaced in a later data compressor is decompressed in a preceding data compressor among a plurality of data decompressors connected in series. A data decompressor mounted on a receiving-side communication device that receives stream data transmitted from a transmitting-side communication device mounted on a data compressor,
A latch that receives an input of an input data string, which is the stream data including a fixed-length symbol, and holds and outputs the input data string in units of symbols;
A memory in which two or more symbols to be converted in a data compressor that has performed compression processing and generated the input data string is registered in association with one symbol before conversion, and is one memory that is output from the latch A memory for outputting two or more symbols corresponding to the symbols;
A detection circuit that outputs a predetermined control signal when two or more symbols are output from the memory;
A selector that outputs the two or more symbols output by the memory when the control signal is input; and otherwise outputs the one symbol input from the latch;
Only contains the memory, <br/> data decompressor said sensing circuit and said selector to fixed processing delay of the decompression process. A data decompressor mounted on a receiving-side communication device that receives stream data transmitted from a transmitting-side communication device,
A latch that receives an input of an input data string, which is the stream data including a fixed-length symbol, and holds and outputs the input data string in units of symbols;
A memory in which two or more symbols are registered in association with one symbol, and outputs two or more symbols corresponding to one symbol output from the latch;
A flag indicating at least one of whether or not the symbol included in the input data sequence has been converted by the data compressor is received from a data compressor that has performed compression processing and generated the input data sequence And when the flag indicates that the symbol included in the input data string has been converted by the data compressor, the two or more symbols output by the memory are output, and the flag is A selector that outputs the one symbol input from the latch, when indicating that the symbol included in the input data sequence is not converted by the data compressor;
Only contains, <br/> data decompressor said memory and said selector to fixed processing delay of the decompression process. The data decompressor according to claim 9 or 10, wherein the memory outputs two or more symbols held in association with symbols held as addresses in a CAM included in the data compressor. The data decompressor according to any one of claims 9 to 11, wherein the same number of data compressors as each of the data compressors are connected, and the flags received from the corresponding data compressors are connected in series. A data decompression device in which a selector of a data decompressor outputs two or more symbols or symbols included in an input data string based on the data decompressor.

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