JP6166192B2 - Data storage device - Google Patents

Description

The present invention relates to a data storage device that checks whether there is an abnormality in transfer data when transferring CPU data to a nonvolatile memory.

Volatile memory is widely used as a temporary storage device because it can read and write at high speed, and volatile memory is used as the memory in the CPU. However, volatile memory loses data when the power is turned off, so data that needs to be saved is transferred from volatile memory to nonvolatile memory and saved in nonvolatile memory. Data transfer is performed by connecting the CPU and the terminals of the nonvolatile memory with a plurality of wires and sending a 0 or 1 signal to each line. The wiring between the terminals is a plurality of address wirings and a plurality of data wirings, and an address consisting of 0 and 1 and a data value consisting of 0 and 1 are sent as a set. Data is transferred by reading an address and data from the CPU 1 and writing a data value corresponding to the designated address of the nonvolatile memory 2.

If a short circuit or disconnection occurs in the address wiring or data wiring, correct data cannot be sent. In order to detect an abnormality during the data transfer, a check by a sum check is often performed. In sum check, data is summed as a value before data transfer, and the total value is transferred together with the data. Similarly, after the data is received, the data values are summed, and the total values are compared before and after the data transfer. In this case, if the total value is the same on the transmitting side and the receiving side, it is determined that the data has been transmitted correctly. However, since the values are simply added, even if the data are different, the same numerical value is assumed. There is a possibility and there is a problem in terms of accuracy. In Japanese Patent Laid-Open No. 3-255555, a check ID code is added to transfer data, and if the check after transfer differs, it is determined that there is an abnormality. However, in this case, it is necessary to set more ID codes for checking in order to increase the reliability of abnormality determination, so the area where data can be stored is reduced, and the possibility of erroneous determination due to chance remains. It was.

JP-A-3-255555

The problem to be solved by the present invention is that data storage that can reliably detect abnormal data transfer due to a short circuit or disconnection of wiring by using a minimum data area for checking when transferring data To provide an apparatus.

The invention described in claim 1 has a non-volatile memory that can store data even after power is lost, and a CPU that writes data to the non-volatile memory, and a plurality of wirings are connected between the terminals of the CPU and the non-volatile memory. The wiring between terminals is composed of a plurality of address wirings for passing a 0 or 1 signal for addressing and a plurality of data wirings for passing a 0 or 1 signal for sending data. In a data storage device in which data is transferred from the CPU to the non-volatile memory as a set of data, when the address is expressed in binary in the transfer data, the signal 1 is 1 or less in the address. For each address, enter a password that is set to a different value instead of data. When transferring data from the CPU to the nonvolatile memory, the After transferring the password, after extracting the data, extract the password stored in the specified address of the non-volatile memory, and detect the abnormality during the data transfer by comparing the extracted password with the set password It is characterized by.

According to the second aspect of the present invention, in the data storage device, the data to be set as a password is also set such that a value in which the signal 1 is 1 or less is set as the password in the data. It is characterized by.

By using the minimum data area, it is possible to reliably detect an abnormal data transfer due to a short circuit or disconnection of wiring.

Transfer data explanatory diagram for explaining a password setting state in one embodiment of the present invention Connection diagram between CPU and nonvolatile memory in the first embodiment of the present invention Transfer data explanatory diagram in the first embodiment of the present invention Transfer data check procedure explanatory diagram in the first embodiment of the present invention Connection diagram between CPU and nonvolatile memory in the second embodiment of the present invention Transfer data explanatory diagram in the second embodiment of the present invention Transfer data check procedure explanatory diagram in the second embodiment of the present invention Connection diagram between CPU and nonvolatile memory in the third embodiment of the present invention Transfer data explanatory diagram in the third embodiment of the present invention Transfer data check procedure explanatory diagram in the third embodiment of the present invention

  An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an explanatory diagram of transfer data for explaining a password setting state in one embodiment of the present invention, and shows normal data read on the CPU side. 2, 5, and 8 are block diagrams illustrating a wiring state between the CPU and the nonvolatile memory. Since the CPU 1 can only store data temporarily and the data is lost when the power is turned off, the data that needs to be saved is transferred to the nonvolatile memory 2 that can be saved even when the power is turned off. An address wiring 3 and a data wiring 4 are connected between the CPU 1 and the nonvolatile memory 2. The address lines 3 are connected by 8 lines from the 0th bit to the 7th bit, and the data lines 4 are also connected by 8 lines from the 0th bit to the 7th bit. When data is transferred from the CPU 1 to the nonvolatile memory 2, data is transferred by flowing 0 or 1 data in each address wiring 3 and data wiring 4. In this case, if the address wiring 3 or the data wiring 4 is disconnected or short-circuited, the signal transmitted from the CPU 1 is different from the signal received on the nonvolatile memory 2 side in the wiring in which an abnormality has occurred. Therefore, correct data cannot be transferred.

Therefore, when data is transferred from the CPU 1 to the nonvolatile memory 2, a password is sent together with the data, and the password is verified after the data is transferred. When the address is expressed in binary, the password is set at each address where the signal 1 is 1 or less in the address, and data values to be stored are stored in the other addresses. The address where the signal 1 in the address is 1 or less is specifically a binary number such as “00000000” “00000001” “00000010” “00000100” “00001000” “00010000” “00100000” “01000000” “10000000” It is. FIG. 1 shows data sent from the CPU 1 to the non-volatile memory 2 together with an address. It is 8-bit data, and there are 256 sets of addresses and data from No. 1 to No. 256. Among them, the data No. for which the password is set and the vicinity are extracted. Here, passwords are set for transfer data Nos. 1, 2, 3, 5, 9, 17, 33, 65, and 129 expressed in decimal numbers. Is set in advance. Different passwords are set for the respective addresses, and the password is set to a value such that the signal 1 is 1 or less in the data. That is, the password is set to “00000000”, “00000001”, “00000010”,... “10000000”, which is the same as the address. The address and password do not have to be combined with the same value, but since it is easier to understand if the same value is used, the address value and the password value are the same in the embodiment.

Data transfer from the CPU 1 to the non-volatile memory 2 is performed in the order of transfer data No., 0 or 1 sent by the address wiring 3 is designated by the combination, and 0 or 0 sent to the designated address through the data wiring 4 Data of one combination is stored. When the data is transferred normally, the correct password is input to the address where each password is set. Therefore, after the data is transferred, the password stored in the designated address of the nonvolatile memory 2 is read and compared with the password at the corresponding address, and the password is confirmed. If the passwords match, it is determined as normal. In this case, if the passwords do not match, it is determined that an abnormality has occurred in the transfer data.

Description will be made based on a specific example. In FIG. 1, data is sequentially written from No. 1 to No. 256. Data No. 1 is set to password 1, and password “00000000” is set to password “00000000”. Similarly, data No. 2 is set up to password 9 such as address “00000001” with password 2 data “00000001”, data No. 3 with address “00000010” and password 3 data “00000010”. . The password 9 is set in the data No. 129. In this case, the address is “10000000” and the password is also “10000000”. Since the address for setting the password is an all-zero address and each address in which 1 is entered in only one bit in the address, the data for which the password is input becomes sparse as it moves backward. In a data area having 256 addresses, there are nine addresses for defining passwords, and the remaining 247 addresses contain data to be stored. Since the data portion is a value that changes every time, the data portion is represented by “*”.

FIG. 2 and subsequent figures are for cases where an abnormality occurs during data transfer. FIGS. 2 to 4 show the data transfer situation when a short circuit occurs between the first bit portion line and the second bit portion line among the eight address lines 3 connecting the CPU 1 and the nonvolatile memory 2. Is shown. In this case, when the signal 1 is output from the CPU through the first bit line of the address portion, the data of the signal 1 is sent to the second bit line in addition to the first bit line. Therefore, when data is read from the CPU, the signal 1 is output to the first bit line of the address portion and the signal 0 is output to the second bit line. Signal 1 is written to both the 1-bit line and the second-bit line. Conversely, the CPU outputs the signal 1 only to the second bit line of the address portion and outputs the signal 0 to the first bit line. However, in the nonvolatile memory 2, the first bit line and the second bit are output. Both lines are recognized as signal 1. FIG. 3 shows this state, and incorrect data is sent in a portion surrounded by a thick frame. In this portion, the signal 0 is shown in FIG. 1 where the data transfer can be normally performed. However, the signal 1 is written in the nonvolatile memory 2 due to the influence of the short circuit.

In this case, some data is input to an address different from the original. Data No. 2 was originally supposed to be sent to address “00000010”, but since the signal in the second bit has changed from 0 to 1, it will be sent to address “00000110”. Yes. Data No. 5 is also sent to the address “00000110” instead of the original address “00000100”. Further, since the address “00000110” is the address where the data No. 7 is entered, the data of the data No. 7 is also sent to the address “00000110”. If data is written in order from No. 1, data No. 3 “0000010” is first written to address “00000110” as shown in FIG. After that, since the No. 5 data is also written to the same address, the No. 3 “00000010” previously written is deleted and the No. 5 data “00000100” is written to this address. Further, since the No. 7 data is also written to the same address, the No. 7 data “******” (* is 0 or 1) is written to this address, and finally the address “ “00000110” contains No. 7 data.

In this case, a mismatch occurs between the password 3 and the password 4 at the time of checking the abnormality performed after the data transfer. In the password 3 check, the data contained in the designated address “00000110” is compared with “00000010” set as the password 3, and if they are different, a data abnormality is determined. The address “00000110” is initially written with “00000010” of the password 3 at the time of data writing, but after that, the data of No. 5 is overwritten and then the data of No. 7 is overwritten. Contains No. 7 data. If the password 3 and the data of No. 7 are compared to confirm that they are different, it is determined that the data is abnormal.

Similarly, the password 4 is also checked. The data of No. 7 stored in “00000110” which is the designated address of password 4 is compared with “00000100” set as password 4. The data of password 4 and No. 7 are compared, and if it can be confirmed that they are different, it is determined that the data is abnormal. The determination of the presence or absence of an abnormality is determined as abnormal if any one of a plurality of set passwords is different, and is determined as normal when all passwords match.

The data of No. 7 changes every time and may be the same as a password by chance. For example, when the data of No. 7 is “00000010”, this is the same value as that of the password 3, and therefore, when comparing with the password 3, the abnormality cannot be detected. However, even in that case, when comparing with the password 4, this value is not the same as that of the password 4, so that an abnormality can be detected. Since the password 3 and the password 4 are set to different values, the password 3 and the password 4 cannot be the same, and the data abnormality determination can be reliably detected.

FIG. 5 to FIG. 7 show the data transfer status when a break occurs in the third bit portion of the eight address lines 3 connecting the CPU 1 and the nonvolatile memory 2. In this case, even if the signal 1 is output from the CPU in the third bit line of the address wiring, the signal 1 is not sent to the third bit line of the nonvolatile memory 2, and the third bit line of the nonvolatile memory 2 is It is always recognized that the signal is 0. FIG. 6 shows this state, and incorrect data is sent in a portion surrounded by a thick frame. This portion is a signal 1 in the normal data described in FIG. 1, but a signal 0 is sent to the nonvolatile memory 2 due to the influence of the disconnection.

Also in this case, some data is input to an address different from the original. Data No. 9 was originally supposed to be sent to address “00001000”, but is supposed to be sent to address “00000000”. The address “00000000” is data No. 1 and “00000000” of password 1 is input, but is overwritten with data No. 9 and is rewritten to “00001000”.

In this case, a mismatch occurs in the password 1 at the time of checking an abnormality after data transfer. In the password 1 check, the data stored in the address “00000000” is compared with “00000000” set as the password 1, and if they are different, a data abnormality is determined. At address “00000000”, when data is written, “00000000” of password 1 is initially written, but since data of No. 9 is overwritten thereafter, the password of No. 9 is finally obtained. “00001000”. When “00000000” of password 1 is compared with “00001000” in the designated address, it is determined that the data is abnormal because they are different.

FIG. 8 to FIG. 10 show the state of data transfer when a short circuit occurs between the second bit portion line and the third bit portion line among the eight data wires 4 connecting the CPU 1 and the nonvolatile memory 2. Is shown. In this case, when the signal 1 is output from the CPU through the second bit line of the data wiring, the data of the signal 1 is sent to the third bit line in addition to the second bit line. Therefore, even if the CPU outputs the signal 1 to the second bit line of the data portion and the signal 0 to the third bit line, the non-volatile memory 2 has the signal 1 to both the second bit line and the third bit line. Will be sent. Even if the CPU outputs the signal 1 to the third bit line of the data portion and outputs the signal 0 to the second bit line, the non-volatile memory 2 also outputs the second bit line and the third bit line. Both are recognized as signal 1. FIG. 7 shows this state, and incorrect data is sent in a portion surrounded by a thick frame. In this portion, the transfer data in FIG. 1 is the signal 0, but the signal 1 is sent to the nonvolatile memory 2 due to the influence of the short circuit.

In this case, data different from the original is input at some addresses. When writing the data of No. 5, the address “00000100” was originally supposed to be sent “00000100”, but since the third bit of the data has changed from 0 to 1, the data “0000100” is changed. To be sent. Data No. 9 also sends data “00001100” instead of the original data “00001000”.

In this case, a mismatch occurs between the password 4 and the password 5 at the time of checking an abnormality after data transfer. The password 4 is checked by comparing the data contained in the address “00000100” with “00000100” set as the password 4, and if they are different, the data abnormality is determined. The address “00000100” is different from the password 4 because “0000100” is written when data is written. If the password 4 and the data are compared to confirm that they are different, it is determined that the data is abnormal.

The password 5 is also checked in the same manner. The data “000001100” stored in the address “00001000” is compared with “00001000” set as the password 5 for the password 5. The password 5 and the data at the address are compared, and if it is confirmed that they are different, it is determined that the data is abnormal.

In the present invention, when an abnormality occurs during transfer, the same value as the accidentally set password is used, so that the occurrence of the abnormality is not overlooked, so that the reliability of data can be improved. In addition, data to be stored cannot be input in the portion where the password is set, but the address used for the password is a small amount compared to the entire data. In the embodiment, there are 8 bits of data and 256 addresses, but the required number of passwords is 9. And if the number of bits increases by one, the password will increase by one, but the number of data areas will double, so the data area used for the password increases as the number of bits increases and the address digits of the data increase. The percentage of will get smaller.

The present invention is not limited to the embodiments described above, and many modifications can be made by those having ordinary knowledge in the art within the technical idea of the present invention.

1 CPU
2 Nonvolatile memory
3 Address wiring 4 Data wiring

Claims (2)

It has a non-volatile memory that can store data even after power is lost, and a CPU that writes data to the non-volatile memory. Multiple wires are connected between the CPU and the non-volatile memory terminals. It consists of a plurality of address wirings that pass 0 or 1 signals to specify and a plurality of data wirings that pass 0 or 1 signals to send data. In a data storage device designed to perform data transfer to the memory,
Of the transfer data, when the address is expressed in binary, each address having one or less signal 1 in the address is input with a password set to a different value instead of the data, and the CPU stores the password. The data is transferred by transferring the password together with the data, extracting the password stored in the specified address of the non-volatile memory, and comparing the extracted password with the set password. A data storage device for detecting an abnormality during transfer. 2. The data storage device according to claim 1, wherein the data set as the password is also set such that a value in which no more than one signal 1 is set in the data as the password. Storage device.

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