JP6145482B2 - Transmission apparatus and failure detection method - Google Patents

Description

  The present invention relates to a transmission apparatus and a failure detection method.

  In recent years, with the spread of mobile terminals and the increase in demand for distribution services such as video and audio, the traffic capacity on the network has increased rapidly. Along with this, the signal capacity handled by each transmission device (Node) constituting the network has been dramatically increased. For this reason, the circuit scale of each transmission device becomes large, and the improvement of network reliability by increasing the failure occurrence rate, identifying the faulty part at the time of the occurrence of a line failure due to a soft error, and prompt signal relief becomes a major issue. ing. As a method for detecting a failure when a line failure occurs, a method for detecting a failure by transmitting / receiving a failure detection signal such as AIS (Alarm Indication Signal) or RDI (Remote Defect Indication) between Nodes is known (for example, patents). Reference 1).

  On the other hand, IP (Internet Protocol) of communication networks has progressed, and various types of paths such as Ethernet (registered trademark) Packet signals and SDH (Synchronous Digital Hierarchy) / SONET (Synchronous Optical NETworking) TDM (Time Division Multiplexing) signals. Is accommodated in the communication network. For this reason, a large-capacity signal is transmitted between points, and the load on the transmission apparatus is increasing. Programmable devices such as FPGA (Field Programmable Gate Array) are often used in order to realize a circuit of a transmission apparatus corresponding to such a network. The Programmable Device can mount an arbitrary circuit by programming circuit configuration information in a configuration memory (CRAM).

Japanese Patent Laid-Open No. 10-065696

  If a soft error occurs in the CRAM, the circuit may malfunction, but the memory area that affects the operation due to the soft error is a small percentage of the entire CRAM cell, and in many cases is not yet available. Operation is not affected because of the area used. However, when a CRAM soft error is handled as a device failure, it is determined as a device failure even when there is no influence on the device operation, which causes a problem that the number of failures increases. On the other hand, if a CRAM soft error is not treated as a device failure, it will not be detected as a device failure even if an error occurs in the circuit in which the CRAM is used. The problem arises that it becomes difficult.

  An object of the transmission device and the failure detection method disclosed herein is to provide a technique for detecting a device failure without increasing the number of failures even when a soft error occurs in the CRAM and identifying the failure location.

  According to one aspect, a programmable device that configures a circuit with program data stored in advance in a memory, an error detection unit that detects a soft error in the memory, and a time count that counts a preset time when a soft error is detected A failure notification detection unit that detects a failure notification signal transmitted from the transmission device of the communication destination, and after the error detection unit detects a soft error, there is a failure until the time counting unit finishes counting the preset time. And a determination unit that determines that the circuit has failed when the notification detection unit detects a failure notification signal.

  According to one aspect, a failure detection method for a transmission apparatus having a programmable device that configures a circuit with program data stored in advance in a memory, and starts counting a preset time when a memory soft error is detected Then, it is determined that the circuit has failed when a failure notification signal transmitted from the transmission apparatus of the communication destination is detected before the preset time is counted.

  The transmission device and the failure detection method disclosed herein can detect a device failure without increasing the number of failures even when a soft error occurs in the CRAM, and specify the failure location.

It is a figure which shows an example of a transport network. It is a figure which shows an example of the path | route between Nodes in a comparative example. It is a figure which shows an example of the path | pass at the time of the normal in a comparative example. It is a figure which shows an example of the flow of the signal at the time of the soft error in a comparative example. It is a figure which shows an example of the signal flow at the time of the soft error in this embodiment. It is a figure which shows an example of Card # 0. It is a figure showing an example of processing until card failure is detected. It is a figure which shows an example of the process sequence in Card # 0. It is a figure which shows an example when the error which generate | occur | produced in CRAM is recovered | restored by error correction. It is a figure which shows an example when the error which generate | occur | produced in CRAM recovers by error correction, but a signal error continues. It is a figure which shows an example which relieves a signal when the user side interface circuit is made redundant. It is a figure showing an example of processing until card failure is detected. It is a figure which shows the example of application to a ring network. It is a figure which shows an example of the flow of the signal at the time of a soft error. It is a figure which shows the process example until a card failure is detected in a ring network. It is a figure which shows an example which relieves a signal by a redundant circuit in a ring network.

  Hereinafter, embodiments of a transmission device and a failure detection method will be described with reference to the drawings.

  FIG. 1 shows an example of a transport network 900. In FIG. 1, the transport network 900 includes a node 901, a node 902, a node 903, and a node 904. Node 902 and Node 903 are connected by a transmission network 905. For example, in FIG. 1, a Node 901 is connected to a user side and transmits / receives an Ethernet signal, a TDM signal, or the like corresponding to Ethernet to / from a Node 902 on the network side. The TDM signal is a signal corresponding to, for example, SDH / SONET. For example, an SDH / SONET TDM signal transmitted from the Node 901 is transferred from the Node 902 to the Node 903 via the transmission network 905, transmitted from the Node 903 to the Node 904, and output from the Node 904 to the user side. Similarly, the Node 904 is connected to the user side and transmits and receives an Ether signal, a TDM signal, and the like to and from the Node 903 on the network side. For example, an SDH / SONET TDM signal transmitted from the Node 904 is transferred from the Node 903 to the Node 902 via the transmission network 905, transmitted from the Node 902 to the Node 901, and output from the Node 901 to the user side.

  As described above, each node dramatically increases the signal capacity by handling various types of signals, and the scale of a circuit realized by an FPGA or the like is increased. Therefore, in the network, there are problems such as an increase in the failure occurrence rate and identification of a failure part when a line failure occurs due to a soft error.

  FIG. 2 shows an example of a path between nodes in the comparative example. In FIG. 2, the transmission network 905 described in FIG. 1 and the like are not described, and the connection relationship of only the Node is illustrated, but each Node may be connected to the transmission network 905.

  In FIG. 2, Node 951A forms a path with Node 951E via Node 951B, Node 951C, and Node 951D, and transmits and receives main signals. Consider a case where a signal error due to a soft error occurs in the Node 951A in the comparative example.

  Here, the soft error is an error (CRAM ERR) of a memory (CRAM: Configuration Random Access Memory) in which an FPGA program constituting the circuit of the Node 951A is stored. An FPGA can be mounted with an arbitrary circuit by changing a program of circuit configuration information stored in a CRAM, and thus is widely used in communication apparatuses that are required to support various services. However, memory bit inversion occurs due to the influence of cosmic rays, etc., and incorrect data is read, causing the FPGA circuit to stop operating or operate differently from the original circuit. A signal error may occur. As described above, when a soft error occurs in the CRAM, a malfunction may occur in the circuit. However, in the configuration memory, the circuit of the actual use portion that affects the operation in the event of a failure is a small percentage of the entire cells of the configuration memory. In other words, most of the cells in the configuration memory are not involved in normal operation because they are unused circuits. Therefore, if all soft errors in the configuration memory are handled as device failures, even if there is no influence on the device operation, it is determined as a failure, and an accurate failure determination cannot be made, and the number of failures increases. On the other hand, if the configuration memory soft error is not treated as a device failure, an error will actually occur in the circuit used and the main signal will be affected, but the device will not detect the failure, so the failure location on the network will be identified. Becomes difficult.

  Thus, in the comparative example, when a signal error due to a soft error occurs in Node 951A, Node 951A cannot determine whether or not a signal error has occurred due to a soft error. For this reason, the network of the comparative example has a problem that the signal error continues to be output without being recovered.

  FIG. 3 shows an example of a normal path in the comparative example. Each block shown in FIG. 3 corresponds to each block having the same sign shown in FIG.

  In FIG. 3, Node 951A has Card # 0, Card # 1, SWF (SWitch Fabrication), and Card-N. Here, the Node 951E has the same or similar blocks as the Node 951A. In addition, although each block is described by the same code name in Node951A and Node951E, when referring to a specific block, it describes as Card # 0 of Node951A, Card # 0 of Node951E, for example. And when performing description common to Node951A and Node951E, it describes like Card # 0 and Card # 1.

  Card # 0 and Card # 1 are interface circuits on the user side of Node 951, and are made redundant by two interface circuits of Card # 0 and Card # 1.

  Card-N is an interface circuit on the network side of Node 951. In the example of FIG. 3, the interface circuit on the network side is one of Card-N, but a plurality of redundancy may be provided.

  SWF switches and switches a signal input / output between the user side connected to Card # 0 or Card # 1 and a signal input / output between the network side connected to Card-N. It is a switch for.

  In the example of FIG. 3, a signal input from the user side to Card # 0 of Node 951A is output from the Card-N of Node 951A to the network side via the SWF of Node 951A and transmitted to Node 951B. A signal transmitted from the Node 951A to the network side is relayed from the Node 951B to the Node 951C and the Node 951D, and transferred to the Node 951E. Conversely, a signal input from the user side to Card # 0 of Node 951E is output from the Card-N of Node 951E to the network side via the SWF of Node 951E, and transmitted to Node 951B. A signal transmitted from the Node 951E to the network side is relayed from the Node 951D to the Node 951C and the Node 951B, and transferred to the Node 951A.

  Here, in the comparative example, the Node 951B, the Node 951C, and the Node 951D operate as relay nodes, and transfer signals transmitted and received between the Node 951A and the Node 951E.

  FIG. 4 shows an example of a signal flow at the time of a soft error in the comparative example. Each block shown in FIG. 4 corresponds to each block having the same sign shown in FIG.

  FIG. 4 illustrates a case where a soft error that affects the circuit occurs in Card # 0 of Node 951A and a signal error is detected in the network. In FIG. 4, the signal error is detected by, for example, the Node 951B, and the AIS is transmitted downstream. Alternatively, Card-N may detect a signal error and transmit AIS. In any case, the AIS reaches the Node 951E via the Node 951C and the Node 951D, and the AIS is detected by the Node 951E. On the other hand, Card # 0 of Node 951E transmits a failure notification signal (for example, RDI) for notifying the communication destination that a failure has occurred in the downlink, to Node 951A of the communication destination. However, Node 951A can recognize that a failure has occurred in the downstream path from Node 951A to Node 951E by RDI, but does not recognize that a failure has occurred due to a soft error of Card # 0 of its own Node. . For this reason, the signal error continues to be output in the network of the comparative example.

  Therefore, the transmission apparatus and the failure detection method according to the present embodiment have a function of determining whether or not a card failure due to a CRAM error has occurred.

  FIG. 5 shows an example of a signal flow at the time of soft error in the present embodiment. 5 corresponds to the comparative example shown in FIG. In the example of FIG. 5, the Node 101A does not determine whether the soft error is involved in the signal error at the time when the CRAM soft error is detected, and the CRAM soft error becomes a signal error due to the reception of RDI from the communication destination. Determine if you are involved.

  In FIG. 5, a soft error is detected at Card # 0 of Node 101A. If a signal error has occurred due to a soft error, the Card-N of the Node 101B or Node 101A transmits an AIS to the Node 101E. The AIS reaches the Node 101E via the Node 101B, Node 101C, and Node 101D, and the AIS is detected by the Node 101E. And Node101E which detected AIS transfers RDI. The RDI reaches the Node 101A via the Node 101D, Node 101C, and Node 101B, and the Node 101A detects the RDI. Then, the Node 101A recognizes that a signal error has occurred due to a card failure of its own Node when it receives RDI from the Node 101E before the preset time elapses after the soft error is detected.

  In this way, the Node 101A detects a card failure of its own Node, and transmits a device alarm indicating the occurrence of the card failure to another Node or a monitoring device. Further, the Node 101A can relieve the signal by switching to another circuit when there is a redundant circuit.

  FIG. 6 shows an example of Card # 0 of Node 101A. In FIG. 6, Card # 0 includes an optical modulation / demodulation unit 201, a programmable device 202, a CRAM error detection unit 203, a CRAM timer unit 204, an RDI detection unit 205, and a card failure determination unit 206. The RDI detection unit 205 may be in the programmable device 202 or may be separate from the programmable device 202. The CRAM error detection unit 203, the CRAM timer unit 204, and the card failure determination unit 206 may be implemented by either hardware / software.

  The optical modulator / demodulator 201 demodulates an optical signal received from the user side into an electrical signal, and modulates the electrical signal transmitted to the user side into an optical signal.

  The programmable device 202 is a device that uses an FPGA or the like and can realize an arbitrary circuit by program data. The programmable device 202 has a CRAM 251 and realizes a circuit of the main signal processing unit 252 by using program data described in the CRAM 251.

  The CRAM error detection unit 203 detects a soft error in the CRAM 251 and outputs a CRAM ERR signal to the card failure determination unit 206 when a soft error is detected.

  The CRAM timer unit 204 counts a predetermined time when the CRAM error detection unit 203 detects a soft error in the CRAM 251. For example, when the time of 2s is set, the CRAM timer unit 204 starts counting after the CRAM error detection unit 203 detects the soft error of the CRAM 251. The data is output to the determination unit 206. The CRAM timer unit 204 stops counting when the counting for a predetermined time is completed. In addition, the timer time is set to be longer than the maximum time assumed in the network configuration. For example, considering the delay time on the network configuration, the alarm detection time of the device, the alarm transfer processing time, etc., from the time when the occurrence of the soft error is detected and the timer is started until the RDI returns from the opposite device and is detected Is the maximum time.

  The RDI detection unit 205 detects RDI transmitted from the communication destination, and outputs an RDI signal to the card failure determination unit 206 when RDI is detected.

  Based on the CRAM ERR signal from the CRAM error detection unit 203, the CTR signal from the CRAM timer unit 204, and the RDI signal from the RDI detection unit 205, the card failure determination unit 206 determines whether or not the card failure is caused by a soft error. judge. If the card failure determination unit 206 recognizes that Card # 0 is a card failure, the card failure determination unit 206 transmits a device alarm indicating the occurrence of the card failure to another node or a network monitoring device (not shown). Further, when there is a redundant circuit, the card failure determination unit 206 switches to another circuit and rescues the signal. Here, the card failure determination unit 206 performs signal relief on a path basis.

  In this way, Card # 0 can recognize that the card is in a card failure state due to a soft error.

  FIG. 7 shows a processing example until a card failure is detected in the present embodiment. Note that FIG. 7 illustrates processing performed between the Node 101A and the Node 101E described in FIG. 5, and the horizontal axis indicates time.

  In FIG. 7, Node 101A and Node 101E operate normally until timing T1. Here, the processing will be described when Card # 0 of Node 101A causes a soft error. However, Card # 1 operates similarly.

  At timing T1, the CRAM error detection unit 203 of Card # 0 shown in FIG. 6 detects a soft error (CRAM ERR) of the CRAM 251 and outputs a CRAM ERR signal to the card failure determination unit 206. Then, the CRAM error detection unit 203 activates the CRAM timer unit 204. The CRAM timer unit 204 starts counting a preset time, and outputs a CTR signal indicating that the timer is being counted to the card failure determination unit 206.

  On the other hand, when a signal error occurs due to the soft error of Node 101A, Node 101B or Card-N of Node 101A detects the signal error and transmits the AIS to the downstream side. Then, the AIS is received at the Node 101E via the Node 101C and the Node 101D after the time t1 from the timing T1. When the Node 101E detects the AIS, the Node 101E transfers the RDI to the Node 101A.

  The RDI transmitted from the Node 101E is received by the Node 101A after the time t2 via the Node 101D, Node 101C, and Node 101B. Then, the RDI detection unit 205 of the Node 101A detects the RDI transmitted from the Node 101E and outputs an RDI signal to the card failure determination unit 206.

  The card failure determination unit 206 of the Node 101A determines whether or not the CRAM error detection unit 203 detects CRAM ERR and the RDI detection unit 205 detects RDI within the timer time of the CRAM timer unit 204 (failure determination condition) ). The card failure determination unit 206 determines that Card # 0 is a card failure (FLT) when the failure determination condition is satisfied. If the failure determination condition is not satisfied, the card failure determination unit 206 determines that a CRAM ERR has occurred but that a fatal signal error has not occurred.

  FIG. 8 shows an example of a processing procedure in Card # 0.

  In step S101, the CRAM error detection unit 203 determines whether or not a CRAM error is detected. If the CRAM error is detected, the process proceeds to step S102. If no CRAM error is detected, the process waits in step S101.

  In step S102, when the CRAM error detection unit 203 detects a CRAM error, the CRAM timer unit 204 starts a timer and starts counting a preset time.

  In step S103, the card failure determination unit 206 determines whether or not the RDI detection unit 205 detects RDI before the occurrence of the CRAM error. If RDI is detected, the process proceeds to step S107, and no RDI detection is detected. In this case, the process proceeds to step S104.

  In step S104, the card failure determination unit 206 determines whether or not the RDI detection unit 205 has detected RDI after the occurrence of a CRAM error. If RDI is detected, the process proceeds to step S105, and if RDI is not detected. Proceed to step S107.

  In step S105, the card failure determination unit 206 determines whether or not the RDI detection is within the timer time of the CRAM timer unit 204. If it is within the timer time, the process proceeds to step S106. The process proceeds to S107.

  In step S106, the card failure determination unit 206 determines that a card failure has occurred in Card # 0. Then, the card failure determination unit 206 transmits a device alarm (failure notification) indicating the occurrence of a card failure to another Node or a monitoring device. Alternatively, if there is a redundant circuit, the card failure determination unit 206 switches to another circuit and relieves the signal.

  In step S107, the card failure determination unit 206 determines that no card failure has occurred in Card # 0. That is, although a CRAM error is detected in Card # 0, it is not a CRAM error in which a signal error continuously occurs, so Card # 0 continues communication without notifying a card failure.

In this manner, the Node 101A according to the present embodiment can detect a device failure without increasing the number of failures even when a soft error occurs in the CRAM, and can identify a failure location.
[When CRAM has error correction function]
FIG. 9 shows an example in which an error occurring in the CRAM is recovered by error correction. FIG. 9 corresponds to FIG. 7, and the horizontal axis indicates time.

  At timing T1, the CRAM error detection unit 203 of Card # 0 shown in FIG. 6 detects a soft error (CRAM ERR) of the CRAM 251 and outputs a CRAM ERR signal to the card failure determination unit 206. Then, the CRAM error detection unit 203 activates the CRAM timer unit 204. The CRAM timer unit 204 starts counting a preset time, and outputs a CTR signal indicating that the timer is being counted to the card failure determination unit 206.

  The operation so far is the same as in FIG. 7, but in the example of FIG. 9, the soft error is recovered by the error correction function of the CRAM and the signal error is also recovered at the timing T2. And AIS which Card-N of Node101B or Node101A transmits is also complete | finished at the timing T2, and returns to a normal state.

  On the other hand, the AIS is received by the Node 101E after the time t1 from the timing T1 via the Node 101B, Node 101C, and Node 101D. When the Node 101E detects the AIS, the Node 101E transfers the RDI to the Node 101A. However, since the AIS ends at the timing T2 and returns to the normal state, the AIS also returns to the normal state at the Node 101E after the time t1 from the timing T2. By returning the AIS to the normal state at the Node 101E, the Node 101E ends the RDI transferred to the Node 101A and returns to the normal state.

  The Node 101A receives the RDI after time t2 from the transmission of the RDI from the Node 101E. However, since it has been recovered by the error correction function of the CRAM, the Node 101A returns to a normal state within the timer time of the CRAM timer unit 204. For this reason, the card failure determination unit 206 of the Node 101A once recognizes the card failure, but does not determine that there is a card failure because the RDI is recovered within the timer time.

  As described above, even if the Node 101A according to the present embodiment once detects a CRAM error, if the RDI received from the communication destination Node 101E recovers within the timer time, the Node 101A continues the communication without determining that the card has failed. Can do. As a result, in the Node 101A according to the present embodiment, even when a soft error occurs in the CRAM, if the soft error is recovered by the error correction function, it is not determined that the card is faulty.

  FIG. 10 shows an example in which an error occurring in the CRAM is recovered by error correction, but a signal error continues. FIG. 10 is a diagram corresponding to FIG. 9, and the horizontal axis indicates time.

  At timing T1, the CRAM error detection unit 203 of Card # 0 shown in FIG. 6 detects a soft error (CRAM ERR) of the CRAM 251 and outputs a CRAM ERR signal to the card failure determination unit 206. Then, the CRAM error detection unit 203 activates the CRAM timer unit 204. The CRAM timer unit 204 starts counting a preset time, and outputs a CTR signal indicating that the timer is being counted to the card failure determination unit 206. Here, when a signal error occurs due to a soft error, the signal error is detected in the interface circuit in the subsequent stage or another node, and the AIS is transmitted downstream.

  At timing T2, the soft error is recovered by the error correction function of the CRAM.

  The operation so far is the same as in the case of FIG. However, in the case of FIG. 10, the soft error is recovered, but the internal circuit of the main signal processing unit 252 cannot be recovered from the abnormality, and for example, the signal disconnection continues. For example, the soft error is recovered by error correction of the CRAM, but the error of the main signal is not recovered even if the soft error is recovered when the statistical processing or the variable at the time of the error is used in the subsequent processing There is. The example shown in FIG. 10 shows a case where the error of the main signal is not recovered even when the soft error is recovered, and the AIS is continuously transmitted to the Node 101E.

  The subsequent operations are performed in the same manner as in FIG. 7, and the AIS is received at the Node 101E, for example, after the time t1 from the timing T1, and the Node 101E transfers the RDI to the Node 101A side. Then, the Node 101A detects the RDI transferred from the Node 101E, and the card failure determination unit 206 satisfies the failure determination condition described with reference to FIG. 7, so Card # 0 is in a failure state (card failure). Is determined.

In this way, the Node 101A according to the present embodiment can determine that the card has failed if the signal error is not recovered even when the CRAM error is recovered.
[Example of signal relief by redundant circuit]
FIG. 11 shows an example of relieving a signal when the user side interface circuit is made redundant. FIG. 11 corresponds to FIG.

  In FIG. 11, Card # 0 of Node 101A detects a CRAM soft error, starts a timer, and assumes that RDI continues until the timer expires after receiving RDI from Node 101E within the timer time. Therefore, the Node 101A can recognize that a signal error has occurred due to a card failure of its own Node, as described with reference to FIG. And since Card # 0 has failed, Node101A switches an interface circuit from Card # 0 to Card # 1 by SWF.

  In this way, the Node 101A in the example of FIG. 11 can relieve the signal by detecting the card failure of its own Node and switching to the redundant circuit.

  FIG. 12 shows a processing example until a card failure is detected in the present embodiment. Note that FIG. 12 illustrates processing performed between the Node 101A and the Node 101E described in FIG. FIG. 12 is the same diagram as FIG. 7, and the horizontal axis indicates time.

  In FIG. 12, Node 101A and Node 101E operate normally until timing T1.

  At timing T1, as described with reference to FIG. 7, the CRAM error detection unit 203 of the Node 101A detects a soft error (CRAM ERR) of the CRAM 251. Then, the CRAM error detection unit 203 activates the CRAM timer unit 204. Here, when a signal error occurs due to a soft error, the signal error is detected in the interface circuit in the subsequent stage or another node, and the AIS is transmitted downstream.

  On the other hand, the AIS is received by the Node 101E 10 ms after the timing T1. The Node 101E transfers the RDI to the Node 101A 1 ms after detecting the AIS.

  The RDI transmitted from the Node 101E is received by the Node 101A after 10 ms via the Node 101D, Node 101C, and Node 101B, and detected by the RDI detection unit 205.

  The card failure determination unit 206 of the Node 101A determines whether or not the CRAM error detection unit 203 detects CRAM ERR and the RDI detection unit 205 detects RDI within the timer time of the CRAM timer unit 204 (failure determination condition) ). Then, the card failure determination unit 206 determines that Card # 0 is a card failure (FLT) when the failure determination condition is satisfied. If the failure determination condition is not satisfied, the card failure determination unit 206 determines that a Card # 0 soft error has occurred, but that a fatal signal error has not occurred. In FIG. 12, as an example performed in the 100 ms polling process, the card failure determination unit 206 of the Node 101A outputs a determination result 100 ms after the reception of the RDI. However, in the case of interrupt processing or the like, the time from reception of RDI to determination result can be made shorter than 100 ms.

Here, when the time from the timing T1 until it is determined to be a card failure is within the timer time, the card failure determination unit 206 determines that the card is defective. In the example of FIG. 12, the sum of the time of 10 ms until the AIS reaches the Node 101E and the time of 1 ms from when the Node 101E receives the AIS until the RDI is transferred is 11 ms. A total of 10 ms until the RDI arrives from the Node 101E to the Node 101A and a processing time of 100 ms until the card failure determination unit 206 determines that a card failure is 110 ms. Accordingly, the total time from the timing T1 until the card failure determination unit 206 determines that there is a card failure is 121 ms, which is less than 2 seconds of the timer time, so the card failure determination unit 206 recognizes that there is a card failure. Then, Node 101A recognizes that the card has failed at timing T3, switches from Card # 0 to Card # 1 of the redundant circuit, recovers the signal, and recovers from the signal error.
[Example of application to a ring network]
FIG. 13 shows an application example to a ring network. In FIG. 13, the interface circuit on the user side of the Node 101A ′ is made redundant to Card # 0 and Card # 1, similarly to the Node 101A shown in FIG. Further, unlike the Node 101A shown in FIG. 5, the interface circuit on the network side of the Node 101A ′ is made redundant to Card (E) and Card (W). The SWF switches signals between Card # 0 and Card # 1, and Card (E) and Card (W). Here, (E) at the end of the sign of Card (E) and Card (W) indicates a path around East, and (W) indicates a path around West.

  In FIG. 13, Card (E) on the East side of Node 101A ′ performs communication with Node 101E ′ via Node 101B, Node 101C, and Node 101D. On the other hand, Card (W) on the West side of Node 101A ′ communicates with Node 101A ′ via Node 101G and Node 101F. Card # 0 has a selection circuit SEL (0) for selecting a signal received by Card (E) or Card (W), and outputs the signal selected by SEL (0) to the user side. Similarly, Card # 1 has a selection circuit SEL (1) for selecting a signal received by Card (E) or Card (W), and outputs the signal selected by SEL (1) to the user side. . Further, the SWF of the Node 101A ′ has a selection circuit SEL (2) for selecting a signal input from the user side by Card # 0 or Card # 1, and the signal selected by SEL (2) is Card (E). And Card (W). Note that the configuration of the Node 101E ′ illustrated in FIG. 13 is the same as that of the Node 101A ′.

  In this way, since the Node 101A 'and the Node 101E' are connected by the ring network, communication can be performed through two paths.

  FIG. 14 shows an example of the signal flow when the Node 101A 'is in soft error. FIG. 14 corresponds to FIG. 12, and shows a case where Card # 0 of Node 101A 'detects a CRAM soft error. In FIG. 14, Card # 0 is the active system, Card # 1 is the standby system, the solid line arrows indicate the flow of the active system signals, and the dotted line arrows indicate the flow of the standby system signals.

  Here, Card # 0 of Node 101A 'has the same basic configuration as Card # 0 of Node 101A described in FIG. In the portion where Card # 0 of Node 101A ′ is different from Card # 0 of Node 101A, a selection circuit SEL (0) for selecting a signal received from the East side and West side paths is provided in the main signal processing unit 252. That is. Further, the RDI detection is performed by the RDI detection unit 205 shown in FIG. 6 on both the East side and the West side. Further, the card failure determination unit 206 determines that a card failure has occurred when the RDI detection unit 205 detects RDI received from both the East side and the West side. If the card failure determination unit 206 does not receive an RDI from any one of the paths within the timer time, the card failure determination unit 206 determines that a soft error has occurred but no fatal signal error has occurred, and that the card failure has not occurred. To do. Card # 1 also has the same blocks as Card # 0. Also, the Node 101E 'has the same block as the Node 101A'.

  In FIG. 14, a soft error occurs at Card # 0 of Node 101A '. Here, when a signal error occurs due to a soft error, the signal error is detected in the interface circuit in the subsequent stage or another node, and the AIS is transmitted downstream. For example, the Node 101B and the Node 101G detect the signal error of the Node 101A ′ and transmit the AIS to the downstream side. Alternatively, Card (E) and Card (W) of Node 101 A ′ may detect a signal error and transmit an AIS. Then, the Node 101E ′ detects the AIS and transfers the RDI to the Node 101A ′. Here, in this embodiment, since the ring network is used, the RDI transferred by the Node 101E 'is transmitted to the East side and the West side via the SEL (2) of the SWF of the Node 101E'.

  The RDI transmitted from Card (E) of Node 101E 'to the East side is transmitted to Node 101A' via Node 101D, Node 101C, and Node 101B. On the other hand, the RDI transmitted from Card (W) of Node 101E ′ to the West side is transmitted to Node 101A ′ via Node 101F and Node 101G.

  Two RDIs, an RDI received from the East side by Card (E) of the Node 101A 'and an RDI received from the West side by Card (W), are input to Card # 0 (SEL (0)) of the Node 101A'. Then, the signal selected by SEL (0) is output to the user side. Here, Card # 0 of Node 101A 'can detect RDI received from both the East side and the West side.

  In this embodiment, Card # 0 of Node 101A ′ has a card failure when Card # 0 receives RDI from both the East side and the West side within a preset time after detecting a soft error. Is determined.

  Here, in the example of FIG. 14, the case of the ring network has been described. However, when there are a plurality of routes to which RDI is transferred, it is applicable as in the case of FIG. 14, and all of the plurality of RDIs are detected. Is determined to be a card failure. In this way, by detecting a card failure by receiving a plurality of RDIs, erroneous detection of a card failure can be prevented.

  FIG. 15 shows a processing example until a card failure is detected in the present embodiment. FIG. 15 is a diagram similar to FIG. 7, and the horizontal axis represents time. In addition, the time chart illustrated in FIG. 15 illustrates processing performed by the Node 101A ′ and the Node 101E ′ illustrated in FIG. In FIG. 15, the Node 101A 'operates normally until timing T1.

  At timing T1, the CRAM error detection unit 203 of Card # 0 shown in FIG. 14 detects a soft error (CRAM ERR) of the CRAM 251 and outputs a CRAM ERR signal to the card failure determination unit 206. Then, the CRAM error detection unit 203 activates the CRAM timer unit 204. The CRAM timer unit 204 starts counting a preset time, and outputs a CTR signal indicating that the timer is being counted to the card failure determination unit 206. Here, when a signal error occurs due to a soft error, the signal error is detected in the interface circuit in the subsequent stage or another node, and the AIS is transmitted downstream.

  On the other hand, the AIS is received by the Node 101E ′ after 10 ms from the timing T1 via the Node 101C and the Node 101D. The Node 101E 'transfers the RDI to the Node 101A' 1 ms after detecting the AIS. Here, in this embodiment, since the ring network is used, the RDI is transmitted to both paths of the East-side Node 101D and the West-side Node 101F. Then, the RDI transmitted to the East side path is received by Card # 0 of Node 101A ′ 10 ms after transmitting RDI via Node 101D, Node 101C, and Node 101B. On the other hand, the RDI transmitted to the West side path is received by Card # 0 of Node 101A ′ after 12 ms from the transmission of RDI via Node 101F and Node 101G. In the Node 101A ′, RDI received from both the East side and the West side is detected before being input to the selection circuit SEL (0) of Card # 0. Then, the card failure determination unit 206 of the Node 101A ′ determines whether or not the CRAM error detection unit 203 detects CRAM ERR and the RDI detection unit 205 detects both RDIs within the timer time of the CRAM timer unit 204. Yes (failure judgment condition). Then, the card failure determination unit 206 determines that Card # 0 of the Node 101A 'is a card failure (FLT) when the failure determination condition is satisfied. Note that the card failure determination unit 206 of the Node 101A 'performs the polling process in the same manner as in the example of FIG. 12, and therefore outputs a determination result 100 ms after the reception of the later RDI (the route on the West side in FIG. 12).

Here, as in the example of FIG. 12, when the time from the timing T1 until it is determined to be a card failure is within the timer time, it is determined that a card failure has occurred. In the example of FIG. 15, the total of 10 ms from the soft error of Node 101A ′ until the AIS arrives at Node 101E ′ and the 1 ms from when Node 101E ′ receives the AIS to when the RDI is transferred is 11 ms. . Then, the total of 12 ms for the RDI to reach Node 101A ′ from the Node 101E ′ to the West side route and the processing time of 100 ms for the card failure determination unit 206 to determine that the card has failed is 112 ms. Therefore, in the example of FIG. 15, the total time from the timing T1 until the card failure determination unit 206 determines that there is a card failure is 123 ms, which satisfies the condition of less than 2 seconds of the timer time. Recognize Card # 0 card failure.
[Example of signal recovery by redundant circuit in ring network]
FIG. 16 shows an example in which a signal is relieved by a redundant circuit in a ring network. Note that Node 101A ′ and Node 101E ′ illustrated in FIG. 16 correspond to Node 101A ′ and Node 101E ′ described in FIGS. 14 and 15, respectively.

  In FIG. 16, as described with reference to FIGS. 14 and 15, Card # 0 of Node 101 </ b> A ′ detects a CRAM soft error and generates a signal error. Then, a signal error is detected in the interface circuit in the subsequent stage or another node, and the AIS is transmitted to the node 101E ′ side. The Node 101E 'receives the AIS and transmits the RDI to the Node 101A', and the Node 101A 'recognizes that a signal error has occurred due to a card failure when the RDI is received within the timer time. The SWF of the Node 101A recovers from the signal error by switching to the redundant Card # 1 because Card # 0 has failed.

  In this way, the Node 101A can relieve the signal by detecting the card failure of its own Node and switching to the redundant circuit.

  As described above, as described in each embodiment, the transmission apparatus and the failure detection method according to this embodiment detect only failures that affect communication without increasing the circuit scale, and autonomously install a failure card. It becomes possible to specify. Further, the specified failure card is notified to the monitoring device and other devices as an alarm, and the signal can be immediately relieved by switching the redundant card, thereby improving the reliability of the network.

  In the transmission apparatus and the failure detection method according to the present embodiment, the type of signal to be accommodated is not limited to a TDM signal or a packet signal, for example, an RDI-equivalent failure detection signal for notifying an opposite apparatus of an error state of a received signal, The present invention can be applied to a device having an alarm signal transfer function.

  In the above-described embodiment, the case where the network is linear or ring has been described. However, the present invention can also be applied to apparatuses used in various networks such as point-to-point.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Also, any improvement and modification should be readily conceivable by those having ordinary knowledge in the art. Therefore, there is no intention to limit the scope of the inventive embodiments to those described above, and appropriate modifications and equivalents included in the scope disclosed in the embodiments can be used.

101A, 101B, 101C, 101D, 101E, 101F, 101G, 901, 902, 903, 904, 951A, 951B, 951C, 951D, 951E ... Node; 201 ... optical modulation / demodulation unit; 202 ... programmable device 203 ... CRAM error detection unit; 204 ... CRAM timer unit; 205 ... RDI detection unit; 206 ... Card failure determination unit; 251 ... CRAM; 252 ... Main signal processing unit; Card # 0, Card # 1, Card-N, Card (E), Card (W)... Interface circuit; SWF... Switch; 900.

Claims (10)

A programmable device that configures a circuit with program data stored in advance in a memory;
An error detection unit for detecting a soft error in the memory;
A timer for counting a preset time when the soft error is detected;
A failure notification detection unit for detecting a failure notification signal transmitted from the transmission apparatus of the communication destination;
After the error detection unit detects a soft error, the failure notification detection unit determines that the circuit has failed if the failure notification detection unit detects the failure notification signal before the time counting unit finishes counting a preset time. A determination unit;
A transmission apparatus comprising: The transmission apparatus according to claim 1,
The determination unit determines that the circuit has failed when the failure notification detection unit continuously detects the failure notification signal until the preset time is counted. Transmission equipment. The transmission apparatus according to claim 1 or 2,
When there are a plurality of routes between the communication destination transmission devices,
The failure notification detection unit detects a plurality of failure notification signals received from the plurality of paths,
The determination unit determines that the circuit has failed when the failure notification detection unit detects a plurality of failure notification signals. In the transmission apparatus as described in any one of Claims 1-3,
A plurality of user interface boards, a network interface board, and a switch board for switching signals transmitted and received by the user interface board and the network interface board,
For each of the plurality of user interface boards, the memory, the programmable device, the error detection unit, the timing unit, the failure notification detection unit, and the determination unit, and for each user interface board A transmission apparatus characterized by determining a failure. The transmission apparatus according to claim 4, wherein
In the switch panel, when the determination unit determines that any one of the user interface boards among the plurality of user interface boards has failed, the switch board includes the failed user interface board and the other user interface board. A transmission device characterized by switching the path of the main signal. A failure detection method for a transmission apparatus having a programmable device that configures a circuit with program data stored in advance in a memory,
When counting a preset time at the time of detection of the soft error in the memory, and when the failure notification signal transmitted from the transmission apparatus of the communication destination is detected before the preset time is counted, A fault detection method characterized by judging that a circuit has failed. The failure detection method according to claim 6,
A failure detection method comprising: determining that the circuit has failed when the failure notification signal is continuously detected until the preset time is counted. In the failure detection method according to claim 6 or 7,
When there are a plurality of paths between the communication destination transmission apparatus and the plurality of fault notification signals received from the plurality of paths, it is determined that the circuit has failed. Method. In the failure detection method according to any one of claims 6 to 8,
The transmission device includes a plurality of user interface boards, a network interface board, and a switch board for switching signals transmitted and received by the user interface board and the network interface board,
A failure detection method, comprising: the memory and the programmable device for each of the plurality of user interface boards; and determining a failure for each of the user interface boards. In the failure detection method according to claim 9,
When it is determined that one of the plurality of user interface boards has failed, the transmission device transmits a main signal from the user interface board having the failed circuit to another user interface board. A fault detection method characterized by switching routes.

Images