JP6113527B2 - DC / DC converter and control circuit thereof, power supply using the same, power adapter, and electronic device - Google Patents

Description

  The present invention relates to a DC / DC converter.

  Various home appliances such as TVs and refrigerators operate by receiving commercial AC power from the outside. Electronic devices such as laptop computers, mobile phone terminals, and PDAs (Personal Digital Assistants) can also be operated with commercial AC power, or the built-in battery can be charged with commercial AC power. . Such home appliances and electronic devices (hereinafter collectively referred to as electronic devices) have built-in power supply devices (also called inverters or AC / DC converters) that convert commercial AC voltages into AC / DC (AC / DC converters), or inverters. Is built into a power adapter (AC adapter) external to the electronic device.

  FIG. 1 is a block diagram showing a basic configuration of an inverter. The inverter 100r mainly includes a fuse 102, an input capacitor Ci, a filter 104, a diode rectifier circuit 106, a smoothing capacitor Cs, and a DC / DC converter 110r.

Commercial AC voltage _{V AC} is input to the filter 104 through a fuse 102 and the input capacitor Ci. Filter 104 removes the commercial AC voltage _{V AC} noise. Diode rectifier 106 is a diode bridge circuit for full-wave rectifying the commercial AC voltage V _AC. The output voltage of the diode rectifier circuit 106 is smoothed by the smoothing capacitor Cs and converted into the DC voltage _VIN .

The isolated DC / DC converter (flyback converter) 110r receives the direct-current voltage _VIN at the input terminal P1, reduces its voltage, and connects the output voltage _VOUT stabilized at the target value to the output terminal P2. Supplied to a load (not shown).

The DC / DC converter 110r includes a control circuit 2r, a switching transistor M1, an output circuit 200, and a feedback circuit 210. The output circuit 200 includes a transformer T1, a first diode D1, a first output capacitor Co1, a detection resistor R _S , a first diode D1, and a second output capacitor Co2. Since the topology of the output circuit 200 is general, the description thereof is omitted.

When the switching transistor M1 is switched, the input voltage _VIN is stepped down and an output voltage _VOUT is generated. The control circuit 2r stabilizes the output voltage _VOUT to the target value by adjusting the switching duty ratio of the switching transistor M1, and controls the coil current Ip flowing through the primary winding W1 of the transformer T1.

The detection resistor _RS is provided in series with the primary winding W1 of the transformer T1 and the switching transistor M1. Sense resistor is _{R S,} a voltage drop proportional to the current Ip flowing through the primary winding W1 and the switching transistor M1 (the detection _{voltage) V CS} is generated. Control circuit 2r on the basis of the detection voltage _{V CS,} and controls the current Ip flowing through the primary winding W1.

The feedback circuit 210 generates a feedback voltage V _FB corresponding to the output voltage _VOUT and supplies it to the feedback terminal (FB terminal) of the control circuit 2r. The feedback circuit 210 includes a shunt regulator 212 and a photocoupler 214. The shunt regulator 212 generates a feedback signal S11 whose level is adjusted so that an error between the output voltage _VOUT and a predetermined target value becomes zero, and supplies the feedback signal S11 to the light emitting diode of the photocoupler 214. The phototransistor (or phototransistor) of the photocoupler 214 converts the optical signal S12 from the light emitting diode into a feedback voltage _VFB corresponding to the feedback signal S11.

In addition to the primary winding W1, an auxiliary winding W3 is provided on the primary side of the transformer T1. The auxiliary winding W3, the second diode D2, and the second output capacitor Co2 form a second DC / DC converter. In response to switching of the switching transistor M1, a DC voltage _VCC is generated in the second output capacitor Co2. DC voltage _{V CC} is supplied to the control circuit 2r of the power supply terminal VCC (VCC terminal).

The control circuit 2r includes a pulse modulator. The control circuit 2r generates a pulse signal (switching output) _SOUT that repeats an on level corresponding to the on state of the switching transistor M1 and an off level corresponding to the off state of the switching transistor M1. The control circuit 2r supplies the switching output _{S OUT} to the gate of the switching transistor M1. By adjusting the duty ratio of the switching output S _OUT , the output voltage V _OUT is stabilized at the target value.

The control circuit 2r in FIG. 1 includes a current mode modulator (not shown). FIG. 2 is a circuit diagram showing the configuration of the control circuit 2r examined by the present inventors. The control circuit 2r includes a pulse modulator 10, a driver 20, a blanking circuit 40, a burst control circuit 50, and a voltage dividing circuit 80. The voltage dividing circuit 80 divides the feedback voltage _VFB at a predetermined voltage dividing ratio (for example, 1/4 times). This voltage division ratio is determined so that sufficient power can be supplied to the load in a heavy load state.

Blanking circuit 40 is provided to remove noise from the detection voltage V _CS. More specifically, the detection signal _VCS is masked for a predetermined blank period immediately after the switching transistor M1 is turned on. The blanking circuit 40 may be omitted.

The pulse modulator 10 generates a pulse signal S _PWM based on the detection voltage V _CS ′ passed through the blanking circuit 40 and the feedback voltage V _FB ′ divided by the voltage dividing circuit 80. The pulse modulator 10 includes an oscillator 12, a comparator 14, and an RS flip-flop 16. The oscillator 12 generates a set signal S _SET that is asserted (for example, at a high level) at a predetermined period, and inputs the set signal S _SET to the set terminal (S) of the RS flip-flop 16. The comparator 14 asserts the reset signal S _RESET (high level) when the detection voltage V _CS ′ reaches the lower one of the feedback voltage V _FB ′ and the predetermined upper limit voltage V _LIM1 during the ON period of the switching transistor M1. , Output to the reset terminal (R) of the flip-flop 16. The pulse signal S _PWM, which is the output of the RS flip-flop 16, is turned off each time the set signal S _SET is asserted, and is turned off when the reset signal S _RESET is asserted. Transition to.

The driver 20 switches the switching transistor M1 based on the pulse signal _SPWM .

  When a microcomputer or the like is connected as a load to the output terminal P2 of the DC / DC converter 110r, when the microcomputer transitions to a standby state (sleep state), the output current of the DC / DC converter 110r becomes very small (light load state). .

  In the light load state, the DC / DC converter 110 operates the switching transistor M1 intermittently (burst operation) in order to reduce power consumption and increase efficiency. Specifically, a switching period in which the switching transistor M1 performs a switching operation and a stop period in which the switching transistor M1 maintains an off state are alternately repeated.

  The DC / DC converter 110r operates in a burst mode (intermittent mode) at light loads. The burst control circuit 50 is provided for detecting a light load state of the DC / DC converter 110 and controlling the burst operation.

FIG. 3 is a diagram for explaining the operation in the burst mode. A light load state is reached at time t0. In a light load state, the output voltage _VOUT increases and the feedback voltage _VFB decreases. Burst control circuit 50 includes a comparator that compares feedback voltage V _FB with a predetermined burst threshold value V _BURST .

When feedback voltage V _FB becomes lower than burst threshold value V _{BURST at} time t1, burst control circuit 50 negates burst control signal S _BURST (for example, low level). While the burst control signal S _BURST is negated, the pulse modulator 10 fixes the pulse signal S _PWM to an off level and stops switching of the switching transistor M1.

When charging to the output capacitor Co1 is stopped due to the stop of switching, the output voltage _VOUT gradually decreases due to the discharge due to the load current. As the output voltage _VOUT decreases, the feedback voltage _VFB increases with time. The feedback voltage V _FB varies with a delay with respect to the output voltage _VOUT , and the amount of the delay depends on the time constant of the feedback loop.

When feedback voltage V _FB exceeds threshold voltage V _BURST at time t2, burst control circuit 50 asserts burst control signal S _BURST (for example, high level). When the burst control signal S _BURST is asserted, the switching of the switching transistor M1 is resumed. As the output voltage V _OUT increases with switching, the feedback voltage V _FB starts to decrease. When the feedback voltage V _FB becomes lower than the threshold voltage V _{BURST at} time t3, switching stops.

JP 2003-164145 A

  As a result of studying the DC / DC converter 110r, the present inventor has recognized the following problems.

In this DC / DC converter 110r, the burst frequency during burst operation (and the inverse burst period) is determined according to the capacitance value of the output capacitor Co1, the inductance of the inductor L1, etc., and further, the magnitude of the load current, It fluctuates according to the input voltage _VIN .

  When the burst frequency is increased, the frequency of switching is increased, so that the switching loss of the DC / DC converter 110r in a light load state is increased and the efficiency is deteriorated. Further, when the burst frequency becomes high and enters the audible band, there is a possibility that sound is generated in the transformer T1.

  In the conventional DC / DC converter 110r, it is necessary to take measures such as increasing the capacitance value of the output capacitor Co1 in order to reduce the fluctuation range of the burst frequency. However, a large-capacitance capacitor has a problem of high cost.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and one of exemplary objects of an embodiment thereof is to provide a DC / DC converter capable of controlling a burst frequency range and a control circuit thereof.

  One embodiment of the present invention relates to a control circuit for a DC / DC converter. The DC / DC converter includes a transformer having a primary winding and a secondary winding, and a switching transistor provided on a current path of the primary winding of the transformer. The control circuit receives a feedback voltage corresponding to the output voltage of the DC / DC converter, and generates a pulse signal that is pulse-modulated so that the output voltage of the DC / DC converter approaches the target value based on at least the feedback voltage. A burst that generates a burst control signal that is asserted in a switching period in which the switching transistor should be switched and negated in a stop period in which switching of the switching transistor should be stopped, and a driver that drives the switching transistor based on the pulse signal A control circuit. The burst control circuit compares the feedback voltage with a predetermined threshold voltage and generates a comparison signal that is asserted when the feedback voltage is higher than the threshold voltage and negated when the feedback voltage is lower than the threshold voltage. A comparator and a maximum frequency setting circuit for generating a mask signal that starts time measurement triggered by the assertion of the comparison signal, is negated from the start to the elapse of a predetermined time, and is asserted after the elapse of time, and (i) the comparison signal And (ii) a logic unit that asserts the burst control signal when the mask signal is asserted and the comparison signal is asserted.

  According to this aspect, if the assertion of the comparison signal is asserted while the mask signal is negated, the assertion is invalidated. Thereafter, when the mask signal is asserted, the burst control signal is asserted. As a result, since the burst period is limited so as not to be shorter than a predetermined time, the burst frequency range can be controlled.

  The maximum frequency setting circuit generates a timer signal that is asserted after a lapse of a predetermined time from the start of time measurement, and when the timer signal is asserted, the mask signal is asserted and the burst control signal is asserted. And a timer control unit that causes the timer circuit to start measuring time.

  The predetermined time may be settable. Thereby, the upper limit value of the burst frequency can be set arbitrarily.

  The timer circuit compares the voltage of the timer capacitor with a predetermined threshold voltage by comparing the voltage of the timer capacitor having a fixed potential at one end, a current source for charging the timer capacitor, and the voltage of the timer capacitor with a predetermined threshold voltage. A timer comparator that asserts a timer signal when the voltage becomes higher than the value voltage and a discharge switch provided in parallel with the timer capacitor may be included. The timer control unit may assert the mask signal when the timer signal is asserted, and may turn off the discharge switch and negate the mask signal when the burst control signal is asserted.

  The timer capacitor may be externally attached to a semiconductor chip on which the control circuit is integrated. Thus, the upper limit value of the burst frequency can be set according to the capacitance value of the timer capacitor.

  The timer circuit may include a counter that counts the clock signal and asserts the timer signal when the count value reaches a predetermined value.

  The logic unit includes an AND gate that generates a logical product of the comparison signal and the mask signal, an RS flip-flop that is set according to the output of the AND gate, is reset according to the inverted signal of the comparison signal, and outputs a burst control signal. , May be included.

  The DC / DC converter may further include a detection resistor provided on the path of the switching transistor. The pulse modulator includes a reset signal generation unit that generates a reset signal that is asserted when a detection voltage corresponding to a voltage drop of the detection resistor reaches a feedback voltage, a set signal generation unit that generates a set signal, and the set signal is asserted. And a flip-flop that generates a pulse signal that transitions to an on level corresponding to the on state of the switching transistor and that transitions to an off level corresponding to the off state of the switching transistor when the reset signal is asserted.

  The set signal generation unit may assert the set signal at a predetermined cycle.

  The set signal generation unit may assert the set signal after a predetermined off time has elapsed since the reset signal was asserted.

  The set signal generation unit may assert the set signal when the energy stored in the transformer becomes substantially zero.

  The transformer may further include an auxiliary winding provided on the primary side. The control circuit may further include an auxiliary terminal to which a voltage at one end of the auxiliary winding is input. The set signal generator (i) compares the voltage of the auxiliary terminal with a predetermined threshold voltage, generates a bottom detection signal that is asserted every time the voltage of the auxiliary terminal crosses the threshold voltage, and (ii ) The set signal may be asserted whenever the number of times the bottom detection signal is asserted reaches the count setting value.

  The transformer may further include an auxiliary winding provided on the primary side. The control circuit may further include an auxiliary terminal to which a voltage at one end of the auxiliary winding is input. The set signal generator (i) compares the voltage of the auxiliary terminal with a predetermined threshold voltage, generates a bottom detection signal that is asserted every time the voltage of the auxiliary terminal crosses the threshold voltage, and (ii ) The set signal may be asserted after a predetermined time has elapsed since the bottom detection signal was asserted.

The control circuit may be integrated on a single semiconductor substrate.
“Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the control circuit as one integrated circuit (IC), the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

  Another aspect of the present invention relates to a DC / DC converter. The DC / DC converter includes a transformer having a primary winding, a secondary winding and an auxiliary winding, a switching transistor connected to the primary winding of the transformer, and a first having an anode connected to the secondary winding. A first output capacitor having one end grounded and the other end connected to the cathode of the first diode; a second diode having an anode connected to the auxiliary winding; and one end grounded and the other end second A second output capacitor connected to the cathode of the diode; a feedback circuit for generating a feedback voltage in accordance with an output voltage generated in the first output capacitor; and any one of the above control circuits for receiving the feedback voltage and switching the switching transistor And may be provided.

  The feedback circuit is a shunt regulator that generates a feedback signal whose level is adjusted so that an error between a voltage obtained by dividing the output voltage and a predetermined target value becomes zero, and a light emitting element on the primary side is controlled by the feedback signal. The signal generated in the light receiving element on the secondary side of the photocoupler may be supplied to the control circuit as a feedback voltage.

  Another embodiment of the present invention relates to a power supply device. The power supply device includes a filter that filters commercial AC voltage, a diode rectifier circuit that full-wave rectifies the output voltage of the filter, a smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage, and a DC input voltage And the above-described DC / DC converter that supplies the voltage to the load.

  Another embodiment of the present invention relates to an electronic device. The electronic device includes a load, a filter that filters commercial AC voltage, a diode rectifier circuit that full-wave rectifies the output voltage of the filter, a smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage, The above-described DC / DC converter that steps down the DC input voltage and supplies it to the load may be provided.

  Another aspect of the present invention relates to a power adapter. The power adapter includes a filter for filtering commercial AC voltage, a diode rectifier circuit for full-wave rectification of the output voltage of the filter, a smoothing capacitor for smoothing the output voltage of the diode rectifier circuit and generating a DC input voltage, and a DC input voltage And the above-described DC / DC converter that generates a direct-current output voltage.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, the burst frequency range of the DC / DC converter can be controlled.

It is a block diagram which shows the basic composition of an inverter. It is a circuit diagram which shows the structure of the control circuit which this inventor examined. It is a figure explaining operation | movement in burst mode. It is a circuit diagram which shows the structure of the control circuit which concerns on embodiment. FIG. 5A is a time chart in the light load state of the control circuit of FIG. 4, and FIG. 5B is a time chart showing the operation of the control circuit according to the comparison technique of FIG. It is a figure which shows an AC adapter provided with an inverter. 7A and 7B are diagrams illustrating an electronic device including an inverter. It is a circuit diagram which shows the structure of the control circuit which concerns on a 2nd modification.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 4 is a circuit diagram showing a configuration of the control circuit 2 according to the embodiment. The control circuit 2 is used in the DC / DC converter 110 shown in FIG.

As shown in FIG. 1, the DC / DC converter 110 includes a control circuit 2, a switching transistor M 1, a detection resistor R _S , an output circuit 200, and a feedback circuit 210. Except for the configuration of the control circuit 2, it is the same as FIG.

Hereinafter, the configuration of the control circuit 2 will be described.
The control circuit 2 is a functional IC integrated on a single semiconductor substrate. The auxiliary circuit (ZT terminal), FB terminal, CS terminal, GND terminal, OUT terminal, VCC terminal, and VH terminal shown in FIG. In addition, it has a frequency setting terminal (FBST terminal). FIG. 4 shows only the FB terminal, the OUT terminal, the CS terminal, and the FBST terminal, and the remaining terminals are omitted.

The control circuit 2 stabilizes the DC output voltage _VOUT to the target level by adjusting the switching duty ratio of the switching transistor M1 of the DC / DC converter 110 based on at least the feedback voltage V _FB at the FB terminal. The switching transistor M1 may be integrated in the control circuit 2.

  The control circuit 2 includes a pulse modulator 10, a driver 20, a blanking circuit 40, and a burst control circuit 50.

Blanking circuit 40 is provided to remove noise from the detection voltage V _CS. More specifically, the detection signal _VCS is masked for a predetermined blank period immediately after the switching transistor M1 is turned on. The blanking circuit 40 may be omitted.

Based on the feedback voltage V _FB and the detection voltage V _CS , the pulse modulator 10 generates a pulse signal S _PWM that is pulse-modulated so that the output voltage V _OUT of the DC / DC converter 110 approaches a target value. In this embodiment, the pulse modulator 10 is a so-called peak current mode modulator.

  The configuration of the pulse modulator 10 is not particularly limited, and a known technique may be used. For example, the pulse modulator 10 includes a set signal generation unit 12, a reset signal generation unit 14, an RS flip-flop 16, and a mask circuit 18.

The reset signal generation unit 14 generates a reset signal S _RESET that is asserted when the detection voltage V _CS reaches the feedback voltage V _FB . For example the reset signal generator 14, the detection voltage _{V CS,} as compared to the lower of the feedback voltage _{V FB} and the upper limit voltage _{V LIM1,} the direction of the detection voltage _{V CS} becomes high, a reset signal _{S RESET} asserted (high level )

The set signal generation unit 12 generates a set signal S _SET . For example, the set signal generation unit 12 may include an oscillator that asserts (sets to a high level) the set signal S _SET every predetermined period.

Alternatively, the set signal generation unit 12 may assert the set signal S _SET after a predetermined off time T _{OFF has} elapsed since the reset signal S _RESET was asserted.

Alternatively, the set signal generation unit 12 may assert the set signal S _SET when the energy stored in the transformer T1 becomes substantially zero (referred to as pseudo resonance control).

In the quasi-resonance control, in one embodiment, the set signal generation unit 12 may be configured with a comparator and a counter. A voltage at one end of the auxiliary winding W3 is divided and input to the ZT terminal. The comparator compares the voltage at one end of the auxiliary winding W3 input to the ZT terminal with a predetermined threshold voltage, and asserts the bottom detection signal by the comparator every time the auxiliary terminal voltage crosses the threshold voltage. To do. The counter may assert the set signal S _SET when the number of times the bottom detection signal is asserted reaches a certain set value.

In the pseudo resonance control, in another embodiment, the set signal generation unit 12 may be configured by a comparator and a timer circuit. The comparator (i) compares the voltage at the auxiliary terminal with a predetermined threshold voltage, and generates a bottom detection signal that is asserted every time the voltage at the auxiliary terminal crosses the threshold voltage. The timer circuit (ii) asserts the set signal S _SET after a predetermined time has elapsed since the bottom detection signal was asserted.

The set signal S _SET generated by the set signal generation unit 12 is input to the set terminal (S) of the RS flip-flop 16. When the set signal S _SET is asserted, the pulse signal S _PWM that is the output of the RS flip-flop 16 transitions to an on level (high level) corresponding to the switching transistor being turned on, and when the reset signal S _RESET is asserted. A transition is made to an off level (low level) corresponding to the off state of the switching transistor.

The mask circuit 18 is provided before the RS flip-flop 16 and allows the set signal S _SET and the reset signal S _RESET to pass while a burst control signal S _BURST from the burst control circuit 50 described later is asserted (high level). . On the contrary, while the burst control signal S _BURST is negated, the mask circuit 18 invalidates the set signal S _SET and the reset signal S _RESET and fixes the output S _PWM of the RS flip-flop 16. As a result, the switching of the switching transistor M1 is stopped while the burst control signal S _BURST is negated. The configuration of the mask circuit 18 is not particularly limited.

The driver 20 drives the switching transistor M1 connected to the OUT terminal based on the pulse signal _SPWM .

The burst control circuit 50 is provided for detecting a light load state. The burst control circuit 50 asserts the burst control signal S _BURST in the switching period in which the switching transistor M1 is to be switched, and negates the burst control signal S _BURST in the stop period in which the switching of the switching transistor M1 is to be stopped.

The burst control circuit 50 includes a burst comparator 52, a maximum frequency setting circuit 54, and a logic unit 56.
The burst comparator 52 compares the feedback voltage V _FB with a predetermined threshold voltage V _BURST . When the feedback voltage V _FB becomes higher than the threshold voltage V _BURST , the burst comparator 52 asserts the comparison signal S1 and the feedback voltage V _FB When it becomes lower than the threshold voltage V _BURST , the comparison signal S1 is negated. The burst comparator 52 may be a hysteresis comparator in which the threshold voltage V _BURST changes in binary.

The maximum frequency setting circuit 54 starts time measurement triggered by the assertion of the comparison signal S1. The maximum frequency setting circuit 54 negates (for example, low level) the mask signal S2 from the start of measurement until a predetermined time τ _FMAX elapses, and asserts the mask signal S2 after the time τ _FMAX elapses.

The time τ _FMAX is preferably settable from outside the IC of the control circuit 2. The maximum frequency setting circuit 54 includes an external timer capacitor 60, a current source 62, a timer comparator 64, a discharge switch 66, and a timer control unit 68.

One end of the timer capacitor 60 is grounded, its potential is fixed, and the other end is connected to the FBST terminal of the control circuit 2. The current source 62 charges the timer capacitor 60 with the current Ic. The timer comparator 64 compares the voltage V _FBST of the timer capacitor 60 with a predetermined threshold voltage V _TIME, and when the voltage V _FBST of the timer capacitor 60 becomes higher than the threshold voltage V _TIME , the timer signal S3 is output. Assert.

The discharge switch 66 is provided in parallel with the timer capacitor 60. The timer control unit 68 turns off the discharge switch 66 when the burst control signal S _BURST is asserted. Thereby, charging of the timer capacitor 60, that is, time measurement is started, triggered by the assertion of the burst control signal _SBURST .

  Further, the timer control unit 68 turns on the discharge switch 66 when the timer signal S3 is asserted. Thus, when the time measurement is completed, the timer capacitor 60 is discharged, and the elapsed time can be reset to zero.

For example, the timer control unit 68 includes a D flip-flop 70 and inverters 71 and 72. The inverter 71 inverts the timer signal S3 and inputs the inverted timer signal S3 # to the reset terminal (inverted logic) of the D flip-flop 70. A high level voltage V _H is input to the input terminal (D) of the D flip-flop 70, and a burst control signal S _BURST is input to its clock terminal. That is, the output S4 of the D flip-flop 70 transitions to a low level whenever the timer signal S3 is asserted, and transitions to a high level whenever the burst control signal S _BURST is asserted.

The inverter 72 inverts the output S4 of the D flip-flop 70 and generates a mask signal S2. The mask signal S2 transitions to a high level each time the timer signal S3 is asserted, and transitions to a low level each time the burst control signal S _BURST is asserted. A mask signal S <b> 2 is input to the gate of the discharge switch 66. The configuration of the timer control unit 68 is not particularly limited.

The time τ _FMAX measured by the maximum frequency setting circuit 54 is given by the following equation when the capacitance value of the timer capacitor 60 is C _FBST .
τ _FMAX = C _FBST × V _TIME / Ic

Therefore, by externally attaching the timer capacitor 60 to the semiconductor chip on which the control circuit 2 is integrated, the time τ _FMAX can be set according to the capacitance value.

The logic unit 56 (i) negates the burst control signal S _BURST when the comparison signal S1 is negated. The logic unit 56 (ii) asserts the burst control signal S _BURST when the mask signal S2 is asserted and the comparison signal S1 is asserted.

The logic unit 56 includes, for example, an AND gate 74, an inverter 75, a one-shot circuit 76, and an RS flip-flop 77.
The AND gate 74 generates a set signal S5 corresponding to the logical product of the comparison signal S1 and the mask signal S2, and inputs the set signal S5 to the set terminal of the RS flip-flop 77. The inverter 75 inverts the comparison signal S1. The one-shot circuit 76 is provided for stabilizing circuit operation, extends the pulse width of the output of the inverter 75, and outputs it to the reset terminal of the RS flip-flop 77. The output of the RS flip-flop 77 is a burst control signal S _BURST .

  The above is the configuration of the control circuit 2. Next, the operation will be described. FIG. 5A is a time chart in the light load state of the control circuit 2 of FIG.

  FIG. 5A shows the operation of two cycles Tcyc1 and Tcyc2.

  The first cycle Tcyc1 will be described. The first cycle is an operation when the burst operation cycle is long (burst frequency is low).

Between times t0 and t1, the DC / DC converter 110 is in a stop period, the burst control signal S _BURST is negated, and the mask signal S2 is asserted.

When the feedback voltage V _FB exceeds the threshold voltage V _BURST at time t1, the comparison signal S1 is asserted, and the set signal S5 transitions to the high level, the burst control signal S _BURST that is the output of the RS flip-flop 77 is asserted. The As a result, a switching period starts and the output voltage _VOUT begins to rise. When a certain delay time elapses from time t1, the feedback voltage _VFB starts to decrease.

When the burst control signal S _BURST is asserted at time t1, the mask signal S2 is negated. The maximum frequency setting circuit 54 starts time measurement and asserts the mask signal S2 at time t2 when a predetermined time τ _FMAX has elapsed.

When the feedback voltage V _FB becomes lower than the threshold voltage V _{BURST at} time t3, the comparison signal S1 is negated. In response to this, the RS flip-flop 77 is reset, the burst control signal S _BURST is negated, and a stop period starts.

When the time t4 the feedback voltage _{V FB} is higher than the threshold voltage _{V BURST,} becomes again switching period.

  Next, the second cycle Tcyc2 will be described. The second cycle is an operation when the cycle of the burst operation is short (burst frequency is high).

Time measurement by the maximum frequency setting circuit 54 is started at time t4, and the mask signal S2 is asserted at time t7 after the time τ _{FMAX has} elapsed.

When the time t5 the feedback voltage _{V FB} is lower than the threshold voltage _{V BURST,} the comparison signal S1 is negated, RS flip-flop 77 is reset, the burst control signal SBURST is negated. Thereby, it becomes a stop period and switching of the switching transistor M1 stops.

When the feedback voltage V _FB becomes higher than the threshold voltage V _{BURST at} time t6, the comparison signal S1 is asserted. However, since the mask signal S2 remains negated at this time, the assertion of the comparison signal S1 is invalidated, the RS flip-flop 77 is not set, and the burst control signal S _BURST maintains the negated state.

When the mask signal S2 is asserted at time t7, the set signal S5, which is the output of the AND gate 74, is asserted, and the burst control signal S _BURST is asserted. With the above control, the burst period of the second cycle Tcyc2 becomes τ _FMAX .

The above is the operation of the control circuit 2.
The advantage of the control circuit 2 becomes clear by comparison with the control circuit according to the comparison technique of FIG.

FIG. 5B is a time chart showing the operation of the control circuit 2r according to the comparison technique of FIG. The conventional control circuit 2r does not include the maximum frequency setting circuit 54 and the logic unit 56. Therefore, when the comparison signal S1 is asserted at time t6, the burst control signal S _BURST is immediately asserted. When the burst control signal S _BURST is asserted, the feedback voltage V _FB starts to decrease thereafter, and becomes lower than the threshold voltage V _{BURST at} time t8.

  As shown in FIG. 5B, in the conventional control circuit 2r, the burst period is very short, Tcyc3 and Tcyc4, and the burst frequency is high. Thereby, the switching period of the switching transistor M1 becomes long, and the power consumption of the DC / DC converter 110r increases. Further, when the burst frequency increases and enters the audible band, a sound is generated by the transformer T1.

  The above is the operation of the conventional control circuit 2r.

Advantages of the control circuit 2 according to the embodiment will be described. According to the control circuit 2, the burst period in the light load state can be limited to the measurement time τ _FMAX or more by the maximum frequency setting circuit 54, in other words, the burst frequency can be limited to the upper limit frequency 1 / τ _FMAX or less.
Thereby, the power consumption in a light load state can be reduced, or the sound of the transformer T1 can be prevented.

Further, by configuring the measurement time τ _FMAX by the maximum frequency setting circuit 54 to be variable, the designer of the DC / DC converter 110 can arbitrarily set the upper limit value of the burst frequency. Since the upper limit of the burst frequency can be set arbitrarily, there is an advantage that the degree of freedom in designing circuit parameters including the capacitance value of the first output capacitor Co1 is increased. For example, if the capacitance value of the first output capacitor Co1 can be reduced, the cost of the DC / DC converter 110 can be reduced.

  Next, the application of the DC / DC converter 110 will be described.

  The DC / DC converter 110 can be suitably used for the inverter (power supply device) 100 shown in FIG. The inverter 100 is preferably used for a power supply block of an AC adapter or an electronic device.

FIG. 6 is a diagram illustrating an AC adapter 800 including the inverter 100. The AC adapter 800 includes a plug 802, a housing 804, and a connector 806. Plug 802 is subjected to a commercial AC voltage _{V AC} from the wall outlet (not shown). The inverter 100 is mounted in the housing 804. The DC output voltage _VOUT generated by the inverter 100 is supplied from the connector 806 to the electronic device 810. Examples of the electronic device 810 include a notebook PC, a digital camera, a digital video camera, a mobile phone, and a mobile audio player.

7A and 7B are diagrams illustrating an electronic device 900 including the inverter 100. FIG. 7A and 7B is a display device, but the type of the electronic device 900 is not particularly limited, and is a device including a power supply device such as an audio device, a refrigerator, a washing machine, or a vacuum cleaner. I just need it.
Plug 902 is subjected to a commercial AC voltage _{V AC} from the wall outlet (not shown). The inverter 100 is mounted in the housing 804. The DC output voltage V _OUT generated by the inverter 100 is supplied to loads such as a microcomputer, a DSP (Digital Signal Processor), a power supply circuit, a lighting device, an analog circuit, and a digital circuit mounted in the same housing 904. .

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
In FIG. 4, the current Ic generated by the current source 62 may be set from the outside, and the threshold voltage V _TIME may be set from the outside. These settings may be performed by a control command from an external microcomputer, or a control pin (terminal) may be provided in the control circuit 2 and changeable depending on the state of the pin.

(Second modification)
FIG. 8 is a circuit diagram showing a configuration of a control circuit 2a according to the second modification.
The control circuit 2a in FIG. 8 differs from the control circuit 2 in FIG. 4 in the configuration of the maximum frequency setting circuit 54. The maximum frequency setting circuit 54 a in FIG. 8 includes a ripple counter 90 and a timer control unit 92.

The ripple counter 90 is a 4-bit counter that counts up for each edge of the clock frequency CK having a predetermined frequency. The ripple counter 90 is supplied with a power-on reset (POR) signal S6 that is asserted when the control circuit 2a is activated and a burst control signal _SBURST . The ripple counter 90 is reset every time the POR signal S6 or the burst control signal S _BURST is asserted, and starts counting up after that, and after a predetermined time τ _FMAX has elapsed, the timer signal S7 that is the output of the ripple counter 90 Asserted. The configuration of the ripple counter 90 in FIG. 8 is common.

When the burst control signal S _BURST is asserted, the timer control unit 92 resets the ripple counter 90 and turns off the discharge switch 66. The timer control unit 92 includes a one-shot circuit 94 and a D flip-flop 96. The one-shot circuit 94 pulses the burst control signal S _BURST from the burst control circuit 50 and supplies it to the reset terminal of the ripple counter 90. Thereby, the time measurement of the ripple counter 90 is started in response to the assertion of the burst control signal S _BURST .

  Further, when the ripple counter 90 asserts the timer signal S7, the timer control unit 68 asserts the mask signal S2.

  Also according to this modification, the upper limit of the burst frequency can be set as in the embodiment.

  In this modification, the upper limit of the burst frequency can be arbitrarily set by making it possible to set the number of bits of the ripple counter 90 or setting the frequency of the clock signal CK. These settings may be performed by a control command from an external microcomputer, or a control pin (terminal) may be provided in the control circuit 2 and changeable depending on the state of the pin.

(Third Modification)
In the embodiment, the case where the shunt regulator (error amplifier) 212 is provided on the secondary side of the transformer T1 has been described. However, this error amplifier may be provided on the primary side, and further incorporated in the control circuit 2. May be.

(Fourth modification)
The circuit described in the embodiment is configured by a positive logic (high active) system in which each signal is asserted at a high level and a negate is allocated at a low level, but may be configured by a negative logic system, You may comprise combining a positive logic system and a negative logic system.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

P1 ... input terminal, P2 ... output terminal, Co1 ... first output capacitor, Co2 ... second output capacitor, D1 ... first diode, D2 ... second diode, T1 ... transformer, W1 ... primary winding, W2 ... 2 Next winding, W3 ... auxiliary winding, M1 ... switching transistor, RS ... detection resistor, 100 ... inverter, 102 ... fuse, Ci ... input capacitor, 104 ... filter, 106 ... diode rectifier circuit, Cs ... smoothing capacitor, 110 ... DC / DC converter, 2 ... control circuit, 200 ... output circuit, 210 ... feedback circuit, 212 ... shunt regulator, 214 ... photocoupler, 10 ... pulse modulator, 12 ... set signal generator, 14 ... reset signal generator, 16 ... RS flip-flop, 18 ... mask circuit, 20 ... driver, 40 ... blanking times 50 ... Burst control circuit, 52 ... Burst comparator, 54 ... Maximum frequency setting circuit, 56 ... Logic unit, 60 ... Timer circuit, 61 ... Timer capacitor, 62 ... Current source, 64 ... Timer comparator, 66 ... Discharge switch , 68 ... Timer control unit, 70 ... D flip-flop, 71, 72 ... inverter, 74 ... AND gate, 75 ... inverter, 76 ... one-shot circuit, 77 ... RS flip-flop, 80 ... voltage divider circuit, 90 ... ripple counter , 92: Timer control unit, 800 ... AC adapter, 802 ... Plug, 804 ... Housing, 806 ... Connector, 810, 900 ... Electronic equipment, 902 ... Plug, 904 ... Housing, S1 ... Comparison signal, S2 ... Mask signal , S3: Timer signal.

Claims (19)

A control circuit for a DC / DC converter,
The DC / DC converter is
A transformer having a primary winding and a secondary winding;
A switching transistor provided on the current path of the primary winding of the transformer;
Have
The control circuit includes:
Pulse modulation that receives a feedback voltage corresponding to the output voltage of the DC / DC converter and generates a pulse signal that is pulse-modulated so that the output voltage of the DC / DC converter approaches a target value based on at least the feedback voltage And
A driver for driving the switching transistor based on the pulse signal;
A burst control circuit that generates a burst control signal that is asserted in a switching period in which the switching transistor is to be switched and negated in a stop period in which switching of the switching transistor is to be stopped;
With
The burst control circuit includes:
A burst that compares the feedback voltage with a predetermined threshold voltage and generates a comparison signal that is asserted when the feedback voltage is higher than the threshold voltage and negated when the feedback voltage is lower than the threshold voltage. A comparator,
A maximum frequency setting circuit that starts time measurement triggered by the assertion of the comparison signal, generates a mask signal that is negated from the start to the elapse of a predetermined time, and asserted after the elapse of time;
(I) a logic unit that negates the burst control signal when the comparison signal is negated, (ii) asserts the burst control signal when the mask signal is asserted, and the comparison signal is asserted;
Bei to give a,
The pulse modulator is
A reset signal generating unit that generates a reset signal that is asserted when a detection voltage corresponding to a current flowing through the switching transistor reaches the feedback voltage;
A set signal generator for generating a set signal;
A mask circuit that passes through the set signal and the reset signal while the burst control signal is asserted, and invalidates the set signal and the reset signal while the burst control signal is negated;
A flip-flop that generates the pulse signal in response to the set signal and the reset signal that have passed through the mask circuit ;
A control circuit comprising: The maximum frequency setting circuit includes:
A timer circuit for generating a timer signal that is asserted after elapse of the predetermined time from the start of time measurement;
When the timer signal is asserted, the mask signal is asserted, and when the burst control signal is asserted, a timer control unit that causes the timer circuit to start measuring time;
The control circuit according to claim 1, comprising:   The control circuit according to claim 2, wherein the predetermined time can be set. The timer circuit is
A timer capacitor with a fixed potential at one end;
A current source for charging the timer capacitor;
A timer comparator that compares the voltage of the timer capacitor with a predetermined threshold voltage and asserts the timer signal when the voltage of the timer capacitor becomes higher than the threshold voltage;
A discharge switch provided in parallel with the timer capacitor;
Including
The timer control unit asserts the mask signal when the timer signal is asserted, and turns off the discharge switch and negates the mask signal when the burst control signal is asserted. Item 4. The control circuit according to Item 3.   5. The control circuit according to claim 4, wherein the timer capacitor is externally attached to a semiconductor chip on which the control circuit is integrated.   4. The control circuit according to claim 3, wherein the timer circuit includes a counter that counts a clock signal and asserts the timer signal when the count value reaches a predetermined value. The logic part is
An AND gate for generating a logical product of the comparison signal and the mask signal;
An RS flip-flop that is set according to the output of the AND gate, reset according to the inverted signal of the comparison signal, and outputs the burst control signal;
The control circuit according to claim 1, further comprising:   The DC / DC converter is
  The control circuit according to claim 1, further comprising a detection resistor provided on a path of the switching transistor, wherein a voltage drop of the detection resistor is the detection voltage.   The control circuit according to claim 8, wherein the set signal generation unit asserts the set signal at a predetermined cycle.   The control circuit according to claim 8, wherein the set signal generation unit asserts the set signal after a predetermined off time has elapsed since the reset signal was asserted.   The control circuit according to claim 8, wherein the set signal generation unit asserts the set signal when the energy stored in the transformer becomes substantially zero. The transformer further includes an auxiliary winding provided on the primary side,
The control circuit further includes an auxiliary terminal to which a voltage at one end of the auxiliary winding is input,
The set signal generator (i) compares the voltage of the auxiliary terminal with a predetermined threshold voltage, and generates a bottom detection signal that is asserted every time the voltage of the auxiliary terminal crosses the threshold voltage. 9. The control circuit according to claim 8, wherein (ii) the set signal is asserted every time the number of times the bottom detection signal is asserted reaches a count setting value. The transformer further includes an auxiliary winding provided on the primary side,
The control circuit further includes an auxiliary terminal to which a voltage at one end of the auxiliary winding is input,
The set signal generator (i) compares the voltage of the auxiliary terminal with a predetermined threshold voltage, and generates a bottom detection signal that is asserted every time the voltage of the auxiliary terminal crosses the threshold voltage. The control circuit according to claim 8, wherein (ii) the set signal is asserted after a predetermined time has elapsed since the bottom detection signal is asserted.   14. The control circuit according to claim 1, wherein the control circuit is monolithically integrated on a single semiconductor substrate. A transformer having a primary winding, a secondary winding and an auxiliary winding;
A switching transistor connected to the primary winding of the transformer;
A first diode having an anode connected to the secondary winding;
A first output capacitor having one end grounded and the other end connected to the cathode of the first diode;
A second diode having an anode connected to the auxiliary winding;
A second output capacitor having one end grounded and the other end connected to the cathode of the second diode;
A feedback circuit for generating a feedback voltage according to an output voltage generated in the first output capacitor;
The control circuit according to claim 1, which receives the feedback voltage and switches the switching transistor;
A DC / DC converter comprising: The feedback circuit includes:
A shunt regulator that generates a feedback signal whose level is adjusted so that an error between a voltage obtained by dividing the output voltage and a predetermined target value becomes zero;
A photocoupler whose light-emitting element on the primary side is controlled by the feedback signal;
16. The DC / DC converter according to claim 15, wherein a signal generated in a light receiving element on the secondary side of the photocoupler is supplied to the control circuit as the feedback voltage. A filter for filtering commercial AC voltage;
A diode rectifier circuit for full-wave rectification of the output voltage of the filter;
A smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage;
The DC / DC converter according to claim 15 or 16, wherein the DC input voltage is stepped down and supplied to a load.
A power supply apparatus comprising: Load,
A filter for filtering commercial AC voltage;
A diode rectifier circuit for full-wave rectification of the output voltage of the filter;
A smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage;
The DC / DC converter according to claim 15 or 16, wherein the DC input voltage is stepped down and supplied to the load.
An electronic device comprising: A filter for filtering commercial AC voltage;
A diode rectifier circuit for full-wave rectification of the output voltage of the filter;
A smoothing capacitor that smoothes the output voltage of the diode rectifier circuit and generates a DC input voltage;
The DC / DC converter according to claim 15 or 16, wherein the DC input voltage is stepped down to generate a DC output voltage.
A power adapter comprising:

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