JP6110560B2 - Method, apparatus and system for handling PCIe link failures - Google Patents

Description

  The present invention relates to the field of data transmission technology, and more particularly to a method, apparatus and system for handling PCIe link failures.

  Currently, in the field of data transmission technology, a peripheral component interconnect express (PCIe) protocol has been widely applied. When the PCIe protocol is applied to devices, data transmission is performed between devices in a point-to-point format. Devices that perform data transmission by using the PCIe protocol are collectively referred to as PCIe devices. In the system, link connection can be realized for communication between two PCIe devices by utilizing a serializer / deserializer (serdes, Serializer / De-Serializer) circuit. When two PCIe devices perform data transmission, data transmission is performed by utilizing serdes with the negotiated rate. The link between two PCIe devices may include 1, 2, 4, 8, 16, or 32 serdes. When there are multiple serdes, these serdes are numbered sequentially by using consecutive numbers in ascending order. One serdes is one lane of the link, and the serdes number is referred to as a lane number.

  The bandwidth (W) of data transmission between two PCIe devices is equal to the product of the number of lanes (N) and the negotiated rate (S), ie the bandwidth equation is W = N × S. . The negotiated rate (S) of the link between two PCIe devices varies depending on the version of the PCIe protocol used and currently indicates the amount of data that can be transmitted by one circuit per second, GEN1 (2. There are four types of negotiated rates: 5 GT / s), GEN2 (5.0 GT / s), GEN3 (8.0 GT / s) and GEN4 (16.0 GT / s). In general, the negotiated rate (S) supported by a link of one PCIe device is fixed, in this case the bandwidth is the link lane in order to meet the increasingly demanding user demand of communication bandwidth (W). It can be improved only by increasing the number (N).

  When two PCIe devices transmit data, all the lanes of the link between the two PCIe devices need to be used simultaneously. If a failure occurs in one of the lanes, data transmission is interrupted. In the prior art, when a failure occurs in a lane connected to a PCIe device, the PCIe device performs link negotiation according to a renegotiation mechanism of the PCIe protocol. During link negotiation, negotiation is performed starting from the lane with the smallest lane number, and link negotiation is sequentially performed in ascending order of lane numbers. A method of continuously executing link renegotiation in ascending order of lane numbers is referred to as upward negotiation. For example, if a failure occurs in lane number 2 of a PCIe device that needs to be initially negotiated for a GEN2 rate and a link width of 16 (PCIe 2.0 × 16), the PCIe device follows the renegotiation mechanism of the PCIe protocol, Link negotiation is performed upward starting from number 0. Negotiation cannot be executed sequentially for lane number 2 due to a failure in lane number 2, and link negotiation cannot be continued after the negotiation from lane number 0 to lane number 1 is executed. In this case, the negotiation is successful for only two lanes, lane number 0 and lane number 1, that is, data transmission can only continue on lane number 0 and lane number 1. According to the lane width of the link between two PCIe devices specified in the PCIe protocol, the lane width of the link between two PCIe devices is 2, which is obtained by renegotiation, i.e. only two lanes of data Can not be provided to the PCIe device for transmitting. In this case, N in the bandwidth equation is changed from the original 16 to 2, and the performance of data transmission between PCIe devices is only 1/8 of the original performance. However, when a failure occurs in lane number 1, according to the above renegotiation method, only one lane can be negotiated. In this case, the data transmission performance is only 1/16 of the original performance.

  In the prior art, when a failure occurs in the lane of a link between PCIe devices, the lane width renegotiation of the link is largely limited by the lane number of the failed lane, and the uncertainty regarding the lane width obtained by renegotiation And a case where the lane width is greatly reduced, which has a significant influence on the data transmission performance of the lane.

  In view of this, the present invention may cause a case where there is uncertainty in the lane width obtained by renegotiation due to the limitation of the lane number of the lane in which the failure occurs, and the lane width is greatly reduced. To solve the problems in the prior art that have a significant impact on lane transmission performance, a method, apparatus and system for handling PCIe link failures is provided.

A first aspect of the invention is a method for handling a PCIe link failure comprising:
A PCIe device detecting that a failure has occurred in a lane of a link between the PCIe device and a downstream PCIe device, and sending a message signaled interrupt MSI message to a central processing unit CPU, the MSI Sending a message having a device ID of said PCIe device;
The PCIe device negotiates with the downstream PCIe device to obtain a current lane width value N;
The CPU obtaining the PCIe device lane negotiation capability value M and the current lane width value N from the PCIe device according to the device ID in the received MSI message;
Said CPU comparing N and M / 2;
If N <M / 2, the CPU instructs the PCIe device to perform lane inversion processing;
The PCIe device performs the lane inversion process on a link between the PCIe device and the downstream PCIe device;
The PCIe device continues to execute data transmission with the downstream PCIe device by negotiating with the downstream PCIe device and using the N ′ lanes to obtain a new current lane width value N ′. Steps,
A method is provided.

  In a first possible implementation manner of the first aspect, the method further comprises: if N ≧ M / 2, the PCIe device uses the N lanes obtained by negotiation to cause the downstream The step of continuing to perform data transmission with other PCIe devices.

  Referring to the first aspect or the first possible implementation manner of the first aspect, in the second possible implementation manner, if N <M / 2, the method further comprises: Invalidating the lane number 0 to the lane number (M / 2-1) of the link between the PCIe device and the downstream PCIe device.

A second aspect of the invention is a method for handling a PCIe link failure comprising:
Receiving a message signaled interrupt MSI message reported by a PCIe device, wherein the MSI message has a device ID of the PCIe device;
Obtaining a lane negotiation capability value M and a current lane width value N of the PCIe device from the PCIe device according to the device ID, the current lane width value N being negotiated with a downstream PCIe device by the PCIe device; A step of obtaining, obtained by
Comparing N and M / 2;
If N <M / 2, instructing the PCIe device to perform lane inversion processing;
A method is provided.

  In a first possible implementation manner of the second aspect, if N <M / 2, the method further includes lane number 0 to lane number () of the link between the PCIe device and the downstream PCIe device. M / 2-1) is invalidated.

  Referring to the second aspect or the first possible implementation scheme of the second aspect, in a second possible implementation scheme, the lane negotiation capability value M of the PCIe device is the PCIe device and the downstream PCIe Equal to the total number of lanes in the link to the device.

A third aspect of the present invention is a method for handling a PCIe link failure comprising:
A PCIe device detecting that a failure has occurred in a lane of a link between the PCIe device and a downstream PCIe device, and sending a message signaled interrupt MSI message to a central processing unit CPU, the MSI Sending a message having a device ID of said PCIe device;
Negotiating with the downstream PCIe device to obtain a current lane width value N;
Receiving an instruction to perform lane inversion processing transmitted by the CPU, and executing the lane inversion processing for a link between the PCIe device and the downstream PCIe device;
Negotiating with the downstream PCIe device to obtain a new current lane width value N ′ and continuing to perform data transmission with the downstream PCIe device by using N ′ lanes;
A method is provided.

  In a first possible implementation manner of the third aspect, if the PCIe device does not receive the instruction to execute the lane inversion processing transmitted by the CPU within a predetermined time, the number of PCIe devices is N. , The data transmission with the downstream PCIe device continues to be executed.

A fourth aspect of the present invention is a system for handling a PCIe link failure, the system comprising a central processing unit CPU, a PCIe device and a downstream PCIe device, the CPU being connected to the PCIe device, The PCIe device is connected to the downstream PCIe device by using a link,
The PCIe device is configured to detect whether a failure has occurred in a lane of a link between the PCIe device and the downstream PCIe device, and report a message / signaled interrupt MSI message to the CPU when the failure occurs. The MSI message has a device ID of the PCIe device, and the PCIe device is further configured to negotiate with the downstream PCIe device to obtain a current lane width value N;
The CPU obtains the lane negotiation capability value M and the current lane width value N of the PCIe device from the PCIe device according to the device ID in the MSI message, compares N with M / 2, and N <M / 2 is configured to instruct the PCIe device to perform lane inversion processing;
The PCIe device further executes the lane inversion processing for the link between the PCIe device and the downstream PCIe device after receiving the instruction to execute the lane inversion processing transmitted by the CPU. A system configured to negotiate with the downstream PCIe device to obtain a current lane width value N ′.

  In a first possible implementation manner of the fourth aspect, when N <M / 2, the CPU further lane number 0 to lane number () of the link between the PCIe device and the downstream PCIe device. M / 2-1) is invalidated.

A fifth aspect of the present invention is a PCIe device for processing a PCIe link failure, and includes a detection module 5031, an MSI module 5033, a negotiate module 5035, a register 5037, and a lane inversion module 5039.
The register 5037 stores a current lane width value N and a lane negotiation capability value M of the PCIe device,
The detection module 5031 monitors the communication state of the link 504 between the PCIe device 503 and the downstream PCIe device, and when detecting that a failure has occurred in the lane of the link 504, the detection module 5031 sends a lane failure indication message to the MSI module. Configured to transmit to 5033,
The MSI module 5033 is configured to transmit an MSI message to the central processing unit CPU 501 after receiving the lane failure indication message transmitted by the detection module 5031, and the MSI message includes a device ID of the PCIe device 503. Including
The negotiate module 5035 is configured to negotiate the lane width of the link between the PCIe device and the downstream PCIe device;
The lane reversal module 5039 performs the lane reversal process on the lane of the link between the PCIe device and the downstream PCIe device after receiving the instruction to perform the lane reversal process transmitted by the CPU. A PCIe device configured as described above is provided.

  Compared to the prior art, the present invention discloses a method, apparatus and system for handling PCIe link failure, and by comparing the current lane width value of the PCIe apparatus and the lane negotiation capability value M, the method comprises: It can be seen from the above technical measures that the PCIe device lane width can be guaranteed to maintain half of the lane negotiation capability value regardless of the lane number of the lane in which the failure occurred. The method, apparatus and system for handling PCIe link failures disclosed in the present invention greatly relaxes the lane number limitation of failed lanes imposed on link renegotiation, so that the optimal link width can be improved after renegotiation. Can be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS To describe the technical solutions in the embodiments of the present invention or in the prior art more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments or the prior art. Apparently, the accompanying drawings in the following description show merely examples of the present invention, and those skilled in the art may still derive other drawings from the provided accompanying drawings.
FIG. 1 is a schematic diagram of a connection between PCIe devices disclosed in an embodiment of the present invention. FIG. 2 is a simplified schematic diagram of connections between PCIe devices disclosed in embodiments of the present invention. FIG. 3 is a simplified schematic diagram of another connection between PCIe devices disclosed in embodiments of the present invention. FIG. 4 is a flowchart of a method for handling a link failure of a PCIe device disclosed in an embodiment of the present invention. FIG. 5 is a schematic configuration diagram of a PCIe device disclosed in an embodiment of the present invention.

  The following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are merely a part rather than all of the embodiments of the present invention.

  The present invention provides a novel method for handling link failures in PCIe (Peripheral Component Interconnect Express) devices. Devices that perform data transmission by using the PCIe protocol are collectively referred to as PCIe devices. The PCIe device may be a chip integrated into an independent device, or may be a physically independent device, and is not limited here. Reference may be made to FIG. 1 for connection relationships between PCIe devices. As shown in FIG. 1, two PCIe devices may be directly connected to perform data transmission, for example, the downstream port of a root complex device is between the root complex and the PCIe device 1 In order to realize this data transmission, it is directly connected to the upstream port of the PCIe device 1. Data transmission may also be performed indirectly between two PCIe devices, for example, implementing data transmission by utilizing a switch. For example, the downstream port of the route complex is connected to the upstream port of the switch, and the downstream port of the switch is connected to the upstream port of the PCIe device 2 in order to realize data transmission between the root complex and the PCIe device 2. Connected. One PCIe device may be simultaneously connected to a plurality of PCIe devices. As shown in FIG. 1, the route complex is simultaneously connected to the PCIe device 1 and the switch. These PCIe devices may be managed by the central processing unit CPU in a centralized manner.

  Data transmission is realized between the two PCIe devices by a link connection, and the link may be a serializer / deserializer (serdesizer, serializer / de-serializer) circuit. For example, the downstream port of the root complex is connected to the upstream port of the PCIe device 1 by using a plurality of serdes, and these serdes form a link between the root complex and the PCIe device 1. There may be 1, 2, 4, 8, 16 or 32 serdes between two PCIe devices, and the serdes between two PCIe devices form a link between the two PCIe devices. The bandwidth (W) of data transmission between two PCIe devices is equal to the product of the number of lanes (N) and the negotiated rate (S), ie the bandwidth equation is W = N × S. . The negotiated rate (S) of the link between two PCIe devices varies depending on the version of the PCIe protocol used and is currently GEN1 (2.5 indicating the amount of data that can be transmitted by one circuit per second. There are four types of negotiated rates: GT / s), GEN2 (5.0 GT / s), GEN3 (8.0 GT / s) and GEN4 (16.0 GT / s). In general, the negotiated rate (S) supported by a link of one PCIe device is fixed, in this case the bandwidth is the link lane in order to meet the increasingly demanding user demand of communication bandwidth (W). It can be improved only by increasing the number (N).

  When there are multiple serdes, these serdes are numbered sequentially by using consecutive numbers in ascending order, where one serdes is a lane of links between two PCIe devices. Yes, the serdes number is referred to as the lane number. For example, the lanes between the root complex shown in FIG. 1 and the PCIe device 1 are sequentially numbered from left to right by using numbers from 0 to 15. The serdes described here utilize the existing serdes structure and support existing functionality and will not be described again here.

  When two PCIe devices are connected, one PCIe device that has started link negotiation is referred to as an upstream PCIe device, and the other connected to the one PCIe device is referred to as a downstream PCIe device. As shown in FIG. 1, when the route complex and the PCIe device 1 are connected, the route complex is an upstream PCIe device, and the PCIe device 1 is a downstream PCIe device. When the route complex and the switch are connected, the route complex is the upstream PCIe device and the switch is the downstream PCIe device. The switch is further connected to a PCIe device 2, in which case the switch is an upstream PCIe device and the PCIe device 2 is a downstream PCIe device. When one PCIe device is simultaneously connected to multiple PCIe devices, data transmission is performed between the one PCIe device and all other PCIe devices by utilizing independent links. For example, a PCIe switch is simultaneously connected to the PCIe device 2 and the PCIe device 3, and data transmission between the PCIe switch and the PCIe device 2 is realized by using the link 1, and the switch is obtained by using the link 2. And the PCIe device 3 are realized. Link 1 and link 2 exist independently of each other and do not affect each other. The number of lanes of link 1 and link 2 may be the same or different. However, data transmission is performed between PCIe devices by utilizing links in the same manner. In the following, an explanation will be given by utilizing a specific example of a method for handling a fault performed on a link between two PCIe devices.

  To make the overall process clearer and more explicit, the connection relationship between the two PCIe devices is simplified, as shown in FIG. 2, where the first PCIe device is the upstream PCIe device. Yes, lane negotiation with the second PCIe device is executed. The second PCIe device is a downstream PCIe device. The central processing unit CPU manages two PCIe devices. The link between the first PCIe device and the second PCIe device includes 16 serdes, each serdes is the lane of the link between the first PCIe device and the second PCIe device, and the 16 lanes are from left to right Are numbered sequentially from 0 to 15. As shown in FIG. 2, the lane number 0 is referred to as lane number 0, the lane number 1 is referred to as lane number 1, and similarly, the lane number 15 is lane number 15. The number of lanes here is used for explanation only. In actual use, 1, 2, 4, 8 or 32 lanes may be set according to the requirements, and its implementation principle is the same as that of 16 lanes.

  A message signaled interrupt (MSI) function is set in the first PCIe device. Upon detecting that a failure has occurred in one or more lanes of the link connected between the first PCIe device and the second PCIe device, the first PCIe device reports an MSI message to the CPU, where the MSI message is the first PCIe device. Contains the device ID of the device. The first PCIe device stores the lane number of the failed lane in the register. The first PCIe device performs lane renegotiation with the second PCIe device according to the renegotiation mechanism of the PCIe protocol in order to obtain the current lane width value N of the link between the first PCIe device and the second PCIe device. During lane renegotiation, according to the lane negotiation mechanism specified in PCIe, the first PCIe device starts from the lane with the lowest lane number and proceeds upward in ascending lane number until the negotiation is performed on the failed lane. The link negotiation with the second PCIe device is continuously executed. Since the negotiation for the failed lane cannot be successfully executed, the renegotiation process ends. The first PCIe device further determines the current lane width value N of the link according to the number of lanes of the link between the two PCIe devices specified in the PCIe protocol. Since the lane numbers need to be contiguous and link negotiation starts from the lowest numbered lane, the number of lanes acquired by renegotiation varies with the lane number of the failed lane, and there is uncertainty. When the lane number of the failed lane is relatively small, the number of lanes acquired by renegotiation is also greatly reduced, i.e., the acquired current lane width value N is greatly reduced, thereby causing the two PCIe devices to The data transmission performance between the two will be seriously affected. For example, if a failure occurs in lane number 3 between the first PCIe device and the second PCIe device, the first PCIe device starts from lane number 0 according to the negotiation mechanism of the PCIe protocol, and performs link negotiation with the second PCIe device. Run. No failure has occurred in lane number 0, so the negotiation is successful, the negotiation proceeds to lane number 1, the negotiation in lane number 1 is successful, the negotiation proceeds to lane number 2, and the negotiation in lane number 2 Succeeds and negotiation proceeds to lane number 3. Since a failure occurs in the lane number, the negotiation cannot be executed successfully. Furthermore, the lane numbers need to be sequential and the negotiation cannot continue after suspending at lane number 3. In this case, only three lanes, ie, lane number 0, lane number 1 and lane number 2 are available. In addition, since the link between two PCIe devices can contain 1, 2, 4, 8, 16 or 32 lanes according to the PCIe protocol, the current obtained by negotiation between the first PCIe device and the second PCIe device The lane width value N is 2. Initially, there are 16 lanes between the first PCIe device and the second PCIe device that can be used to perform data transmission, but after a failure occurs in lane number 3, it is obtained by renegotiation, and data transmission is performed. There are only two lanes available to run, which is 1/8 of the original. In this case, the lane width of the link between the first PCIe device and the second PCIe device is greatly reduced, and the data transmission performance is clearly reduced. Similarly, when a failure occurs in lane number 1 between the first PCIe device and the second PCIe device, only lane number 0 can be used. In this case, the current lane width value N acquired by renegotiation between the first PCIe device and the second PCIe device is 1, which is 1/16 of the initial value, and the data transmission performance is greatly deteriorated.

  In this embodiment of the invention, after receiving the MSI message reported by the first PCIe device, the CPU enters an interrupt processing process. The CPU acquires the current lane width value N of the first PCIe device and the lane negotiation capability value M of the first PCIe device from the first PCIe device according to the device ID of the first PCIe device in the MSI message. The lane negotiation capability value M of the first PCIe device represents a maximum lane width value that can be acquired by the first PCIe device negotiating with the second PCIe device. The maximum lane width value that can be acquired by negotiation by the first PCIe device is the total number of lanes of the link between the first PCIe device and the second PCIe device. In this embodiment, there are 16 lanes of the link between the first PCIe device and the second PCIe device, and therefore the maximum lane width value that can be obtained by the first PCIe device negotiating with the second PCIe device is 16. The lane negotiation capability value M of the first PCIe device is 16. The current lane width value N of the first PCIe device is a current lane width value N acquired when the first PCIe device renegotiates with the second PCIe device. For example, as described above, there are 16 lanes connecting the first PCIe device and the second PCIe device, and when a failure occurs in lane number 3 between the first PCIe device and the second PCIe device, the first PCIe device In order to obtain a current lane width value N of 2, renegotiate with the second PCIe device according to the renegotiation mechanism of the PCIe protocol.

  The CPU compares the current lane width value N acquired by the first PCIe device with the lane negotiation capability value M. In the present invention, the CPU compares N and M / 2 according to the rule of the number of lanes of links between two PCIe devices.

  When N ≧ M / 2, the CPU does not execute the process. If the first PCIe device does not receive the instruction transmitted by the CPU within a predetermined time, the first PCIe device performs data transmission with the second PCIe device by using N lanes acquired by renegotiation. Keep doing. In this case, N ≧ M / 2 indicates that the lane number of the failed lane is greater than (M / 2-1), and the link between the two PCIe devices is 1, 2, 4, 8, 16 Alternatively, the current lane width value N obtained by the first PCIe device renegotiating with the second PCIe device is M / 2 since the first PCIe device may include 32 lanes, and the first PCIe device is a link obtained by the renegotiation. By using the lane, data transmission with the second PCIe device is continued.

When N <M / 2, the CPU instructs the first PCIe device to execute the lane inversion process for the link between the first PCIe device and the second PCIe device. When N <M / 2, the current lane width obtained by the first PCIe device renegotiating with the second PCIe device is less than half of the total link width, because the lane number of the failed lane is Indicates less than M / 2. The lane inversion process indicates that the first PCIe device renumbers the lane of the link between the first PCIe device and the second PCIe device in the opposite direction. If the lane of the link between the first PCIe device and the second PCIe device is initially numbered from 0 to 15 starting from 0 to the left, the first PCIe device performs the lane inversion process and then the first PCIe device The lane of the link between the device and the second PCIe device is numbered from 0 to 15 from right to left, and vice versa. For example, in the present embodiment, after the first PCIe device performs the lane inversion process, the lane number of the original lane number 15 is changed from 15 to 0, that is, the original lane number 15 is changed to lane number 0, The lane number of the original lane number 14 is changed from 14 to 1, that is, the original lane number 14 is changed to lane number 1 and the rest can be similarly derived. Before instructing the first PCIe device to execute the lane inversion process, the CPU may further invalidate the lane number (M / 2-1) from lane number 0 between the first PCIe device and the second PCIe device. . After the lane number 0 to lane number (M / 2-1) is invalidated, the first PCIe device no longer needs to number the invalidated lanes. In this case, the first PCIe device executes lane inversion processing until the lane number of the original lane number M / 2 is changed to (M / 2-1), and the lane number of the original lane number M is set to 0. And the lane number of the original lane number (M-1) is changed to 1.

  After executing the lane inversion process, the first PCIe device executes renegotiation on the new current lane width value with the second PCIe device in order to obtain a new current lane width value N ′. The method for the first PCIe device to renegotiate the current lane width with the second PCIe device is the same as the above-described renegotiation method. In accordance with the request of the PCIe protocol, the first PCIe device executes the negotiation starting from the lowest-numbered lane after the inversion, and continuously re-executes the link negotiation with the second PCIe device upward in the ascending order of the lane numbers. That is, the first PCIe device performs the negotiation starting from the inverted lane number 0, and thereafter, for lane number 1 and lane number 2, until the negotiation is performed for the lane number (M / 2-1). Perform negotiations sequentially. The first PCIe device executes the lane inversion process when N <M / 2, and in this case, the lane number of the failed lane is less than M / 2, that is, the failed lane is lane number 0 to lane No. from lane number 0 to lane number (M / 2-1) is invalid, but no failure occurs from lane number M / 2 to lane number M. Instead, data transmission can be performed. Therefore, after the first PCIe device performs the lane inversion, a failure does not occur in the new lane number 0 to lane number (M / 2-1), and the first PCIe device is acquired by renegotiating with the second PCIe device. The new current lane width value N ′ is M / 2.

  When a failure occurs in a lane of a PCIe device, using the measures of the present invention, the lane width obtained by renegotiation is 1/2 of the original lane width regardless of the lane number of the failed lane. When the lane number of the failed lane is relatively small, the lane value of the PCIe device is greatly reduced, which affects the data transmission rate between the PCIe devices. To avoid.

  The technical measures of the present invention are described and explained in detail below by utilizing specific embodiments. The connection relationship between the PCIe devices is shown in FIG. 3, and see FIG. 4 for the processing of the method.

  A PCIe device described below refers to a device that communicates with other devices by utilizing the PCIe protocol. As shown in FIG. 3, a root complex device is a PCIe device that communicates with a downstream PCIe device by utilizing the PCIe protocol, ie, an upstream PCIe device such as the first PCIe device shown in FIG. Represents. The PCIe device 1 (PCIe apparatus 1) represents a PCIe device that communicates with an upstream PCIe device by using the PCIe protocol, that is, a downstream PCIe device such as the second PCIe device shown in FIG. Further, the PCIe device may be a physically independent device, or may be a chip integrated into the device, and is not limited to the PCIe device shown in FIG.

  The root complex is connected to the upstream port of the PCIe device 1 by realizing data transmission using the downstream port. The present embodiment will be described by using a specific example in which there are 16 serdes between the root complex and the PCIe device 1. These 16 serdes form a link between the root complex and the PCIe device 1, and one serdes is referred to as one lane. That is, the number of lanes between the root complex and the PCIe device 1 is 16, that is, X16. In addition, the 16 lanes are numbered consecutively from 0 to 15 from left to right. In this case, the maximum lane width value between the root complex and the PCIe device 1 is 16. The lane negotiation capability value M of the root complex is equal to the maximum lane width value of the root complex, and the maximum lane width value of the root complex is the maximum number of lanes between the root complex and the PCIe device 1 that can be obtained by negotiation by the root complex. Represents. In the present embodiment, the lane negotiation capability value M of the root complex is equal to 16. The root complex stores the lane negotiation capability value M of the root complex in a register. The link between two PCIe devices may include 1, 2, 4, 8, 16, or 32 lanes, as defined by the PCIe protocol. This embodiment will be described by using 16 lanes as a specific example. When a link has 1, 2, 4, 8 or 32 lanes, its implementation is the same as that of 16 lanes.

  The root complex may also be connected to other PCIe devices. When the root complex is connected to multiple PCIe devices, as shown in FIG. 1, the root complex may be further connected to a switch, and the lane negotiation capability value between the root complex and the PCIe device For distinction, they may be recorded separately as M1, M2 and M3. In the following method, an explanation is given by using a specific example in which a root complex is connected to one PCIe device. When the root complex is connected to a plurality of PCIe devices, the method for handling a failure in the lane between the root complex and one of the PCIe devices is the same as in the present embodiment.

  A message signaled interrupt (MSI, message signal interrupt) function is set to the root complex. The root complex monitors the lane connected to the PCIe device 1 and detects that the lane width between the root complex and the PCIe device 1 has changed, and the root complex reports an MSI message to the CPU. When the root complex executes data transmission with the PCIe device 1, all lanes connected between the two devices (that is, all serdes) are used. If a failure occurs in any one or more of the lanes, the root complex detects that the lane width between the root complex and the PCIe device 1 has been changed, and the root complex generates an MSI message and generates an MSI message. To the CPU. The MSI message includes a root complex device ID such as B: D: F (bus number: device number: function number) of the root complex port. The root complex stores the lane number of the failed lane in a register. In the present embodiment, a failure occurs in lane number 5 between the root complex and the PCIe device 1, and the root complex detects that a failure has occurred in lane number 5, and stores the lane number information of the failed lane in a register. Remember.

  After reporting the MSI message to the CPU, the root complex renegotiates with the PCIe device 1 to obtain the current lane width value N. According to the specification of the PCIe protocol, the lane negotiation of the link between the PCIe devices is started from the lowest-numbered lane until the negotiation is performed on the lane where the failure has occurred. In this way, the lane numbers of the lanes that have been successfully negotiated are still sequential, and the number of lanes available for transmitting data may be obtained. In this embodiment, the root complex starts with lane number 0 and negotiates with the PCIe device 1, and after the negotiation executed for lane number 0 is successful (that is, lane number 0 is normal and data is transmitted). Then, negotiation is performed for lane number 0. The rest can be guided as well. When the negotiation is executed for the lane number 5, since a failure has occurred in the lane number 5, the negotiation executed for the lane number 5 is unsuccessful, and the root complex is negotiated with the PCIe device 1. Stop. Negotiations for lane number 0 to lane number 4 between the root complex and the PCIe device 1 are successful, that is, negotiations for five lanes between the root complex and the PCIe device 1 are successful. At this time, the current lane width value between the root complex and the PCIe device 1 according to the specification of the PCIe protocol in which the lane between the two PCIe devices may include 1, 2, 4, 8, 16, or 32 lanes. It is determined that N is 4. The root complex stores the current lane width value N acquired by renegotiation in a register.

  After receiving the MSI message reported by the root complex, the CPU enters an interrupt processing process. The CPU extracts the root complex ID from the MSI message, and then reads the current lane width value N and lane negotiation capability value M of the root complex from the root complex register according to the acquired ID. The current lane width value N of the root complex is obtained by renegotiation with the PCIe device 1 after the root complex detects that a failure has occurred in the lane between the root complex and the PCIe device 1. In the present embodiment, the current lane width value N acquired by renegotiation is 4 after a failure has occurred in the serdes lane number 5 between the root complex and the PCIe device 1. The specific negotiation method is described in the previous paragraph and is not individually re-explained here. Furthermore, as described above, in this embodiment, there are 16 lanes between the root complex and the PCIe device 1, and thus the lane negotiation capability value M of the root complex is 16.

  The CPU compares the current lane width value N of the root complex with the lane negotiation capability value M of the root complex. In the present invention, the CPU compares N and M / 2 according to the rule for the number of lanes of links between two PCIe devices.

  When N ≧ M / 2, the current lane width value obtained by the root complex negotiating with the PCIe device 1 is half of the maximum lane width value, and in this case, the CPU does not execute processing. If the root complex does not receive the instruction sent by the CPU within a predetermined time, the root complex performs data transmission for one PCIe device by using N link lanes acquired by renegotiation. Keep doing.

  When N <M / 2, the current lane width value obtained by the root complex negotiating with the PCIe device 1 is less than half of the maximum lane width value. In this case, the root complex and the PCIe device 1 The width of the link in between is greatly reduced. In this case, the CPU invalidates the lane number 0 to the lane number (M / 2-1) between the root complex and the PCIe device 1 and instructs the root complex to start the lane inversion process. In the lane reversal process, the PCIe device renumbers the lanes of the link between the PCIe device and the downstream PCIe device in the opposite direction. After starting the lane inversion process, the root complex renumbers the lanes between the root complex and the PCIe device 1 in the opposite direction. Lanes between the root complex and the PCIe device 1 are sequentially numbered from left to right in ascending order. After starting the lane inversion process, the root complex sequentially numbers the lanes between the root complex and the PCIe device 1 in ascending order from right to left. A related description of the specific numbering process is provided above and will not be reintroduced here individually. Since the original lane number 0 to the lane number (M / 2-1) are invalidated, the root complex does not number invalidated lanes after starting the lane inversion process. In this way, the root complex sequentially numbers the lanes between the root complex and the PCIe device 1 starting from 0 in ascending order from right to left to (M / 2-1).

  After completing the lane inversion process, the root complex then performs a lane width negotiation with the PCIe device 1 to obtain a new current lane width value N ′ of the link between the root complex and the PCIe device. According to the rules of the PCIe protocol, negotiations between PCIe devices are started from the lowest numbered lane until negotiation is performed on the failed lane. After completing the lane inversion process, the root complex executes a negotiation starting from a new lane number 0 until the negotiation is performed on the lane in which the failure has occurred, and determines the number of lanes available for communication. The root complex then determines a new current lane width value N 'according to the requirement for the number of lanes of the link between two PCIe devices as defined in the PCIe protocol. The root complex continues to execute data transmission with the PCIe device 1 by using the new N ′ number of lanes acquired by the negotiation.

  In this embodiment, a failure occurs in lane number 5, N is 4, M is 16, and 4 <8 (N <M / 2). The CPU invalidates the lane number 0 to the lane number (M / 2-1) (that is, No. 7) between the root complex and the PCIe device 1 and instructs the root complex to execute the lane inversion process. After receiving the instruction, the root complex renumbers the lanes between the root complex and the PCIe device 1 in the opposite direction. The lane number of lane number 15 is changed from 15 to 0, that is, the original lane number 15 is changed to lane number 0, and the lane number of lane number 14 is changed from 14 to 1, that is, the original lane number 14 Is changed to lane number 1 and the rest can be led in the same way. Since the lane number 0 to the lane number (M / 2-1) (ie, No. 7) are invalidated, the lane inversion processing is performed so that the original lane number M / 2 (ie, No. 8) / 2-1) (i.e., No. 7) and then finished. After completing the lane inversion, the root complex executes the lane renegotiation with the PCIe device 1, the negotiation starting from the newly inverted lane number 0 is executed, and the negotiation is continuously executed upward according to the lane number. . Since the data transmission can be performed for the original lane number 8 to the original lane number 15 in which no failure occurs, when the root complex executes the lane renegotiation with the PCIe device 1 again, the data transmission is performed in eight lanes. The negotiation is successfully executed. Further, since the PCIe protocol stipulates that the lane width is one of 1, 2, 4, 8, 16 and 32, a new current lane acquired by renegotiation by the route complex with the PCIe device 1 The width value N ′ is 8.

  The root complex continues to perform data transmission by utilizing the new inverted lane number 0 to the new inverted lane number 7 (ie, number 8) between the root complex and the PCIe device 1. . The specific data transmission process is the same as that of the existing implementation method, and is not described again here.

  Thus, in the event of a failure in the lane of the link between two PCIe devices, utilizing the measures provided in the present invention will reduce the number of lane negotiation capability values of ½ of the PCIe device. The lane can be guaranteed to be usable regardless of the lane number of the failed lane, and the transmission speed and performance of the link between the PCIe devices are guaranteed to the maximum extent.

  The present invention further provides a system for handling link failures of PCIe devices, the system configuration being shown in FIG. The system includes a central processing unit CPU 201, a first PCIe device 203, and a second PCIe device 205. The first PCIe device and the second PCIe device are connected by using a plurality of serializer / deserializer (serdes, Serializer / De-Serializer) circuits. The plurality of serdes constitute a link 204 used to transmit data between the first and second PCIe devices, each serdes is a lane, and the lanes are sequentially numbered in a certain order. . There may be 1, 2, 4, 8, 16 or 32 serdes between two PCIe devices, and this embodiment will be described by using 16 serdes as a specific example. That is, there are 16 serdes, that is, 16 lanes between the first PCIe device 203 and the second PCIe device 205, and these 16 lanes are sequentially and sequentially from left to right starting from 0 to 15. Numbered. The lane number 0 is lane number 0. Similarly, the lane number 15 is lane number 15. serdes uses the existing serdes structure and supports existing functionality and is not individually re-described here. In this embodiment of the present invention, the realization principle is the same regardless of how many serdes are in the link.

  A message signaled interrupt (MSI) function is set in the first PCIe device 203. When detecting that a failure has occurred in one or more lanes of the link 204 connected to the second PCIe device 205, the first PCIe device 203 reports an MSI message to the CPU 201, where the MSI message is the device of the first PCIe device 203. Includes ID.

  The first PCIe device 203 performs lane renegotiation with the second PCIe device 205 according to the PCIe protocol renegotiation mechanism in order to obtain the current lane width value N of the link 204 between the first PCIe device 203 and the second PCIe device 205. . During lane renegotiation, according to the lane negotiation mechanism specified in the PCIe protocol, the first PCIe device 203 starts from the lane with the lowest lane number and proceeds upward in ascending lane number until the failed lane is negotiated. The link negotiation with the second PCIe device 205 is continuously executed again. Since the negotiation cannot be successfully executed for the failed lane, the renegotiation process is terminated. The first PCIe device 203 further determines the current lane width value N of the link according to the number of lanes of the link between the two PCIe devices specified by the PCIe protocol.

  Since the lane numbers need to be consecutive and link negotiation starts from the lane with the smallest number, the number of lanes acquired by renegotiation varies depending on the lane number of the failed lane, and there is uncertainty. When the lane number of the failed lane is relatively small, the number of lanes acquired by renegotiation is also greatly reduced, i.e., the acquired current lane width value N is greatly reduced, and therefore between two PCIe devices. Will significantly affect the performance of data transmission.

  In this embodiment of the invention, after receiving the MSI message reported by the first PCIe device 203, the CPU 201 enters an interrupt processing process. The CPU 201 acquires the current lane width value N of the first PCIe device 203 and the lane negotiation capability value M of the first PCIe device 203 from the first PCIe device 203 according to the device ID of the first PCIe device 203 in the MSI message. The lane negotiation capability value M of the first PCIe device 203 is the maximum lane width value that can be acquired by the first PCIe device 203 negotiating with the second PCIe device 205, that is, the lane between the first PCIe device 203 and the second PCIe device 205. Represents the total number of In the present embodiment, there are 16 lanes between the first PCIe device 203 and the second PCIe device 205. Therefore, the maximum lane width value that can be acquired by the first PCIe device 203 negotiating with the second PCIe device 205 is 16 The lane negotiation capability value M of the first PCIe device 203 is 16. The current lane width value N of the first PCIe device 203 is the current lane width value N acquired when the first PCIe device 203 renegotiates with the second PCIe device 205.

  The CPU 201 compares the acquired current lane width value N and the lane negotiation capability value M of the first PCIe device 203. In the present invention, the CPU 201 compares N and M / 2 according to the rule for the number of lanes of links between two PCIe devices.

  When N ≧ M / 2, the first PCIe device 203 continues to execute data transmission with the second PCIe device 205 by using the link lane acquired by renegotiation. In this case, N ≧ M / 2 indicates that the lane number of the failed lane is greater than (M / 2-1), and the link between the two PCIe devices is 1, 2, 4, 8, 16, or 32. Since the first PCIe device 203 re-negotiates with the second PCIe device 205, the current lane width value N obtained by re-negotiation with the second PCIe device 205 is M / 2, and the first PCIe device 203 is acquired by renegotiation. By using the link lane, data transmission with the second PCIe device 205 is continued. The CPU 201 does not execute processing in such a state. The first PCIe device 203 may set a period, and if the first PCIe device 203 does not receive an instruction from the CPU 201 within the set period, the first PCIe device 203 uses a link lane acquired by renegotiation. As a result, the data transmission with the second PCIe device 205 is continued.

  When N <M / 2, the CPU 201 instructs the first PCIe device 203 to execute lane inversion processing. When N <M / 2, the current lane width obtained by the first PCIe device 203 renegotiating with the second PCIe device 205 is less than half of the total link width, and the lane number of the failed lane is M Indicates less than / 2. In the lane inversion process, the first PCIe device 203 renumbers the lanes between the first PCIe device 203 and the second PCIe device 205 in the opposite direction. For example, in this embodiment, the lanes between the first PCIe device 203 and the second PCIe device 205 are initially numbered from left to right starting at 0 and ending at 15. After the first PCIe device 203 executes the lane inversion process, the lane number of the original lane number 15 is changed from 15 to 0, that is, the original lane number 15 is changed to lane number 0, and the original lane number 14 The lane number is changed from 14 to 1, that is, the original lane number 14 is changed to lane number 1 and the rest can be similarly derived. Before instructing the first PCIe device to execute the lane inversion process, the CPU 201 further disables the lane number 0 to the lane number (M / 2-1) between the first PCIe device and the second PCIe device. Good. After the lane number 0 to the lane number (M / 2-1) are invalidated, the first PCIe device 203 changes the lane number of the original lane number M to 0, and the original lane number (M-1) The lane inversion process is executed until the lane number of the original lane number M / 2 is changed to (M / 2-1), such as changing the lane number of the original lane number to 1. After executing the lane inversion process, the first PCIe device 203 performs renegotiation on the new current lane width by the second PCIe device 205 in order to obtain a new current lane width value N ′. The method in which the first PCIe device 203 renegotiates the current lane width with the second PCIe device 205 is the same as the above-described renegotiation method. In accordance with the request of the PCIe protocol, the first PCIe device 203 performs negotiation starting from the lowest numbered lane after inversion, and continuously re-executes link negotiation with the second PCIe device 205 in the ascending order of the lane numbers. That is, the first PCIe device 203 executes the negotiation starting from the inverted lane number 0, and then changes to lane number 1 and lane number 2 until the negotiation is performed on the lane number (M / 2-1). Negotiations are executed sequentially. The first PCIe device 203 performs the lane inversion process when N <M / 2, and in this case, the lane number of the failed lane is less than M / 2, that is, the failed lane has the lane number 0 to the lane number. (M / 2-1) and lane number 0 to lane number (M / 2-1) are invalid, but a failure occurs from lane number M / 2 to lane number M. Data transmission is possible. Thereafter, after the first PCIe device 203 performs lane inversion, no failure occurs from the new lane number 0 to the lane number (M / 2-1), and the first PCIe device 203 renegotiates with the second PCIe device 205. The new current lane width value N ′ obtained by this is M / 2. The first PCIe device 203 continues to execute data transmission with the second PCIe device 205 by using a new lane link acquired by renegotiation.

  When a failure occurs in a lane of a PCIe device, using the measure of the present invention is that the lane width acquired by renegotiation is 1/2 of the original lane width regardless of the lane number of the failed lane. The lane number of the PCIe device is greatly reduced when the lane number of the failed lane is relatively small, and therefore the data transmission speed between the PCIe devices is affected.

  Refer to FIG. 5 for an internal configuration diagram of the first PCIe device 503 in the embodiment of the present invention. As shown in FIG. 5, the first PCIe device 503 includes a detection module 5031, an MSI module 5033, a negotiate module 5035, a register 5037, and a lane inversion module 5039.

  The detection module 5031 is configured to monitor the communication state of the link 504 between the first PCIe device 503 and the second PCIe device 505. The link 504 between the first PCIe device 503 and the second PCIe device 504 has a plurality of serializer / deserializer (serdes, Serializer / De-Serializer) circuits, and each serdes is a lane. When detecting that a failure has occurred in one or more lanes of the link 504, the detection module 5031 sends a lane failure indication message to the MSI module 5033 and sends information about the failed lane to the register 5037 for storage.

  The MSI module 5033 is configured to send the MSI message to the central processing unit CPU 501 after receiving the lane failure indication message of the detection module 5031. The transmitted MSI message includes the device ID of the first PCIe device 503.

  The negotiate module 5035 is configured to negotiate the lane width between the first PCIe device 503 and the second PCIe device 505. The lanes of links between two PCIe devices are numbered consecutively in some order. The link between two PCIe devices may have 1, 2, 4, 8, 16, or 32 lanes, and this embodiment is illustrated by utilizing 16 lanes as an example. The For example, as shown in FIG. 5, the lanes of the link 504 between the first PCIe device 503 and the second PCIe device 505 are sequentially numbered from left to right starting with 0. Lane number 0, lane number 1, lane number 2,. . . . And there is lane number 15. According to the PCIe protocol negotiation mechanism, when link negotiation is performed, the negotiation starts with the lowest numbered lane and continues upward in ascending lane number until the negotiation is performed on the failed lane. Thus, the link negotiation with the second PCIe device 505 is executed again. Since the negotiation for the failed lane cannot be successfully executed, the renegotiation process ends. The first PCIe device 503 further determines a current lane width value N of the link between the first PCIe device 503 and the second PCIe device 505 according to the number of lanes of the link between the two PCIe devices specified by the PCIe protocol.

  The register 5037 is configured to store information including information such as the current lane width value N and the lane negotiation capability value M of the first PCIe device 503.

  The lane inversion module 5039 is configured to perform lane inversion processing on the lane of the link 504 after receiving an instruction to perform lane inversion processing.

  When detecting that a failure has occurred in one or more lanes of the link 504, the detection module 5031 sends a lane failure indication message to the MSI module 5033 and sends information about the failed lane to the register 5037 for storage.

  The negotiate module 5035 starts renegotiation and determines a current lane width value N between the first PCIe device 503 and the second PCIe device 505. The negotiate module 5035 performs the negotiation starting from the lowest numbered lane in the link 504, that is, the negotiation is performed starting from the lane number 0, and the negotiation is successfully performed for the lane number 0. Negotiations are performed on the rest, and the rest can be similarly guided until negotiations are performed on the failed lane. In the present embodiment, it is assumed that a failure has occurred in lane number 5 of the link 504. When the negotiate module 5035 starts renegotiation, the negotiation is successfully executed for lane number 0 to lane number 4. In this case, five lanes are available for communication, but the link between the two PCIe devices may have 1, 2, 4, 8, 16 or 32 lanes, so the first PCIe device The current lane width value N between 503 and the second PCIe device 505 is 4.

  After receiving the MSI message transmitted by the MSI module 5033, the CPU 501 obtains the current lane width value N and lane negotiation capability value M of the first PCIe device from the register 5037 of the first PCIe device 503 according to the device ID included in the MSI message. get. In this embodiment, the number of lanes of the link between the first PCIe device and the second PCIe device is 16, and therefore the lane negotiation capability value M of the first PCIe device acquired by the CPU 501 is 16. The current lane width value N is 4.

  The CPU 501 compares the acquired lane negotiation capability value M and the current lane width value N. In the present invention, the CPU 501 compares N and M / 2 according to the rule of the number of lanes of links between two PCIe devices.

  When N <M / 2, the CPU 501 performs the lane inversion process, that is, the first PCIe to renumber the lanes of the link 504 between the first PCIe device 503 and the second PCIe device 505 in the opposite direction. Instruct the lane inversion module 5039 of the device 503. For example, as shown in FIG. 5, currently the lanes of link 504 are sequentially numbered from left to right starting at 0 and ending at 15. When the lane inversion process is executed, the lane number of the lane number 15 of the link 504 is changed from 15 to 0, that is, the lane number 15 is changed to lane number 0, the lane number of the lane number 14 is changed to 1, That is, lane number 14 is changed to lane number 1, and the rest can be derived in the same manner. After the lane inversion process is performed, the lanes of link 504 are sequentially numbered from 0 to 15 starting from 0 to the right. After the lane reversal module 5039 of the first PCIe device 503 completes the lane reversal process, the negotiate module 5035 then resumes lane negotiation for the link 504 between the first PCIe device 503 and the second PCIe device 505, and a new The current lane width value N ′ is determined and the negotiation method is the same as described above and will not be re-explained here separately. The first PCIe device 503 performs data transmission with the second PCIe device 505 by using the new current lane width acquired by the negotiation. Since N <M / 2 indicates that the lane number of the failed lane is less than (M / 2-1), the new current lane width value acquired by renegotiation is M / 2 or more. In this case, it is possible to guarantee that the lane width value acquired by renegotiation after a failure occurs in the lane of the link 504 is M / 2 or more, and the transmission performance of the link 504 is guaranteed.

  When N <M / 2, the CPU 501 further invalidates the lane number 0 to lane number (M / 2-1) of the link 504 between the first PCIe device 503 and the second PCIe device 505 first, and then the lane The lane inversion module 5039 of the first PCIe device 503 is instructed to execute the inversion process. Since N <M / 2 and the current lane width obtained by negotiation is less than M / 2, it indicates that the lane number of the failed lane is less than (M / 2-1). No failure occurs from lane number M / 2 to lane number M, and data transmission can be executed. As described above, when the CPU 501 invalidates the lane number 0 to the lane number (M / 2-1) of the link 504 and executes the lane inversion process, the lane inversion module 5039 of the first PCIe device 503 causes the lane number M / Until the lane number of 2 is changed from M / 2 to (M / 2-1), the lane number of lane number M is changed from M to 0, and the lane number of lane number (M-1) is changed to (M- For example, change from 1) to 0. Since the original lane number 0 to the original lane number (M / 2-1) of the link is invalidated, the lane inversion module 5039 of the first PCIe device 503 performs lane inversion for these invalidated lanes. No longer run. After the lane inversion is completed, the negotiate module 5035 resumes lane negotiation for the link 504 between the first PCIe device 503 and the second PCIe device 505, and determines a new current lane width value N ′. In this case, a new lane number 0 to a new lane number (M / 2-1) of the link 504 can be used for communication. That is, after a failure occurs in the lane of the link 504, the lane width value acquired by renegotiation is equal to M / 2, and the transmission performance of the link 504 is guaranteed.

When N ≧ M / 2, it indicates that the current lane width of the link between the first PCIe device 503 and the second PCIe device 505 is M / 2 or more, and in this case, the performance of the link 504 is the maximum. Hold up. The CPU 501 does not execute processing. If the 1PCIe device 503 does not receive an indication of CPU501 within a predetermined time limit, the 1PCIe device 503, by using the current lane width N acquired by the negotiation data between the first 2PCIe 504 5 Perform transmission. The transmission performance of the link 504 is also guaranteed.

  In this embodiment of the present invention, the lane negotiation capability value M of the first PCIe device 503 is 16, a failure occurs in the lane number 5 of the link 504, and the negotiation module 5035 of the first PCIe device re-negotiates with the second PCIe device 505. The current lane width value N obtained by doing this is 4. In this case, 4 <16/2, that is, N <M / 2, and the CPU 501 invalidates the lane numbers 0 to 7 of the link 504 and executes the lane inversion so that the first PCIe device 503 performs the lane inversion. The lane inversion module 5039 is instructed. The lane inversion module 5039 of the first PCIe device 503 changes the lane number of the lane number 15 of the link 504 to 0 and changes the lane number of the lane number 14 to 1 until the lane number of the lane number 8 is changed to 7. To do. Since the original lane number 0 through the original lane number 7 of the link 504 have been invalidated, the lane inversion module 5039 no longer numbers them. In this way, the link 504 between the first PCIe device 503 and the second PCIe device 505 currently includes eight lanes. The negotiation module 5035 of the first PCIe device 503 performs lane renegotiation with the second PCIe device 505 in order to obtain a new current lane width value N ′ of 8. The first PCIe device 503 continues to execute data transmission with the second PCIe device 505 by using the eight lanes of the link 504.

  Thus, by utilizing the technical measures provided in the present invention, if a failure occurs in the lane of a link between two PCIe devices, the two PCIe devices will be half the lane of the original link. Can be provided to continue to perform data transmission regardless of the number of the failed lane, which relaxes the lane number limitation of the failed lane imposed on the link width in the prior art, thereby providing the optimum Link width can be achieved after renegotiation.

As used herein, an entity or process having a relational word such as first and second is only used to distinguish it from others, and there is any actual relationship or sequence between these entities or processes. It should be further noted that this is not necessarily necessary or implied. Further, the terms “comprising”, “comprising” or any other variation thereof are intended to cover non-exclusive inclusions, whereby a process, method, article or device including a list of elements is included. In addition to including these elements, other elements not explicitly listed are also included, or further elements specific to the process, method, article or device are included. An element preceding “comprising” does not exclude the presence of additional identical elements in a process, method, article or device that includes the elements without further restriction.
Those skilled in the art may implement or utilize the invention in accordance with the above description of the disclosed embodiments. The normal principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Accordingly, the present invention is not limited to the embodiments described herein, but extends to the widest scope consistent with the principles and novelty disclosed herein.

Claims (6)

A method of handling a Peripheral Component Interconnect Express (PCIe) link failure, comprising:
The PCIe device detects that a failure has occurred in the lane of the link between the PCIe device and a downstream PCIe device, and sends a message signaled interrupt (MSI) message to the central processing unit (CPU). The MSI message has a device ID of the PCIe device;
The PCIe device negotiates with the downstream PCIe device to obtain a current lane width value N;
The CPU obtaining the PCIe device lane negotiation capability value M and the current lane width value N from the PCIe device according to the device ID in the received MSI message;
Said CPU comparing N and M / 2;
If N <M / 2, the CPU instructs the PCIe device to perform lane inversion processing;
The PCIe device performs the lane inversion process on a link between the PCIe device and the downstream PCIe device;
The PCIe device negotiates with the downstream PCIe device to obtain a new current lane width value N ′, and uses N ′ (N ′ ≧ 1) lanes to communicate with the downstream PCIe device. Continuing to perform data transmission;
The CPU invalidating the lane number 0 to the lane number (M / 2-1) of the link between the PCIe device and the downstream PCIe device;
Having a method. The method further includes:
If it is N ≧ M / 2, the PCIe device, by utilizing the N lanes obtained by the negotiation, including the step of continuing to perform data transmission with the downstream PCIe device, according to claim 1, wherein the method of. A method of handling a Peripheral Component Interconnect Express (PCIe) link failure, comprising:
Receiving a message signaled interrupt (MSI) message reported by a PCIe device, the MSI message having a device ID of the PCIe device;
Obtaining a lane negotiation capability value M and a current lane width value N of the PCIe device from the PCIe device according to the device ID, the current lane width value N being negotiated with a downstream PCIe device by the PCIe device; A step of obtaining, obtained by
Comparing N and M / 2;
If N <M / 2, instructing the PCIe device to perform lane inversion processing;
Invalidating lane number 0 to lane number (M / 2-1) of the link between the PCIe device and the downstream PCIe device;
Having a method. 4. The method of claim 3 , wherein the lane negotiation capability value M of the PCIe device is equal to the total number of lanes on the link between the PCIe device and the downstream PCIe device. A method of handling a Peripheral Component Interconnect Express (PCIe) link failure, comprising:
The PCIe device detects that a failure has occurred in a lane of a link between the PCIe device and a downstream PCIe device, and sends a message signaled interrupt MSI message to a central processing unit (CPU), Transmitting the MSI message having a device ID of the PCIe device;
Negotiating with the downstream PCIe device to obtain a current lane width value N;
Receiving an instruction to perform lane inversion processing transmitted by the CPU, and executing the lane inversion processing for a link between the PCIe device and the downstream PCIe device;
Negotiating with the downstream PCIe device to obtain a new current lane width value N ′ and continuing to perform data transmission with the downstream PCIe device by using N ′ lanes;
If the PCIe device does not receive the instruction to execute the lane inversion processing transmitted by the CPU within a predetermined time, the PCIe device uses the N lanes to Continuing to execute the data transmission of
Having a method. A system for handling Peripheral Component Interconnect Express (PCIe) link failures, comprising:
The system includes a central processing unit (CPU), a PCIe device, and a downstream PCIe device, and the CPU is connected to the PCIe device, and the PCIe device is connected to the downstream PCIe device by using a link. ,
The PCIe device detects whether a failure has occurred in the lane of the link between the PCIe device and the downstream PCIe device, and reports a message signaled interrupt (MSI) message to the CPU when the failure occurs. The MSI message has a device ID of the PCIe device, and the PCIe device is further configured to negotiate with the downstream PCIe device to obtain a current lane width value N;
The CPU obtains the lane negotiation capability value M and the current lane width value N of the PCIe device from the PCIe device according to the device ID in the MSI message, compares N with M / 2, and N <M / When 2, the lane inversion process is instructed to the PCIe device, and the lane number 0 to lane number (M / 2-1) of the link between the PCIe device and the downstream PCIe device is invalidated. is configured to,
The PCIe device further executes the lane inversion processing for the link between the PCIe device and the downstream PCIe device after receiving the instruction to execute the lane inversion processing transmitted by the CPU. A system configured to negotiate with the downstream PCIe device to obtain a current lane width value N ′.

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