JP6102511B2 - Integrated circuit, control apparatus, control method, and control program - Google Patents

Description

  The present invention relates to an integrated circuit, a control device, a control method, and a control program.

  Conventionally, there is a technique in which a plurality of users can use a plurality of FPGAs via a server by connecting a plurality of FPGAs (Field Programmable Gate Array) to the server (see, for example, Patent Document 1 below). . For example, the server controls the FPGA that is being used by the user not to be used by other users.

U.S. Pat. No. 7,376,917

  However, when a plurality of users jointly use the same FPGA, there may be interference between users when accessing the storage area of the user via the FPGA. For this reason, there exists a problem that a user's processing environment becomes unstable.

  In one aspect, an object of the present invention is to provide an integrated circuit, a control device, a control method, and a control program that can stabilize a processing environment of a user.

  According to one aspect of the present invention, an integrated circuit can reconfigure an internal circuit, and partial circuits assigned to each of a plurality of computers are configured in different areas. Each of the different storage areas allocated to each of the partial circuits is accessible, accepts an access request from any of the partial circuits, and the access destination indicated by the received access request is the request source of the access request If the storage area is allocated to the partial circuit, the access unit executes access based on the access request, and if it is not the allocated storage area, the access unit does not execute access based on the access request. An integrated circuit and a control method are proposed.

  According to another aspect of the present invention, the control device is an integrated circuit in which an internal circuit can be reconfigured, and an integrated circuit in which partial circuits assigned to each of a plurality of computers are configured in different regions. Connected. An access request to the integrated circuit is received from any of a plurality of computers, and the access destination indicated by the received access request is an area in which a partial circuit assigned to the requesting computer of the access request is configured. In some cases, a control device, a control method, and a control program that execute access based on the access request and that do not execute access based on the access request when the area is not configured are proposed.

  According to one aspect of the present invention, the user's processing environment can be stabilized.

FIG. 1 is an explanatory diagram of an operation example 1 of the system according to the present embodiment. FIG. 2 is an explanatory diagram of an operation example 2 of the system according to the present embodiment. FIG. 3 is an explanatory diagram showing a detailed example of the system. FIG. 4 is a block diagram illustrating a hardware configuration example of the terminal and the server. FIG. 5 is an explanatory diagram of an example of software execution by the server. FIG. 6 is an explanatory diagram showing an example of a flow at the start of use of the system. FIG. 7 is an explanatory diagram illustrating an example of a development system. FIG. 8 is a flowchart illustrating an example of a generation processing procedure by a server that executes a virtual machine generation program. FIG. 9 is a flowchart illustrating an example of an initial setting process procedure by the server during operation. FIG. 10 is an explanatory diagram illustrating a data flow example of a server that executes an acceptance inspection program. FIG. 11 is a block diagram illustrating a functional configuration example of the server. FIG. 12 is an explanatory diagram of an example of memory allocation. FIG. 13 is an explanatory diagram showing a detailed example of the storage area allocated to each user module. FIG. 14 is a block diagram illustrating an example of each user module configured in the FPGA. FIG. 15 is an explanatory diagram of a setting example of the access permission setting register. FIG. 16 is an explanatory diagram showing an example of correspondence between user modules and ports. FIG. 17 is an explanatory diagram illustrating an example of a table included in the device driver. FIG. 18 is an explanatory diagram of an example of access from the virtual machine to the user module. FIG. 19 is an explanatory diagram illustrating an example of access from the user module to the memory in the server. FIG. 20 is an explanatory diagram illustrating a detailed example of the address determination process. FIG. 21 is an explanatory diagram showing a detailed example of the data amount restriction process.

  In this embodiment, a plurality of different users are configured in the same FPGA. In the present embodiment, a computer assigned to each of a plurality of users accesses the FPGA via a server that is a control device.

  In addition, when a plurality of users use the same FPGA jointly, when accessing the user's storage area via the FPGA, the FPGA is connected to a computer bus such as a server. Can be accessed even in the storage area. Therefore, interference between users may occur. In the present embodiment, when accessing a user's storage area via the FPGA, the management module in the FPGA controls not to access the storage area of a different user.

  In addition, when a plurality of users use the same FPGA jointly, when the plurality of users access the FPGA, the user can access the circuits of different users in the FPGA. Interference may occur. In the present embodiment, when the user accesses the FPGA, the server controls so as not to access the circuits of different users.

  Exemplary embodiments of an integrated circuit, a control device, a control method, and a control program according to the present invention will be explained below in detail with reference to the accompanying drawings.

  FIG. 1 is an explanatory diagram of an operation example 1 of the system according to the present embodiment. The system 100 includes a server 111, a computer 121 assigned to each of a plurality of users, and an FPGA 101 connected to the server 111. A detailed example of the system 100 is shown in FIG.

  The server 111 is a control device that can control access from the computer 121 to the FPGA 101. The FPGA 101 is an integrated circuit that can reconfigure an internal circuit. In the example of FIG. 1, the FPGA 101 includes a user module 102-1, a user module 102-2, and a management module 103 as partial circuits. For example, the software that reconfigures the internal circuit of the FPGA 101 has a partial configuration function that allows the user module 102 to be configured only in a permitted area in the FPGA 101. Therefore, in the FPGA 101, the user module 102-1, the user module 102-2, and the management module 103 can be configured in different areas. For example, the user module 102-1 is assigned to the computer 121-1, and can be accessed by the computer 121-1. For example, the user module 102-2 is assigned to the computer 121-2 and can be accessed by the computer 121-2. For example, the computer 121-1 and the computer 121-2 have different users. The computer 121 assigned to each of a plurality of users may be a physical device as shown in FIG. 1 or may be a virtual machine constructed on the server 111.

  The management module 103 includes an access unit 104, a reception unit 105, and a control unit 106. The access unit 104 can access each of the different storage areas 112 assigned to each of the user modules 102. The access unit 104 has, for example, a DMA (Direct Memory Access) function. The accepting unit 105 accepts an access request from either the user module 102-1 or the user module 102-2. In the example of FIG. 1, the accepting unit 105 accepts an access request from the user module 102-1. When the access unit 104 implements the DMA function, specifically, the access request has a DMA parameter. The DMA parameters include, for example, a transfer direction, a transfer destination address, a transfer source address, and a data length. The transfer direction is either from the FPGA 101 to the server 111 or from the server 111 to the FPGA 101.

  For example, the control unit 106 includes a storage unit 107. The storage unit 107 stores information indicating the storage area 112 allocated to the user module 102 for each user module 102. The storage area 112 may be a memory area in the server 111 connected to the FPGA 101. The information indicating the storage area 112 is, for example, an address indicating the storage area 112. Alternatively, when the computer 121-1 and the computer 121-2 are physical computers 121, the storage area 112 may be a memory area provided in each computer 121. The information indicating the storage area 112 is, for example, an address of the storage device. For example, the user module 102-1 is the storage area 112-1 indicated by number 0 to 100, and the user module 102-2 is the storage area 112-2 indicated by number 300 to 400.

  When the access destination indicated by the access request received by the receiving unit 105 is the storage area 112-1, the control unit 106 causes the access unit 104 to perform access based on the access request. For example, the control unit 106 causes the access unit 104 to perform access based on an access request to the storage area 112-1 indicated by the numbers 0 to 100 from the user module 102-1.

  On the other hand, if the storage unit 112-1 is not allocated, the control unit 106 does not cause the access unit 104 to perform access based on the access request. For example, the control unit 106 does not cause the access unit 104 to perform access based on an access request to the storage area 112-2 indicated by the numbers 300 to 400 from the user module 102-1.

  As shown in FIG. 1, a storage area assigned to another circuit in the FPGA 101 that can be used by another user is not accessed from a circuit in the FPGA 101 that can be used by a certain user. Accordingly, it is possible to prevent a user having a storage area of another user from being interfered with an available circuit. Therefore, the processing environment of each user can be made to function stably.

  FIG. 2 is an explanatory diagram of an operation example 2 of the system according to the present embodiment. Since the system 100 uses the same example as in FIG. 1, detailed description is omitted. The server 111 includes a receiving unit 211 and a control unit 212.

  The accepting unit 211 accepts an access request to the FPGA 101 from any one of the plurality of computers 121. In the example of FIG. 2, the control unit 212 receives an access request from the computer 121-1.

  The control unit 212 includes a storage unit 213. The storage unit 213 stores information indicating the storage area 201 in which the user module 102 assigned to the computer 121 is configured for each of the plurality of computers 121. For example, the information indicating the area in which the user module 102 is configured is an address indicating the storage area 201 in which the memory in the user module 102 is configured in the memory of the FPGA 101.

  When the access destination indicated by the received access request is an area in which the user module 102 assigned to the requesting computer 121 is configured based on the storage contents of the storage unit 213, the control unit 212 accesses Perform request-based access. For example, the control unit 212 executes access based on an access request from the computer 121-1 to the storage area 201-1 indicated by the numbers 0 to 100 in the memory in the FPGA 101.

  On the other hand, the control unit 212 does not execute access based on the access request when the user module 102 allocated to the requesting computer 121 is not configured based on the storage content of the storage unit 213. For example, the control unit 212 does not execute access based on an access request to the storage area 201-2 indicated by the numbers 300 to 400 of the memory in the FPGA 101 from the computer 121-1.

  As shown in FIG. 2, the FPGA 101 does not access a user module 102 in the FPGA 101 assigned to another user from a certain user. Accordingly, it is possible to prevent the user module in the FPGA 101 assigned to another user from being interfered by a certain user. Therefore, the processing environment of each user can be made to function stably.

  FIG. 3 is an explanatory diagram showing a detailed example of the system. In the system 100, a plurality of users realize a desired circuit using the FPGA 101 connected to a server in the data center 301. The system 100 includes a terminal 302 and a data center 301. The data center 301 has a plurality of servers.

  The terminal 302 is a device that can be directly operated by the user. In the example of FIG. 3, since there are two users, the terminal 302-1 and the terminal 302-2 are shown. The terminal 302 is, for example, a PC (Personal Computer) or a workstation.

  Specifically, the data center 301 includes, for example, servers 304-1 and 304-2 for the development system 303 for generating configuration data for causing the FPGA 101 to program. In addition, the data center 301 includes a server 111 connected to the FPGA 101 in which an internal circuit is configured by programming configuration data. A plurality of development systems 303 and servers 111 are prepared according to the assumed total number of users.

  The data center 301 includes a database server 306 that stores a server pool database 332 and an FPGA database 331. The database server 306 for the server pool database 332 and the database server 306 for the FPGA database 331 may be separately provided.

  The data center 301 includes a server 305 that executes a virtual machine generation program 321 described later and a server 307 that executes an acceptance inspection program 322 described later. Further, the data center 301 includes a control server 308 that executes an overall control program 323 that controls the entire system 100 according to the present embodiment. The data center 301 includes a general operation management server 309.

  Here, the computer 121 illustrated in FIGS. 1 and 2 may be the terminal 302 or the virtual machine VM, but in this embodiment, the virtual machine VM is taken as an example. By using the virtual machine VM, the time required for communication can be shortened. Each user configures a desired user module 102 by the FPGA 101 connected to the server 111 and constructs a virtual machine VM on the server 111. Thus, each user can exchange data between the application software executed on the virtual machine VM realized by the server 111 and the user module 102 configured in the FPGA 101. In the example of FIG. 3, the server 111 constructs a virtual machine VM1 assigned to the terminal 302-1 and a virtual machine VM2 assigned to the terminal 302-2. The virtual machine VM1 is assigned to the user module 102-1, and the virtual machine VM2 is assigned to the user module 102-2.

  FIG. 4 is a block diagram illustrating a hardware configuration example of the terminal and the server. The server 111 includes, for example, a CPU 411, a memory 412, a disk 413, a disk drive 414, a PCIe (Peripheral Component Interconnect express) 415, and a network interface 416.

  The server 111 is connected to the expansion board 401 on which the FPGA 101 is mounted by the PCIe 415. The PCIe 415 is a kind of interface. The expansion board 401 includes, for example, an FPGA 101, a memory 402 external to the FPGA 101, an I / O (Input / Output) interface 403, and the like. The server 111 is connected to a terminal 302 that can be directly operated by a user via a network NET through a network interface 416.

  First, the CPU 411 governs overall control of the server 111. The memory 412 is a storage unit used as a work area for the CPU 411. Examples of the memory 412 include a RAM (Random Access Memory). The disk drive 414 controls data read / write with respect to the disk 413 according to the control of the CPU 411. The disk 413 is a storage unit that stores data written under the control of the disk drive 414. Examples of the disk 413 include a magnetic disk and an optical disk.

  The network interface 416 is connected to a network NET such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and is connected to other devices via the network NET. The network interface 416 serves as an internal interface with the network NET, and controls data input / output from an external device. As the network interface 416, for example, a modem or a LAN adapter can be employed.

  The various servers in the data center 301 have the same hardware configuration as the server 111.

  Examples of the terminal 302 include a PC and a workstation. The terminal 302 includes, for example, a CPU 421, a memory 422, a disk 423, a disk drive 424, an input device 425, an output device 426, and a network interface 427.

  The CPU 421 governs overall control of the terminal 302. The memory 422 is a storage unit used as a work area for the CPU 421. The disk drive 424 controls reading / writing of data with respect to the disk 423 according to the control of the CPU 421. The disk 423 stores data written under the control of the disk drive 424. Examples of the disk 423 include a magnetic disk and an optical disk.

  The network interface 427 is connected to a network NET such as a LAN, a WAN, or the Internet through a communication line, and is connected to another device via the network NET. The network interface 427 serves as an internal interface with the network NET, and controls data input / output from an external device. As the network interface 427, for example, a modem or a LAN adapter can be employed.

  The input device 425 is an interface for inputting various data by a user operation such as a keyboard, a mouse, and a touch panel. The input device 425 can also capture images and moving images from the camera. The input device 425 can also capture audio from a microphone. The output device 426 is an interface that outputs data in accordance with an instruction from the CPU 421. Examples of the output device 426 include a display and a printer.

  FIG. 5 is an explanatory diagram of an example of software execution by the server. The server 111 executes a hypervisor HV, a virtual machine VMc that executes a management OS (Operating System) 501-c, and the like when the CPU 411 loads a program stored in a storage device such as the disk 413. For example, the server 111 executes the virtual machine VMc and the hypervisor HV that controls each of the virtual machines VMx (x = 1, 2 in FIG. 5) assigned to each of the terminals 302.

  For the purpose of explanation, the virtual machine VM, OS 501, application software 503, and device driver 502 are executed by the server 111. Here, however, they will be described as execution subjects for explanation. The virtual machine VMc executes a management OS 501-c, a device driver 502-c called by the management OS 501-c, and software 503-c executed by the management OS 501-c. The software 503-c is a program that manages the entire virtual machine VM assigned to the terminal 302. The device driver 502-c is software that controls the expansion board 401 and provides an interface to each application software 503.

  Each virtual machine VMx assigned to the terminal 302-x executes the OS 501-x. The virtual machine VMx executes a device driver 502-x called by the OS 501-x and application software 503-x executed by the OS 501-x. The device driver 502-x controls access to the user module 102-x in the FPGA 101 assigned to each of the virtual machines VMx.

(At start of use)
FIG. 6 is an explanatory diagram showing an example of a flow at the start of use of the system. The server 308 that executes the overall control program 323 controls the entire system by controlling the development system 303, the server 305, the server 307, the server 111, and the like. The overall control program 323 is stored in a storage device such as a disk 413 in the control server 308, and the CPU 411 in the server 308 reads the overall control program 323 from the storage device and executes it. Thereby, the function coded in the overall control program 323 is realized. Specifically, the server 308 assigns the development system 303 so that the user can operate in accordance with an instruction from each user. The server 308 performs overall control such as requesting the server 307 that executes the acceptance inspection program 322 and the server 305 that executes the virtual machine generation program 321 to perform processing.

  Each user designs the user module 102 operating on the FPGA 101 by the development system 303. The development system 303 generates configuration data indicating the user module 102 designed by the user.

  In addition, the server 305 determines the server 111 on which the virtual machine VM can be placed, based on the virtual machine specification definition file 611 and the virtual machine VM registered in the server pool database 332. The virtual machine specification definition file 611 includes information indicating the specifications of the virtual machine VM, identification information indicating configuration data, and the like. The information indicating the specifications of the virtual machine VM indicates specifications of the CPU, memory, disk, network interface, and the like. The user determines the specifications of the virtual machine and inputs the virtual machine specification definition file 611 to the data center 301 via the terminal 302. Further, the server 307 determines whether or not the user module 102 designed by the user can be configured in the FPGA 101 of the expansion board 401 connected to the determined server 111.

  FIG. 7 is an explanatory diagram illustrating an example of a development system. The data center 301 includes a server 304-1 connected to the expansion board 704, a server 304-2 executing the FPGA development software 703, and a gateway 701. The expansion board 704 is a board similar to the expansion board 401.

  The FPGA programming cable 705 connects the server 304-2 and the expansion board 704. The management module 103 may be configured in advance on the expansion board 704. The FPGA programming cable 705 can write configuration data indicating the user module 102 designed by the server 304-2 to the expansion board 704 by JTAG. Also, the FPGA programming cable 705 can refer to or change the internal state in the FPGA 101. The terminal 302 is connected to the gateway 701 of the data center 301 via the network NET. The user designs and debugs the user module 102 using the FPGA development software 703 being executed by the server 304-2 via the terminal 302. Further, the server 304-2 may be constructed as a virtual machine VM on the server 304-1.

  Since the user can access the entire inside of the FPGA 101 of the expansion board 704 by JTAG, the development system 303 is restricted from being used by a plurality of users at the same time by the server 308 that executes the overall control program 323. May be. Therefore, a plurality of development systems 303 are prepared according to the number of users assumed.

  Further, when the user occupies the server 304-1, the development system 303 is provided with a function of the remote control 702, and a mechanism capable of powering on or off the server 304-1, resetting, console access, etc. is prepared. The

  FIG. 8 is a flowchart illustrating an example of a generation processing procedure by a server that executes a virtual machine generation program. For example, the virtual machine generation program 321 is stored in a storage device such as the disk 413 in the server 305, and the CPU 411 in the server 305 reads the virtual machine generation program 321 from the storage device and executes it. Thereby, the function coded in the virtual machine generation program 321 is realized.

  First, the server 305 receives a virtual machine specification definition file 611 and configuration data 802 (step S801). As described above, the virtual machine specification definition file 611 includes information indicating the specifications of the virtual machine VM, identification information indicating the configuration data 802, and the like.

  Next, the server 305 searches the server pool database 332 and identifies the server 111 on which the virtual machine VM indicated by the virtual machine specification definition file 611 can be placed (step S802). Then, the server 305 determines whether or not there is an unselected server 305 in the identified server 111 (step S803). The server pool database 332 stores information indicating what virtual machine VM is operating on each server 111 used during operation, resource information assigned to each virtual machine VM, and the like. The resource information assigned here includes information indicating the CPU in the server 111, the storage area in the memory 412, the storage area in the disk 413, etc., assigned to each virtual machine VM. The resource information includes information indicating which user module 102 is configured in the FPGA 101 connected to the server 305.

  When there is an unselected server 111 (step S803: Yes), the server 305 selects one server 111 from the unselected servers 111 (step S804). The server 305 searches the FPGA database 331 and confirms whether the FPGA 101 of the expansion board 401 connected to the selected server 111 can be used (step S805). The server 305 determines whether the FPGA 101 can be used (step S806). If it is not available (step S806: No), the server 305 returns to step S803.

  If it is available (step S806: Yes), the server 305 proceeds to step S807. The server 305 lays out the user module 102 using the FPGA 101 design tool based on the configuration data 802 from the development system 303. Then, the server 305 generates configuration data 803 to be written in the FPGA 101 connected to the selected server 111 (step S807). Next, the server 305 generates a virtual machine definition file 804 (step S808), the server 305 transfers the virtual machine definition file 804 to the selected server 111 (step S809), and ends a series of processing. The virtual machine definition file 804 includes information indicating the specifications of the virtual machine VM, a disk image such as a memory or a disk included in the virtual machine VM, the configuration data 803 generated in step S807, and the like.

  In step S803, when there is no unselected server 111 (step S803: No), the server 305 outputs an error (step S810) and ends a series of processing.

  FIG. 9 is a flowchart illustrating an example of an initial setting process procedure by the server during operation. The server 111 determines whether the virtual machine definition file 804 has been received (step S901). If the virtual machine definition file 804 has not been received (step S901: NO), the server 111 returns to step S901. When the virtual machine definition file 804 is received (step S901: Yes), the server 111 executes the inspection program 322 that accepts whether the user module 102 indicated by the configuration data 803 is reconfigured only in the permitted area. Confirmation is requested to 307 (step S902).

  The server 111 determines whether or not reconfiguration is possible (step S903). When reconfiguration is possible (step S903: Yes), the server 111 constructs a virtual machine VM by the hypervisor HV (step S904). The server 111 configures the user module 102 in the FPGA 101 by using the partial reconfiguration function by the management OS 501-c (step S905). The server 111 sets the physical address range of the memory 412 accessible by the user module in an access permission setting register (to be described later) in the management module 103 in the FPGA 101 by the management OS 501-c (step S906).

  Next, the server 111 recognizes the new user module 102 in the FPGA 101 by using the device driver 502 (step S907). Then, the server 111 activates the virtual machine VM with the hypervisor HV (step S908), and ends a series of processing. As a result, the user executes application software on the virtual machine VM, and the user module 102 configured in the FPGA 101 can be used. On the other hand, if reconfiguration is not possible in step S903 (step S903: No), the server 111 outputs an error (step S909) and ends a series of processing.

  FIG. 10 is an explanatory diagram illustrating a data flow example of a server that executes an acceptance inspection program. The acceptance inspection program 322 is stored in, for example, a storage device such as the disk 413 in the server 307, and the CPU 411 in the server 307 reads the acceptance inspection program 322 from the storage device and executes it.

  The server 307 receives the configuration data 803 and the device information 1001 as input by the acceptance inspection program 322. The device information 1001 includes information on the area of the FPGA 101 that can be programmed by the user, information on the area that the device maps to the address space, and the like. Based on the FPGA database 331, the server 307 determines, by the acceptance inspection program 322, which FPGA 101 in the data center 301 can be configured by the user module 102 designed by the user. In addition, the server 307 actually writes to the FPGA 101 connected to the server 311, and checks whether the area of the management module 103, another user module 102, etc. has been changed by a CRC (Cyclic Redundancy Check) checksum or the like. May be. The server 307 registers the inspection result in the FPGA database 331 when the acceptance inspection program 322 determines that it is acceptable.

  For example, as an inspection result, 1. 1. identification information indicating configuration data 803; Configuration data 803,3. 3. Identification information of creator, Usage permission information, 5. Modification permission information, 6. Device type information is registered in the FPGA database 331. The creator identification information may be, for example, user name information or identification information of the terminal 302 that can be operated by the user. The usage permission information is information indicating which user or terminal 302 can use the configuration data 803. With the use permission information, a plurality of users can share the configuration data 803, and a plurality of users can use the user module 102 having the same function. The modification permission information is information indicating which user or terminal 302 can change the configuration data 803. The device type information is information indicating which type of FPGA 101 can be used.

(Example of functional configuration of server 111)
FIG. 11 is a block diagram illustrating a functional configuration example of the server. The server 111 includes a reception unit 211, a control unit 212, and a measurement unit 1101. The reception unit 211, the control unit 212, and the measurement unit 1101 are coded in the device driver 502-c of the management OS 501-c, for example, and the server 111 executes the management OS 501-c by the virtual machine VMc. Thereby, the reception part 211, the control part 212, and the measurement part 1101 are implement | achieved.

  Further, the measurement unit 1101 may be provided in the management module 103 instead of the function of the server 111. When the measurement module 1101 is provided in the management module 103, the control unit 212 has a function of acquiring a data amount from the management module 103.

  FIG. 12 is an explanatory diagram of an example of memory allocation. In the virtual machine environment, two-stage address translation is performed. A virtual address space 1211-c and a physical address space 1213 for accessing various devices such as the memory 412 and the FPGA 101 are associated with the virtual machine VMc. The virtual address space 1211-c of the virtual machine VMc includes, for example, a memory address space used by the management OS 501-c. In the memory used by the management OS 501-c, for example, a table 1201 for converting a logical address into a physical address is stored. The virtual address space 1211-c of the virtual machine VMc has, for example, respective address spaces of a memory used by various device drivers 502-c and a memory used by software 503-c. The memory used by the device driver 502-c stores an accumulated data amount counter for measuring the amount of data transferred by the server 111. This accumulated data amount counter is the measuring unit 1101.

  The virtual machine VMx assigned to the terminal 302-x is associated with the virtual address space 1211-x and the physical address space 1213 for accessing the user module 102-x assigned to the virtual machine VM-x. It is done. The virtual address space 1211-x of the virtual machine VMx includes, for example, an address space of a memory used by the OS 501-x. The memory used by the OS 501-x includes, for example, a table 1202 for converting a logical address into a physical address. Further, the virtual address space 1211-x of the virtual machine VM-x has an address space of a memory used by the device driver 502-x for the user module 102-x. Further, the virtual address space 1211-x of the virtual machine VMx has a virtual address space of a memory used by the application software 503-x. The memory used by the device driver 502-x and the memory used by the application software 503-x are, for example, the buffer memory 1203, and at least the memory used by the application software 503-x by the device driver 502-x. Either one. The buffer memory 1203 is a memory for transferring data between the FPGA 101 and the device driver 502-x or application software 503-x.

  The virtual address space 1212 is recognized at the level of the hypervisor HV. The physical address space 1213 includes an area used by each OS, device driver 502, and application in the memory 412, and a memory used by each user module 102 in the FPGA 101. An MMU (Memory Management Unit) included in the CPU 411 performs address conversion between the virtual address space 1211 and the virtual address space 1212 of each virtual machine VM. Further, the MMU included in the CPU 411 performs address conversion between the virtual address space 1212 and the physical address space 1213.

  FIG. 13 is an explanatory diagram showing a detailed example of the storage area allocated to each user module. For example, the I / O memory used by the management OS 501-c in the virtual address space 1211 is the storage area ac, the storage area au 1, and the storage area au 2 in the physical address space 1213. The storage area ac is an area in the memory 412 allocated to the management module 103. The storage area au1 is an area in the memory 412 allocated to the user module 102-1. The storage area au2 is an area in the memory 412 allocated to the user module 102-2.

  The memory used by the virtual machine VM1 in the virtual address space 1211 is a storage area a1 in the memory 412 in the physical address space 1213. The I / O memory used by the virtual machine VM1 in the virtual address space 1211 is the storage area au1 in the physical address space 1213. The memory used by the virtual machine VM2 in the virtual address space 1211 is a storage area a2 in the memory 412 in the physical address space 1213. The I / O memory used by the virtual machine VM2 in the virtual address space 1211 is the storage area au2 in the physical address space 1213.

  The address range indicating the storage area ac is e0000000 to e00fffff. The address range indicating the storage area au1 is e0100000 to e01fffff. The address range indicating the storage area au2 is e0200000 to e02fffff.

(Each user module 102 configured in the FPGA 101)
FIG. 14 is a block diagram illustrating an example of each user module configured in the FPGA. The FPGA 101 includes a management module 103 and a user module 102. The management module 103 includes a DMA circuit 1403, a reconfiguration circuit 1404, a PCIe 1405, a control circuit 1406, a memory controller 1407, and a memory 1408. The user module 102 is designed by the user and assigned to the user terminal 302 as described above. The user module 102 includes a memory 601 and a circuit 1401. The management module 103 and the user module 102 are connected via a port 1402. The management module 103 can determine the requesting user module 102 based on which port 1402 the access request is received through.

  The DMA circuit 1403 has a register 1411 for setting DMA parameters. As described above, the DMA parameters include, for example, the transfer direction, the transfer destination address, the transfer source address, and the data length. The transfer direction is either from the FPGA 101 to the server 111 or from the server 111 to the FPGA 101. The control circuit 1406 includes an accumulated data amount counter 1412 and an access permission setting register 1413. The accumulated data amount counter 1412 is a measuring unit that measures the amount of data by the DMA circuit 1403 based on an access request from the user module 102. The access permission setting register 1413 is a storage unit 107 that stores information indicating a storage area allocated to the virtual machine VM associated with the user module 102 for each user module 102 in the memory 412 in the server 111. is there.

  The access permission setting register 1413 is a storage unit 107 that stores, for each user module 102, an address range indicating an accessible area in the memory 412 and a transfer amount restriction value. For example, in the access permission setting register 1413, when the user module 102 is configured by the management OS 501-c, information indicating an address range and a data amount limit value are set for the memory 412 by the management OS 501-c. Is done. A setting example is shown in FIG.

  The access permission setting register 1413 stores information indicating access permission of the memory 402, the memory 602, the I / O interface 403, and the like for each user module 102. For example, when the user module 102 is configured by the management OS 501-c, information indicating access permission is set in the access permission setting register 1413 by the management OS 501-c for the memory 402, the memory 602, and the I / O interface 403. Is done. Therefore, access from the user module 102 to the memory 402, the memory 602, the I / O interface 403, and the like is performed via the control circuit 1406. Although detailed examples of access from the user module 102 to the memory 402, the memory 602, the I / O interface 403, and the like are omitted, it is determined whether or not the control circuit 1406 is accessible in the same manner as the access from the user module 102 to the memory 412. to decide.

  The reconfiguration circuit 1404 has a function of configuring the port 1402 and the like when the user module 102 is configured in the FPGA 101 based on the configuration data 803 from the server 111. The memory controller 1407 controls the memory 1408. The PCIe 1405 performs control when accessing the server 111 via the PCIe 415.

  FIG. 15 is an explanatory diagram of a setting example of the access permission setting register. Here, for easy understanding, the access permission setting register 1413 is represented as a table. In the access permission setting register 1413, for each user module 102, an address range indicating an accessible area in the memory 412 and a transfer amount restriction value are set.

  The restriction value of the transfer amount is for determining the access priority of the user module 102 for preventing the access from being occupied by any of the user modules 102 when the access requests from the plurality of user modules 102 overlap. Is the threshold value. The restriction value of the transfer amount is determined based on the circuit scale of the user module 102, for example. For example, the transfer amount restriction value is determined by the acceptance inspection program 322, the management OS 501-c, or the like. For example, the management module 103 is assumed to be more important than the other user modules 102, and access is not restricted by the transfer amount restriction value. For example, for the management module 103, the address range is e0000000 to e00fffff, and the transfer amount restriction value is ∞. For the user module 102-1, the address range is e0100000 to e01fffff, and the transfer amount restriction value is 500 [Mbps]. For example, for the user module 102-2, the address range is e0200000 to e02fffff, and the transfer amount restriction value is 1000 [Mbps].

  FIG. 16 is an explanatory diagram showing an example of correspondence between user modules and ports. For example, as shown in the table 1600, the user module 102-1 is connected to the port 1402-1 of the management module 103, and the user module 102-2 is connected to the port 1402-2 of the management module 103. For example, the correspondence between the user module 102 and the port 1402 may be tabulated in the management module 103. Further, for example, a plurality of ports 1402 may be prepared in the management module 103 in advance, and the port 1402 used for the user module 102 may be determined according to the area where the user module 102 is configured.

  FIG. 17 is an explanatory diagram illustrating an example of a table included in the device driver. The table 1700 is a storage unit 213 that indicates an area in the FPGA 101 allocated to the virtual machine VM. The area in the FPGA 101 assigned to the virtual machine VM is a storage area included in the area in which the user module 102 in the FPGA 101 assigned to the virtual machine VM is configured. The table 1700 is stored in, for example, a storage area in the memory 412 assigned to the device driver 502-c. Specifically, the table 1700 stores an address range indicating the storage area of the user module 102 in the FPGA 101 assigned to the virtual machine VM for each virtual machine VM.

  The virtual machine VMc is made accessible to all areas in the FPGA 101 in order to manage the virtual machine VMx assigned to the terminal 302. Further, regarding the virtual machine VMc, it is assumed that the importance of the access request is higher than that of the virtual machine VMx assigned to the terminal 302, and the access is not restricted by the transfer amount restriction value. Therefore, for the virtual machine VMc, the address range is e0100000 to e03fffff, and the transfer amount restriction value is ∞. For the virtual machine VM1, the address range is e0100000 to e01fffff, and the transfer amount restriction value is 500 [Mbps]. For the virtual machine VM2, the address range is e0200000 to e02fffff, and the transfer amount restriction value is 1000 [Mbps].

(Access request from the virtual machine VM to the user module 102)
In this embodiment, access from the virtual machine VM to the user module 102 is realized by PIO (Programmed I / O) or Memory Mapped I / O.

  The accepting unit 211 accepts an access request to the FPGA 101 from any of the virtual machines VM assigned to the terminal 302. When the access destination indicated by the received access request is an area in which the user module 102 assigned to the requesting virtual machine VM is configured, the control unit 212 performs access based on the access request. Specifically, when the address indicating the area in the FPGA 101 included in the access request is included in the address range of the access request requesting virtual machine VM based on the table 1700, the control unit 212 determines that the access request Perform access based on. If the area is not a configured area, the control unit 212 does not perform access based on the access request. Specifically, when the address indicating the area in the FPGA 101 included in the access request is not included in the address range for the virtual machine VM that requested the access request based on the table 1700, the control unit 212 determines that the access request Do not perform access based on. Further, when the area is not a configured area, the control unit 212 may output an error to the virtual machine VM that has requested the access request.

  In addition, when the area is not the configured area, the control unit 212 corrects the access request to an access request to the area where the user module 102 allocated to the requesting virtual machine VM is configured, and executes the corrected access request. May be. Specifically, based on the table 1700, the control unit 212 corrects the access request to an access request to an area included in the address range when the virtual machine VM is not included in the address range based on the table 1700. A more detailed example will be described later with reference to FIG.

  In addition, in the case where the control unit 212 is executing the access based on the access request from the other virtual machine VM in the configured area, the control unit 212 terminates the access based on the access request from the other virtual machine VM. stand by. Here, for example, the request source of the newly accepted access request is the first virtual machine VM, and the other virtual machine VM is the second virtual machine VM. Then, after the end, the control unit 212 executes access based on the access request from the first virtual machine VM. As a result, even when accesses from a plurality of virtual machines VM to the FPGA 101 overlap, the access indicated by the access request can be terminated in the order from the time when the access request is received.

  In addition, if any one of the virtual machines VM continuously uses a shared resource such as PCIe 1405 that connects the FPGA 101 and the server 111, the other virtual machine VM cannot use the PCIe 1405. Therefore, the measurement unit 1101 receives the first data amount per predetermined time transferred based on the access request from the first virtual machine VM and the predetermined data per predetermined time transferred based on the previous access request from the second virtual machine VM. The second data amount is measured. The predetermined time is determined by the developer of the system 100 and the administrator of the data center 301 before operation. Specifically, the measurement unit 1101 accumulates the amount of data transferred based on the access request from the first virtual machine VM, and measures the amount of data transferred per predetermined time by sampling at a predetermined time interval. .

  When executing access based on an access request from the second virtual machine VM, the control unit 212 includes a first data amount measured by the measurement unit 1101 and a second data amount measured by the measurement unit 1101. Based on the first state and the second state. The first state is a state in which access based on an access request from the first virtual machine VM is executed, and the second state is a state in which access based on an access request from the second virtual machine VM is executed.

  Based on the comparison result between the first data amount and the threshold value for the first virtual machine VM, and the comparison result between the second data amount and the threshold value for the first virtual machine VM, the control unit 212 performs the first state. And the second state. The threshold value is the transfer amount restriction value described above. For example, in the case of the first state, the control unit 212 switches from the first state to the second state when the first data amount exceeds the regulation value for the first virtual machine VM. For example, in the case of the second state, the control unit 212 switches from the second state to the first state when the second data amount exceeds the regulation value for the second virtual machine VM. A more detailed example will be described later with reference to FIG. In this way, by switching the execution of access based on the access request from each virtual machine VM, a plurality of virtual machines VM can use shared resources such as PCIe 415 in the server 111 fairly.

  Here, as described above, the reception unit 211 and the control unit 212 are realized by the device driver 502-c of the management OS 501-c, so that unauthorized or erroneous access to the FPGA 101 by the requesting virtual machine VM. Can be prevented. For example, when the functions of the receiving unit 211 and the control unit 212 are realized by the management module 103, the management module 103 cannot distinguish which virtual machine VM has received the access request. Even if it is determined in advance that the identification information of the requesting virtual machine VM is added to the access request, each virtual machine VM may intentionally or mistakenly add the identification information of another virtual machine VM. In this case, since the management module 103 cannot determine whether the identification information of the requesting virtual machine VM included in the access request is correct, there is a possibility that unauthorized access or incorrect access may occur.

  On the other hand, the device driver 502-c of the management OS 501-c can determine the requesting virtual machine VM. For this reason, the reception unit 211 and the control unit 212 are realized by the device driver 502-c of the management OS 501-c, so that unauthorized access and incorrect access to the FPGA 101 by the requesting virtual machine VM can be prevented. .

  FIG. 18 is an explanatory diagram of an example of access from the virtual machine to the user module. The management OS 501-c, the virtual machine VM, each device driver 502, and the hypervisor HV are software executed by the server 111. However, in order to facilitate understanding, each will be described as an execution subject.

  For example, when there is an access request from the application software 503-1 running on the virtual machine VM1, the OS 501-1 running on the virtual machine VM1 generates an access request to the FPGA 101. Then, the OS 501-1 running on the virtual machine VM1 calls the device driver 502-1 and notifies the device driver 502-1 of an access request (step S1801). In FIG. 18, the application software 503-1 is omitted.

  Upon receiving the access request, the device driver 502-1 notifies the access request to the hypervisor HV (step S1802). The hypervisor HV notifies the management OS 501-c of an access request from the device driver 502-1 (step S1803). When the management OS 501-c receives an access request for which the virtual machine VM1 is a request source from the hypervisor HV, the management OS 501-c calls the device driver 502-c and notifies the received access request to the device driver 502-c (step S1804).

  When the access destination address included in the access request is included in the address range of the virtual machine VM1 that is the request source of the received access request, the device driver 502-c executes access based on the access request (step S1805). . In step S1805, the device driver 502-c corrects the access request when the access destination address included in the access request is not included in the address range of the virtual machine VM1 that is the request source of the received access request. Specifically, the device driver 502-c corrects the access request to be included in the address range for the virtual machine VM1. The device driver 502-c executes access based on the corrected access request. The management module 103 accesses the user module 102-1 based on the execution of access based on the access request by the device driver 502-c (step S1806).

(Access request from the user module 102 to the memory 412 in the server 111)
Next, an access request from the user module 102 to the memory 412 in the server 111 will be described. In the present embodiment, access from the user module 102 to the memory 412 is realized by DMA. As described above, the control circuit 1406 includes the reception unit 105, the control unit 106, and the measurement unit. As described above, the DMA circuit 1403 includes the access unit 104.

  The control circuit 1406 accepts an access request from any of the user modules 102 by the accepting unit 211. The access request includes a DMA parameter to be given to the DMA circuit 1403.

  When the access destination indicated by the received access request is a storage area allocated to the user module 102 that requested the access request, the control circuit 1406 causes the DMA circuit 1403 to execute access based on the access request. Specifically, when the access destination indicated by the access request is included in the address range set in the access permission setting register 1413 for the requesting user module 102, the control circuit 1406 stores the DMA parameter in the access request in the register 1411. Set.

  On the other hand, if it is not the allocated storage area, the control circuit 1406 does not cause the DMA circuit 1403 to perform access based on the access request. Specifically, when the access destination indicated by the access request is not included in the address range, the control circuit 1406 does not set the DMA parameter in the access request in the register 1411 of the DMA circuit 1403. If it is not the allocated storage area, the control circuit 1406 corrects the access request to an access request to the storage area allocated to the requesting user module 102 and causes the DMA circuit 1403 to execute the corrected access request. Specifically, when the access destination indicated by the access request is not included in the address range, the control circuit 1406 corrects the DMA parameter in the access request so as to be included in the address range. Then, the control circuit 1406 sets the corrected DMA parameter in the register 1411.

  Further, in the case of the allocated storage area, when the control circuit 1406 causes the DMA circuit 1403 to execute an access based on an access request from another user module 102, the control circuit 1406 waits for the end of the access. Here, the user module 102 that is the request source of the newly accepted access request is referred to as a first user module 102, and the other user module 102 is referred to as a second user module. Then, the control circuit 1406 causes the DMA circuit 1403 to execute access based on the access request from the first user module 102 after the end.

  In addition, if any user module 102 in the FPGA 101 continuously uses a shared resource such as the PCIe 1405 that connects the FPGA 101 and the server 111, the other user module 102 cannot use the PCIe 1405. Therefore, the control circuit 1406 measures the first data amount per predetermined time by the DMA circuit 1403 based on the access request from the first user module 102 by the accumulated data amount counter 1412. The control circuit 1406 measures the second data amount per predetermined time by the access unit 104 based on the access request from the second user module 102 by the accumulated data amount counter 1412. The predetermined time is determined by the developer of the system 100 and the manager of the data sensor before the operation. Specifically, the control circuit 1406 accumulates the amount of data transferred based on the access request from the first user module 102, and measures the amount of data transferred per predetermined time by sampling at a predetermined time interval. .

  The control circuit 1406 switches between the first state and the second state based on the measured first data amount and the measured second data amount. The first state is a state in which the DMA circuit 1403 executes access based on the access request from the first user module 102. The second state is a state in which the access unit 104 executes access based on an access request from the second user module 102.

  Further, the control circuit 1406, based on the comparison result between the first data amount and the threshold value for the first user module 102, and the comparison result between the second data amount and the threshold value for the second user module 102, Switching between the first state and the second state. The threshold for each user module 102 is a transfer amount restriction value set in the access permission setting register 1413 described above. For example, in the case of the first state, the control circuit 1406 switches from the first state to the second state when the first data amount exceeds the regulation value for the first user module 102. For example, in the case of the second state, the control circuit 1406 switches from the second state to the first state when the second data amount exceeds the regulation value for the second user module 102. A more detailed example will be described later with reference to FIG. As described above, by switching the execution of access based on the access request from each user module 102, the shared resources such as the PCIe 1405 of the FPGA 101 can be used fairly by the plurality of user modules 102. The user can use the system 100 without being aware of other users who share the FPGA 101.

  FIG. 19 is an explanatory diagram illustrating an example of access from the user module to the memory in the server. The user module 102-1 generates a DMA parameter, and transmits an access request including the generated DMA parameter to the management module 103 via the port 1402-1 (step S1901).

  When receiving an access request via the port 1402-1, the control circuit 1406 determines the request source of the access request based on the port 1402-1. Based on the access permission setting register 1413, the control circuit 1406 sets the DMA parameter in the register 1411 when the address of the access destination indicated by the DMA parameter is included in the address range assigned to the request source (step S1902, S1903). In steps S1902 and S1903, when the access destination address is not included in the address range for the request source, the control circuit 1406 corrects the DMA parameter so that the access destination address is included in the address range. Then, the control circuit 1406 sets the corrected DMA parameter in the register 1411 in the DMA circuit 1403.

  The DMA circuit 1403 accesses the memory 412 in the server 111 via the PCIe 1405 based on the DMA parameter set in the register 1411 (steps S1904 and S1905).

  FIG. 20 is an explanatory diagram illustrating a detailed example of the address determination process. On the upper side of FIG. 20, BASE_ADDR_USER1 and MASK_ADDR_USER1 indicate parameter examples determined when the virtual machine VM1 is constructed. BASE_ADDR_USER2 and MASK_ADDR_USER2 indicate parameter examples determined when the virtual machine VM2 is constructed. The upper side of FIG. 20 shows the same thing as the setting of each address range in the access permission setting register 1413 and the table 1700, for example.

  On the lower side of FIG. 20, the address determination process of the device driver 502-c when an access request from the virtual machine VM1 is received, or the management module 103 when an access request from the user module 102-1 occurs. An address determination process is shown. In the address determination process, the input of the start address of the access destination indicated by the access request and the data length of the access destination indicated by the access request are accepted. In the address determination process, when the input head address is included in the address range indicated by BASE_ADDR_USER1 and MASK_ADDR_USER1, the input head address is output as it is. In the address determination process, if the input start address is not included in the address range, the corrected start address is output so that the input start address is included in the address range.

  In the address determination process, when the input data length is within the data length indicated by MASK_ADDR_USER1, the input data length is output as it is. In the address determination process, when the input data length is larger than the data length indicated by MASK_ADDR_USER1, the data length corrected to be within the data length indicated by MASK_ADDR_USER1 is output.

  FIG. 21 is an explanatory diagram showing a detailed example of the data amount restriction process. FIG. 21 illustrates an example of a data amount restriction process of the device driver 502-c when an access request is received from a plurality of virtual machines VM. The same applies to the data amount restriction processing of the management module 103 when a plurality of access requests are received.

  number_of_requester () indicates the number of access requests. When number_of_requester () is 1, since the data amount restriction process has accepted one access request, access based on the accepted access request is executed. get_requesters_top () indicates a process of acquiring the first access request in the queue that can register the access request from each virtual machine VM. do_transfer () indicates processing for executing access based on the access request in parentheses.

  When number_of_requester () is greater than 1, the access requests are sorted in descending order based on “(restriction value) − (recent measured data amount)” for the virtual machine VM that requested the access request. In the data amount restriction process, after the sorting, the access is executed in order from the access based on the top access request.

  For example, get_requesters () indicates a process for acquiring all access requests registered in a queue capable of registering access requests. In reqs, the acquired access request is registered. The access requests registered in reqs are sorted in descending order based on ““ restriction value ”−“ recent measured data amount ”for the virtual machine VM that is the request source of each access request. reqs. top () indicates a process for acquiring an access request registered at the top. do_transfer () indicates processing for executing access based on the access request in (), and here, access based on the access request registered at the head of reqs is executed.

  Further, in the data amount restriction process, when a virtual machine VM requesting an access request whose data amount exceeds the regulation value is detected, the management OS 501-c is notified.

  As described above, the integrated circuit according to the present embodiment has a storage area allocated from a circuit in an FPGA allocated to a certain user to another circuit in the FPGA allocated to another user. Do not allow access. Accordingly, it is possible to prevent a user having a storage area of another user from being interfered with an available circuit. Therefore, the processing environment of each user can be made to function stably.

  Further, the integrated circuit according to the present embodiment is assigned to the request source circuit when the access destination of the access request from the circuit assigned to a certain user is not the storage area assigned to the request source circuit. It corrects to the access request to the storage area. Thereby, it is possible to prevent the circuit in the FPGA assigned to another user from being interfered by a certain user. Therefore, the processing environment of each user can be made to function stably.

  In addition, since the integrated circuit is connected to the server via one bus, there is a possibility that access requests to the server from a plurality of circuits in the integrated circuit overlap. Therefore, when there are a plurality of access requests, the integrated circuit according to the present embodiment waits for the access based on the access request with the earlier received time to end, and performs the access based on the access request with the later received time. Run. Thereby, access based on the access requests can be executed in the order in which the access requests are generated.

  In addition, when any circuit in the integrated circuit continuously uses the bus connecting the integrated circuit and the control device, other circuits in the integrated circuit cannot access the storage area in the control device. Therefore, the integrated circuit according to the present embodiment measures the transfer amount from the circuit to the storage area in the control device for each circuit in the integrated circuit, and the access request from any circuit based on the measured data amount. Switch whether to perform access based on. Thereby, a plurality of users can use the integrated circuit fairly.

  The control device switches the access request to be executed when the amount of data transferred by the access being executed exceeds the restriction value for the request source of the access request for the access being executed. Thereby, a plurality of users can use the integrated circuit fairly.

  As described above, the control device according to the present embodiment does not allow a user to access a circuit in the FPGA assigned to another user. Thereby, it is possible to prevent the circuit in the FPGA assigned to another user from being interfered by a certain user. Therefore, the processing environment of each user can be made to function stably.

  In addition, the control device according to the present embodiment, when the access destination of the access request from a certain user is not a circuit in the integrated circuit assigned to the request source, to the circuit assigned to the request source user. Correct for access requests. Thereby, it is possible to prevent a circuit in an integrated circuit assigned to another user from being interfered by a certain user. Therefore, the processing environment of each user can be made to function stably.

  In addition, since the control device is connected to the integrated circuit via a single bus, there is a possibility that requests for access to the integrated circuit from a plurality of users may overlap. Therefore, when there are a plurality of access requests, the control device according to the present embodiment waits for the access based on the access request with the earlier received time to end, and performs the access based on the access request with the later received time. Run. Thereby, access based on the access requests can be executed in the order in which the access requests are generated.

  In addition, if any one of the users continuously uses the bus connecting the integrated circuit and the control device, other users cannot use the integrated circuit. Therefore, the control device according to the present embodiment measures the transfer amount from the user to the circuit in the integrated circuit for each user, and based on the access request from any user based on the measured data amount. Switch whether to perform access. Thereby, a plurality of users can use the integrated circuit fairly.

  The control device switches the access request to be executed when the amount of data transferred by the access being executed exceeds the restriction value for the request source of the access request for the access being executed. Thereby, a plurality of users can use the integrated circuit fairly.

  Further, according to the present embodiment, the processing environment between users is separated in both the virtual machine and the FPGA executed on the server, and the shared resource can be used fairly. Therefore, a plurality of users can share the same server and FPGA in a stable processing environment.

  Further, by enabling the FPGA to be used jointly by a plurality of users as in cloud computing, it is possible to reduce the investment cost and the operation cost compared to the case where the FPGA is assigned to each user. The operation cost is, for example, a time cost. In addition, if the system described in this embodiment can be provided as an ASP (Application Service Provider) service, various users can use it.

  In addition, for example, even power-efficient hardware such as dedicated hardware or GPGPU (General-Purpose computing on Graphics Processing Unit) has performance per unit of power if it is not compatible with those hardware. May be reduced. Even if the processing is not suitable for dedicated hardware or GPGPU, the processing performance per power consumption can be improved by using the FPGA. Therefore, in the system according to the present embodiment, power efficiency can be improved as compared with the case where dedicated hardware, GPGPU, or the like is used. Even a circuit that does not have enough demand to develop dedicated hardware can be realized by the FPGA.

  In this embodiment, an example in which a user designs a user module has been described. However, a user module prepared in advance may be selected and used.

  The following additional notes are disclosed with respect to the embodiment described above.

(Appendix 1) An integrated circuit in which an internal circuit can be reconfigured, wherein partial circuits assigned to each of a plurality of computers are configured in different areas,
An access unit capable of accessing each of the different storage areas assigned to each of the partial circuits;
A receiving unit that receives an access request from any of the partial circuits;
When the access destination indicated by the access request received by the accepting unit is a storage area assigned to the partial circuit that is the request source of the access request, the access unit performs access based on the access request and is assigned If it is not the storage area, a control unit that does not allow the access unit to execute access based on the access request,
An integrated circuit comprising:

(Supplementary Note 2) If the storage unit is not the allocated storage area, the control unit corrects the access request to an access request to the storage area allocated to the requesting partial circuit, and the corrected access request is The integrated circuit according to appendix 1, wherein the integrated circuit is executed by an access unit.

(Supplementary Note 3) In the case where the control unit is the allocated storage area, a second part different from the requesting partial circuit (hereinafter referred to as “first partial circuit”) of the partial circuits. When the access unit executes an access based on an access request from a circuit, an access based on the access request from the first partial circuit after the access based on the access request from the second partial circuit is completed 3. The integrated circuit according to appendix 1 or 2, wherein the access unit is caused to execute.

(Supplementary Note 4) The first data amount per predetermined time by the access unit based on the access request from the first partial circuit, and the predetermined time by the access unit based on the access request from the second partial circuit A measurement unit that measures the second data amount of
The control unit performs access based on the access request from the first partial circuit based on the first data amount measured by the measurement unit and the second data amount measured by the measurement unit. The integrated circuit according to appendix 3, wherein a first state to be executed by the access unit and a second state in which the access unit executes an access based on the access request from the second partial circuit are switched.

(Additional remark 5) The said control part is compared with the comparison result with the threshold value about the said 1st data amount and the said 1st partial circuit, and the comparison result with the said 2nd data amount and the threshold value about the said 2nd partial circuit. The integrated circuit according to appendix 4, wherein the first state and the second state are switched based on the first state.

(Supplementary note 6) The integrated circuit according to any one of Supplementary notes 1 to 5, wherein each of the plurality of computers is either a physical device or a virtual device.

(Appendix 7) An integrated circuit capable of reconfiguring an internal circuit, wherein the control circuit is connected to an integrated circuit in which partial circuits assigned to each of a plurality of computers are configured in different regions,
A receiving unit that receives an access request to the integrated circuit from any of the plurality of computers;
When the access destination indicated by the received access request is an area in which a partial circuit assigned to the requesting computer of the access request is configured, access based on the access request is executed, and the configured area If not, a control unit that performs control not to execute access based on the access request
A control device comprising:

(Supplementary note 8) If the control unit is not the configured area, the control unit corrects the access request to an access request to the area where the partial circuit allocated to the requesting computer is configured, and corrects the access The control device according to appendix 7, wherein the control is executed.

(Additional remark 9) When the said control part is the area | region comprised, the access request from the 2nd computer different from the said requesting computer (henceforth a "1st computer") among the said computers. Or an access based on the access request from the first computer after the access based on the access request from the second computer is completed. 8. The control device according to 8.

(Supplementary Note 10) The first data amount per predetermined time transferred based on the access request from the first computer and the second data per predetermined time transferred based on the access request from the second computer A measuring unit that measures the quantity,
The control unit, when executing an access based on an access request from the second computer, the first data amount measured by the measurement unit, the second data amount measured by the measurement unit, And switching between a first state in which access based on the access request from the first computer is executed and a second state in which access based on the access request from the second computer is executed. The control device according to appendix 9.

(Additional remark 11) The said control part is based on the comparison result of the said 1st data amount and the threshold value about the said 1st computer, and the comparison result of the said 2nd data amount and the threshold value about the said 2nd computer. The control device according to appendix 10, wherein the control unit switches between the first state and the second state.

(Supplementary Note 12) The integrated circuit transfers the first data amount per predetermined time transferred based on the access request from the first computer and the predetermined time transferred based on the access request from the second computer. A measurement unit for measuring the second data amount per hit,
The control unit, when executing an access based on an access request from the second computer, the first data amount measured by the measurement unit, the second data amount measured by the measurement unit, And switching between a first state in which access based on the access request from the first computer is executed and a second state in which access based on the access request from the second computer is executed. The control device according to appendix 9.

(Supplementary note 13) The control device according to any one of supplementary notes 7 to 12, wherein each of the plurality of computers is either a physical device or a virtual device.

(Supplementary Note 14) An integrated circuit in which internal circuits can be reconfigured, wherein the partial circuits allocated to each of the plurality of computers are configured in different areas, and are allocated to each of the partial circuits. An integrated circuit having an access unit accessible to each of the different storage areas
Accepting an access request from any of the partial circuits;
When the access destination indicated by the received access request is a storage area assigned to the partial circuit that is the request source of the access request, the access unit executes access based on the access request, and the assigned storage area If not, do not allow the access unit to perform access based on the access request,
A control method characterized by executing processing.

(Supplementary Note 15) An integrated circuit in which an internal circuit can be reconfigured, and a control device to which an integrated circuit in which partial circuits assigned to each of a plurality of computers are configured in different regions is connected,
Receiving an access request to the integrated circuit from any of the plurality of computers;
When the access destination indicated by the received access request is an area in which a partial circuit assigned to the requesting computer of the access request is configured, access based on the access request is executed, and the configured area If not, do not perform access based on the access request,
A control method characterized by executing processing.

(Supplementary Note 16) An integrated circuit capable of reconfiguring an internal circuit, wherein a partial circuit assigned to each of a plurality of computers is connected to an integrated circuit configured in a different area,
Receiving an access request to the integrated circuit from any of the plurality of computers;
When the access destination indicated by the received access request is an area in which a partial circuit assigned to the requesting computer of the access request is configured, access based on the access request is executed, and the configured area If not, do not perform access based on the access request,
A control program characterized by causing a process to be executed.

(Supplementary Note 17) An integrated circuit in which an internal circuit can be reconfigured, and a control device to which an integrated circuit in which partial circuits assigned to each of a plurality of computers are configured in different regions is connected,
Receiving an access request to the integrated circuit from any of the plurality of computers;
When the access destination indicated by the received access request is an area in which a partial circuit assigned to the requesting computer of the access request is configured, access based on the access request is executed, and the configured area If not, do not perform access based on the access request,
A recording medium on which a control program for executing processing is recorded.

100 system 101 FPGA
DESCRIPTION OF SYMBOLS 102 User module 103 Management module 104 Access part 105, 211 Acceptance part 106, 212 Control part 111 Server 112 Storage area 121 Computer 1101 Measurement part 1403 DMA circuit 1406 Control circuit 1412 Cumulative data amount counter 1413 Access permission setting register VM Virtual machine

Claims (13)

An integrated circuit capable of reconfiguring an internal circuit, wherein the partial circuits assigned to each of a plurality of computers are configured in different areas,
An access unit capable of accessing each of the different storage areas assigned to each of the partial circuits;
A receiving unit that receives an access request from any of the partial circuits;
When the access destination indicated by the access request received by the accepting unit is a storage area assigned to the partial circuit that is the request source of the access request, the access unit performs access based on the access request and is assigned If it is not the storage area, a control unit that does not allow the access unit to execute access based on the access request,
An integrated circuit comprising:   In the case where the control unit is the allocated storage area, the control unit accesses from a second partial circuit different from the requesting partial circuit (hereinafter referred to as “first partial circuit”) of the partial circuits. When the access unit performs access based on a request, the access unit performs access based on the access request from the first partial circuit after the access based on the access request from the second partial circuit ends. The integrated circuit according to claim 1, wherein the integrated circuit is executed. The first data amount per predetermined time by the access unit based on the access request from the first partial circuit, and the second data per predetermined time by the access unit based on the access request from the second partial circuit. A measuring unit that measures the quantity,
The control unit performs access based on the access request from the first partial circuit based on the first data amount measured by the measurement unit and the second data amount measured by the measurement unit. 3. The integrated circuit according to claim 2, wherein the integrated circuit is switched between a first state to be executed by the access unit and a second state in which the access unit executes an access based on the access request from the second partial circuit. . Wherein, in the case of the first state, when the first data amount exceeds the threshold value for said first partial circuit, switching to the second state, in the case of the second state, the second 4. The integrated circuit according to claim 3 , wherein when the amount of data exceeds a threshold value for the second partial circuit, the integrated circuit is switched to the first state .   The integrated circuit according to claim 1, wherein each of the plurality of computers is one of a physical device and a virtual device. An integrated circuit capable of reconfiguring an internal circuit, wherein a control circuit is connected to an integrated circuit in which partial circuits assigned to each of a plurality of computers are configured in different regions,
A receiving unit that receives an access request to the integrated circuit from any of the plurality of computers;
When the access destination indicated by the received access request is an area in which a partial circuit assigned to the requesting computer of the access request is configured, access based on the access request is executed, and the configured area If not, a control unit that performs control not to perform access based on the access request;
A control device comprising:   In the case of the configured area, the control unit performs access based on an access request from a second computer different from the requesting computer (hereinafter referred to as “first computer”) of the computers. 7. The control according to claim 6, wherein when executing, the access based on the access request from the first computer is executed after the access based on the access request from the second computer is completed. apparatus. A first data amount per predetermined time transferred based on the access request from the first computer and a second data amount transferred per predetermined time based on the access request from the second computer; Has a measuring unit to measure,
The control unit, when executing an access based on an access request from the second computer, the first data amount measured by the measurement unit, the second data amount measured by the measurement unit, And switching between a first state in which access based on the access request from the first computer is executed and a second state in which access based on the access request from the second computer is executed. The control device according to claim 7. Wherein, in the case of the first state, when the first data amount exceeds the threshold value for said first computer, switch to the second state, in the case of the second state, the second data If the amount exceeds the threshold value for said second computer control device according to claim 8, characterized in that switching to the first state.   The control device according to claim 6, wherein each of the plurality of computers is either a physical device or a virtual device. An integrated circuit capable of reconfiguring an internal circuit, wherein the partial circuits assigned to each of a plurality of computers are integrated circuits in different areas, and different memories assigned to each of the partial circuits An integrated circuit having an access portion accessible to each of the regions;
Accepting an access request from any of the partial circuits;
When the access destination indicated by the received access request is a storage area assigned to the partial circuit that is the request source of the access request, the access unit executes access based on the access request, and the assigned storage area If not, do not allow the access unit to perform access based on the access request,
A control method characterized by executing processing. An integrated circuit in which an internal circuit can be reconfigured, and a control device to which an integrated circuit in which partial circuits assigned to each of a plurality of computers are configured in different regions is connected,
Receiving an access request to the integrated circuit from any of the plurality of computers;
When the access destination indicated by the received access request is an area in which a partial circuit assigned to the requesting computer of the access request is configured, access based on the access request is executed, and the configured area If not, do not perform access based on the access request,
A control method characterized by executing processing. An integrated circuit in which an internal circuit can be reconfigured, wherein a partial circuit assigned to each of a plurality of computers is connected to an integrated circuit configured in a different area,
Receiving an access request to the integrated circuit from any of the plurality of computers;
When the access destination indicated by the received access request is an area in which a partial circuit assigned to the requesting computer of the access request is configured, access based on the access request is executed, and the configured area If not, do not perform access based on the access request,
A control program characterized by causing a process to be executed.

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