JP6095528B2 - Plasma processing method - Google Patents

Plasma processing method Download PDF

Info

Publication number
JP6095528B2
JP6095528B2 JP2013183508A JP2013183508A JP6095528B2 JP 6095528 B2 JP6095528 B2 JP 6095528B2 JP 2013183508 A JP2013183508 A JP 2013183508A JP 2013183508 A JP2013183508 A JP 2013183508A JP 6095528 B2 JP6095528 B2 JP 6095528B2
Authority
JP
Japan
Prior art keywords
step
gas
trench
processing method
plasma processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2013183508A
Other languages
Japanese (ja)
Other versions
JP2015050440A (en
Inventor
益法 石原
益法 石原
石村 裕昭
裕昭 石村
敏明 西田
敏明 西田
亨 伊東
亨 伊東
尚裕 川本
尚裕 川本
Original Assignee
株式会社日立ハイテクノロジーズ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立ハイテクノロジーズ filed Critical 株式会社日立ハイテクノロジーズ
Priority to JP2013183508A priority Critical patent/JP6095528B2/en
Publication of JP2015050440A publication Critical patent/JP2015050440A/en
Application granted granted Critical
Publication of JP6095528B2 publication Critical patent/JP6095528B2/en
Application status is Active legal-status Critical
Anticipated expiration legal-status Critical

Links

Images

Description

  The present invention relates to a plasma processing method.

  As background art of this technical field, there is JP-A-2007-235136 (Patent Document 1). This publication describes a technique in which side passivation is managed by selectively forming an oxidation passivation layer on the side and / or bottom of the etching layer.

  Moreover, there exists Unexamined-Japanese-Patent No. 2010-118549 (patent document 2) as background art of this technical field. In this publication, the supply and stop of alternating current bias power to the mounting table are alternately repeated, and the alternating current bias power supply period and the alternating current bias power stop period are combined. A plasma etching method is described in which the AC bias power is controlled so that the ratio is 0.1 or more and 0.5 or less.

JP 2007-235136 A JP 2010-118549 A

  In recent years, shallow trench isolation (hereinafter abbreviated as STI) is used as an element isolation technique in the field of manufacturing semiconductor devices. In STI, trenches (etching grooves) are formed in a silicon substrate by, for example, anisotropic etching. Also called).

  By the way, the silicon substrate has a relatively narrow trench width and a relatively dense trench area (hereinafter abbreviated as a pattern dense portion), a relatively wide trench width, A relatively sparse region (hereinafter, abbreviated as a pattern sparse portion) is formed. In the step of forming the trench in the silicon substrate by etching, it is essential to process the trench so that the trench has the same depth and shape in the dense pattern portion and the loose pattern portion. However, in the dense pattern portion where the trench width is 20 nm or less, there is a problem that dense microloading occurs and the desired trench depth and shape cannot be obtained.

  Therefore, the present invention provides a plasma processing method capable of reducing dense microloading in a dense pattern portion where a trench formed in a silicon substrate has a width of 20 nm or less.

  In order to solve the above problems, the present invention forms a trench having a predetermined depth in a silicon substrate by repeating the first step, the second step, and the third step a plurality of times. In the first step, the silicon substrate is etched using a chlorine-containing gas while applying time-modulated high-frequency power using a mask on which a trench pattern of 20 nm or less is formed. The OFF time of the time-modulated high frequency electrode is 5 ms or more. In the second step, the deposit deposited on the side surface of the trench formed in the first step is removed using a gas containing fluorine. In the third step, the side and bottom surfaces of the trench from which the deposits are removed in the second step are oxidized using a gas containing oxygen.

  According to the present invention, it is possible to provide a plasma processing method capable of reducing dense microloading in a dense pattern portion where a trench formed in a silicon substrate has a width of 20 nm or less.

  Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

It is the schematic of the plasma etching apparatus in an Example. It is principal part sectional drawing of the semiconductor substrate explaining the manufacturing process of the semiconductor device in an Example. FIG. 3 is a principal part cross-sectional view of the same place as in FIG. 2 in the process of manufacturing the semiconductor device, following FIG. 2; FIG. 4 is a principal part cross-sectional view of the same place as in FIG. 2 in the process of manufacturing the semiconductor device, following FIG. 3; FIG. 5 is an essential part cross-sectional view of the same place as that in FIG. 2 during the manufacturing process of the semiconductor device, following FIG. 4; FIG. 6 is a principal part cross-sectional view of the same place as in FIG. 2 in the process of manufacturing the semiconductor device, following FIG. 5; (A) is a graph which shows the relationship between the high frequency electric power in a 2nd process, and sparse microloading, (b) is a graph which shows the relationship between the high frequency electric power and a line dimension in a 2nd process. . (A) is the graph which shows the relationship between the OFF time of intermittent high frequency electric power modulated in the 1st process, and dense microloading, and (b) is the time modulation in the 1st process. It is a graph which shows the relationship between the OFF time of intermittent high frequency electric power, and a line dimension. It is principal part sectional drawing of the semiconductor substrate explaining the manufacturing process of the semiconductor device in a comparative example.

  In the following embodiments, when necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other, and one is the other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say.

  In addition, when referring to “consisting of A”, “consisting of A”, “having A”, and “including A”, other elements are excluded unless specifically indicated that only that element is included. It goes without saying that it is not what you do. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Further, in the drawings used in the following embodiments, hatching may be added to make the drawings easy to see even if they are plan views. In all the drawings for explaining the following embodiments, components having the same function are denoted by the same reference numerals in principle, and repeated description thereof is omitted. Hereinafter, the present embodiment will be described in detail with reference to the drawings.

  First, since it is considered that the method of manufacturing a semiconductor device according to the embodiment will become clearer, as a comparative example, the STI trench forming process studied by the present inventors will be described in detail with reference to FIG. FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate for explaining a manufacturing process of a semiconductor device in a comparative example.

  The semiconductor element is miniaturized, for example, with a scaling rule of about 0.7 times. The design rule (design standard) of 32 nm or 22 nm applied to the current semiconductor products is 20 nm or less in the next generation semiconductor products, and the width of the STI trench is further reduced.

  However, in the STI where the width of the trench in the dense pattern portion is 20 nm or less, there are various technical problems described below. That is, as shown in FIG. 9, in the etching of the silicon substrate 201, a small amount of the reaction product 203 is deposited on the side surfaces of the silicon substrate 201 and the hard mask 202 even during the etching process of the silicon substrate 201. Becomes narrower or the trench 208 is closed. For this reason, the progress of etching becomes difficult. In addition, since the width of the trench 208 is narrow, the reaction product deposited near the bottom surface of the trench 208 is particularly difficult to remove. Therefore, the density microloading that is the difference in the depth of the trench 208 is increased.

  The etching of the pattern dense portion can be progressed by controlling the etching conditions to reduce the reaction product or removing the excessive reaction product in the next step. However, in such a case, the density microloading can be reduced, but the trench side protection is insufficient, so the line dimension between adjacent trenches becomes smaller than the prescribed line dimension, or the trench is side The problem of becoming an etched shape occurs. That is, it is a problem to achieve both reduction of density microloading and prevention of fluctuations in line dimensions and abnormal shapes of trenches.

  A plasma etching apparatus in the embodiment will be described with reference to FIG. FIG. 1 is a schematic view of a plasma etching apparatus in an embodiment.

  As shown in FIG. 1, a shower plate 104 (for example, made of quartz) and a dielectric window 105 (for example, made of quartz) for introducing a processing gas into the vacuum vessel 101 are installed on the upper portion of the vacuum vessel 101. The processing chamber 106 is configured by sealing the above. A gas supply device 107 for flowing a processing gas is connected to the shower plate 104. In addition, a vacuum exhaust device (not shown) is connected to the vacuum container 101 via a vacuum exhaust port 108.

  In order to transmit power for generating plasma to the processing chamber 106, a waveguide 109 for transmitting electromagnetic waves is provided above the dielectric window 105. The electromagnetic wave (plasma generating high frequency) transmitted to the waveguide 109 is oscillated from the electromagnetic wave generating power source 103. The frequency of the electromagnetic wave is not particularly limited, but in this embodiment, a 2.45 GHz microwave (high frequency for plasma generation) is used. A magnetic field generating coil 110 that forms a magnetic field is provided on the outer periphery of the processing chamber 106, and the electric power (microwave power in the present embodiment) oscillated from the electromagnetic wave generating power source 103 is the same as the formed magnetic field. Due to this interaction, high-density plasma is generated in the processing chamber 106.

  A wafer mounting electrode 102 is provided below the vacuum vessel 101 so as to face the shower plate 104. The wafer mounting electrode 102 is coated with a sprayed film (not shown) on the electrode surface, and a DC power source 115 is connected via a high frequency filter 114. Further, a high frequency power supply 113 which is a high frequency power supply for bias is connected to the wafer mounting power supply 102 via a matching circuit 112. A temperature controller (not shown) is also connected to the wafer mounting electrode 102.

  The wafer 111, which is a sample transported into the processing chamber 106, is adsorbed onto the wafer mounting electrode 102 by the electrostatic force of the DC voltage applied from the DC power source 115, and the temperature is adjusted. After supplying a desired processing gas into the vacuum vessel 101 by the gas supply device 107, the inside of the vacuum vessel 101 is set to a predetermined pressure, and plasma is generated in the processing chamber 106. By applying high frequency power from a high frequency power supply 113 connected to the wafer mounting electrode 102, ions are drawn from the plasma into the wafer, and the wafer 111 is plasma processed. Further, since the high frequency power supply 113 includes a pulse oscillator, it is possible to apply time-modulated intermittent high frequency power or continuous high frequency power to the wafer mounting electrode 102.

  Next, a plasma processing method using the above-described plasma etching apparatus in the embodiment will be described with reference to FIGS. 2-6 is principal part sectional drawing of the semiconductor substrate explaining the manufacturing process of the semiconductor substrate in an Example. FIGS. 7A and 7B are graphs showing the relationship between high-frequency power and dense microloading in the second step, and graphs showing the relationship between high-frequency power and line dimensions in the second step, respectively. is there. FIGS. 8A and 8B are graphs showing the relationship between the OFF time of the time-modulated intermittent high-frequency power in the first step and the density microloading, and the time modulation in the first step, respectively. It is a graph which shows the relationship between the OFF time of the intermittent high frequency electric power, and the line dimension.

  In this embodiment, a trench having a depth of 240 nm is formed in a silicon substrate using a plasma etching apparatus, and a plasma processing method in which three steps are repeated a plurality of times is used for forming the trench. Table 1 summarizes an example of processing conditions of the plasma processing method in this embodiment.

  First, as shown in FIG. 2, a silicon substrate 201 is prepared, and a hard mask 202 patterned into a predetermined shape is formed on the silicon substrate 201. The interval between adjacent hard masks 202 in the dense pattern portion is 20 nm or less, for example, about 10 nm.

Next, as shown in FIG. 3, a trench 208 is formed in the silicon substrate 201 by etching using the hard mask 202 in the first step. As processing conditions, Cl 2 gas was used, the flow rate of Cl 2 gas was 400 mL / min or more, and the pressure was 1.0 Pa or less. This is because good density microloading is obtained, and the depth of the trench 208 is the same at the center and the outer periphery of the wafer. Typically, the flow rate of Cl 2 gas was 420 mL / min, and the pressure was 0.65 Pa.

  Here, plasma is generated with a microwave power of 1100 W, and the silicon substrate 201 is etched while applying intermittent high frequency power modulated with time with a power value of 350 W and a duty ratio of 35% from a high frequency power supply. The duty ratio is expressed as duty ratio = Ton / (Ton + Toff), where Ton is the ON time of intermittent high frequency power that is time-modulated and Toff is the OFF time.

  During the etching, the reaction product 203 is deposited on the inner wall (side surface and bottom surface) of the trench 208 and the side surface of the hard mask 202. Therefore, the trench 208 is narrowed and clogged even with a small amount of the reaction product 203 in the pattern dense portion. To do. Therefore, in this embodiment, the depth of the trench 208 is, for example, about 20 nm and the thickness of the reaction product 203 is set so that the etching time of the first step is too long and the trench 208 is not blocked during the etching. For example, the etching time was set to 6 seconds so as to be about 1 nm.

Next, as shown in FIG. 4, the reaction product 203 is removed in the second step. This prevents the trench 208 from being narrowed and blocked due to the deposition of the reaction product 203. As processing conditions, a gas in which CF 4 gas and Ar gas were mixed was used, the flow rate of CF 4 gas was 10 mL / min, and the flow rate of Ar gas was 50 mL / min. Furthermore, the pressure was 0.6 Pa. Plasma is generated with a microwave power of 600 W, and the reaction product 203 is etched while applying a continuous high frequency power having a power value of 50 W from a high frequency power source. The etching time was set to 2 seconds.

  Next, as shown in FIG. 5, in a third step, oxidized portions 204 are formed on the side and top surfaces of the hard mask 202 and the inner walls (side and bottom surfaces) of the trench 208. By providing this oxidized portion 204, when the silicon substrate 201 is further etched in the depth direction in the next step, the side surface of the hard mask 202 and the side surface of the trench 208 can be prevented. The abnormal shape of the trench can be suppressed.

As processing conditions, a mixed gas of O 2 gas, Ar gas, and He gas was used, the flow rate of O 2 gas was 200 mL / min, the flow rate of Ar gas was 300 mL / min, and the flow rate of He gas was 300 mL / min. . Furthermore, the pressure was 6.0 Pa. Plasma was generated with a microwave power of 700 W, and plasma treatment was performed without applying high-frequency power. Since the oxidized portion 204 is thinner than the reaction product 203, the side surface of the trench 208 can be protected while keeping the width of the trench 208 in the dense pattern portion wide. If the processing time of the third step is too long, the bottom surface of the trench 208 in the dense pattern portion is excessively oxidized, and etching is hindered when the silicon substrate 201 is etched further in the depth direction in the next step. . For this reason, the processing time was set to 10 seconds as a range in which the etching of the bottom surface of the trench 208 in the dense pattern portion was not hindered.

  In this example, the above-described FIG. 3 (first step), the above-described FIG. 4 (second step), and the above-described FIG. 5 (third step) are used under the processing conditions shown in Table 1 above. The three steps described above are repeated 12 times (a total of 36 steps). Thereby, as shown in FIG. 6, a trench 208 having a depth of 240 nm is formed in the dense pattern portion.

  Here, in the case where the depth of the trench 208 in the dense pattern portion is 240 nm, the density microloading that is the difference between the depth 205 of the trench 208 in the dense pattern portion and the depth 206 of the trench 208 in the coarse pattern portion is reduced. There is a need to.

  FIG. 7A shows the case where the three steps shown in Table 1 above are repeated 12 times in order to make the depth of the trenches in the dense pattern portion 240 nm, and the high frequency power and the sparse microscopic power in the second step. It is a graph which shows the relationship with loading. FIG. 7B shows the high frequency power and the line size in the second process when the three processes shown in Table 1 are repeated 12 times in order to make the depth of the trench in the pattern dense part 240 nm. It is a graph which shows the relationship. Here, the line dimension is, for example, the line dimension 207 shown in FIG.

  As shown in FIG. 7A, when high frequency power is not applied, the density microloading is 100.5 nm. On the other hand, when high frequency power of 50 W or more was applied, the density microloading was 79.6 to 81.7 nm, which was 10 nm or more smaller than when no high frequency power was applied. Moreover, as shown in FIG.7 (b), even if a high frequency electric power is applied, it turns out that a line dimension is 16.1-16.3 nm and is not changing.

  Since the line dimensions have not changed, the reaction product on the bottom surface of the trench is completely removed by applying high frequency power in the second step without changing the effect of removing the reaction product on the side surface of the trench. This is considered to be because the etching of the dense pattern portion in the first step is likely to proceed.

In addition, in this example, it is known that a reaction product having a thickness of about 1 nm adheres in one iteration. Therefore, the amount of scraping was set to 0.88 nm using a wafer on which a SiO 2 film having a property close to that of the reaction product was formed, and the high frequency power was set to 50 W so that the reaction product was etched by about 1 nm.

  A method of extending the etching time without applying high frequency power is also conceivable. However, in this method, since it is difficult to remove the reaction product on the bottom surface of the trench, the reaction product on the side surface of the trench is removed while the reaction product on the bottom surface of the trench is being removed. Etching to the substrate causes a reduction in line size and an abnormal shape of the trench. Therefore, a method of applying high-frequency power that can completely remove the reaction product on the bottom surface of the trench in a short time is effective.

  FIG. 8A shows the time-modulated intermittent in the first step when the three steps shown in Table 1 are repeated 12 times in order to set the depth of the trench in the pattern dense portion to 240 nm. It is a graph which shows the relationship between the OFF time of typical high frequency electric power, and dense / micro loading. FIG. 8B shows the time-modulated intermittent in the first step when the three steps shown in Table 1 are repeated 12 times in order to make the depth of the trench in the pattern dense portion 240 nm. It is a graph which shows the relationship between the OFF time of typical high frequency electric power, and a line dimension. Here, the line dimension is, for example, the line dimension 207 shown in FIG.

  As shown in FIG. 8A, the OFF time is in the range of 0.32 to 3.2 ms, and the dense microloading is 79.3 to 83.3 nm. On the other hand, when the OFF time is 5 ms or more, The density microloading is 50.0-56.7 nm. Moreover, as shown in FIG.8 (b), even if it changes OFF time, it turns out that a line dimension is 16.1-16.5 nm and is not changing.

  This is due to the fact that etching does not proceed during the OFF time. That is, the increase in the reaction product is suppressed by extending the OFF time, and the reaction product is exhausted before being reattached to the wafer by promoting the exhaust, so that during the etching in the first step This is because the trenches in the dense pattern portion are less likely to be narrowed, and etching is possible even with narrow trenches. In addition, by increasing the OFF time, the reaction product deposited during the etching of the first step is reduced, but the line size does not become small because the side surface of the trench is not affected by the effect of the third step. This is because it was sufficiently oxidized and protected.

  Thus, a method for reducing reaction products during etching in the first step, a method for removing reaction products after etching in the second step, and a trench in which the reaction products in the third step are removed and exposed. By the method of protecting the side surfaces of the semiconductor device, the variation in the line size of the pattern dense portion and the abnormal shape of the trench can be suppressed, and the reduction of the density microloading can be realized.

  In addition, as a final form of the present embodiment, it was necessary to further increase the line size. The silicon substrate used in this example was observed to have a silicon scraping of about 5 nm before forming the hard mask before etching, and processing was started from the third step in order to protect a slight side surface of the shaved portion. Then, the process is repeated 12 times in the order of the first process and the second process, and further, 50 W of continuous high frequency power is applied to the third process at the start of the process to promote oxidation, thereby increasing the line size. The target was 18 nm, and the density microloading was 48 nm. From this, it is possible to repeat the order of the third step, the first step, and the second step, and repeat the order of the second step, the third step, and the first step, as in this embodiment. Effects can be obtained.

In the first step of this embodiment, Cl 2 gas is used. However, a mixed gas in which one or more of O 2 , N 2 , HBr, Ar, and He is mixed with Cl 2 gas is used. The same effects as in the present embodiment may be obtained.

  In the second step of this embodiment, continuous high-frequency power is applied, but time-modulated intermittent high-frequency power may be applied, and the same effects as in this embodiment can be obtained.

Further, in the second step of this example, a mixed gas of CF 4 and Ar was used as a gas for removing the reaction product, but CF 4 , CHF 3 , C 4 F 8 , CH 2 F 2 , using NF 3, single gas containing any one of SF 6 or CF 4, CHF 3, C 4 F 8, CH 2 F 2, NF 3, mixed gas obtained by mixing two or more of SF 6, In other words, the same effect as in the present embodiment can be obtained.

The mixing in the third step of the present embodiment uses a mixed gas of O 2, Ar and He, alone gases O 2, a mixed gas of O 2 and Ar, or O 2 and He Gas may be used, and the same effect as in this embodiment can be obtained.

  In the third step of the present embodiment, high frequency power is not applied, but high frequency power may be applied, and the same effect as in the present embodiment can be obtained.

  As the plasma etching apparatus, a microwave plasma etching apparatus, an inductively coupled plasma etching apparatus, a helicon wave plasma etching apparatus, a two-frequency excitation parallel plate plasma etching apparatus, or the like is employed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

DESCRIPTION OF SYMBOLS 101 Vacuum container 102 Wafer mounting electrode 103 Electromagnetic wave generation power supply 104 Shower plate 105 Dielectric window 106 Processing chamber 107 Gas supply apparatus 108 Vacuum exhaust port 109 Waveguide 110 Magnetic field generation coil 111 Wafer 112 Matching circuit 113 High frequency power supply 114 High-frequency filter 115 DC power supply 201 Silicon substrate 202 Hard mask 203 Reaction product 204 Oxidation portion 205 Pattern dense portion trench depth 206 Pattern sparse portion trench depth 207 Line size 208 Trench

Claims (5)

  1. A plasma processing method for forming a first trench in a silicon substrate by plasma etching the silicon substrate using a mask in which a trench pattern having a width of 20 nm or less is formed,
    (A) a first step of etching the silicon substrate using a chlorine-containing gas while applying time-modulated high-frequency power;
    (B) a second step of removing deposits deposited on the side and bottom surfaces of the second trench formed in the first step using a fluorine-containing gas;
    (C) a third step of oxidizing the side and bottom surfaces of the second trench from which the deposit has been removed in the second step using a gas containing oxygen;
    Have
    By repeating the first step to the third step, the first trench is formed,
    The plasma processing method, wherein an OFF time of the time-modulated high-frequency power is 5 ms or more.
  2. The plasma processing method according to claim 1,
    The fluorine-containing gas is tetrafluoromethane gas,
    The plasma processing method, wherein a processing time of the first step is longer than a processing time of the second step and shorter than a processing time of the third step.
  3. The plasma processing method according to claim 1,
    In the third step, a plasma processing method of applying high frequency power.
  4. In the plasma processing method of any one of Claims 1-3,
    The pressure of the first step relative to the total gas flow rate of the first step is equal to the pressure of the second step relative to the total gas flow rate of the second step and the third pressure relative to the total gas flow rate of the third step. The plasma processing method is lower than the pressure of the process.
  5. In the plasma processing method of any one of Claims 1-4,
    The gas used in the first step is chlorine gas,
    The gas used in the second step is a mixed gas of tetrafluoromethane gas and argon gas,
    The plasma processing method, wherein the gas used in the third step is a mixed gas of oxygen gas, argon gas, and helium gas.
JP2013183508A 2013-09-04 2013-09-04 Plasma processing method Active JP6095528B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2013183508A JP6095528B2 (en) 2013-09-04 2013-09-04 Plasma processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013183508A JP6095528B2 (en) 2013-09-04 2013-09-04 Plasma processing method

Publications (2)

Publication Number Publication Date
JP2015050440A JP2015050440A (en) 2015-03-16
JP6095528B2 true JP6095528B2 (en) 2017-03-15

Family

ID=52700167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2013183508A Active JP6095528B2 (en) 2013-09-04 2013-09-04 Plasma processing method

Country Status (1)

Country Link
JP (1) JP6095528B2 (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0265132A (en) * 1988-08-30 1990-03-05 Sony Corp Dry etching method
JP4356117B2 (en) * 1997-01-29 2009-11-04 財団法人国際科学振興財団 Plasma device
JP3838397B2 (en) * 1997-12-02 2006-10-25 ユーシーティー株式会社 Semiconductor manufacturing method
US7368394B2 (en) * 2006-02-27 2008-05-06 Applied Materials, Inc. Etch methods to form anisotropic features for high aspect ratio applications
JP2010118549A (en) * 2008-11-13 2010-05-27 Tokyo Electron Ltd Plasma etching method and plasma etching device
JP2012169390A (en) * 2011-02-14 2012-09-06 Hitachi High-Technologies Corp Plasma processing method
JP2013131587A (en) * 2011-12-21 2013-07-04 Hitachi High-Technologies Corp Plasma processing method

Also Published As

Publication number Publication date
JP2015050440A (en) 2015-03-16

Similar Documents

Publication Publication Date Title
US9343327B2 (en) Methods for etch of sin films
JP6087845B2 (en) Etching method of metal and metal oxide film
US8921234B2 (en) Selective titanium nitride etching
US8980763B2 (en) Dry-etch for selective tungsten removal
JP4555404B2 (en) Anisotropic fluorine-based plasma etching method for silicon
KR101941828B1 (en) Rapid and uniform gas switching for a plasma etch process
TWI625824B (en) Air gaps between copper lines
US10424485B2 (en) Enhanced etching processes using remote plasma sources
TWI458008B (en) Pulsed plasma system with pulsed sample bias for etching semiconductor structures
DE69835032T2 (en) Improved method to eat an oxide layer
US9236266B2 (en) Dry-etch for silicon-and-carbon-containing films
US9064816B2 (en) Dry-etch for selective oxidation removal
US9837284B2 (en) Oxide etch selectivity enhancement
US8541312B2 (en) Selective suppression of dry-etch rate of materials containing both silicon and nitrogen
TWI471932B (en) Dry-etch for silicon-and-nitrogen-containing films
KR20150034660A (en) High aspect ratio etch with combination mask
US6090718A (en) Dry etching method for semiconductor substrate
US9425058B2 (en) Simplified litho-etch-litho-etch process
US9299575B2 (en) Gas-phase tungsten etch
US9190293B2 (en) Even tungsten etch for high aspect ratio trenches
US20130298942A1 (en) Etch remnant removal
JP6272873B2 (en) Selective etching of silicon carbonitride
US6287974B1 (en) Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features
US8883028B2 (en) Mixed mode pulsing etching in plasma processing systems
TWI608544B (en) Method for processing a wafer

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160314

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170125

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170131

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170214

R150 Certificate of patent or registration of utility model

Ref document number: 6095528

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150