JP6089543B2 - Test method and processing equipment - Google Patents

Description

  The present invention relates to a test method and a processing apparatus for performing a power-on test of a processing apparatus using a power-on packet.

  There is a technology for externally controlling the power supply of information devices such as computers. For example, there is a Wake-On-LAN (Local Area Network) technique as a technique for operating a power source of an information device such as a computer from the outside. Wake-On-LAN is a technique for remotely operating a computer connected to a network such as a LAN by sending a power-on packet called a magic packet.

  For example, it is assumed that there is a storage apparatus having a Wake-On-LAN function. When performing a power-on test using a power-on packet with this storage device as a test target, a personal computer (PC) or server is connected to the test-target storage device via a LAN. A test is performed to check that the power-off state of the storage device is switched to the power-on state by inputting a power-on packet from a PC or server connected to the LAN to the power-off storage device.

  A technique is known in which a remote power supply is controlled to turn off and turn on an information processing apparatus connected to the remote power supply. In addition, for a terminal that has not been notified by a power-off instruction via a network, the network communication control unit of the unreported terminal is initialized from another terminal via another interface, and the unreported terminal is re-established. A technique for instructing power-off via a network is known. In addition, in a storage system in which a plurality of storage apparatuses and information processing apparatuses are connected, a technique for controlling the power supply of the storage apparatus and the information processing apparatus in conjunction with each other is known.

JP 2001-184145 A JP 2001-202162 A JP 2004-334535 A

  For example, in the power-on test using the power-on packet for the above-described test target storage device, if the storage device cannot be turned on, the LAN-connected PC or server remains inaccessible to the storage device. The failure location cannot be easily identified. In such a power-on test of a processing apparatus using a power-on packet, there is a demand for easily identifying a failure location.

  In one aspect, an object of the present invention is to provide a technique capable of easily identifying a failure location in a power-on test of a processing apparatus using a power-on packet.

In one aspect, in the test method, the first control unit included in the processing device transmits a power-on packet to the second control unit included in the processing device via the first path, and transmits the power-on packet. second when the power supply of the control unit has not been turned in, the power of the second control unit via the monitoring circuit and the second monitor circuit control unit is provided that includes a first control unit capable of communicating with each other by The control circuit is controlled to turn on the power, and after the second control unit is turned on, a process of transmitting a status information acquisition request message to the second control unit via the second path is executed. .

  In one aspect, the failure location can be easily identified in the power-on test of the processing apparatus using the power-on packet.

It is a figure explaining WOL by this Embodiment. It is a figure which shows the structural example of the RAID apparatus by this Embodiment. It is a figure which shows the function structural example of the test control CM by this Embodiment, and test object CM. It is a figure explaining the example of a fault location specific by this Embodiment. It is a figure which shows the example of the test management table by this Embodiment. It is a test processing flowchart by test control CM of this Embodiment. It is a sequence diagram of a WOL test process by the test control CM and the test object CM of the present embodiment. It is a sequence diagram of a WOL test process by the test control CM and the test object CM of the present embodiment. It is a sequence diagram of the failure location identification process by the test control CM and test object CM of this Embodiment. It is a sequence diagram of the failure location identification process by the test control CM and test object CM of this Embodiment.

  Hereinafter, the present embodiment will be described with reference to the drawings. In the example of the present embodiment, an example in which the storage apparatus is a processing apparatus to be tested will be described.

  FIG. 1 is a diagram for explaining WOL according to the present embodiment.

  A RAID (Redundant Array of Inexpensive Disks) device 1 is a storage device having a plurality of disks. The RAID device 1 shown in FIG. 1 has a Wake-On-LAN function, and performs power-on in response to a power-on packet from the PC 2 connected via the LAN 3. Hereinafter, Wake-On-LAN is also referred to as WOL. The power-on packet is also called a magic packet.

  FIG. 2 is a diagram illustrating a configuration example of a RAID device according to the present embodiment.

  The RAID device 1 includes a CE (Controller Enclosure) 10 and a DE (Drive Enclosure) 40. The CE 10 is a housing in which a CM (Controller Module) 20 that is a module for managing all operations in the subsystem is mounted. A plurality of CMs 20 can be mounted on the CE 10. In the example shown in FIG. 2, two CMs 20 are mounted on the CE 10. The DE 40 is a casing in which a plurality of disks 41 are mounted.

  The CM 20 serving as a control unit of the RAID device 1 includes a CPU (Central Processing Unit) 21, a memory 23 serving as a main memory, a system volume 24, a PCH (Platform Controller Hub) 25, a PCI (Peripheral Component Interconnect) bus bridge 26, and a CA ( Channel Adapter) 27, SAS (Serial Attached SCSI) controller 28, LAN controller 29, WAKE signal line 30, system monitoring circuit 31, and power supply control circuit 32. The CPU 21 also includes a DMA (Direct Memory Access) controller 22. Although omitted in FIG. 2, it is assumed that the plurality of CMs 20 included in the RAID device 1 shown in FIG. 2 have the same configuration.

  The DMA controller 22 performs data transfer by DMA. The DMA controller 22 is interconnected between the CMs 20 and used for data communication between the CMs 20. In the present embodiment, data transfer between CMs 20 is realized by transferring data to other CMs 20 by the DMA controller 22.

  The system volume 24 is a storage device such as an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a USB (Universal Serial Bus) memory. In the present embodiment, the system volume 24 is also used as a boot destination for a diagnostic system monitor and a storage unit for a test program executed by the CM 20.

  The PCH 25 is a chip that integrates the functions of the North Bridge and the South Bridge. The PCH 25 includes PCI (Peripheral Component Interconnect) Express, serial ATA (Advanced Technology Attachment), USB, LAN, graphics output function, and the like.

  The PCI bus bridge 26 is a bus for performing communication between the CPU 21 and peripheral devices. The CA 27 is an adapter having a host interface, is connected to a host (not shown), and is used for data communication between the host and the RAID device 1. The SAS controller 28 is a chip connected to the DE 40 and used for writing / reading data to / from the disk 41.

  The LAN controller 29 is a chip that controls communication via a LAN. Each LAN controller is set with a unique MAC (Media Access Control) address.

  The system monitoring circuit 31 is a circuit that performs system power control, error monitoring, and the like. The system monitoring circuit 31 operates the power control circuit 32 in its own CM 20 to supply power to each part. The system monitoring circuit 31 is realized by, for example, an FPGA (Field-Programmable Gate Array). The power supply control circuit 32 is a circuit that executes power on / off control of the own CM 20 by an operation from the system monitoring circuit.

  The terminal 4 is a computer terminal connected to the PCH 25 by a serial interface. The terminal 4 is used for starting a test program by a user operation and presenting information to the user.

  The LAN controller 29 according to the present embodiment is compatible with WOL. For example, when the LAN controller 29 receives a magic packet via the LAN, the PME status of the LAN controller 29 becomes “1”. The state is reflected on the WAKE signal line 30, and the WAKE signal is notified to the system monitoring circuit 31. Thereafter, the system monitoring circuit operates the power supply control circuit to turn on the power supply of the own CM 20. The PME status is a status indicating whether or not the LAN controller 29 has received a Wakeup event (magic packet). The WAKE signal is a signal indicating the state of the PME status of the LAN controller 29. When the PME status is “1” (ON state), the WAKE signal is also “1” (ON state). When the WAKE signal becomes “1”, the system monitoring circuit 31 accesses the power control circuit 32 and turns on the power. Even when the power supply of the CM 20 is OFF, power is supplied to the LAN controller 29, the system monitoring circuit 31, the power supply control circuit 32, and the like.

  When the CM 20 with the RAID device 1 receives the magic packet, the system monitoring circuit 31 of the CM 20 operates the power control circuit 32 in the own CM 20 to supply power to each part, and at the same time, the other CM 20 The system monitoring circuit 31 is notified that there is a WAKE signal. The system monitoring circuit 31 can communicate with other CMs 20. The system monitoring circuit 31 of each CM 20 that has received a notification that there is a WAKE signal from the system monitoring circuit 31 of the CM 20 that has received the magic packet, operates the power control circuit 32 in the own CM 20, respectively. Supply power.

  Hereinafter, an example in which a test of the WOL function according to the present embodiment is performed on the RAID apparatus 1 having the WOL function will be described.

  FIG. 3 is a diagram illustrating a functional configuration example of the test control CM and the test target CM according to the present embodiment.

  In FIG. 3, a CM 20a is the CM 20 serving as a first control unit that controls the WOL test. Hereinafter, the CM 20 that controls the WOL test is referred to as a test control CM 20a. The CM 20b is the CM 20 serving as the second control unit that is the subject of the WOL test. Hereinafter, the CM 20 that is the subject of the WOL test is referred to as a test subject CM 20b. In this embodiment, when the WOL test of the RAID device 1 is performed, each LAN controller 29 of the test control CM 20a and each LAN controller 29 of the test target CM 20b are connected by a LAN via the HUB 5, for example. And

  The test control CM 20a includes a test processing unit 100. The test processing unit 100 is a functional unit that executes processing on the test control CM 20a side in the WOL test according to the present embodiment. The test processing unit 100 includes a test execution unit 110, a power-on control unit 120, an information acquisition unit 130, a test management information storage unit 140, and an output unit 150.

  The test execution unit 110 performs control to execute the WOL test. More specifically, the test execution unit 110 issues a WOL test start instruction to the test target CM 20b, and turns off the power of the test target CM 20b. Thereafter, the packet transmission unit 111 of the test execution unit 110 transmits a magic packet to the test target CM 20b via the LAN that is the first path.

  The power-on control unit 120 controls the power control circuit 32 of the test target CM 20b via the system monitoring circuit 31 of both CMs 20 when the power of the test target CM 20b is not turned on due to the transmission of the magic packet. Turn on the power of the CM 20b.

  The information acquisition unit 130 acquires status information such as information on a failure location from the test target CM 20b when the power of the test target CM 20b is not turned on by transmitting a magic packet. At this time, the message transmission unit 131 of the information acquisition unit 130 performs the test via the second path which is a communication path using data transfer to the memory 23 between the CMs 20 after the test target CM 20b is powered on. A status information acquisition request message is transmitted to the target CM 20b. Data transfer between the CMs 20 to the memory 23 is performed using the DMA controller 22.

  The test management information storage unit 140 is a storage unit that stores test management information. The test management information is information in which the result of the WOL test is recorded. For example, in the test management information of the test management information storage unit 140, information such as a failure location acquired from the test target CM 20b by the information acquisition unit 130 is recorded.

  The output unit 150 outputs the result of the WOL test recorded in the test management information in the test management information storage unit 140 to the terminal 4. For example, the result of the WOL test is displayed on the display of the terminal 4.

  The test target CM 20b includes a test processing unit 200. The test processing unit 200 is a functional unit that executes processing on the test target CM 20b side in the WOL test according to the present embodiment. The test processing unit 200 includes a test preparation unit 210, a startup notification unit 220, and a failure location specifying processing unit 230.

  In response to the instruction to start the WOL test from the test control CM 20a, the test preparation unit 210 turns off the power of the subject test target CM 20b.

  The start-up notification unit 220 notifies the test control CM 20a that the self-test target CM 20b has started up when the self-test target CM 20b changes from the power-off state to the power-on state and the test processing unit 200 is activated.

  After receiving the status information acquisition request message from the test control CM 20a, the failure location identification processing unit 230 checks the register of the LAN controller 29, the register of the system monitoring circuit 31, and the like to identify the failure location. The failure location identification processing unit 230 transmits information on the identified failure location to the test control CM 20a.

  Each functional unit included in the test control CM 20a and the test target CM 20b illustrated in FIG. 3 can be realized by hardware such as the CPU 21 and the memory 23 included in each CM 20, and a software program. Programs that can be executed by the CM 20 are stored in the system volume 24, read into the memory 23 at the time of execution, and executed by the CPU 21. When testing the WOL function of the RAID device 1, a test program is stored in the system volume 24 of each CM 20.

The test program stored in the system volume 24 of each CM 20 is activated, for example, by the following procedure after the RAID device 1 to be tested is turned on.
(1) A BIOS (Basic Input / Output System) of a flash ROM (Read Only Memory) (not shown) is activated.
(2) The BIOS loads the diagnostic system monitor in the system volume 24 onto the memory 23 and passes control. The diagnostic system monitor is an OS (Operating System) for operating a test program on the CM 20. Execute diagnostic system monitor initialization.
(3) The IO driver modules in the system volume 24 are loaded into the memory 23 by the number of IO (Input / Output) drivers, and the initialization process of the IO drivers is executed.
(4) After the startup process of the diagnostic system monitor is completed, an operation screen is displayed on the terminal 4. The user performs an operation for starting the test program from the terminal 4.
(5) The diagnostic system monitor loads the test program and utility commands from the system volume 24 to the memory 23 and executes them.

  It should be noted that automatic operation is also possible by previously writing an executable statement from the terminal 4 in a file. Further, among the plurality of CMs 20 included in the RAID device 1, which CM 20 is the test control CM 20a and which CM 20 is the test target CM 20b may be determined by, for example, designation from the user who operates the terminal 4. , May be determined automatically.

  As described above, the test program is executed by the CM 20 included in the RAID device 1, thereby realizing the test processing unit 100 of the test control CM 20a and the test processing unit 200 of the test target CM 20b illustrated in FIG.

  FIG. 4 is a diagram for explaining an example of identifying a failure location according to the present embodiment.

  Here, an example of a location to be checked by specifying a failure location and a failure location candidate specified from the check result will be described. The location to be checked and the failure location identified from the check result correspond to the specifications and design of the RAID device 1 to be tested.

  For example, the failure location identification processing unit 230 of the test target CM 20b checks the status indicating the reception state of the magic packet by reading from the register of the LAN controller 29. When the magic packet is not in a reception state, the LAN controller 29 of the test target CM 20b, the LAN controller 29 of the test control CM 20a, the LAN cable, and the like are considered as failure point candidates.

  In addition, for example, the failure location identification processing unit 230 of the test target CM 20 b checks the PME status by reading from the register of the LAN controller 29. When the PME status is “0”, the LAN controller 29 of the test target CM 20b or the like is considered as a failure location candidate.

  Further, for example, the failure location specifying processing unit 230 of the test target CM 20b checks the register of the system monitoring circuit 31 to determine the WAKE signal state. When the WAKE signal state is “0”, the WAKE signal line 30 or the like is considered as a failure location candidate.

  If there is no abnormality in checking the reception state of the magic packet, the PME status, and the WAKE signal state, the system monitoring circuit 31, the power supply control circuit 32, and the like are considered as possible fault locations.

  FIG. 5 is a diagram showing an example of a test management table according to the present embodiment.

  The test management table 145 shown in FIG. 5 shows an example of test management information stored in the test management information storage unit 140 of the test control CM 20a. The test management table 145 shown in FIG. 5 has CM number, LAN port number, MAC address, test result, and failure location information.

  The CM number indicates the slot ID of the CM 20 included in the RAID device 1 to be tested. The LAN port number indicates a LAN port number included in the CM 20. The record of the test management table 145 is a record for each LAN port indicated by the LAN port number in the CM 20 indicated by the CM number. The MAC address indicates the MAC address of the LAN controller 29 of the corresponding LAN port.

  The test result indicates the test result of the WOL test for the corresponding LAN port. In the test results, “0” indicates that the WOL test has not been performed. In the test result, “1” indicates that the test result is OK, that is, the power of the test target CM 20b is turned on in the WOL test for the corresponding LAN port of the test target CM 20b. In the test result, “2” indicates a case where the test result is NG, that is, a case where the power of the test target CM 20b is not turned on in the WOL test for the corresponding LAN port of the test target CM 20b.

  The failure location indicates the identified failure location when the test result is NG. The four numerical values at the failure location represent from the left the failure of the LAN controller 29 of the test target CM 20b, the WAKE signal line 30, the system monitoring circuit 31or power supply control circuit 32, and the LAN controller 29orLAN cable of the test control CM 20a. In the failure location, “0” indicates that the corresponding location is not a failure location candidate, and “1” indicates that the corresponding location is a failure location candidate.

  For example, in the check result shown in FIG. The failure location in the test management table 145 is “1001”. When the PME status is “0”, the failure location in the test management table 145 is “1000”. When the WAKE signal state is “0”, the failure location in the test management table 145 is “0100”. Otherwise, the failure location in the test management table 145 is “0010”.

  Hereinafter, a flow of processing of a series of WOL tests by the test control CM 20a and the test target CM 20b according to the present embodiment will be described with reference to FIGS.

  FIG. 6 is a test process flowchart according to the test control CM of the present embodiment.

  In the test control CM 20a, the test processing unit 100 selects one LAN port to be tested in order from the LAN port of the CM to be tested 20b (Step S10). The test processing unit 100 executes the WOL test process for the LAN port to be tested (step S11). The WOL test process is a test process in which the test target CM 20b is powered on by transmitting a magic packet from the test control CM 20a to the test target LAN port in the test target CM 20b in the power-off state. Details of the WOL test process will be described later.

  The test processing unit 100 determines whether the test result is OK (step S12). In the WOL test process, the test result is OK if the test target CM 20b is turned on, and the test result is NG if the test target CM 20b is not turned on. If the test result is OK (YES in step S12), the test processing unit 100 records in the record of the test target LAN port of the test target CM 20b in the test management table 145 that the test result is OK (step). S14).

  If the test result is not OK (NO in step S12), that is, if the test result is NG, the test processing unit 100 executes a failure location specifying process (step S13). The failure location identification processing is processing for identifying the failure location by turning on the power of the test target CM 20b from the test control CM 20a. Details of the failure location specifying process will be described later. The test processing unit 100 records information indicating that the test result is NG and information on the specified failure location in the test target LAN port record of the test target CM 20b in the test management table 145 (step S14).

  The test processing unit 100 determines whether the processing has been completed for all the LAN ports of the test target CM 20b (step S15). If the processing has not been completed for all LAN ports (NO in step S15), the test processing unit 100 returns to the processing in step S10 and proceeds to the processing for the next LAN port. If the processing has been completed for all the LAN ports (YES in step S15), the output unit 150 of the test processing unit 100 sends the WOL for the test target CM 20b recorded in the test management table 145 to the terminal 4. The test result is output (step S16).

  In the present embodiment, the series of processing shown in FIG. 6 is executed for each CM 20 included in the RAID device 1 while changing the test control CM 20a and the test target CM 20b. When the WOL test of the RAID device 1 is performed by the technique of the present embodiment, it becomes possible to easily identify the failure location.

  7 and 8 are sequence diagrams of the WOL test processing by the test control CM and the test target CM according to the present embodiment.

  In the test processing unit 100 of the test control CM 20a, the test execution unit 110 transfers WOL test start instruction data including designation of the test target LAN port to the test target CM 20b (step S20). Here, the DMA controller 22 of the test control CM 20a transfers WOL test start instruction data in a predetermined format to a predetermined area on the memory 23 of the test target CM 20b. After the data transfer, the test execution unit 110 issues an interrupt notification to the test target CM 20b. The interrupt notification notifies the test processing unit 200 of the test target CM 20b that the data has been transferred to the memory 23 of the self test target CM 20b. Depending on the specifications of the DMA controller 22, even if the test execution unit 110 does not control interrupt notification, the interrupt notification may be automatically performed after data transfer.

  In the test processing unit 200 of the test target CM 20b, when the test preparation unit 210 receives the WOL test start instruction data, the MAC address data of the LAN controller 29 of the test target LAN port designated by the data is sent to the test control CM 20a. Transfer (step S21). Here, the DMA controller 22 of the test target CM 20b transfers the MAC address data in a predetermined format to a predetermined area on the memory 23 of the test control CM 20a. After the data transfer, the test preparation unit 210 issues an interrupt notification to the test control CM 20a.

  The test execution unit 110 of the test control CM 20a records the MAC address in the test target LAN port record of the test target CM 20b in the test management table 145 (step S22). The test execution unit 110 transfers the power OFF instruction data to the test target CM 20b (step S23). Here, the DMA controller 22 of the test control CM 20a transfers power OFF instruction data in a predetermined format to a predetermined area on the memory 23 of the test target CM 20b. After the data transfer, the test execution unit 110 issues an interrupt notification to the test target CM 20b.

  When the test preparation unit 210 of the test target CM 20b receives the power OFF instruction data, the test preparation unit 210 performs setting for enabling the WOL of the test target LAN port (step S24). The test preparation unit 210 starts the process of turning off the power of the subject test subject CM 20b (step S25). The test preparation unit 210 repeatedly transfers counter data, which is incremented by 1 each time it is transferred, to the test control CM 20a (step S26). Here, the DMA controller 22 of the test target CM 20b transfers the counter data in a predetermined format to a predetermined area on the memory 23 of the test control CM 20a. The power-off process has a time lag until the process is completed. The test target CM 20b sends counter data to the test control CM 20a to notify the test control CM 20a whether the power source of the self test target CM 20b is in an ON state or an OFF state. When the test target CM 20b is powered off, the counter data transfer is completed.

  The test execution unit 110 of the test control CM 20a monitors the area where the counter data of the memory 23 of the self test control CM 20a is recorded, and waits until there is no change in the value of the counter data (step S27). The test execution unit 110 determines that the power of the test target CM 20b is turned off when the value of the counter data no longer changes. Note that the test execution unit 110 may use a timer to wait for a time that is considered sufficient for the test target CM 20b to be in the power-off state.

  When determining that the power of the test target CM 20b has been turned off, the test execution unit 110 generates a magic packet (step S28). The packet transmission unit 111 of the test execution unit 110 transmits a magic packet to the test target LAN port of the test target CM 20b (step S29). Here, since the power supply of the test target CM 20b is in the OFF state, the magic packet is transmitted using the MAC address. Thereafter, the test execution unit 110 monitors the area where the power-on notification data is recorded in the memory 23 of the self-test control CM 20a, and waits for the transfer of the power-on notification data from the test target CM 20b (step S30).

  In the test target CM 20b, when the power is successfully turned on by the magic packet, the diagnostic system monitor is booted and the test program is booted. After the test program is started, in the test processing unit 200 of the test target CM 20b, the start-up notification unit 220 transfers power-on notification data that notifies the test control CM 20a that the power of the self-test target CM 20b is turned on. (Step S31). Here, the DMA controller 22 of the test target CM 20b transfers power-on notification data in a predetermined format to a predetermined area on the memory 23 of the test control CM 20a.

  The test execution unit 110 of the test control CM 20a determines that the test result is OK when the transfer of the power-on notification data from the test target CM 20b can be confirmed (step S32).

  Note that, when power-on of the test target CM 20b by the magic packet fails, the power-on notification data is not transferred from the test target CM 20b to the test control CM 20a. The test execution unit 110 of the test control CM 20a determines that the test result is NG if the transfer of the power-on notification data from the test target CM 20b cannot be confirmed even after waiting for a certain time.

  FIG. 9 and FIG. 10 are sequence diagrams of failure location specifying processing by the test control CM and the test target CM of this embodiment.

  In the test processing unit 100 of the test control CM 20a, the power-on control unit 120 turns on the power of all the CMs 20 by controlling the power control circuit 32 via the system monitoring circuit 31 of each CM 20, thereby powering the test target CM 20b. Is forcibly entered (step S40). Thereafter, the information acquisition unit 130 monitors the area where the power-on notification data of the memory 23 of the self-test control CM 20a is recorded, and waits for the transfer of the power-on notification data from the test target CM 20b (step S41).

  In the test target CM 20b, after the power is turned on, the diagnostic system monitor is booted and the test program is started. After the test program is started, in the test processing unit 200 of the test target CM 20b, the start-up notification unit 220 transfers power-on notification data that notifies the test control CM 20a that the power of the self-test target CM 20b is turned on. (Step S42). Here, the DMA controller 22 of the test target CM 20b transfers power-on notification data in a predetermined format to a predetermined area on the memory 23 of the test control CM 20a.

  When the information acquisition unit 130 of the test control CM 20a confirms the transfer of the power-on notification data from the test target CM 20b, the message transmission unit 131 instructs the test target CM 20b to specify the test target LAN port. The specific process start instruction data is transferred (step S43). The failure location specifying process start instruction data is a status information acquisition request message such as a failure location. Here, the DMA controller 22 of the test control CM 20a transfers failure location specifying process start instruction data in a predetermined format to a predetermined area on the memory 23 of the test target CM 20b. After the data transfer, the information acquisition unit 130 issues an interrupt notification to the test target CM 20b.

  The failure location identification processing unit 230 of the test target CM 20b performs setting for enabling the WOL of the test target LAN port (step S44). The failure location identification processing unit 230 transfers the IP (Internet Protocol) address data of the test target LAN port to the test control CM 20a (step S45). Here, the DMA controller 22 of the test target CM 20b transfers the IP address data in a predetermined format to a predetermined area on the memory 23 of the test control CM 20a. After the data transfer, the failure location identification processing unit 230 issues an interrupt notification to the test control CM 20a.

  Upon receiving the IP address data transfer, the information acquisition unit 130 of the test control CM 20a designates the obtained IP address and transmits a magic packet to the test target LAN port of the test target CM 20b (step S46). . Here, since the power of the test target CM 20b is in the ON state, the magic packet is transmitted using the IP address.

  When receiving the magic packet, the failure location specifying unit 230 of the test target CM 20b checks the reception state of the magic packet with the register of the LAN controller 29 of the test target LAN port (step S47). Further, the failure location identification processing unit 230 checks the PME status with the register of the LAN controller 29 of the test target LAN port (step S48). In addition, the failure location identification processing unit 230 checks the WAKE signal status in the register of the system monitoring circuit 31 of the test target CM 20b (step S49).

  The failure location identification processing unit 230 identifies the failure location from the check results of steps S47 to S49 (step S50). The failure location identification processing unit 230 transfers failure location data including failure location information to the test control CM 20a (step S51). Here, the DMA controller 22 of the test target CM 20b transfers failure location data in a predetermined format to a predetermined area on the memory 23 of the test control CM 20a. After the data transfer, the failure location identification processing unit 230 issues an interrupt notification to the test control CM 20a.

  The information acquisition unit 130 of the test control CM 20a can obtain information on the failure location by transferring the failure location data from the test target CM 20b. Note that the information acquisition unit 130 may acquire the check result data of Steps S47 to S49 from the test target CM 20b and specify the failure location.

  Although the present embodiment has been described above, the present invention can naturally be modified in various ways within the scope of the gist thereof.

  For example, in this embodiment, an example in which a storage device is used as a processing device to be tested has been described. However, the processing device to be tested does not necessarily have to be a storage device. For example, the processing apparatus to be tested may be an information processing apparatus such as a server that communicates between internal controllers. For example, the system has a plurality of control units, and these control units can communicate with each other and have a mechanism for common power control. The power-on function using a power-on packet is provided. The testing technique according to the present embodiment can be applied to any processing apparatus having such a processing apparatus.

1 RAID device 2 PC
3 LAN
4 terminal 5 HUB
10 CE
20 CM
20a Test control CM
20b Test CM
21 CPU
22 DMA controller 23 Memory 24 System volume 25 PCH
26 PCI bus bridge 27 CA
28 SAS controller 29 LAN controller 30 WAKE signal line 31 System monitoring circuit 32 Power supply control circuit 40 DE
41 disk 100 test processing unit 110 test execution unit 111 packet transmission unit 120 power-on control unit 130 information acquisition unit 131 message transmission unit 140 test management information storage unit 150 output unit 200 test processing unit 210 test preparation unit 220 startup notification unit 230 Fault location processing unit

Claims (3)

The first control unit provided in the device under test is
A power-on packet is transmitted to the second control unit included in the test target device via the first path,
A monitoring circuit provided in the first control unit and a monitoring circuit provided in the second control unit that can communicate with each other when the power of the second control unit is not turned on by transmission of the power-on packet; The power control circuit of the second control unit is controlled via the power supply ,
A test method comprising: executing a process of transmitting a status information acquisition request message to the second control unit via a second path after the second control unit is powered on. The second pass, use the data transfer to the first controller and the second of said first from said memory of the control unit the second control unit comprises a memory between the control unit The test method according to claim 1, wherein the test path is a communication path. In a processing apparatus including a first controller and a second controller connected by a plurality of paths,
The first controller is
A packet transmission unit that transmits a power-on packet to the second control unit via a first path;
A monitoring circuit provided in the first control unit and a monitoring circuit provided in the second control unit that can communicate with each other when the power of the second control unit is not turned on by transmission of the power-on packet; A power-on control unit for controlling the power control circuit of the second control unit via the power source ,
And a message transmission unit that transmits a status information acquisition request message to the second control unit via a second path after the second control unit is powered on. .

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