JP6079586B2 - Short circuit detection circuit for electromagnetic equipment - Google Patents

Description

  The present invention relates to a short circuit detection circuit that detects a short circuit between windings of an electromagnetic device.

  Various configurations for detecting a short circuit of a resolver (electromagnetic device) which is a kind of angle sensor have been proposed. For example, in Patent Document 1, when a DC voltage V1 is connected to the cosine phase and a bias voltage is applied, and the cosine phase and the sine phase are short-circuited, the bias voltage applied to the cosine phase is also applied to the sine phase. It is constituted so that. At this time, the capacitor C7 is charged, the voltage between the terminals rises, the output level of the comparator OP3 changes from high to low, and a short circuit is detected.

JP 2000-166205 A (see FIG. 1)

  In the configuration of Patent Document 1, the potential of the inverting input terminal of the comparator OP3 includes an AC component, and a capacitor C7 is disposed for the purpose of preventing malfunction due to noise. As a result, the circuit mounting area increases and the cost increases. For example, if the capacitor is removed, the threshold value can be lowered to avoid erroneous detection, but naturally the detection accuracy is lowered.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a short-circuit detection circuit for an electromagnetic device that can prevent a decrease in detection accuracy without using a capacitor in the short-circuit determination circuit. .

  According to the short circuit detection circuit for an electromagnetic device according to claim 1, the first comparison voltage generation circuit includes a first DC offset voltage as a sum of terminal voltages with respect to the ground for one of the multiphase windings. Is added to generate a first comparison voltage, and the first comparison circuit compares the first comparison voltage with the first threshold voltage. The second comparison voltage generation circuit generates a second comparison voltage by adding a second offset voltage of DC to the sum of the terminal voltages with respect to the ground for the other one of the multiphase windings, The second comparison circuit compares the second comparison voltage with the second threshold voltage.

The threshold voltage generation circuit generates the first and second threshold voltages as voltage signals that change at the same frequency as the excitation signal input to the excitation winding, and the detection signal output circuit outputs the first and second comparisons. When a circuit output signal is input and a short circuit between two windings is detected based on the change in the output signal, a short circuit detection signal is output.
With this configuration, the first and second threshold voltages given to the first and second comparison circuits respectively become voltage signals that change at the same frequency as the excitation signal, so a capacitor for smoothing the threshold voltage is unnecessary. It becomes. Therefore, an increase in circuit mounting area and an increase in cost can be suppressed while maintaining the accuracy of short circuit detection.

  According to the short circuit detection circuit for an electromagnetic device according to claim 2, the threshold voltage generation circuit includes a delay circuit that delays the phase of the excitation signal, and the first and second threshold voltages are voltages based on the delayed phase. Generate as a signal. Thereby, even when the phase of each voltage signal on the secondary side is deviated from the excitation signal, a short circuit between the windings can be reliably detected by synchronizing the change of the threshold voltage with the comparison voltage.

Functional block diagram showing the configuration of the resolver and the short circuit detection circuit according to the first embodiment FIG. 1 shows a more specific circuit. Diagram showing detailed configuration of digital filter Timing chart showing operation of digital filter 1 equivalent diagram when a phase change circuit is added Figure 2 equivalent figure Timing chart showing normal resolver operation and no phase shift Fig. 7 equivalent diagram when the secondary winding is short-circuited 7 equivalent diagram when there is a phase shift Equivalent to FIG. 8 when there is a phase shift Timing chart showing the case where the excitation winding and secondary winding are short-circuited (part 1) Timing chart showing the case where the excitation winding and secondary winding are short-circuited (Part 2) Equivalent to Fig. 8 when rare short between secondary windings 13 equivalent diagram when there is a phase shift FIG. 2 equivalent view showing the second embodiment FIG. 2 equivalent view showing the third embodiment FIG. 1 equivalent diagram showing the fourth embodiment

(First embodiment)
As shown in FIG. 1, the resolver 1 (electromagnetic device) includes a primary side excitation winding I1, a secondary side cosine phase winding I2_1, and a sine phase winding I2_2. A capacitor C5 is connected to both ends of the excitation winding I1, and an excitation signal is applied to the non-ground side terminal via the excitation signal applying circuit 2 and the electrolytic capacitor C6. Between both terminals of the cosine phase winding I2_1 (multiphase winding), a first offset voltage generating circuit 3 (1), a first comparison voltage generating circuit 4 (1), and a first differential amplifier circuit 5 (1) are provided. Is connected. A second offset voltage generation circuit 3 (2), a second comparison voltage generation circuit 4 (2), and a second differential amplifier circuit 5 (between both terminals of the sine phase winding I2_2 (multiphase winding). 2) is connected.

  The first offset voltage generation circuit 3 (1) generates a first offset voltage V3 that biases the midpoint voltage between the terminals of the cosine phase winding I2_1, and the second offset voltage generation circuit 3 (2) A second offset voltage V4 that biases the midpoint voltage between the terminals of the sine phase winding I2_2 is generated. The first differential amplifier circuit 5 (1) differentially amplifies the inter-terminal voltage of the cosine phase winding I2_1 and outputs a COS signal to an R / D converter (not shown). The second differential amplifier circuit 5 (2) Differentially amplifies the voltage across the sine phase winding I2_2 and outputs a SIN signal to the R / D converter.

  The first comparison voltage generation circuit 4 (1) outputs the midpoint voltage between both terminals of the cosine phase winding I2_1 as the detection target voltage V1 to the first comparison circuit 6 (1). The second comparison voltage generation circuit 4 (2) outputs the midpoint voltage between both terminals of the sine phase winding I2_2 as the detection target voltage V2 to the second comparison circuit 6 (2).

  The excitation signal is input to the first and second threshold voltage generation circuits 7 (1) and 7 (2) via the excitation signal applying circuit 2. The first and second threshold voltage generation circuits 7 (1, 2) generate the first and second threshold voltages VT1, VT2 based on the input excitation signal, and the first and second comparison circuits 6 (1, 2). Output to 2). The first and second comparison circuits 6 (1, 2) respectively compare the comparison results between the detection target voltages V1, V2 (first and second comparison voltages) and the first and second threshold voltages VT1, VT2 with the digital filter 8. Output to (detection signal output circuit). The digital filter 8 outputs a short circuit detection signal based on the input comparison result.

  In FIG. 2, the first offset voltage generation circuit 3 (1) is composed of a series circuit of resistance elements R1 and R2, and an offset voltage V3 is applied to a common connection point between them. The first comparison voltage generation circuit 4 (1) is composed of a series circuit of resistance elements R3 and R4, and the detection target voltage V1 is output from the common connection point of both. The first differential amplifier circuit 5 (1) includes an operational amplifier OP1 and resistance elements R5 to R8. The non-inverting input terminal and the inverting input terminal of the operational amplifier OP1 are connected to the respective terminals of the cosine phase winding I2_1 via resistance elements R5 and R6, respectively. The center voltage (reference voltage) of the voltage output from the first differential amplifier circuit 5 (1) is applied to the non-inverting input terminal of the operational amplifier OP1 through the resistance element R7. The resistor is connected to the output terminal of the operational amplifier OP1 via the resistor element R8.

The second offset voltage generating circuit 3 (2), the second comparison voltage generating circuit 4 (2), and the second differential amplifier circuit 5 (2) arranged on the sine phase side are respectively the resistance element R9 and It comprises a series circuit of R10, a series circuit of resistance elements R11 and R12, an operational amplifier OP2, and resistance elements R13 to R16. The connection relationship of each element is the same as the corresponding element of the first offset voltage generation circuit 3 (1), the second comparison voltage generation circuit 4 (1), and the first differential amplifier circuit 5 (1). A series circuit of noise removing capacitors C1 and C2 and a series circuit of capacitors C3 and C4 are connected to both ends of the cosine phase winding I2_1 and the sine phase winding I2_2, respectively. Connected to ground.
First, second comparison circuit 6 (1,2) is composed of a comparator CP1, CP2 respectively, to the non-inverting input terminal of the comparator CP1, CP2, detected voltages V1, V2, respectively is applied, inversion Threshold voltages VT1 and VT2 are applied to the input terminals, respectively.

  The excitation signal applying circuit 2 includes an operational amplifier OP7, a buffer B1, and resistance elements R21 to R23. An excitation signal is given to the inverting input terminal of the operational amplifier OP7 through the resistance element R23. The inverting input terminal is connected to the ground via a resistance element R22 and is connected to the output terminal of the buffer B1 via a resistance element R21. The reference voltage REF3 is applied to the non-inverting input terminal of the operational amplifier OP7. The input terminal of the buffer B1 is connected to the output terminal of the operational amplifier OP7, and an excitation signal is output from the output terminal of the buffer B1 to the excitation winding I1.

  The first threshold voltage generation circuit 7 (1) is configured as an inverting amplifier circuit by the operational amplifier OP5 and the resistance elements R17 and R18. The inverting input terminal of the operational amplifier OP5 is connected to the excitation signal applying circuit 2 via the resistance element R18. It is connected to the output terminal of the operational amplifier OP7. The inverting input terminal is connected to the output terminal of the operational amplifier OP5 through the resistance element R17. A reference voltage REF1 is applied to the non-inverting input terminal of the operational amplifier OP5, and the threshold voltage VT1 is output from the output terminal of the operational amplifier OP5.

  The second threshold voltage generation circuit 7 (2) includes an operational amplifier OP6 and resistance elements R19 and R20, and an inverting input terminal of the operational amplifier OP6 is connected to an output terminal of the operational amplifier OP7 via the resistance element R20. . The inverting input terminal is connected to the output terminal of the operational amplifier OP6 through the resistance element R19. The reference voltage REF2 is applied to the non-inverting input terminal of the operational amplifier OP6, and the threshold voltage VT2 is output from the output terminal of the operational amplifier OP6.

  As shown in FIG. 3, the digital filter 8 includes an AND gate 11, a counter 12 (measurement circuit), a D flip-flop 13, a NOT gate 14, a timer 15, a one-shot pulse generation circuit 16, and the like. The negative logic input terminal of the AND gate 11 is connected to the output terminals of the comparators CP 1 and CP 2 and is pulled up by the resistance element 17. The clock signal CLK is given to the positive logic input terminal of the AND gate 11, and the output terminal of the AND gate 11 is connected to the clock terminal of the counter 12.

  The output terminal Q of the counter 12 is connected to the input terminal D of the D flip-flop 13, and a short-circuit detection signal is output from the output terminal Q of the D flip-flop 13 through the NOT gate 14. The clock signal CLK is also input to the timer 15 and the one-shot pulse generation circuit 16. The timer 15 divides the clock signal CLK and outputs it to the clock terminals of the one-shot pulse generation circuit 16 and the D flip-flop 13. The one-shot pulse generation circuit 16 outputs a one-shot pulse signal generated based on the input signal to the counter 15 as a reset signal.

  As shown in FIGS. 4A and 4C, when the resolver 1 is normal, the detection target voltages V1 and V2 input to the comparators CP1 and CP2 are always higher than the threshold voltages VT1 and VT2, and the comparators CP1 and CP2 The output signals of CP2 are all at a high level. Note that the waveforms shown in FIGS. 4A and 4C are modeled for ease of explanation, and are different from the waveforms actually detected.

  From this state, for example, when a short circuit between the cosine phase winding I2_1 and the sine phase winding I2_2 occurs on the secondary side of the resolver 1, the detection target voltage input to the comparators CP1 and CP2 The output voltage of the comparators CP1 and CP2 periodically shows a low level. Details of the change in the signal will be described later.

  If the output signals of the comparators CP1 and CP2 are at a high level, the counter 12 does not perform a count operation because no count clock is input, and the count operation is intermittently performed only during a period when the output signal is at a low level (FIG. 4 (e)). reference). Further, the counter 12 has a built-in magnitude comparator, and when the count value exceeds the threshold indicated by the broken line in FIG. 4E, the output terminal Q is changed to the high level (see FIG. 4F).

  The timer 14 greatly divides the clock signal CLK and outputs a divided signal having a period T1 (monitoring period). The one-shot pulse generation circuit 16 synchronizes with the rising edge of the divided signal (a slight delay time). 1) A 1-shot pulse signal is output. Therefore, after the counter 12 changes the output terminal Q to the high level, the D flip-flop 13 changes the output terminal Q to the high level at the next timing when the rising edge of the divided signal arrives. As a result, a low-level short-circuit detection signal is output to the outside (see FIG. 4G). Thereafter, the counter 12 is reset. In the configuration described above, the short circuit detection circuit 18 is configured except the resolver 1 and the differential amplifier circuit 5.

  The short circuit detection circuit 21 shown in FIG. 5 is obtained by adding a phase change circuit 22 (delay circuit, threshold voltage generation circuit) to the short circuit detection circuit 18, and the phase change circuit 22 includes the excitation signal generation circuit 2 and the threshold value. It is inserted between the voltage generation circuit 7. As shown in FIG. 6, the phase change circuit 22 is configured as a phase shift circuit by an operational amplifier OP8, resistance elements R24 to R26, and a capacitor C7.

  The inverting input terminal and the non-inverting input terminal of the operational amplifier OP8 are connected to the output terminal of the operational amplifier OP7 via resistance elements R24 and R25, respectively. The inverting input terminal is connected to the output terminal of the operational amplifier OP8 via the resistor element R26, and the non-inverting input terminal is connected to the ground via the capacitor C7. The output terminal of the operational amplifier OP8 is connected to the input terminal of the threshold voltage generation circuit 7. As a result, the excitation signal input to the phase change circuit 22 via the operational amplifier OP7 is output to the threshold voltage generation circuit 7 at the next stage with the phase delayed by 90 degrees.

  Next, the operation of this embodiment will be described. Note that the timing charts shown in FIGS. 7 to 14 are signal waveforms in a state where the rotation of the resolver 1 is stopped. As shown in FIG. 7, if the operation of the resolver 1 is normal and there is no ideal phase shift between the signals, the detection target voltage V1 is one terminal voltage COS of the cosine phase winding I2_1. And, it becomes constant at the midpoint voltage V3 with respect to the other terminal voltage COSG in the opposite phase (see FIG. 7B). Similarly, the detection target voltage V2 is constant at the midpoint voltage V4 between the terminal voltage SIN of the sine phase winding I2_2 and the terminal voltage SING having the opposite phase (see FIG. 7C).

In the same figure, threshold voltages VT1 'and VT2' which are set at a constant level in the past are also shown. The threshold voltage VT1 ′ is set between the voltage V3 and the voltage (V3 + V4) / 2, and the threshold voltage VT2 ′ is set between the voltage V4 and the voltage V4 / 2. The threshold voltage VT1 generated by the short circuit detection circuit 18 is a voltage that changes in the opposite phase of the excitation signal V5 with the voltage VT1 ′ (= REF1) as the center.
When the cosine phase winding I2_1 and the sine phase winding I2_2 are short-circuited from this state, the detection target voltages V1 and V2 are equal to (V3 + V4) / 2 as shown in FIG. At this time, since the output signal of the comparator CP1 is continuously at the low level, the count value of the counter 12 of the digital filter 8 is increased, and the short circuit detection signal is output as described above.

  FIG. 9 shows a case where the terminal voltages COS and SIN have a phase shift with respect to the excitation signal V5, and there is also a phase shift between the terminal voltages COS and COSG and between the terminal voltages SIN and SING. In this case, it is necessary to cope with the short circuit detection circuit 21 provided with the phase change circuit 22, and the phase difference of the detection target voltages V1 and V2 is measured to adjust the phase delay to be applied to the threshold voltages VT1 and VT2. . In the example shown in FIG. 9, the threshold voltages VT1 and VT2 (the present plan threshold) are synchronized with the AC changes indicated by the detection target voltages V1 and V2 by giving a phase difference of 90 degrees.

  FIG. 10 shows a case where the cosine phase winding I2_1 and the sine phase winding I2_2 are short-circuited in a state where the terminal voltages COS and COSG have a phase shift different from the case shown in FIG. However, the phase difference applied to the threshold voltage VT1 is the same as that shown in FIG. In this case, the change in the threshold voltage VT1 is not completely synchronized with the change in the detection target voltage V1, but the latter becomes lower than the former for every predetermined interval in the period of the excitation signal. Therefore, a short circuit detection signal is output by the digital filter 8.

  FIG. 11 shows a case where the voltage COS side terminal of the cosine phase winding I2_1 and the ground side terminal of the primary side excitation winding I1 are short-circuited. Since the terminal voltage COS = 0V, the detection target voltage V1 changes in an alternating manner around 0V. Although not shown, when a diode is used as the negative voltage side protection circuit, the negative voltage is clamped by the forward voltage Vf of the diode. In this case, since the detection target voltage V1 is continuously lower than the threshold voltage VT2, a short circuit detection signal is output by the digital filter 8. FIG. 12 shows a case where the voltage SIN side terminal of the sine phase winding I2_2 and the ground side terminal of the primary side excitation winding I1 are short-circuited, and shows the same change as in FIG.

FIG. 13 shows a case where the cosine phase winding I2_1 and the sine phase winding I2_2 are short-circuited in a state where there is no phase shift. Since the detection target voltage V1 does not decrease greatly, it cannot be detected by the conventional constant level threshold voltage VT1 ′. However, in this embodiment, the detection target voltage V1 periodically falls below the threshold voltage VT1, and the digital filter 8 A short circuit detection signal is output. FIG. 14 is a diagram corresponding to FIG. 13 when there is a phase shift. In this case as well, the former periodically falls below the latter according to the phase difference between the detection target voltage V1 and the threshold voltage VT1. .
The above description has been made with respect to a state in which the rotation of the detection target by the resolver 1 is stopped. However, even when the detection target is rotating, the period of the excitation signal is generally greater than the rotation period of the detection target. Since it is set sufficiently short, detection can be performed similarly.

  As described above, according to the present embodiment, the first comparison voltage generation circuit 4 (1) uses the DC first offset voltage V3 as the sum of the terminal voltages with respect to the ground for the cosine phase winding I2_1. In addition, the comparison target voltage V1 is generated, and the first comparison circuit 6 (1) compares the comparison target voltage V1 with the first threshold voltage VT1. The second comparison voltage generation circuit 4 (2) generates a comparison target voltage V2 by adding the second DC offset voltage V4 to the sum of the terminal voltages with respect to the ground for the sine phase winding I2_2. The second comparison circuit 6 (2) compares the comparison target voltage V2 with the second threshold voltage VT2.

  Then, the first and second threshold voltage generation circuits 7 (1) and 7 (2) change the first and second threshold voltages VT1 and VT2 at the same frequency as the excitation signal input to the excitation winding I1. Generated as a voltage signal, the digital filter 8 receives the output signals of the first and second comparison circuits 6 (1) and 6 (2), and between the two windings I2_1 and I2_2 based on the change of the output signal Or a short circuit between the excitation winding I1 and the secondary windings I2_1 and I2_2 is output.

With this configuration, the first and second threshold voltages VT1 and VT2 applied to the first and second comparison circuits 6 (1) and 6 (2), respectively, are voltage signals that change at the same frequency as the excitation signal. Therefore, a capacitor for smoothing the threshold voltage becomes unnecessary. Therefore, an increase in circuit mounting area and an increase in cost can be suppressed while maintaining the accuracy of short circuit detection.
Further, the phase change circuit 22 for delaying the phase of the excitation signal is provided, and the first and second threshold voltages VT1 and VT2 are generated as voltage signals based on the delayed phase. Therefore, even when there is a deviation in the phase of each voltage signal on the secondary side with respect to the excitation signal, a short circuit between the windings can be reliably detected.

  Further, the average level of the threshold voltage VT1 corresponding to the first offset voltage V3 (VH) side is set to a range lower than the first offset voltage V3 and higher than the voltage (V3 + V4) / 2, and the second offset voltage V4. The average level of the threshold voltage VT2 corresponding to the (VL) side was set lower than the second offset voltage V4. Thereby, a short circuit between the windings I2_1 and I2_2, a short circuit between the excitation winding I1 and the secondary windings I2_1 and I2_2, and a rare short circuit between the windings I2_1 and I2_2 can be detected.

  In addition, the digital filter 8 is a frequency-divided clock signal output by the timer 15 for the time when the level of the output signal of the first or second comparison circuit 6 (1) or 6 (2) has changed from the level indicated at normal time. The counter 12 continuously measuring within the period T1 is provided, and a short circuit detection signal is output when the count value of the counter 12 exceeds a predetermined value within the period T1. Accordingly, when the comparison target voltages V1 and V2 and the threshold voltages VT1 and VT2 change in an alternating manner, an output signal of the first or second comparison circuit 6 (1) or 6 (2) when a short circuit occurs. Even when the level changes intermittently, a short circuit can be reliably detected.

(Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different parts will be described. As shown in FIG. 15, the short-circuit detection circuit 23 of the second embodiment includes two phase change circuits 22 corresponding to the threshold voltages VT1 and VT2. The phase change circuit 22 (1) has the same configuration as the phase change circuit 22 of the first embodiment, and the output terminal of the operational amplifier OP8 is connected only to the resistor element R18.

Further, the phase change circuit 22 (2) is configured similarly to the phase change circuit 22 (1) by an operational amplifier OP9, resistance elements R27 to R29, and a capacitor C8. However, when it is necessary to change the phase difference applied to the threshold voltages VT1 and VT2 by the phase change circuits 22 (1) and 22 (2), for example, the resistance value of the resistance element in one circuit is changed. Make adjustments.
As described above, according to the second embodiment, since the phase change circuits 22 (1) and 22 (2) are individually provided corresponding to the threshold voltages VT1 and VT2, the cosine phase winding I2_1 side, Even when the amount of phase shift generated on the winding I2_2 side is different, it can be individually adjusted.

(Third embodiment)
As shown in FIG. 16, the short circuit detection circuit 31 of the third embodiment includes a voltage generation circuit 32 (1, 2) instead of the threshold voltage generation circuit 7 (1, 2) of the first embodiment. . The first threshold voltage generation circuit 32 (1) includes an NPN transistor TR1 and resistance elements R31 to R33, and the base of the NPN transistor TR1 is connected to the output terminal of the operational amplifier OP5. The emitter of the NPN transistor TR1 is connected to the ground, and the collector is connected to the common connection point of the series circuit composed of the resistance elements R31 and R32 via the resistance element R33. The other end of the resistor element R31 is connected to the power source, and the other end of the resistor element R32 is connected to the ground. The threshold voltage VT1 is output from the other end of the resistance element R31. The second threshold voltage generation circuit 32 (2) includes an NPN transistor TR2 and resistance elements R34 to R36, and has a circuit configuration similar to that of the first threshold voltage generation circuit 32 (1).

  According to the third embodiment configured as described above, the bases of the NPN transistors Tr1 and Tr2 are driven by the output signals of the operational amplifiers OP5 and OP6, so that the threshold voltages VT1 and VT2 are binary level signals (rectangular waves). Signal).

(Fourth embodiment)
As shown in FIG. 16, the short circuit detection circuit 41 of the fourth embodiment is applied to an electromagnetic device 42 having a three-phase secondary winding instead of the resolver 1. The electromagnetic device 42 includes a first phase winding I2_1, a second phase winding I2_2, and a third phase winding I2_3 as secondary windings.

  The short-circuit detection circuit 41 includes a third offset voltage generation circuit 3 (3), a third comparison voltage generation circuit 4 (3), a second comparison circuit, and the like in accordance with the addition of the winding I2_3 to the configuration of the first embodiment. 3 differential amplifier circuit 5 (3), 3rd comparison circuit 6 (3), and 3rd threshold voltage generation circuit 7 (3) are provided. The output terminals of the first to third comparison circuits 6 (1 to 3) are respectively connected to the input terminals of the digital filter 8, and the short-circuit detection is performed by the digital filter 8 as in the first embodiment.

  In the case of the fourth embodiment, each of the circuits 3, 4, 6, and 7 has first to third, and one of the two phases in which a short circuit occurs and the other of the two phases are claims. This corresponds to the first and second. According to the fourth embodiment configured as described above, the short circuit detection circuit 41 can be applied to the electromagnetic device 42 in which the secondary winding has a three-phase configuration.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The internal logic of the digital filter 8 may be appropriately changed within a range in which short circuit detection can be performed in the same manner.
A delay line or the like may be used for the delay circuit.
You may apply to the electromagnetic equipment from which a secondary side coil becomes a structure of 4 phases or more.

  In the drawings, 1 is a resolver (electromagnetic device), 3 is an offset voltage generation circuit, 4 is a comparison voltage generation circuit, 6 is a comparison circuit, 7 is a threshold voltage generation circuit, 8 is a digital filter (detection signal output circuit), and 12 is Counter (measurement circuit), 18 and 21 are short circuit detection circuits, 22 is a phase change circuit (delay circuit, threshold voltage generation circuit), I1 is an excitation winding, I2_1 is a cosine phase winding (multiphase winding), and I2_2 is A sine phase winding (multi-phase winding) is shown.

Claims (4)

Short circuit between the excitation winding (I1) arranged on the primary side of the electromagnetic device (1) and the multiphase winding (I2_1, I2_2) arranged on the secondary side of the electromagnetic device, or the multiphase winding In a short circuit detection circuit that detects at least one of short circuits between lines,
A first comparison voltage generation circuit (4 (1)) that generates a first comparison voltage by adding a first DC offset voltage to the sum of terminal voltages with respect to the ground in one of the multiphase windings. When,
A first comparison circuit (6 (1)) for comparing the first comparison voltage with a first threshold voltage;
The second comparison voltage is obtained by adding a second DC offset voltage set to a value different from the first offset voltage to the sum of the terminal voltages with respect to the ground in the other one of the multiphase windings. A second comparison voltage generation circuit (4 (2)) for generating
A second comparison circuit (6 (2)) for comparing the second comparison voltage with a second threshold voltage;
First and second threshold voltage generation circuits (7 (1), 7 (2) that generate the first and second threshold voltages as voltage signals that change at the same frequency as the excitation signal input to the excitation winding. )When,
And a detection signal output circuit (8) for outputting a short-circuit detection signal when the output signal of the first and second comparison circuits is input and the short circuit is detected based on a change in the output signal. Short circuit detection circuit for electromagnetic equipment. The first and second threshold voltage generation circuits include a delay circuit (22) that delays the phase of the excitation signal,
The short circuit detection circuit for an electromagnetic device according to claim 1, wherein the first and second threshold voltages are generated as voltage signals based on the delayed phase. Of the first and second offset voltages, the higher voltage is the voltage VH, and the lower voltage is the voltage VL.
An average level of the threshold voltage corresponding to the voltage VH side is set to a range lower than the voltage VH and higher than the voltage (VH + VL) / 2;
The short circuit detection circuit for an electromagnetic device according to claim 1 or 2, wherein an average level of a threshold voltage corresponding to the voltage VL side is set lower than the voltage VL. The detection signal output circuit includes a measurement circuit (12) that continuously measures within a predetermined monitoring period the time when the level of the output signal of the first or second comparison circuit has changed from the level indicated at the normal time. ,
4. The electromagnetic device according to claim 1, wherein the short-circuit detection signal is output when a measurement value of the measurement circuit exceeds a predetermined value at the end of the monitoring period. 5. Short circuit detection circuit.

Images