JP6078458B2 - Thyristor converter voltage detection error detection circuit - Google Patents

Description

  This embodiment is used for DC power transmission and the like, and a voltage detection abnormality that detects an abnormality in the output of a forward voltage detection circuit and / or a reverse voltage detection circuit provided in a thyristor converter having a thyristor valve in which a plurality of thyristors are connected in series The present invention relates to a detection circuit.

  In the thyristor converters such as Patent Document 1 and Patent Document 2, from the viewpoint of preventing the apparatus from continuing abnormal operation due to an abnormality in the forward voltage detection circuit or the reverse voltage detection circuit, the forward voltage detection circuit is abnormal. A detection circuit and a reverse voltage detection circuit abnormality detection circuit are provided.

  In this case, if the normal device is normal, the forward voltage detection signal and the reverse voltage detection signal are at the H level within the period of the frequency of the AC system to which the thyristor converter is connected. In addition, the forward voltage detection circuit abnormality detection circuit and the reverse voltage detection circuit abnormality detection circuit use the repetition of L level and L level as an abnormality when the forward voltage detection signal or the reverse voltage detection signal continues to be at the H level or the L level for a predetermined period. It is usually done to detect.

  In addition, when the gate control device is a single system, the abnormality detection time limit of the forward voltage detection circuit and the reverse voltage detection circuit is shorter than the set time limit of the commercial frequency detection relay from the viewpoint of facilitating investigation of the cause of failure, and is about 100 ms. It is desirable to do. In addition, when the abnormality detection time limit of the forward voltage detection circuit and the reverse voltage detection circuit is relatively short as described above, in the case of special operation such as bypass pair operation, the bypass pair arm is in the bypass pair state even if the device is normal. The anomaly detection signal of the forward voltage detection signal and the reverse voltage detection signal is locked.

Japanese Patent Laid-Open No. 5-56663 JP-A-5-344707

  In the circuits of Patent Document 1 and Patent Document 2, there is a problem that an abnormality of the voltage detection circuit is unnecessarily detected due to the main circuit phenomenon at the time of stoppage even if a device failure does not occur. In order to avoid such unnecessary detection, if the time limit of the forward voltage circuit FV and the reverse voltage detection circuit RV is made extremely long to eliminate the influence of the transient phenomenon of DC voltage superposition, a commercial frequency intrusion detection relay is used. The detection time limit (approximately 150 ms) and the continuous commutation failure detection cannot be coordinated, and there is a problem that it becomes difficult to investigate the cause of the malfunction when an actual operation occurs.

  The purpose of this embodiment is to detect abnormalities in the output of the forward voltage detection circuit and / or the reverse voltage detection circuit without making the detection time limit extremely long and without causing unnecessary operation when the converter is stopped. An object of the present invention is to provide a detection abnormality detection circuit.

According to a typical embodiment, the power of the electric power system is converted into electric power, and a circuit breaker is connected between the electric power system and a thyristor valve configured by connecting a plurality of thyristors in series. A plurality of forward voltage detection circuits for detecting a forward voltage applied to each thyristor and outputting a forward voltage detection signal; and detecting a reverse voltage applied to at least one of the thyristors. and a reverse voltage detection circuit for outputting a reverse voltage detection signal, the one-shot circuit for outputting a predetermined time Mapa pulse signal after receiving a gate block signal from the control circuit, the output signal of the one-shot circuit, the control a bypass pair signal and breaker open state detection signal indicating the open state of the circuit breaker from the circuit inputs respectively, out of the logic signals when these signals are all absent A first summing circuit for inverting the forward voltage detection signal, a second inverting circuit for inverting the reverse voltage detection signal, and the output of the OR circuit are input to one input terminal, respectively. The forward voltage detection signal , the reverse voltage detection signal , the output of the first inversion circuit, and the output of the second inversion circuit are input to the other input terminals, respectively , and the logical signal is output when the logical product condition is satisfied. 4 AND circuits to be output, 4 delay circuits to which outputs of the AND circuits are input, and output after being delayed by a predetermined time shorter than an output pulse time of the one-shot circuit, and the delays input to the set terminal having an output of the circuit to each respective forward voltage signal continuously perforated abnormality signal from an output terminal with each reverse voltage signal continuously perforated abnormality signal, the forward voltage signal continuously no abnormal signal, and the reverse voltage signal Continued no abnormal signal is output, respectively, the control circuit voltage detection abnormality of the thyristor converter equipped with four reset flip-flop output signal is no when input to the reset terminal, the having a reset signal to each of the This is a detection circuit.

The figure which shows the DC power transmission system with which this embodiment is applied. The figure for demonstrating the main circuit of the 12 phase thyristor converter of FIG. The figure showing the connection of the thyristor valve module for demonstrating some thyristor valves of the thyristor converter of FIG. The circuit diagram showing the inside of one thyristor valve module which constitutes the thyristor valve of FIG. The schematic block diagram of the conventional voltage detection abnormality detection circuit. 6 is a time chart for explaining the operation of FIG. The schematic block diagram for demonstrating the voltage detection abnormality detection circuit of this embodiment. 8 is a time chart for explaining the operation of FIG.

  Hereinafter, embodiments will be described with reference to the drawings. First, problems of the inventions in Patent Documents 1 and 2, which are conventional devices, will be described with reference to FIGS. FIG. 1 shows a DC power transmission circuit connected between a power system A and a power system B via transformers 1, 2, 7, and 8. Thyristor converters 3 and 4 connected in series, Furthermore, thyristor converters 5 and 6 and DC reactors 9 and 10 connected in series are provided. Depending on the system, the DC reactor may be only one of 9 and 10.

  FIG. 2 is a diagram for explaining a main circuit of a 12-phase thyristor converter, which is the thyristor converters 5 and 6 of FIG. 1, and is configured as follows. It consists of 12 thyristor arms constituting a power converter, and thyristor valves 5U, 5V, 5W, 5X, 5Y, 5Z, 6U, 6V, 6W, 6X, 6Y, and 6Z are connected to each thyristor arm.

  The primary output winding (star connection) of the high voltage side conversion transformer 7 is connected to the AC output terminal of the thyristor converter 5, and the secondary winding (star connection) of the transformer 7 is connected to the power system. Connected to B. The primary side winding (triangular connection) of the low-voltage side conversion transformer 8 is connected to the AC output terminal of the thyristor converter 6, and the secondary winding (star connection) of the transformer 8 is connected to the power system B. It is connected to the.

  FIG. 3 is a view for explaining the configuration of the thyristor valve 5U of FIG. The thyristor valve 5U is generally constituted by connecting a plurality of thyristor valve modules 5UM-1 to 5UM-N in series as shown in FIG. The thyristor valves 5V, 5W, 5X, 5Y, 5Z, 6U, 6V, 6W, 6X, 6Y, and 6Z have the same configuration.

  FIG. 4 shows one set of thyristor valve modules among the thyristor valve modules 5UM-1 to 5UM-N of FIG. 3, for example, seven optical thyristors TH1 to TH7 (hereinafter simply referred to as thyristors TH1 to TH7). A series connection, anode reactors AL1 and AL2 are connected to both ends of the series connection, a snubber circuit consisting of a series circuit of a capacitor C1 and a resistor RS1 is connected in parallel to a thyristor TH1, and a snubber circuit consisting of a capacitor C1 and a resistor RS1 A series circuit of a voltage dividing resistor RD1 and a voltage detector VD1 is connected in parallel, and a snubber circuit and a voltage detector are similarly connected to the other thyristors TH2 to TH7.

That is, a snubber circuit composed of a series circuit of a capacitor C2 and a resistor RS2 is connected in parallel to the thyristor TH2, and a series circuit of a voltage dividing resistor RD2 and a voltage detector VD2 is connected in parallel to a snubber circuit composed of the capacitor C2 and the resistor RS2. ,
A snubber circuit composed of a series circuit of a capacitor C3 and a resistor RS3 is connected in parallel to the thyristor TH3, and a series circuit of a voltage dividing resistor RD3 and a voltage detector VD3 is connected in parallel to a snubber circuit composed of the capacitor C3 and the resistor RS3.
A snubber circuit consisting of a series circuit of a capacitor C4 and a resistor RS4 is connected in parallel to the thyristor TH4, and a series circuit of a voltage dividing resistor RD4 and a voltage detector VD4 is connected in parallel to a snubber circuit consisting of a capacitor C4 and a resistor RS4.
A snubber circuit composed of a series circuit of a capacitor C5 and a resistor RS5 is connected in parallel to the thyristor TH5, and a series circuit of a voltage dividing resistor RD5 and a voltage detector VD5 is connected in parallel to the snubber circuit composed of the capacitor C5 and the resistor RS5.
A snubber circuit composed of a series circuit of a capacitor C6 and a resistor RS6 is connected in parallel to the thyristor TH6, and a series circuit of a voltage dividing resistor RD6 and a voltage detector VD6 is connected in parallel to the snubber circuit composed of the capacitor C6 and the resistor RS6.
A snubber circuit composed of a series circuit of a capacitor C7 and a resistor RS7 is connected in parallel to the thyristor TH7, and a series circuit of a voltage dividing resistor RD7 and a voltage detector VD7 is connected in parallel to the snubber circuit composed of the capacitor C7 and the resistor RS7. is there.

  A gate signal from a gate control circuit (not shown) is supplied to the gates of the thyristors TH1 to TH7 via gate light guides G1 to G7, respectively.

  The voltage detectors VD1 to VD6 are provided with forward voltage detection circuits FV1 to FV6, respectively. The voltage detector VD7 includes a forward voltage detection circuit FV7 and a reverse voltage detection circuit RV7.

  In each of the forward voltage detection circuits FV1 to FV7, when a forward voltage (direction from the anode to the cathode of the thyristor) is applied to the thyristor, the light emitting diode emits light, and this optical signal is converted into a voltage signal by the photoelectric converter. These voltage signals are converted and output to a control circuit (not shown) via voltage detection light guides F1 to F7, respectively.

  Similarly to the forward voltage detection circuit FV, the reverse voltage detection circuit RV1 emits light from a light emitting diode when a reverse voltage (direction from the cathode of the thyristor toward the anode) is applied to the thyristor, and photoelectrically converts this optical signal. The voltage signal is converted by a detector, and the voltage signal is output to a control circuit (not shown) via the voltage detection light guide R1. As with the reverse voltage detection circuit RV1, the reverse voltage detection circuit RV2 emits light from a light emitting diode when a reverse voltage (direction from the cathode of the thyristor toward the anode) is applied to the thyristor, and photoelectrically converts this optical signal. The voltage signal is converted by a detector, and the voltage signal is output to a control circuit (not shown) via a voltage detection light guide (not shown).

  The thyristor converters 3, 4, 5, and 6 are all configured in the same way and convert power of the power system (A and B in FIG. 1), and are formed by connecting a plurality of thyristors in series. Multiple sets of valve modules are arranged, and each thyristor valve module is connected in series to provide a thyristor valve, which detects the open state of a circuit breaker (not shown) connected to the power system and responds to this. Circuit breaker open state detection signal, bypass pair signal (BPP signal) given to thyristor valve, reset signal, gate block signal (GB signal) given to said thyristor valve, and gate signal given to thyristor valve are outputted at desired timing A control circuit (not shown).

  FIG. 5 is a configuration diagram of a conventional voltage detection abnormality detection circuit. The OR circuit 31 detects a forward voltage applied to each thyristor constituting each thyristor valve module shown in FIG. 4 and outputs a plurality of forward voltage detection circuits FV1 to FVN for outputting a forward voltage detection signal (FV signal). The signal is received by an opto-electric conversion circuit (not shown), converted into an electric signal, and then the logical sum of these signals is integrated to output a forward voltage detection signal (FV signal). The inversion circuit 17 is a first inversion circuit that inverts the output of the OR circuit 31.

  The inverting circuit 18 detects a reverse voltage applied to at least one of the thyristors constituting the thyristor valve module shown in FIG. 4 and outputs a reverse voltage detection signal to a photoelectric conversion circuit (not shown). And a second inverting circuit for inverting the reverse voltage detection signal (RV signal) received and converted into an electrical signal.

  The OR circuit 12 includes a circuit breaker open state signal from a circuit breaker (not shown) installed between the power system shown in FIG. 1 and the transformers 7 and 8, and a bypass pair signal (BPP signal) from a control circuit (not shown). Is a logical sum circuit that outputs a logical sum of

The inversion circuit 32 is a third inversion circuit that inverts the output of the OR circuit 12.

The logical product circuit 13 inputs the output of the logical sum circuit 31 to one input terminal, inputs the output of the third inverting circuit 32 to the other input terminal, and outputs a logical signal when the logical product condition is satisfied. AND circuit.

  The AND circuit 14 inputs the output of the first inverting circuit 17 to one input terminal, inputs the output of the third inverting circuit 32 to the other input terminal, and outputs a logic signal when the AND condition is satisfied. This is a second AND circuit.

  The AND circuit 15 detects a reverse voltage applied to at least one of the thyristors constituting the thyristor valve module shown in FIG. 4, and outputs a reverse voltage detection signal RV1 which is not shown in the figure. When the reverse voltage detection signal (RV signal) received and converted into an electric signal is input to one input terminal and the output of the third inverting circuit 32 is input to the other input terminal, the logical product condition is satisfied. A third AND circuit that outputs a logic signal.

  The AND circuit 16 inputs the output of the second inverting circuit 18 to one input terminal, inputs the output of the third inverting circuit 32 to the other input terminal, and outputs a logic signal when the AND condition is satisfied. This is a fourth logical product circuit.

  The delay circuit 19 is a first delay circuit whose output becomes H level when the duration time during which the output signal of the first AND circuit 13 is in the H level state is equal to or longer than a preset time T1.

  The delay circuit 20 is a second delay circuit whose output becomes H level when the duration time during which the output signal of the second AND circuit 14 is in the H level state is equal to or longer than a preset time T2.

  The delay circuit 21 is a third delay circuit whose output becomes H level when the duration time during which the output signal of the third AND circuit 15 is in the H level state is equal to or longer than a preset time T3.

  The delay circuit 22 is a fourth delay circuit whose output becomes H level when the duration time during which the output signal of the fourth AND circuit 16 is in the H level state is equal to or longer than a preset time T4.

  Here, the setting time periods T1 to T4 of the delay circuits 19 to 22 may be set to about 100 ms.

  The flip-flop 23 inputs the output of the first delay circuit to the set terminal, inputs a reset signal from a control circuit (not shown) to the reset terminal, and the output becomes H when the set terminal is at the H level and the reset terminal is at the L level. This is the first flip-flop to be set, and its output signal becomes a forward voltage signal continuous abnormality signal (FV signal continuous abnormality).

  The flip-flop 24 inputs the output of the second delay circuit to the set terminal, inputs a reset signal from a control circuit (not shown) to the reset terminal, and the output becomes H when the set terminal is at the H level and the reset terminal is at the L level. The second flip-flop to be set, and its output signal becomes a forward voltage signal continuous non-abnormal signal (FV signal continuous non-abnormal).

  The flip-flop 25 inputs the output of the third delay circuit to the set terminal, inputs a reset signal from a control circuit (not shown) to the reset terminal, and the output becomes H when the set terminal is at the H level and the reset terminal is at the L level. The third flip-flop to be set, and its output signal becomes a reverse voltage signal continuous abnormality signal (RV signal continuous abnormality).

  The flip-flop 26 inputs the output of the fourth delay circuit to the set terminal, inputs a reset signal from a control circuit (not shown) to the reset terminal, and the output becomes H when the set terminal is at the H level and the reset terminal is at the L level. The fourth flip-flop to be set, and its output signal becomes a reverse voltage signal continuous non-abnormal signal (RV signal continuous non-abnormal).

  FIG. 6 is a time chart showing the operation of the circuit of FIG. While the converter is in operation, since the circuit breaker (not shown) installed between the power system shown in FIG. 1 and the transformers 7 and 8 is in the on state, the circuit breaker open state signal is at L level, and control not shown in the figure. The bypass pair signal (BPP signal) from the circuit is also at the L level. Therefore, the output of the OR circuit 12 is L level, and the output of the inverting circuit 32 is H level.

  Further, since the thyristor valve repeats turning on and off while the converter is operating, the thyristor is turned off at time t1, and when the voltage of the thyristor exceeds the reverse voltage detection level in the negative direction, the RV signal becomes H level, and the inverting circuit 18 Are at the L level, the output of the AND circuit 15 is at the H level, and the output of the AND circuit 16 is at the L level. At this time, since the voltage of the thyristor is lower than the forward voltage detection level, the FV signal output from the OR circuit 31 is at L level, the output of the inverting circuit 17 is at H level, and the output of the AND circuit 13 is at L level. The output of the AND circuit 14 is at the H level.

  When the voltage of the thyristor exceeds the reverse voltage detection level in the positive direction at time t2, the RV signal becomes L level, the output of the inverting circuit 18 is H level, the output of the AND circuit 15 is L level, and the AND circuit The output of 16 is H level. Further, when the voltage of the thyristor exceeds the forward voltage detection level in the positive direction, the FV signal that is the output of the OR circuit 31 becomes H level, the output of the inverting circuit 17 becomes L level, and the output of the AND circuit 13 is H level. Yes, the output of the AND circuit 14 is at L level.

  When the thyristor is turned off at time t3, since the voltage of the thyristor is below the forward voltage detection level at this time, the FV signal that is the output of the OR circuit 31 is L level, and the output of the inverting circuit 17 is H level. The output of the product circuit 13 is L level, and the output of the AND circuit 14 is H level.

  When the thyristor is turned off at time t4 and the voltage of the thyristor exceeds the reverse voltage detection level in the negative direction, the RV signal becomes H level, the output of the inverting circuit 18 is L level, and the output of the AND circuit 15 is H level. Yes, the output of the AND circuit 16 is at L level.

  In this manner, since the H level and the L level are repeated at least once during one cycle of the frequency of the power system, the AND circuits 13, 14, 15, and 16 are set time limits of the delay circuits 19, 20, 21, and 22, respectively. There is no continuous H level for a period longer than T1, T2, T3, and T4. Therefore, since the flip-flops 23, 24, 25 and 26 are not set, the forward voltage no abnormality detection signal (FV signal continuous no abnormality), the reverse voltage presence abnormality detection signal (RV signal continuous abnormality), the reverse voltage no abnormality None of the detection signals (RV signal continuous no abnormality) is detected.

  Here, although not shown in FIG. 6, when the reverse voltage signal RV continuously becomes H level due to some component failure during operation, the output of the AND circuit 15 continuously becomes H level, so that the delay circuit 21 The flip-flop 26 is set when the output of the AND circuit 15 continues to be at the H level for the set time T3 or longer, and becomes a reverse voltage abnormality detection signal (RV signal continuous abnormality).

  During the bypass pair period, the FV signal and the RV signal are continuously at the L level in the main circuit even if no device failure occurs. Therefore, the logical sum is obtained by setting the BPP signal to the H level from a control circuit (not shown). Since the output of the circuit 12 becomes H level and the output of the inverting circuit 32 becomes L level, the input at one end of the AND circuits 13, 14, 15 and 16 becomes L level, so regardless of the signal state at the other end. When the outputs of the AND circuits 13, 14, 15, and 16 become L level, a forward voltage presence / absence detection signal (FV signal continuous presence / absence), a forward voltage absence / abnormality detection signal (FV signal continuity / abnormality), a reverse voltage presence Unnecessary operations of the abnormality detection signal (RV signal continuous abnormality) and the reverse voltage non-abnormality detection signal (RV signal continuous abnormality) are prevented.

  Further, when a circuit breaker (not shown) installed between the power system shown in FIG. 1 and the transformers 7 and 8 is in an open state, the FV signal and the RV signal are continuously at the L level in the main circuit. Since the FV signal and the RV signal may be continuously at H level due to induction, residual charge, etc., the circuit breaker (not shown) installed between the power system shown in FIG. Since the circuit breaker open state signal becomes H level, the output of the OR circuit 12 becomes H level, the output of the inverting circuit 32 becomes L level, and the input at one end of the AND circuits 13, 14, 15 and 16 is applied. Since it becomes L level, regardless of the signal state at the other end, the outputs of the AND circuits 13, 14, 15, 16 become L level, so that a forward voltage presence / absence detection signal (FV signal continuous presence / absence) and forward voltage no abnormality Detection signal (FV No. Continuous no abnormality), the reverse voltage chromatic abnormality detection signal (RV signal continuous chromatic abnormality), thereby preventing unnecessary operations of the inverse voltage is not abnormal detection signal (RV signal continuous no abnormality).

  However, even if the 12-phase converter in which 6 pulse bridges are connected in series is not in the bypass pair state, when the transition from the bypass pair state to the gate block state is made, the extinction timing of the bypass pair arm is the AC voltage and the forced ignition circuit It may shift slightly due to the action of (strong point circuit). Depending on the timing at this time, the converter 5 that is the upper bridge of the 12-phase converter and the converter 6 that is the lower bridge may be charged to the vicinity of the DC rated voltage in reverse polarity. The AC voltage component applied to the arm after the gate block is equivalent to the phase voltage, and depending on the amount of DC component, the forward voltage detection circuit or reverse voltage detection circuit of the arm may operate continuously or may not operate continuously. As a result, the anomaly detection circuit may operate unnecessarily.

  This phenomenon will be described with reference to the timing chart of FIG. The period from time t5 to t6 is a bypass pair period. During this period, since the BPP signal becomes H level from a control circuit (not shown), the output of the OR circuit 12 becomes H level, and the output of the inverting circuit 32 becomes L level, so that the outputs of the AND circuits 13 to 16 all become L level. Become. When a gate block signal is output from a control circuit (not shown) at time t6, the BPP signal also goes to L level from the control circuit (not shown). At this time, since the bypass pair arm is still energized, the voltage of the thyristor valve is almost zero as shown in FIG. 6, the FV signal (output of the OR circuit 31) and the RV signal are L level, and the AND circuit 14 And 16 outputs become H level.

  Since the thyristor valve is not turned on after time t6, when the current of the DC circuit is cut off and the thyristor is turned off at time t7, a voltage is applied to the thyristor. The 12-phase converter with 6-pulse bridges connected in series is sensitive to the timing of extinguishing the bypass pair arm due to the AC voltage and the forced firing circuit (strong point circuit) when transitioning from the bypass pair state to the gate block state. May shift. Depending on the timing at this time, the upper bridge and the lower bridge of the 12-phase converter may be charged to the vicinity of the DC rated voltage with opposite polarity. That is, the converter 5 and the converter 6 are charged with opposite polarities.

  FIG. 6 shows a case where the converter 5 is charged in the forward direction and the converter 6 is charged in the reverse direction with such a waveform. When the thyristor valve is turned off at t7, the AC voltage component applied to the arm is equivalent to the phase voltage. When the DC component is greater than the AC component, the forward DC voltage is superimposed on the thyristor as shown at time t8. Even at the negative peak, the voltage of the thyristor is higher than the forward voltage detection. Therefore, the FV signal is at the H level and the RV signal is maintained at the L level. Since the output of the inverting circuit 32 is at the H level after t6, the output of the AND circuit 13 is maintained at the H level, the output of the AND circuit 14 is maintained at the L level, and the output of the AND circuit 15 is at the L level. , And the output of the AND circuit 16 maintains the H level. The direct current component superimposed on the thyristor converter is gradually discharged and reduced by a voltage dividing resistor connected in parallel to the thyristor, for example, RD1 to RD7. This discharge time constant is determined by a circuit constant, but may be about 100 ms.

  As shown in FIG. 6, when the voltage of the thyristor becomes equal to or lower than the forward voltage detection level at time t9, the FV signal becomes L level, so that the output of the AND circuit 13 becomes L level and the output of the AND circuit 14 becomes H level. Become. However, since there is a considerable amount of DC component superposition, the thyristor voltage does not exceed the reverse voltage detection level in the negative direction, and when the thyristor voltage becomes equal to or higher than the forward voltage detection level again at time t10, the FV signal becomes H level. Therefore, the output of the AND circuit 13 becomes H level, and the output of the AND circuit 14 becomes L level.

  Further, when the direct current component is attenuated and time t12 is reached, when the voltage of the thyristor falls below the forward voltage detection level, the FV signal becomes L level, so that the output of the AND circuit 13 becomes L level and the output of the AND circuit 14 becomes Becomes H level. At time t13, when the thyristor voltage exceeds the reverse voltage detection level in the negative direction, the RV signal becomes H level, so that the output of the AND circuit 15 becomes H level and the output of the AND circuit 16 becomes L level. .

  Further, when the voltage of the thyristor exceeds the reverse voltage detection level at time t14, the RV signal becomes L level, so that the output of the AND circuit 15 becomes L level and the output of the AND circuit 16 becomes H level.

  Further, at time t15, when the voltage of the thyristor becomes equal to or higher than the forward voltage detection level, the FV signal becomes H level, so that the output of the AND circuit 13 becomes H level and the output of the AND circuit 14 becomes L level.

  Thereafter, since the voltage peak value in the negative direction of the thyristor exceeds the reverse voltage detection level of the thyristor in the negative direction, the same repetition is performed, and the FV signal and the RV signal repeat H level and L level.

  As can be seen from FIG. 6, the output of the AND circuit 16 is kept at the H level during the period from t6 to t13. In FIG. 6, since the period during which the output of the AND circuit 16 is at the H level is longer than the set time limit (about 100 ms) of the delay circuit 22, the output of the delay circuit 22 becomes the H level at time t11 and the flip-flop 26 is set. A phenomenon occurs in which the reverse voltage no abnormality detection signal (RV signal continuous no abnormality) operates. FIG. 6 shows an example of the unnecessary operation of the reverse voltage no-abnormality detection signal (RV signal continuous no-abnormality). However, whether other voltage signal abnormality is detected by the set values of the delay circuits 19 to 22 or the polarity of the superimposed DC voltage is shown. It will be detected unnecessarily.

  As described above, the conventional circuit has a problem that the abnormality of the voltage detection circuit is unnecessarily detected due to the main circuit phenomenon at the time of stop even if no device failure occurs.

  In order to avoid such unnecessary detection, if the time limit of the forward voltage circuit FV and the reverse voltage detection circuit RV is made extremely long to eliminate the influence of the transient phenomenon of DC voltage superposition, a commercial frequency intrusion detection relay is used. The detection time limit (approximately 150 ms) and the continuous commutation failure detection cannot be coordinated, and there is a problem that it becomes difficult to investigate the cause of the malfunction when an actual operation occurs.

  In view of this, the voltage detection abnormality detection circuit of the present embodiment has the configuration shown in FIG. 7 in the thyristor converter shown in FIGS. 1 to 4 described above. Specifically, the OR circuit 31 detects a forward voltage applied to each thyristor constituting each thyristor valve module shown in FIG. 4, and outputs a plurality of forward voltage detection signals (FV signals). The circuits FV1 to FVN are received by a photoelectric conversion circuit (not shown), converted into an electrical signal, and then ORed together to output a forward voltage detection signal (FV signal). The inversion circuit 17 is a first inversion circuit that inverts the output of the OR circuit 31.

  The inverting circuit 18 detects a reverse voltage applied to at least one of the thyristors constituting the thyristor valve module shown in FIG. 4 and outputs a reverse voltage detection signal to a photoelectric conversion circuit (not shown). And a second inverting circuit for inverting the reverse voltage detection signal (RV signal) received and converted into an electrical signal.

  The one-shot circuit 11 is a circuit that outputs an H level signal for a predetermined time T5, for example, 140 ms after receiving a gate block signal from a control circuit (not shown).

The OR circuit 12a includes a circuit breaker open state signal from a circuit breaker (not shown) installed between the power system shown in FIG. 1 and the transformers 7 and 8, and a bypass pair signal (BPP signal) from a control circuit (not shown). ) And the logical sum of the output signals of the one-shot circuit 11.

  The inverting circuit 32 is a third inverting circuit that inverts the output of the OR circuit 12a.

The logical product circuit 13 inputs the output of the logical sum circuit 31 to one input terminal, inputs the output of the third inverting circuit 32 to the other input terminal, and outputs a logical signal when the logical product condition is satisfied. AND circuit.

  The AND circuit 14 inputs the output of the first inverting circuit 17 to one input terminal, inputs the output of the third inverting circuit 32 to the other input terminal, and outputs a logic signal when the AND condition is satisfied. This is a second AND circuit.

  The AND circuit 15 detects a reverse voltage applied to at least one of the thyristors constituting the thyristor valve module shown in FIG. 4, and outputs a reverse voltage detection signal RV1 which is not shown in the figure. When the reverse voltage detection signal (RV signal) received and converted into an electric signal is input to one input terminal and the output of the third inverting circuit 32 is input to the other input terminal, the logical product condition is satisfied. A third AND circuit that outputs a logic signal.

  The AND circuit 16 inputs the output of the second inverting circuit 18 to one input terminal, inputs the output of the third inverting circuit 32 to the other input terminal, and outputs a logic signal when the AND condition is satisfied. This is a fourth logical product circuit.

  The delay circuit 19 is a first delay circuit whose output becomes H level when the duration time during which the output signal of the first AND circuit 13 is in the H level state is equal to or longer than a preset time T1.

  The delay circuit 20 is a second delay circuit whose output becomes H level when the duration time during which the output signal of the second AND circuit 14 is in the H level state is equal to or longer than a preset time T2.

  The delay circuit 21 is a third delay circuit whose output becomes H level when the duration time during which the output signal of the third AND circuit 15 is in the H level state is equal to or longer than a preset time T3.

  The delay circuit 22 is a fourth delay circuit whose output becomes H level when the duration time during which the output signal of the fourth AND circuit 16 is in the H level state is equal to or longer than a preset time T4.

  The flip-flop 23 inputs the output of the first delay circuit to the set terminal, inputs a reset signal from a control circuit (not shown) to the reset terminal, and the output becomes H when the set terminal is at the H level and the reset terminal is at the L level. This is the first flip-flop to be set, and its output signal becomes a forward voltage signal continuous abnormality signal (FV signal continuous abnormality).

  The flip-flop 24 inputs the output of the second delay circuit to the set terminal, inputs a reset signal from a control circuit (not shown) to the reset terminal, and the output becomes H when the set terminal is at the H level and the reset terminal is at the L level. The second flip-flop to be set, and its output signal becomes a forward voltage signal continuous non-abnormal signal (FV signal continuous non-abnormal).

  The flip-flop 25 inputs the output of the third delay circuit to the set terminal, inputs a reset signal from a control circuit (not shown) to the reset terminal, and the output becomes H when the set terminal is at the H level and the reset terminal is at the L level. The third flip-flop to be set, and its output signal becomes a reverse voltage signal continuous abnormality signal (RV signal continuous abnormality).

  The flip-flop 26 inputs the output of the fourth delay circuit to the set terminal, inputs a reset signal from a control circuit (not shown) to the reset terminal, and the output becomes H when the set terminal is at the H level and the reset terminal is at the L level. The fourth flip-flop to be set, and its output signal becomes a reverse voltage signal continuous non-abnormal signal (RV signal continuous non-abnormal).

  Here, the setting time periods T1 to T4 of the delay circuits 19 to 22 may be set to about 100 ms as described above.

  FIG. 8 is a time chart showing the operation of the circuit of FIG. The description up to time t6 is omitted because it is the same as FIG. When a gate block signal is output from a control circuit (not shown) at time t6, the BPP signal also goes to L level from the control circuit (not shown).

  Further, the output of the one-shot circuit 11 becomes H level during a preset period T5 by a gate block signal from a control circuit (not shown), and this state continues until time t16. Therefore, during the period from time t6 to time t16, the output of the OR circuit 12a becomes H level regardless of other input signals. Therefore, the output of the inverting circuit 32 is at the L level during the period from time t6 to time t16.

  At time t6, since the bypass pair arm is still energized, the voltage of the thyristor valve is almost zero as shown in FIG. 6, the FV signal (OR output 31) and the RV signal are at the L level, and the inverting circuit The outputs of 17 and 18 are at the H level, but since the output of the inverting circuit 32 is at the L level, the outputs of the AND circuits 13, 14, 15, and 16 become the LH level.

  Since the thyristor valve is not turned on after time t6, when the current of the DC circuit is cut off and the thyristor is turned off at time t7, a voltage is applied to the thyristor.

  The 12-phase converter with 6-pulse bridges connected in series is sensitive to the timing of extinguishing the bypass pair arm due to the AC voltage and the forced firing circuit (strong point circuit) when transitioning from the bypass pair state to the gate block state. May shift. Depending on the timing at this time, the upper bridge and the lower bridge of the 12-phase converter may be charged to the vicinity of the DC rated voltage with opposite polarity. That is, the converter 5 and the converter 6 are charged with opposite polarities.

  FIG. 8 shows a case where the converter 5 is charged in the forward direction and the converter 6 is charged in the reverse direction with such a waveform. When the thyristor valve is turned off at t7, the AC voltage component applied to the arm is equivalent to the phase voltage. When the DC component is greater than the AC component, the forward DC voltage is superimposed on the thyristor as shown at time t8. Even at the negative peak, the voltage of the thyristor is higher than the forward voltage detection. Therefore, the FV signal is at the H level and the RV signal is maintained at the L level. Since the output of the inverting circuit 32 is at the L level after t6, the outputs of the AND circuits 13, 14, 15 and 16 maintain the L level. The direct current component superimposed on the thyristor converter is gradually discharged and reduced by a voltage dividing resistor connected in parallel to the thyristor, for example, RD1 to RD7. This discharge time constant is determined by a circuit constant, but may be about 100 ms.

  As shown in FIG. 8, when the voltage of the thyristor becomes equal to or lower than the forward voltage detection level at time t9, the FV signal becomes L level. However, since the output of the inverting circuit 32 is L level after t6, the AND circuits 13, 14 , 15 and 16 maintain the L level.

  At time t10, since there is a considerable amount of DC component superposition, the thyristor voltage does not exceed the reverse voltage detection level in the negative direction, and when the thyristor voltage again exceeds the forward voltage detection level, the FV signal goes to H level. However, since the output of the inverting circuit 32 is at the L level after t6, the outputs of the AND circuits 13, 14, 15 and 16 maintain the L level.

  Further, when the direct current component is attenuated and time t12 is reached, the FV signal becomes L level when the voltage of the thyristor falls below the forward voltage detection level, but the output of the inverting circuit 32 is L level after t6. , 14, 15 and 16 maintain the L level.

When the voltage of the thyristor exceeds the reverse voltage detection level in the negative direction at time t13, the RV signal becomes H level. However, since the output of the inverting circuit 32 is L level after t6, the AND circuits 13, 14, The outputs of 15 and 16 maintain the L level.

  Further, when the voltage of the thyristor exceeds the reverse voltage detection level at time t14, the RV signal becomes L level. However, since the output of the inverting circuit 32 is L level after t6, the AND circuits 13, 14, 15 and The output of 16 maintains the L level.

  Further, when the voltage of the thyristor becomes equal to or higher than the forward voltage detection level at time t15, the FV signal becomes H level, but since the output of the inverting circuit 32 is L level after t6, the AND circuits 13, 14, 15 and The output of 16 maintains the L level.

  Here, at time t16, the output of the one-shot circuit 11 becomes L level. At this time, the circuit breaker open state signal from the circuit breaker (not shown) is L level, and the bypass pair signal (BPP signal) from the control circuit (not shown) is also L level, so the output of the OR circuit 12a is L level. The output of the inverting circuit 32 becomes H level.

  After time t15, the voltage peak value in the negative direction of the thyristor exceeds the reverse voltage detection level of the thyristor in the negative direction, so that the same repetition occurs, and the FV signal and the RV signal repeat H level and L level. Although the outputs of the circuits 17 and 18 alternately repeat the H level and the L level, the outputs of the AND circuits 13, 14, 15 and 16 alternately repeat the H level and the L level after the time t16.

  As can be seen from FIG. 8, since the RV signal continues to be at the L level for the set period of the delay circuit 22, the input at one end of the AND circuit 16 that is the output of the inverting circuit 18 continues to be at the H level for the set period of the delay circuit 22 Will do. However, since the output of the inverting circuit 32 is at the L level during this time, the output of the AND circuit 16 is at the L level, and the input signal of the delay circuit 22 does not continue to be at the H level for the set period or longer. Therefore, at time t11, the output of the delay circuit 22 does not become H level, and the flip-flop 26 is not set, so that the reverse voltage no abnormality detection signal (RV signal continuous no abnormality) does not operate. . Therefore, it is no longer necessary to detect an abnormality in the reverse voltage no abnormality detection circuit (RV signal continuous no abnormality) due to the superimposition of the DC voltage at the time of stop.

  Although FIG. 8 shows an example of preventing unnecessary operation of the reverse voltage non-abnormality detection signal (RV signal continuous non-abnormality), the unnecessary operation of other voltage signal abnormality detection can be similarly prevented.

  By adopting the embodiment of FIG. 7, the time limit of the forward voltage circuit and the reverse voltage detection circuit can be made shorter than the time limit of the commercial frequency detection relay, and the cause of the commercial frequency detection relay can be easily traced. .

  The commercial frequency intrusion detection relay monitors the voltage of the DC circuit from the system of FIG. 1 and outputs an abnormal signal when the frequency component of the AC system is detected for a predetermined period in the voltage of the DC circuit.

  The thyristor valve described above has been described as being constituted by a plurality of sets of thyristor valve modules. However, a thyristor valve having no thyristor valve module can be similarly implemented.

  In this embodiment, in FIG. 5, the reverse voltage detection signal system, specifically, the inverting circuit 18, the AND circuits 15 and 16, the delay circuits 21 and 22, the reset flips 25 and 26 do not exist, or the forward voltage detection signal The system, specifically, the inverting circuit 17, the AND circuits 13 and 14, the delay circuits 19 and 20, and the reset flips 23 and 24 can be implemented similarly.

  1, 2 ... Transformer 3, 4, 5, 6 ... Thyristor converter, 5U, 5V, 5W, 5X, 5Y, 5Z, 6U, 6V, 6W, 6X, 6Y, 6Z ... Thyristor valve, 7 ... High pressure side Transformer for conversion, 8 ... Transformer for low voltage side conversion, 9, 10 ... DC reactor, 5UM-1 to 5UM-N ... Thyristor valve module, AL1, AL2 ... Anode reactor, G1-G7 ... Light guide for gate, TH1 TH7: Optical thyristor, RS1-RS7: Resistor, C1-C7: Capacitor, RD1-RD7: Voltage dividing resistor, VD1-VD7: Voltage detector, FV1-FV7: Forward voltage detection circuit, RV1: Reverse voltage detection circuit, F1 to F7, R1 ... light guide for voltage detection, 11 ... one-shot circuit, 12, 12a, 31 ... OR circuit, 13, 14, 15, 16 ... AND circuit, 17,18 32 ... inverting circuit, 19, 20, 21, 22 ... delay circuit, 23, 24, 25, 26 ... flip-flop.

Claims (3)

In a thyristor converter comprising a thyristor valve configured to convert electric power of an electric power system , wherein a circuit breaker is connected between the electric power system and a plurality of thyristors are connected in series,
A plurality of forward voltage detection circuits for detecting a forward voltage applied to each thyristor and outputting a forward voltage detection signal;
A reverse voltage detection circuit for detecting a reverse voltage applied to at least one of the thyristors and outputting a reverse voltage detection signal;
A one-shot circuit for outputting a predetermined time Mapa pulse signal after receiving a gate block signal from the control circuit,
The output signal of the one-shot circuit inputs respectively the bypass pair signal and breaker open state detection signal indicating the open state of the circuit breaker from the control circuit, for outputting a logic signal when these signals are all absent An OR circuit,
A first inverting circuit for inverting the forward voltage detection signal;
A second inverting circuit for inverting the reverse voltage detection signal;
The output of the OR circuit is input to one input terminal, and the output of the forward voltage detection signal , the reverse voltage detection signal , the first inverter circuit, and the second inverter circuit is input to the other input terminal. 4 AND circuits for outputting logic signals when the AND condition is satisfied, and
Four delay circuits for inputting the outputs of the logical product circuits and outputting the delayed outputs by a predetermined time shorter than the output pulse time of the one-shot circuit ;
The output of each delay circuit is input to each set terminal, and a forward voltage signal continuous abnormality signal , a reverse voltage signal continuous abnormality signal , a forward voltage signal continuous abnormality signal , and a reverse voltage are output from each output terminal. Four reset flip-flops that each output a continuous signal non-abnormal signal and have no output signal when the reset signal from the control circuit is input to each reset terminal;
A voltage detection abnormality detection circuit for a thyristor converter, comprising: In a thyristor converter comprising a thyristor valve configured to convert electric power of an electric power system , wherein a circuit breaker is connected between the electric power system and a plurality of thyristors are connected in series,
A plurality of forward voltage detection circuits for detecting a forward voltage applied to each thyristor and outputting a forward voltage detection signal;
A one-shot circuit for outputting a predetermined time Mapa pulse signal after receiving a gate block signal from the control circuit,
The output signal of the one-shot circuit inputs respectively the bypass pair signal and breaker open state detection signal indicating the open state of the circuit breaker from the control circuit, for outputting a logic signal when these signals are all absent An OR circuit,
A first inverting circuit for inverting the forward voltage detection signal;
The output of the OR circuit is input to one input terminal, and the forward voltage detection signal and the output of the first inverting circuit are input to the other input terminal, respectively, and a logical signal is output when the AND condition is satisfied. Two AND circuits that each output,
Wherein each logical inputs the output of the circuit, two delay circuits output pulse a predetermined time during it only delays shorter than the time for the output of the one-shot circuit,
The outputs of the delay circuits are respectively input to set terminals, the forward voltage signal continuous abnormal signal and the forward voltage signal continuous abnormal signal are output from the output terminals of the respective delay circuits, and the reset signal from the control circuit is output. Two reset flip-flops in which there is no output signal when input to the reset terminal of each,
A voltage detection abnormality detection circuit for a thyristor converter, comprising: In a thyristor converter comprising a thyristor valve configured to convert electric power of an electric power system , wherein a circuit breaker is connected between the electric power system and a plurality of thyristors are connected in series,
A reverse voltage detection circuit for detecting a reverse voltage applied to at least one of the thyristors and outputting a reverse voltage detection signal;
A one-shot circuit that outputs a pulse signal for a predetermined time after receiving the gate block signal from the control circuit;
The output signal of the one-shot circuit inputs respectively the bypass pair signal and breaker open state detection signal indicating the open state of the circuit breaker from the control circuit, for outputting a logic signal when these signals are all absent An OR circuit,
A second inverting circuit for inverting the reverse voltage detection signal;
The output of the OR circuit is input to one input terminal, the reverse voltage detection signal and the output of the second inverting circuit are input to the other input terminal, respectively, and a logical signal is output when the AND condition is satisfied. Two AND circuits that each output,
Wherein each logical inputs the output of the circuit, two delay circuits output pulse a predetermined time during it only delays shorter than the time for the output of the one-shot circuit,
The output of each delay circuit is input to each set terminal, and a reverse voltage signal continuous abnormal signal and a reverse voltage signal continuous abnormal signal are output from each output terminal, and a reset signal from the control circuit is output. Two reset flip-flops in which there is no output signal when input to the reset terminal of each,
A voltage detection abnormality detection circuit for a thyristor converter, comprising:

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