JP6060853B2 - Processor and processor processing method - Google Patents

Description

  The present invention relates to a processor and a processing method of the processor.

  Pipeline is well known as a technique for realizing a reduction in processor cycle time and an improvement in instruction processing rate with a small circuit scale. Pipelines are employed in many processors including supercomputers, mainframes, and embedded.

  For example, FIG. 14 shows an example of a general processor that employs a pipeline. A processor 900 illustrated in FIG. 14 includes n logic circuits 901 (901_1 to 901_n) that execute each stage of an instruction including n stages. In each clock cycle, the logic circuit 901_1 acquires data and executes the processing of stage 1. In each next clock cycle, the logic circuit 901_2 performs the process of stage 2 based on the process result of stage 1 sent from the logic circuit 901_1. In this way, each logic circuit 901 executes the processing of the corresponding stage based on the processing result of the previous stage, and when the processing is completed, the corresponding stage based on the processing result of the previous stage sent next time. Repeat the process. Further, the processor 900 generally provides a register (not shown) between the logic circuits 901 in order to synchronize the processing timing of each stage. As a result, the processor 900 can send data to the logic circuit 901 one after another on the basis of the processing time of the most time-consuming stage, as compared with the case where the next instruction is started after processing all the stages of the instruction. , Can speed up the process. Further, in such a processor 900, by increasing the number of stage stages and shortening the processing time of each stage, the cycle time of the processor can be further shortened and the instruction processing rate can be further improved with a small increase in circuit scale. Can do.

  An example of a processor that processes vector data by such a pipeline operation is described in Patent Document 1. In the processor described in Patent Document 1, the pipeline control unit arranges the data read from the main storage device and writes the data to the vector register, and the arithmetic unit reads the data read from the vector register one after another as the pipeline. A predetermined vector operation is performed using the processing.

JP-A-8-305658

  However, the processor described with reference to FIG. 14 and the processor described in Patent Document 1 have the following problems.

  In the above-described processor, due to the recent reduction in cycle time and improvement in process technology, the number of register stages increases between stages, and overheads such as setup and clock skew increase, making it difficult to further speed up. Further, in the above-described processor, in order to deepen the number of pipeline stages and reduce the delay of the stage, it is necessary to consider the balance between stages and the flush process at the time of pipeline hazard. For this reason, circuit design has become complicated. Further, in the above-described processor, power consumption is increasing with the speeding up by the pipeline. On the other hand, as the circuit scale that can be integrated into LSI (Large Scale Integration) increases due to the improvement of process technology, the merit of the pipeline that can realize high speed with a small circuit scale is diminishing.

  The present invention has been made to solve the above-described problems, and realizes a speed equal to or higher than that of a pipeline while suppressing the overhead between stages in the pipeline, the complexity of circuit design, and the increase in power consumption. An object is to provide a processor.

  The processor of the present invention includes a data holding unit that holds each data read from the main storage device, and a plurality of arithmetic units that start the series of processes based on the next data after finishing the series of processes based on the data And an arithmetic unit that executes a series of processes based on the respective data in parallel.

  Further, the processor processing method of the present invention includes a plurality of processes for starting the series of processes based on the next data after finishing a series of processes based on each data read from the main storage device and held in the data holding unit. A series of processing based on each data is executed in parallel using the computing unit.

  The present invention can provide a processor that realizes a speed equal to or higher than that of a pipeline while suppressing overhead between stages in the pipeline, complexity of circuit design, and increase in power consumption.

It is a block diagram which shows the structure of the processor as the 1st Embodiment of this invention. It is a block diagram which shows the structure of the processor as the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the processor as the 3rd Embodiment of this invention. It is a block diagram which shows the structure of the processor as the 4th Embodiment of this invention. It is a block diagram which shows the structure of the processor as the 5th Embodiment of this invention. It is a block diagram which shows the structure of the processor as the 6th Embodiment of this invention. It is a block diagram which shows the structure of the processor as the 7th Embodiment of this invention. It is a block diagram which shows the structure of the processor as the 8th Embodiment of this invention. It is a block diagram which shows the structure of the processor as the 9th Embodiment of this invention. It is a block diagram which shows the structure of the other aspect of the processor as the 9th Embodiment of this invention. It is a block diagram which shows the structure of the processor as the 10th Embodiment of this invention. It is a block diagram which shows the structure of the processor as the 11th Embodiment of this invention. It is a block diagram which shows the structure of the processor as the 12th Embodiment of this invention. It is a block diagram which shows the structure of the processor of related technology.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 shows the configuration of the processor 1 as the first embodiment of the present invention.

  In FIG. 1, the processor 1 includes a data holding unit 11 and a calculation unit 12.

  The data holding unit 11 is configured by a register, for example, and holds each data read from the main storage device 800. The data holding unit 11 sequentially reads and holds data from the main storage device 800 so that data can be continuously supplied to the arithmetic unit 12.

  The computing unit 12 includes a plurality of computing units 13. The computing unit 12 uses these computing units 13 to execute a series of processes based on each data held in the data holding unit 11 in parallel. Although four arithmetic units 13 are shown in FIG. 1, the number of arithmetic units included in the arithmetic unit in the present invention is not limited.

  The arithmetic unit 13 ends the execution of a series of processes for one data and then starts a series of processes for the next data.

  In the processor 1 configured as described above, a series of processing based on other data is performed by another computing unit 13 while a series of processing based on certain data held in the data holding unit 11 is in progress by the computing unit 13. It is possible to start. Each computing unit 13 ends the execution of a series of processes for one data, and then starts a series of processes for the next data.

  As a result, the processor 1 according to the first embodiment of the present invention achieves a speed equivalent to or higher than that of the pipeline while suppressing overhead between stages in the pipeline, complexity of circuit design, and increase in power consumption. can do.

  The reason is that each arithmetic unit included in the arithmetic unit starts a series of processes for the next data after completing a series of processes for one data, and operates in parallel. As described above, since the arithmetic unit in the present embodiment executes a series of processes in one stage, the operating frequency can be reduced and increase in power consumption can be suppressed as compared with the case where the arithmetic unit is executed in a plurality of stages. In addition, since the arithmetic unit in this embodiment executes a series of processes in one stage, no register is required between the stages. Therefore, in the present embodiment, overhead problems such as setup and clock skew associated with an increase in the number of register stages between stages do not occur. In this embodiment, it is not necessary to balance between stages, and it is not necessary to consider flush processing at the time of pipeline hazard. Therefore, the circuit design of the processor as this embodiment is easy. As described above, this embodiment avoids problems in the pipeline by increasing the number of arithmetic units included in the arithmetic unit instead of increasing the number of stage stages in the pipeline. Since the circuit scale that can be integrated into an LSI has increased due to the improvement in process technology, it is relatively easy to increase the number of arithmetic units. As a result, this embodiment can increase the number of a series of processes that proceed in parallel by increasing the number of computing units, and can achieve high speed while avoiding problems in the pipeline. .

(Second Embodiment)
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. In this embodiment, an example in which the processor of the present invention is applied to a vector processor will be described.

  First, FIG. 2 shows the configuration of a vector processor 2 as a second embodiment of the present invention.

  In FIG. 2, the vector processor 2 includes a vector register unit 21 and a calculation unit 22.

  The vector register unit 21 constitutes an embodiment of the data holding unit in the present invention. The vector register unit 21 holds vector data read from the main storage device 800. For example, the vector register unit 21 includes a plurality of vector registers.

  Here, the vector register unit 21 sequentially reads and holds the vector data from the main storage device 800 so that the data elements of the vector data can be continuously supplied to the respective arithmetic units 22. For example, as illustrated in FIG. 2, the main storage device 800 may include a plurality of memories 801 and a memory interleave unit 802. In this case, the memory interleaving unit 802 may interleave vector data stored in the plurality of memories 801 and hold the vector data in the vector register unit 21. In this case, the memory interleaving unit 802 may write back the result of the calculation written back to the vector register unit 21 by the calculation unit 22 in the memory 801. Various known techniques for inputting / outputting data to / from the vector register unit 21 can be applied to such a main storage device 800. Although FIG. 2 shows four memories 801, the number of memories included in the main memory connected to the processor of the present invention is not limited.

  The computing unit 22 includes n computing units 23 (23_1 to 23_n) and an interleaving unit 24. Here, n is an integer equal to or greater than 1, and is equal to the number of stages n when it is assumed that an operation based on one data is processed in a pipeline by one arithmetic unit 23. In FIG. 2, four arithmetic units 23 are shown, but the number of arithmetic steps and the number of arithmetic units included in the arithmetic unit in the present invention are not limited.

  Each computing unit 23 executes the computation for each data element of the vector data in one stage. That is, each arithmetic unit 23 ends the calculation for a certain data element and then starts the calculation for the next data. Each arithmetic unit 23 is supplied with a data element by an interleave unit 24 described later. Each computing unit 23 inputs the result of the computation to the interleaving unit 24.

  In the example of FIG. 2, each arithmetic unit 23 executes exponent part comparison, mantissa part shift, mantissa part addition, and normalization in a floating-point addition operation as one stage for each data element. In the example of FIG. 2, since the series of processing (floating point addition) is composed of four stages, the arithmetic unit 22 of the vector processor 2 includes four arithmetic units 23.

  The interleaving unit 24 interleaves data elements from the vector register unit 21 to each computing unit 23. That is, the interleaving unit 24 inputs the first data element from the vector register unit 21 to the computing unit 23_1 in a certain clock cycle, and inputs the second data element to the computing unit 23_2 in the next clock cycle. Thereafter, the interleaving unit 24 inputs the third to nth data elements to the computing units 23_3 to 23_n one after another in each subsequent clock cycle. Then, the interleaving unit 24 sequentially inputs the (n + 1) th and subsequent data elements in order from the arithmetic unit 23_1 that has completed the operation on the previous data element.

  In the above-described floating point addition, each computing unit 23 requires two operands. In this case, the interleave unit 24 reads data elements including two operands one after another from the vector register unit 21 and inputs them to each computing unit 23. Actually, the interleave unit 24 may input one element of a vector register included in the vector register unit 21 and one element of another vector register to the computing unit 23 as two operands. Hereinafter, in order to simplify the description, it is assumed that the data elements input from the vector register unit 21 to each computing unit 23 include the number of operands necessary for the computation.

  Further, the interleave unit 24 writes back the result of the operation input from each calculator 23 to the vector register unit 21. For example, the interleave unit 24 may write the result data back into a vector register different from the vector register in which the data element that is the operand is held.

  The operation of the vector processor 2 configured as described above will be described below. In the following description, each computing unit 23 performs floating-point addition on the input data element with four stages of exponent part comparison, mantissa part shift, mantissa part addition, and normalization as one stage. To do. Further, it is assumed that the arithmetic unit 22 includes four arithmetic units 23_1 to 23_4 which are equal to the number of stages 4 of floating point addition.

  In the first clock cycle, the interleave unit 24 inputs the first data element read from the vector register unit 21 to the calculator 23_1. The computing unit 23_1 performs exponent part comparison, mantissa shift, mantissa addition, and normalization on the input data element. Then, the arithmetic unit 23_1 inputs the result to the interleave unit 24 in the fifth clock cycle after the fourth clock cycle. The interleave unit 24 writes the input result data back to the vector register unit 21.

  Next, in the second clock cycle, the interleave unit 24 inputs the second data element read from the vector register unit 21 to the computing unit 23_2. The computing unit 23_2 performs exponent part comparison, mantissa shift, mantissa addition, and normalization on the input data element. Then, the arithmetic unit 23_2 inputs the result to the interleaving unit 24 in the sixth clock cycle after the fourth clock cycle. The interleave unit 24 writes the input result data back to the vector register unit 21.

  Next, in the third clock cycle, the interleave unit 24 inputs the third data element read from the vector register unit 21 to the calculator 23_3. The computing unit 23_3 performs exponent part comparison, mantissa shift, mantissa addition, and normalization on the input data element. The computing unit 23_3 inputs the result to the interleaving unit 24 in the seventh clock cycle after the fourth clock cycle. The interleave unit 24 writes the input result data back to the vector register unit 21.

  Next, in the fourth clock cycle, the interleave unit 24 inputs the fourth data element read from the vector register unit 21 to the computing unit 23_4. The computing unit 23_4 performs exponent part comparison, mantissa shift, mantissa addition, and normalization on the input data element. Then, the arithmetic unit 23_4 inputs the result to the interleaving unit 24 in the eighth clock cycle after the fourth clock cycle. The interleave unit 24 writes the input result data back to the vector register unit 21.

  Next, at the fifth clock cycle, the interleave unit 24 inputs the fifth data element read from the vector register unit 21 to the arithmetic unit 23_1. At this time, the arithmetic unit 23_1 has completed the floating-point addition of the data element input at the first clock. Therefore, the arithmetic unit 23_1 performs exponent part comparison, mantissa part shift, mantissa part addition, and normalization on the input data element. Then, the arithmetic unit 23_1 inputs the result to the interleave unit 24 in the ninth clock cycle after the fourth clock cycle. The interleave unit 24 writes the input result data back to the vector register unit 21.

  Thereafter, the vector processor 2 repeats the same operation.

  Next, the effect of the second exemplary embodiment of the present invention will be described.

  The vector processor according to the second embodiment of the present invention achieves the same speed as an n-stage pipeline while suppressing the overhead between stages in the pipeline, the complexity of circuit design, and the increase in power consumption. be able to.

  The reason is that the arithmetic unit has the same number of stages as the number of stages when the operations executed by the respective arithmetic units are pipeline processed, and the interleave unit stores the vector data in each arithmetic unit in each clock cycle. This is because the elements are supplied sequentially. This is because each arithmetic unit executes a series of operations for one element as one stage. As a result, the vector processor according to the present embodiment starts operations for each data element continuously and executes them in parallel as in the case where the vector operations are pipelined. Moreover, the vector processor according to the present embodiment does not require registers between stages as in the case of pipeline processing of vector operations. Therefore, this embodiment has no overhead such as setup between stages and clock skew. In the vector processor of this embodiment, it is not necessary to consider the balance between stages and the pipeline hazard in the circuit design.

  Further, in the vector processor of the present embodiment, the circuit scale is n times as compared with the case where equivalent vector operations are processed by an n-stage pipeline using one arithmetic unit, but the operating frequency is 1 / N. Here, assuming that the power consumption of the processor is proportional to the operating frequency × circuit scale × voltage × voltage, the power consumption of the present embodiment is almost the same as in the case of pipeline processing.

  In this way, this embodiment consumes almost the same as the pipeline while avoiding problems in the pipeline by increasing the number of arithmetic units that can be executed in parallel instead of increasing the number of stages in the pipeline. Equivalent high throughput with power.

(Third embodiment)
Next, a third embodiment of the present invention will be described in detail with reference to the drawings. This embodiment differs from the second embodiment of the present invention in that the type of calculation can be switched for each element of vector data. In the description of the present embodiment and each drawing, the same reference numerals are given to the same components as those in the second embodiment of the present invention, and the detailed description in the present embodiment is omitted.

  The configuration of the vector processor 3 as the third embodiment of the present invention is shown in FIG. In FIG. 3, the vector processor 3 includes a vector register unit 31 and a calculation unit 32.

  The vector register unit 31 constitutes an embodiment of the data holding unit in the present invention. The vector register unit 31 is constituted by a plurality of vector registers, for example, and holds vector instructions and vector data. Vector instructions and vector data are read from the main storage device 800.

  Vector data consists of data elements including the number of operands necessary for the operation.

  The vector instruction is composed of instruction elements indicating types of operations performed on each element of vector data.

  The computing unit 32 includes n computing units 33 (33_1 to 33_n) and an interleaving unit 34. Here, n is an integer greater than or equal to 1, and is equal to the number of stages n when it is assumed that the operation by one arithmetic unit 33 is processed in the pipeline. In FIG. 3, four arithmetic units 33 are shown, but the number of arithmetic steps and the number of arithmetic units included in the arithmetic unit in the present invention are not limited.

  Each computing unit 33 decodes the instruction element to specify the type of operation, and executes a series of processes for performing the specified type of operation on the data element in one stage. For example, each computing unit 33 may be capable of selectively executing floating point addition and floating point multiplication.

  Each arithmetic unit 33 is supplied with a data element and an instruction element by an interleave unit 34 described later. Each computing unit 33 inputs the result of the computation to the interleave unit 34.

  The interleaving unit 34 sequentially supplies data elements and instruction elements from the vector register unit 31 to each computing unit 33. That is, the interleave unit 34 inputs the first instruction element and the first data element to the computing unit 33_1 in a certain clock cycle. Thereafter, the interleaving unit 34 inputs the second to n-th instruction elements and data elements to the computing units 33_2 to 23_n one after another in each subsequent clock cycle. Then, the interleave unit 34 sequentially supplies subsequent instruction elements and data elements sequentially from the arithmetic unit 33_1 that has completed a series of processes based on the previous instruction elements and data elements.

  In the case of floating point addition or floating point multiplication, each arithmetic unit 33 requires two operands. Therefore, the interleave unit 34 reads out an instruction element and a data element including two operands from the vector register unit 31 and inputs them to each computing unit 33.

  Further, the interleave unit 34 writes back the result of the calculation input from each calculator 33 to the vector register unit 31. The interleaving unit 34 writes back the operation result in a vector register different from the vector register in which the vector instruction and the vector data serving as the operand are stored in the vector register unit 31.

  The operation of the vector processor 3 configured as described above will be described below. In the following description, it is assumed that each arithmetic unit 33 executes instruction element decoding and floating point multiplication or floating point addition on data elements in one stage. In addition, the calculation unit 32 includes four calculation units 33_1 to 33_4 that are equal to the number of stages 4 of processing performed by the calculation unit 33.

  In the first clock cycle, the interleave unit 34 inputs the first instruction element and the first data element read from the vector register unit 31 to the calculator 33_1. The computing unit 33_1 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. The computing unit 33_1 inputs the result to the interleave unit 34 in the fifth clock cycle after the fourth clock cycle. The interleave unit 34 writes the input result data back to the vector register unit 31.

  In the second clock cycle, the interleave unit 34 inputs the second instruction element and the second data element read from the vector register unit 31 to the calculator 33_2. The computing unit 33_2 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. Then, the computing unit 33_2 inputs the result to the interleaving unit 34 in the sixth clock cycle after the fourth clock cycle. The interleave unit 34 writes the input result data back to the vector register unit 31.

  In the third clock cycle, the interleave unit 34 inputs the third instruction element and the third data element read from the vector register unit 31 to the calculator 33_3. The computing unit 33_3 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. The computing unit 33_3 inputs the result to the interleaving unit 34 in the seventh clock cycle after the fourth clock cycle. The interleave unit 34 writes the input result data back to the vector register unit 31.

  In the fourth clock cycle, the interleave unit 34 inputs the fourth instruction element and the fourth data element read from the vector register unit 31 to the computing unit 33_4. The computing unit 33_4 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. The computing unit 33_4 inputs the result to the interleaving unit 34 in the eighth clock cycle after the fourth clock cycle. The interleave unit 34 writes the input result data back to the vector register unit 31.

  In the fifth clock cycle, the interleaving unit 34 inputs the fifth instruction element and the fifth data element read from the vector register unit 31 to the computing unit 33_1. At this time, the calculator 33_1 has completed the calculation for the data element input in the first clock cycle. Therefore, the arithmetic unit 33_1 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. Then, the arithmetic unit 33_1 inputs the result to the interleave unit 34 in the ninth clock cycle after the fourth clock cycle. The interleave unit 34 writes the input result data back to the vector register unit 31.

  Thereafter, the vector processor 3 repeats the same operation.

  Next, effects of the third exemplary embodiment of the present invention will be described.

  The vector processor according to the third embodiment of the present invention can perform different operations for each element of vector data when realizing the high speed equivalent to the n-stage pipeline while avoiding the problems in the pipeline. As increasing flexibility.

  The reason is that the vector register unit holds vector instructions in addition to vector data, the interleave unit sequentially supplies data elements and instruction elements to n arithmetic units, and each arithmetic unit is a type indicated by the instruction element. This is because a series of processes to be performed on the data element by selecting this operation is executed in one stage.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings. This embodiment is different from the third embodiment of the present invention in that the number of arithmetic units included in the arithmetic unit is N (N is an integer of 1 or more) times. In the description of the present embodiment and each drawing, the same reference numerals are given to the same components as those of the third embodiment of the present invention, and the detailed description in the present embodiment will be omitted.

  FIG. 4 shows the configuration of the vector processor 4 as the fourth embodiment of the present invention. In FIG. 4, the vector processor 4 includes a vector register unit 31 and a calculation unit 42.

  The computing unit 42 includes n × N computing units 33 (33_1 to 33_nN) and an interleaving unit 44. Here, n is an integer greater than or equal to 1, and is equal to the number of stages n when it is assumed that the operation by one arithmetic unit 33 is processed in the pipeline. N is an integer of 1 or more. In FIG. 4, eight arithmetic units 33 are shown as n = 4 and N = 2, but the values of n and N and the number of arithmetic units included in the arithmetic unit in the present invention are not limited. .

  The interleaving unit 44 is configured in the same manner as the interleaving unit 34 in the third embodiment of the present invention. However, the number of arithmetic units 33 to which instruction elements and data elements read from the vector register unit 31 are sequentially supplied is different.

  Specifically, the interleave unit 44 sequentially supplies data elements and instruction elements read from the vector register unit 31 to the n × N arithmetic units 33. That is, the interleaving unit 44 inputs the first to n × Nth instruction elements and data elements to the arithmetic units 33_1 to 33_nN one after another in each clock cycle. Then, the interleaving unit 34 sequentially inputs the n × N + 1 and subsequent instruction elements and data elements in order from the arithmetic unit 33_1 that has completed a series of processes based on the previous data elements and instruction elements.

  The operation of the vector processor 4 configured as described above will be described below. In the following description, each computing unit 33 performs floating point multiplication or floating point addition in one stage. The computing unit 32 includes eight computing units 33_1 to 33_8 that are twice the number of stages of processing 4 performed by each computing unit 33.

  In the first clock cycle, the interleave unit 44 inputs the first instruction element and the first data element read from the vector register unit 31 to the computing unit 33_1. The computing unit 33_1 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. The computing unit 33_1 inputs the result to the interleaving unit 44 in the ninth clock cycle after the eight clock cycles. The interleave unit 44 writes the input data back to the vector register unit 31.

  Thereafter, similarly in the second to eighth clock cycles, the interleaving unit 44 converts the second to eighth instruction elements and data elements read from the vector register unit 31 into the arithmetic units 33_2 to the arithmetic unit 33_2. The data is sequentially input to the device 33_8. The computing units 33_2 to 33_8 decode the input instruction element, and execute floating point addition or floating point multiplication on the data element according to the decoding result, respectively. Then, the computing units 33_2 to 33_8 input the results to the interleaving unit 44 at the 10th to 16th clock cycles after the 8th clock cycle. The interleave unit 44 writes the input data back to the vector register unit 31.

  In the ninth clock cycle, the interleave unit 44 inputs the ninth instruction element and data element read from the vector register unit 31 to the computing unit 33_1. At this time, the calculator 33_1 has completed the calculation for the data element input in the first clock cycle. Therefore, the arithmetic unit 33_1 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. The computing unit 33_1 inputs the result to the interleaving unit 44 at the 17th clock cycle after 8 clock cycles. The interleave unit 44 writes the input data back to the vector register unit 31.

  Thereafter, the vector processor 4 repeats the same operation.

  Next, effects of the fourth exemplary embodiment of the present invention will be described.

  The vector processor according to the fourth embodiment of the present invention achieves higher performance than an n-stage pipeline while avoiding problems in the pipeline.

  The reason is that the arithmetic unit has n × N arithmetic units in the third embodiment of the present invention, and the interleave unit has elements of vector instructions and vector data for the n × N arithmetic units. It is because it supplies sequentially. Thereby, this embodiment can make the clock cycle 1 / N and the operating frequency N times that of the third embodiment of the present invention, and as a result, N times the throughput can be obtained. It will be.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described in detail with reference to the drawings. This embodiment is different from the third embodiment of the present invention in that the vector register section is divided and each divided portion is associated with each arithmetic unit. In the description of the present embodiment and each drawing, the same reference numerals are given to the same components as those of the third embodiment of the present invention, and the detailed description in the present embodiment will be omitted.

  The configuration of the vector processor 5 as the fifth embodiment of the present invention is shown in FIG. In FIG. 5, the vector processor 5 includes a vector register unit 51 and a calculation unit 52.

  The vector register unit 51 constitutes an embodiment of the data holding unit in the present invention. The vector register unit 51 is divided into n division units 55 (55_1 to 55_n), which is the same number as the arithmetic units 53 included in the arithmetic unit 52 described later. In each division unit 55, vector instructions and vector data read from the main storage device 800 are divided into n pieces and held.

  That is, when the number of elements of the vector instruction and vector data is m, the dividing unit 55 holds m / n elements of the vector instruction and vector data. For example, when n = 4, the division unit 55_1 holds the element number 4i (i = 0, 1,...) Of the vector instruction and vector data. Further, the division unit 55_2 holds the element 4i + 1 of the vector instruction and vector data. The dividing unit 55_1 holds the element 4i + 2 of the vector instruction and vector data. The dividing unit 55_3 holds element 4i + 3 of the vector instruction and vector data.

  Each division unit 55 is associated with each computing unit 53.

  The computing unit 52 includes n computing units 53 (53_1 to 53_n). Here, n is an integer greater than or equal to 1, and is equal to the number of stages n when it is assumed that the calculation by one calculator 53 is processed in the pipeline. In FIG. 5, four division units 55 and four arithmetic units 53 are shown as n = 4, but the value of n, the number of divisions of the vector register unit 51, and the arithmetic unit in the present invention are included. The number of arithmetic units is not limited.

  Each computing unit 53 is configured in substantially the same manner as the computing unit 33 in the third embodiment of the present invention, except that the data element and the instruction element are acquired from the corresponding dividing unit 55.

  In the case of floating-point addition or floating-point multiplication, each arithmetic unit 53 requires two operands. In this case, each computing unit 53 reads an instruction element and a data element including two operands from the corresponding dividing unit 55.

  Each computing unit 53 writes the result of the computation back to the corresponding dividing unit 55. Note that each computing unit 53 writes the result back to a location different from the data element and the instruction element in each division unit 55.

  The operation of the vector processor 5 configured as described above will be described below. In the following description, each computing unit 53 performs floating point multiplication or floating point addition in one stage. The computing unit 52 includes four computing units 53_1 to 53_4 that are equal to the number of stages 4 of processing performed by each computing unit 53. Further, it is assumed that the vector register unit 51 is divided into four division units 55 that are the same number as the arithmetic units 53.

  In the first clock cycle, the arithmetic unit 53_1 reads the first instruction element and the first data element of the dividing unit 55_1. The arithmetic unit 53_1 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. Then, the arithmetic unit 53_1 writes the result back to the dividing unit 55_1 in the second clock cycle after the first clock cycle.

  Similarly, in the first clock cycle, the arithmetic unit 53_2 reads the first instruction element and the first data element of the dividing unit 55_2. The arithmetic unit 53_2 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. The computing unit 53_2 then writes the result back to the dividing unit 55_2 in the second clock cycle after the first clock cycle.

  Similarly, in the first clock cycle, the arithmetic unit 53_3 reads the first instruction element and the first data element of the dividing unit 55_3. The arithmetic unit 53_3 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. The computing unit 53_3 writes the result back to the dividing unit 55_3 in the second clock cycle after the first clock cycle.

  Similarly, in the first clock cycle, the arithmetic unit 53_4 reads the first instruction element and the first data element of the dividing unit 55_4. The arithmetic unit 53_4 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. Then, the arithmetic unit 53_4 writes the result back to the dividing unit 55_4 in the second clock cycle after one clock cycle.

  In the second clock cycle, the calculators 53_1 to 53_4 each complete the calculation for the data element input in the first clock cycle. Therefore, the arithmetic units 53_1 to 53_4 read out the second command element and data element of the dividing units 55_1 to 55_4, respectively. The arithmetic units 53_1 to 53_4 decode the input instruction element, and execute floating point addition or floating point multiplication on the data element according to the decoding result. Then, the arithmetic units 53_1 to 53_4 write the results back to the division units 55_1 to 55_4 in the third clock cycle after the first clock cycle.

  Thereafter, the vector processor 5 repeats the same operation.

  Next, effects of the fifth exemplary embodiment of the present invention will be described.

  The vector processor according to the fifth embodiment of the present invention reduces the circuit scale and power consumption when realizing performance equal to or better than that of an n-stage pipeline while avoiding problems in the pipeline. Can be reduced.

  The reason is that the vector register unit is divided into n number of division units, which is the same number as the arithmetic units, and is associated with each arithmetic unit, and each division unit divides and holds the vector data. This is because a series of processes based on the instruction elements and data elements read from the corresponding dividing units are executed in one stage.

  As a result, the present embodiment eliminates the need for an interleaving unit, which is necessary when realizing performance equivalent to that of an n-stage pipeline using n arithmetic units in the third embodiment of the present invention. . Therefore, this embodiment reduces the circuit scale as compared with the third embodiment of the present invention. In this embodiment, the clock cycle of the interface between the vector register unit and the arithmetic unit is increased by n times. As a result, the present embodiment can reduce the operating frequency and further reduce the power consumption as compared with the third embodiment of the present invention.

(Sixth embodiment)
Next, a sixth embodiment of the present invention will be described in detail with reference to the drawings. This embodiment is different from the fifth embodiment of the present invention in that it has the same number of arithmetic units as the number of elements of the vector register. Note that, in the description of the present embodiment and each drawing, the same components as those in the fifth embodiment of the present invention are denoted by the same reference numerals, and detailed description in the present embodiment is omitted.

  A configuration of a vector processor 6 as a sixth embodiment of the present invention is shown in FIG. In FIG. 6, the vector processor 6 includes a vector register unit 61 and a calculation unit 62.

  The vector register unit 61 includes m element units 66 (66_ to 66_m). Each element unit 66 holds a data element including the number of operands necessary for the calculation by the calculator 63 and a corresponding instruction element.

  The computing unit 62 includes the same number m of computing units 63 (63_1 to 63_m) as the element unit 66.

  Each computing unit 63 is configured in substantially the same manner as the computing unit 53 in the fifth embodiment of the present invention, except that a data element and an instruction element are obtained from the corresponding element unit 66.

  Each computing unit 63 writes back the result of the computation in the corresponding element unit 66. Note that each computing unit 63 writes the result back to a location different from the data element and the instruction element in each element unit 66.

  The operation of the vector processor 6 configured as described above will be described below. In the following description, each computing unit 63 performs floating point multiplication or floating point addition in one stage.

  In the first clock cycle, the arithmetic unit 63_1 reads the instruction element and the data element from the element unit 66_1. The arithmetic unit 63_1 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. The computing unit 63_1 then writes the result back to the element unit 66_1 in the second clock cycle after the first clock cycle.

  Similarly, in the first clock cycle, the arithmetic units 63_2 to 63_m read the instruction element and the data element from the element units 66_2 to 66_m, respectively. The arithmetic units 63_2 to 63_m decode the input instruction element, and execute floating point addition or floating point multiplication on the data element according to the decoding result, respectively. Then, the computing units 63_2 to 63_m write back the results to the element units 66_2 to 66_m in the second clock cycle after the first clock cycle.

  In the second clock cycle, the calculators 63_1 to 63_m each complete the calculation for the data element input in the first clock cycle. Therefore, the arithmetic units 63_1 to 63_m read the instruction element and the data element from the element units 66_1 to 66_m, respectively. The arithmetic units 63_1 to 63_m decode the input instruction, and execute floating point addition or floating point multiplication on the data element according to the decoding result. Then, the computing units 63_1 to 63_m write the results back to the element units 66_1 to 66_m in the third clock cycle after the first clock cycle.

  Thereafter, the vector processor 6 repeats the same operation.

  Next, effects of the sixth exemplary embodiment of the present invention will be described.

  The vector processor according to the sixth embodiment of the present invention can achieve high performance equal to or higher than that of a pipeline while avoiding problems in the pipeline.

  The reason is that the arithmetic unit has the same number of arithmetic units as the number m of elements in the vector register unit, and each arithmetic unit reads the instruction element and the data element from the corresponding element unit and executes a series of processes in one stage. Because it does.

  Thus, since this embodiment includes m computing units that perform n stages of processing in one stage, m / n times performance can be realized with respect to an n stage pipeline.

(Seventh embodiment)
Next, a seventh embodiment of the present invention will be described in detail with reference to the drawings. This embodiment is different from the sixth embodiment of the present invention in that a part of data held in the vector register unit is broadcast to each arithmetic unit. Note that, in the description of the present embodiment and the respective drawings, the same components as those in the sixth embodiment of the present invention are denoted by the same reference numerals, and detailed description thereof will be omitted.

  FIG. 7 shows the configuration of a vector processor 7 as a seventh embodiment of the present invention. In FIG. 7, the vector processor 7 includes a vector register unit 71 and a calculation unit 72.

  The vector register unit 71 includes m element units 66 (66_ to 66_m) and a broadcast unit 77. Vector data and vector instructions read from the main storage device 800 are held in the m element units 66 and the broadcast unit 77. The vector command and vector data held in the broadcast unit 77 are broadcast to each computing unit 73 described later.

  The computing unit 72 includes the same number m of computing units 73 (73_1 to 73_m) as the element unit 66.

  Each computing unit 73 acquires the data element and the instruction element from the broadcast unit 77 and the corresponding element unit 66, and executes the operation indicated by the instruction element on the data element. At this time, each computing unit 73 may read out a data element as an operand from one or both of the element unit 66 and the broadcast unit 77. Each computing unit 73 may read the command element from either the element unit 66 or the broadcast unit 77. As a result, the arithmetic unit 72 can execute the same instruction on different operands in all the arithmetic units 73. Alternatively, the calculation unit 72 can execute different calculations using at least one identical operand in all the calculation units 73.

  Each computing unit 73 writes the result of the computation back to the corresponding element unit 66.

  The operation of the vector processor 7 configured as described above will be described below. In the following description, each computing unit 73 performs floating point multiplication or floating point addition in one stage. In the following description, it is assumed that a data element representing one of an instruction element and an operand is broadcast from the broadcast unit 77, and a data element representing the other of the operands is read from the element unit 66.

  In the first clock cycle, the arithmetic unit 73_1 receives the command element and data element broadcast from the broadcast unit 77 and the data element read from the element unit 66_1 as inputs. The arithmetic unit 73_1 decodes the input instruction element, and performs floating point addition or floating point multiplication on the data element according to the decoding result. Then, the arithmetic unit 73_1 writes the result back to the element unit 66_1 in the second clock cycle after the first clock cycle.

  Similarly, in the first clock cycle, the arithmetic units 73_2 to 73_m respectively receive the command element and data element broadcast from the broadcast unit 77 and the data element read from the element units 66_2 to 66_m as inputs. The arithmetic units 73_2 to 73_m decode the input instruction element, and execute floating point addition or floating point multiplication on the data element according to the decoding result, respectively. Then, the computing units 73_2 to 73_m write the results back to the element units 66_2 to 66_m in the second clock cycle after the first clock cycle.

  In the second clock cycle, the arithmetic units 73_1 to 73_m each complete a series of processes for the data element input in the first clock cycle. Therefore, the arithmetic units 73_1 to 73_m obtain the command element and the data element broadcast from the broadcast unit 77 and the data element read from the element units 66_1 to 66_m as inputs. The computing units 73_1 to 73_m decode the input instruction element, and execute floating point addition or floating point multiplication on the data element according to the decoding result. Then, the arithmetic units 73_1 to 73_m write the results back to the element units 66_1 to 66_m in the third clock cycle after the first clock cycle.

  Thereafter, the vector processor 7 repeats the same operation.

  Next, effects of the seventh exemplary embodiment of the present invention will be described.

  The vector processor according to the seventh embodiment of the present invention efficiently performs an operation that makes the instructions or operands the same in all operations when realizing performance equivalent to that of the pipeline while avoiding problems in the pipeline. Make it executable.

  The reason is that the vector register unit has an element unit and a broadcast unit, and each arithmetic unit uses an instruction element or data element broadcast from the broadcast unit and an instruction element or data element read from the element unit. This is because a series of processing is executed in one stage. As a result, this embodiment can prevent the throughput with the memory from becoming a performance bottleneck when the same instruction is to be executed in all the arithmetic units or the same operand is to be used in all the arithmetic units. .

(Eighth embodiment)
Next, an eighth embodiment of the present invention will be described in detail with reference to the drawings. In this embodiment, an example in which the processor of the present invention is applied to a scalar processor will be described.

  First, FIG. 8 shows a configuration of a scalar processor 8 as an eighth embodiment of the present invention.

  In FIG. 8, the scalar processor 8 includes an instruction cache unit 81 and a calculation unit 82.

  The instruction cache unit 81 constitutes an embodiment of the data holding unit in the present invention. The instruction cache unit 81 holds an instruction read from the main storage device 800. For example, the instruction cache unit 81 is configured as a cache that can hold a plurality of instructions.

  Here, the instruction cache unit 81 sequentially reads and holds instructions from the main storage device 800 so that instructions can be continuously supplied to the arithmetic unit 82. Various known techniques can be applied to the configuration of the instruction cache unit 81.

  The computing unit 82 includes n computing units 83 (83_1 to 83_n) and an interleaving unit 84. Here, n is an integer of 1 or more, and is equal to the number n of stages when the above-described instruction is processed in the pipeline. For example, one instruction can be processed in a 5-stage pipeline of fetch, decode, execute, memory access, and write back. In this case, the calculation unit 82 includes five calculation units 83. Although FIG. 8 shows five arithmetic units 83 with n = 5, the number of instruction stages and the number of arithmetic units included in the arithmetic unit in the present invention are not limited.

  Each computing unit 83 executes each stage of one instruction supplied from the instruction cache unit 81 in one stage. An instruction is supplied to each computing unit 83 from an interleaving unit 84 described later. Each computing unit 83 inputs the result of the instruction to the interleave unit 84.

  In addition, the arithmetic unit 82 has a forwarding path between the arithmetic units 83. Data generated by each computing unit 83 is input to the next computing unit 83 via the forwarding path. For example, in the example of FIG. 8, the result of the execution stage of the computing unit 83_1 and the result of the memory access stage are input to the execution stage of the next computing unit 83_2.

  The interleaving unit 84 sequentially supplies instructions from the instruction cache unit 81 to each computing unit 83. That is, the interleave unit 84 inputs the first instruction to the computing unit 83_1 in a certain clock cycle, and inputs the second instruction to the computing unit 83_2 in the next clock cycle. Thereafter, the interleave unit 84 inputs the third to n-th instructions to the arithmetic units 83_3 to 83_n one after another in each subsequent clock cycle. Then, the interleave unit 84 sequentially inputs the (n + 1) th and subsequent instructions in order from the arithmetic unit 83_1 that has completed a series of processes based on the previous instruction.

  Further, the interleave unit 84 writes back the result of the calculation input from each calculator 83 to a cache (not shown).

  The operation of the scalar processor 8 configured as described above will be described below. In the following description, it is assumed that each arithmetic unit 23 executes an instruction with five stages of fetch, decode, execution, memory access, and write back as one stage. Further, it is assumed that the arithmetic unit 82 includes five arithmetic units 83_1 to 83_5 that are equal to the number of stages 5 in the instruction pipeline.

  In the first clock cycle, the interleave unit 84 inputs the first instruction read from the instruction cache unit 81 to the arithmetic unit 83_1. The arithmetic unit 83_1 fetches the input instruction and executes decoding, execution, memory access, and write back. The result of the execution stage and the result of the memory access stage are forwarded to the arithmetic unit 83_2. The arithmetic unit 83_1 inputs the result to the interleave unit 84 in the sixth clock cycle after the fifth clock cycle. The interleaving unit 84 writes the input result data back to the cache.

  In the second clock cycle, the interleave unit 84 inputs the second instruction read from the instruction cache unit 81 to the arithmetic unit 83_2. The arithmetic unit 83_2 fetches the input instruction and executes decoding, execution, memory access, and write back. The result of the execution stage and the result of the memory access stage are forwarded to the computing unit 83_3. Then, the arithmetic unit 83_2 inputs the result to the interleave unit 84 at the seventh clock cycle after the fifth clock cycle. The interleaving unit 84 writes the input result data back to the cache.

  In the third clock cycle, the interleave unit 84 inputs the third instruction read from the instruction cache unit 81 to the arithmetic unit 83_3. The arithmetic unit 83_3 fetches the input instruction and performs decoding, execution, memory access, and write back. The result of the execution stage and the result of the memory access stage are forwarded to the computing unit 83_4. The arithmetic unit 83_3 inputs the result to the interleave unit 84 in the eighth clock cycle after the fifth clock cycle. The interleaving unit 84 writes the input result data back to the cache.

  In the fourth clock cycle, the interleave unit 84 inputs the fourth instruction read from the instruction cache unit 81 to the arithmetic unit 83_4. The arithmetic unit 83_4 fetches the input instruction and executes decoding, execution, memory access, and write back. The result of the execution stage and the result of the memory access stage are forwarded to the computing unit 83_5. The arithmetic unit 83_4 inputs the result to the interleave unit 84 in the ninth clock cycle after the fifth clock cycle. The interleaving unit 84 writes the input result data back to the cache.

  In the fifth clock cycle, the interleave unit 84 inputs the fifth instruction read from the instruction cache unit 81 to the arithmetic unit 83_5. The arithmetic unit 83_5 fetches the input instruction and performs decoding, execution, memory access, and write back. The result of the execution stage and the result of the memory access stage are forwarded to the arithmetic unit 83_1. The computing unit 83_5 inputs the result to the interleaving unit 84 at the 10th clock cycle after the 5th clock cycle. The interleaving unit 84 writes the input result data back to the cache.

  In the sixth clock cycle, the interleave unit 84 inputs the sixth instruction read from the instruction cache unit 81 to the arithmetic unit 83_1. At this time, the arithmetic unit 83_1 has completed a series of processes based on the instruction input in the first clock cycle. Therefore, the arithmetic unit 83_1 fetches the input instruction and executes decoding, execution, memory access, and write back. The result of the execution stage and the result of the memory access stage are forwarded to the arithmetic unit 83_2. The computing unit 83_1 inputs the result to the interleaving unit 84 in the 11th clock cycle after 5 clock cycles. The interleaving unit 84 writes the input result data back to the cache.

  Thereafter, the scalar processor 8 repeats the same operation.

  Next, effects of the eighth exemplary embodiment of the present invention will be described.

  The scalar processor according to the eighth embodiment of the present invention achieves the same speed as an n-stage pipeline while suppressing the overhead between stages in the pipeline, the complexity of circuit design, and the increase in power consumption. be able to.

  The reason is that the arithmetic unit has the same number of arithmetic units as the number of stages when it is assumed that the instruction is pipelined by each arithmetic unit, and the interleaving unit sends an instruction to each arithmetic unit in each clock cycle. It is because it supplies sequentially. This is because each arithmetic unit executes an instruction executed in the n-stage pipeline as one stage. As a result, the scalar processor according to the present embodiment starts each instruction continuously and executes it in parallel as in the case where the instructions are pipelined. Moreover, the scalar processor of this embodiment does not require registers between stages as in the case of pipeline processing of instructions. Therefore, this embodiment has no overhead such as setup between stages and clock skew. In the scalar processor of this embodiment, it is not necessary to consider the balance between stages and the pipeline hazard in the circuit design.

  Further, in the scalar processor of the present embodiment, the circuit scale is n times as compared with the case where an instruction is processed by an n-stage pipeline using one arithmetic unit, but the operating frequency is approximately 1 / n. It becomes. As described above, assuming that the power consumption of the processor is proportional to the operating frequency × circuit scale × voltage × voltage, the power consumption of the present embodiment is almost the same as in the case of pipeline processing.

  In this way, this embodiment consumes almost the same as the pipeline while avoiding problems in the pipeline by increasing the number of arithmetic units that can be executed in parallel instead of increasing the number of stages in the pipeline. Equivalent high throughput with power.

(Ninth embodiment)
Next, a ninth embodiment of the present invention will be described in detail with reference to the drawings. This embodiment is different from the eighth embodiment of the present invention in that the number of arithmetic units included in the arithmetic unit is N (N is an integer of 1 or more) times. Note that, in the description of the present embodiment and the drawings, the same components as those in the eighth embodiment of the present invention are denoted by the same reference numerals, and detailed description in the present embodiment is omitted.

  FIG. 9 shows the configuration of the scalar processor 9 as the ninth embodiment of the present invention. In FIG. 9, the scalar processor 9 includes an instruction cache unit 81 and a calculation unit 92.

  The computing unit 92 includes n × N computing units 83 (83_1 to 83_nN) and an interleaving unit 94. Here, n is an integer of 1 or more, and is equal to the number n of stages when the instruction is pipelined. N is an integer of 1 or more.

  Interleaving unit 94 is configured in the same manner as interleaving unit 84 in the eighth embodiment of the present invention. However, the number of arithmetic units 83 to which instructions read from the instruction cache unit 81 are sequentially supplied is different.

  Specifically, the interleave unit 94 inputs instructions read from the instruction cache unit 81 to n × N arithmetic units 83_1 to 83_nN one after another in each clock cycle. Then, the interleaving unit 94 sequentially inputs n × N + 1 and subsequent instructions from the arithmetic unit 83_1 that has completed a series of processes based on the previous instruction.

  The operation of the scalar processor 9 configured as described above will be described below. In the following description, it is assumed that each arithmetic unit 83 processes an instruction with five stages of fetch, decode, execution, memory access, and write back as one stage. Further, it is assumed that the arithmetic unit 92 includes ten arithmetic units 83_1 to 83_10 that are equal to twice the number of stages of the instruction pipeline.

  In the first clock cycle, the interleave unit 94 inputs the first instruction read from the instruction cache unit 81 to the arithmetic unit 83_1. The arithmetic unit 83_1 fetches the input instruction, and performs decoding, execution, memory access, and write back. The result of the execution stage and the result of the memory access stage are forwarded to the next computing unit 83_2. Then, the arithmetic unit 83_1 inputs the result to the interleaving unit 94 in the 11th clock cycle after 10 clock cycles. The interleaving unit 94 writes the input result data back to the cache.

  Thereafter, similarly in the second clock cycle to the tenth clock cycle, the interleaving unit 94 sequentially inputs the instructions read from the instruction cache unit 81 to the arithmetic units 83_2 to 83_10. The arithmetic units 83_2 to 83_10 fetch input instructions and perform decoding, execution, memory access, and write back, respectively. The result of the execution stage and the result of the memory access stage are forwarded to the next computing unit 83, respectively. The arithmetic units 83_2 to 83_10 input the results to the interleaving unit 94 at 12th to 20th clock cycles after 10 clock cycles, respectively. The interleaving unit 94 writes the input result data back to the cache.

  In the eleventh clock cycle, the interleave unit 94 inputs the eleventh instruction read from the instruction cache unit 81 to the arithmetic unit 83_1. At this time, the arithmetic unit 83_1 has completed a series of processes based on the instruction input in the first clock cycle. Therefore, the arithmetic unit 83_1 fetches the input instruction and performs decoding, execution, memory access, and write back. The result of the execution stage and the result of the memory access stage are forwarded to the next computing unit 83_2. Then, the arithmetic unit 83_1 inputs the result to the interleaving unit 94 at the 21st clock cycle after 10 clock cycles. The interleaving unit 94 writes the input result data back to the cache.

  Thereafter, the scalar processor 9 repeats the same operation.

  Next, effects of the ninth exemplary embodiment of the present invention will be described.

  The scalar processor according to the ninth embodiment of the present invention achieves higher performance than the n-stage pipeline while avoiding problems in the pipeline.

  The reason is that the arithmetic unit has N arithmetic units in the eighth embodiment of the present invention, and the interleave unit sequentially inputs instructions to the n × N arithmetic units. is there. As a result, the present embodiment can make the clock cycle 1 / N and the operating frequency N times that of the eighth embodiment of the present invention, and as a result, the eighth embodiment of the present invention. N times the throughput can be obtained.

  In the eighth and ninth embodiments of the present invention, a case is considered in which the instructions held in the instruction cache unit 81 are restricted so as not to have a dependency relationship. For example, a case may be assumed in which instructions that are previously constrained so as to have no dependency are stored in the main storage device 800 during compilation. In this case, in each embodiment, as shown in FIG. 10, the forwarding path between the computing units 83 can be omitted. As a result, this embodiment can simplify the circuit, and can further achieve the effects of reducing the circuit scale and power consumption.

(Tenth embodiment)
Next, a tenth embodiment of the present invention will be described in detail with reference to the drawings. This embodiment is different from the ninth embodiment of the present invention in that the instruction cache unit is divided according to the number of arithmetic units. Note that in the description of the present embodiment and the drawings, the same components as those in the ninth embodiment of the present invention are denoted by the same reference numerals, and detailed description thereof will be omitted.

  FIG. 11 shows the configuration of a scalar processor 100 as a tenth embodiment of the present invention. In FIG. 11, the scalar processor 100 includes an instruction cache unit 101 and a calculation unit 102.

  The instruction cache unit 101 constitutes an embodiment of a data holding unit in the present invention. The instruction cache unit 101 is divided into n × N division units 105 (105_1 to 105_n), which is the same number as the arithmetic units 103 included in the calculation unit 102 described later. The dividing unit 105 holds an instruction read from the main storage device 800. Each division unit 105 is associated with one of n × N computing units 103.

  The computing unit 102 includes n × N computing units 103 (103_1 to 103_nN). Here, n is an integer of 1 or more, and is equal to the number n of stages when the instruction is pipelined. N is an integer of 1 or more. In FIG. 11, 10 arithmetic units 103 and 10 division units 105 are shown as n = 5 and N = 2, but the values of n and N in the present invention, the arithmetic units included in the arithmetic units, The number and the division number of the instruction cache unit are not limited.

  Each computing unit 103 is configured in substantially the same manner as the computing unit 83 in the ninth embodiment of the present invention, except that an instruction is acquired from the corresponding dividing unit 105. Each computing unit 103 writes the result of the instruction back to a cache (not shown).

  The operation of the scalar processor 100 configured as described above will be described below. In the following description, it is assumed that each arithmetic unit 103 processes an instruction with five stages of fetch, decode, execution, memory access, and write back as one stage. Further, it is assumed that the arithmetic unit 102 includes ten arithmetic units 103_1 to 103_10 that are equal to twice the number of stages of the instruction pipeline. The instruction cache unit 101 is divided into ten division units 105 (105_1 to 105_10), which is the same number as the arithmetic unit 103.

  In the first clock cycle, the arithmetic units 103_1 to 103_10 respectively receive the instructions read from the dividing units 105_1 to 105_10 as inputs. The arithmetic units 103_1 to 103_10 fetch input instructions and perform decoding, execution, memory access, and write back, respectively. Then, the arithmetic units 103_1 to 103_10 respectively write back the results to the cache in the second clock cycle after the first clock cycle.

  In the second clock cycle, the arithmetic units 103_1 to 103_10 respectively receive the instructions read from the dividing units 105_1 to 105_10 as inputs. At this time, the arithmetic units 103_1 to 103_10 each complete a series of processes based on the instruction input in the first clock cycle. Therefore, the arithmetic units 103_1 to 103_10 fetch the input instruction, and perform decoding, execution, memory access, and write back, respectively. Then, the arithmetic units 103_1 to 103_10 respectively write back the results to the cache in the third clock cycle after the first clock cycle.

  Thereafter, the scalar processor 100 repeats the same operation.

  Next, effects of the tenth embodiment of the present invention will be described.

  The scalar processor according to the tenth embodiment of the present invention reduces the circuit scale and power consumption when realizing performance equal to or better than that of an n-stage pipeline while avoiding problems in the pipeline. Can be reduced.

  The reason is that the instruction cache unit is divided into n × N division units, which is the same number as the arithmetic units, and each arithmetic unit executes a series of processes based on instructions read from each division unit in one stage. It is.

  As a result, the present embodiment does not require the interleaving unit that is necessary in the ninth embodiment of the present invention to achieve performance equivalent to an n-stage pipeline using n × N arithmetic units. And Therefore, the present embodiment reduces the circuit scale as compared with the ninth embodiment of the present invention. Further, in this embodiment, the clock cycle of the interface between the instruction cache unit and the arithmetic unit is increased by n times as compared with the ninth embodiment of the present invention. As a result, the present embodiment further reduces the circuit scale and power consumption while obtaining the same effects as those of the ninth embodiment of the present invention.

(Eleventh embodiment)
Next, an eleventh embodiment of the present invention will be described in detail with reference to the drawings. This embodiment is different from the tenth embodiment of the present invention in that it has the same number of arithmetic units as the number of instruction registers. Note that, in the description of the present embodiment and each drawing, the same components as those in the tenth embodiment of the present invention are denoted by the same reference numerals, and detailed description thereof will be omitted.

  FIG. 12 shows the configuration of the scalar processor 110 according to the eleventh embodiment of the present invention. 12, the scalar processor 110 includes M instruction registers 111 (111_1 to 111_M) and an arithmetic unit 112.

  The M instruction registers 111 hold instructions read from the main storage device 800.

  The arithmetic unit 112 includes the same number of M arithmetic units 113 (113_1 to 113_M) as the instruction register 111.

  Each computing unit 113 is configured in substantially the same manner as the computing unit 103 in the tenth embodiment of the present invention, except that an instruction is acquired from the corresponding instruction register 111. Each computing unit 113 writes the processing result back to a register (not shown).

  The operation of the scalar processor 110 configured as described above will be described below. In the following description, it is assumed that each arithmetic unit 113 processes an instruction with five stages of fetch, decode, execution, memory access, and write back as one stage.

  In the first clock cycle, the arithmetic unit 113_1 receives an instruction read from the instruction register 111_1 as an input. The arithmetic unit 113_1 fetches the input instruction and performs decoding, execution, memory access, and write back. Then, the arithmetic unit 113_1 writes the result back to the register in the second clock cycle after the first clock cycle.

  Similarly, in the first clock cycle, the calculators 113_2 to 113_M respectively receive the instructions read from the instruction registers 111_2 to 111_M as inputs. The arithmetic units 113_2 to 113_M fetch the input instruction and perform decoding, execution, memory access, and write back, respectively. Then, the arithmetic units 113_2 to 113_M write the results back to the registers in the second clock cycle after the first clock cycle.

  In the second clock cycle, the arithmetic units 113_1 to 113_M respectively receive the instructions read from the instruction registers 111_1 to 111_M as inputs. The arithmetic units 113_1 to 113_M fetch the input instruction and perform decoding, execution, memory access, and write back, respectively. Then, the arithmetic units 113_1 to 113_M write the results back to the registers in the third clock cycle after the first clock cycle.

  Thereafter, the scalar processor 110 repeats the same operation.

  Next, effects of the eleventh embodiment of the present invention will be described.

  The scalar processor according to the eleventh embodiment of the present invention can achieve high performance equal to or higher than that of a pipeline while avoiding problems in the pipeline.

  This is because the arithmetic unit has the same number of arithmetic units as the number M of instruction registers, and each arithmetic unit reads an instruction from the corresponding instruction register and executes a series of processes in one stage.

  As described above, since this embodiment includes M arithmetic units that perform n-stage instructions in one stage, it is possible to realize M / n times performance with respect to an n-stage pipeline.

(Twelfth embodiment)
Next, a twelfth embodiment of the present invention will be described in detail with reference to the drawings. In the present embodiment, an example in which the scalar processor according to the eleventh embodiment of the present invention is applied to each arithmetic unit in the seventh embodiment of the present invention will be described. In the description of the present embodiment and the drawings, the same reference numerals are given to the same configurations and steps that operate in the same manner as in the seventh and eleventh embodiments of the present invention, and the details in the present embodiment. The detailed explanation is omitted.

  FIG. 13 shows the configuration of a processor 120 according to the twelfth embodiment of the present invention. In FIG. 13, the processor 120 includes a vector register unit 71 and a calculation unit 122.

  The calculation unit 122 includes m scalar processors 110 (110_1 to 110_m) having the same number as the number of elements of the vector register. Each scalar processor 110 acquires vector data and a vector instruction from the broadcast unit 77 and the corresponding element unit 66, and executes an operation indicated by each instruction element on each data element. At this time, each scalar processor 110 can execute M processes based on the broadcasted vector data and the M elements of the vector instruction using M computing units 113. For example, each scalar processor 110 may read a data element as an operand from either or both of the element unit 66 and the broadcast unit 77. Each computing unit 113 may read the command element from either the element unit 66 or the broadcast unit 77. Thereby, the arithmetic unit 122 can operate the same instruction on different operands in all the scalar processors 110. Alternatively, the arithmetic unit 122 can execute different operations using at least one identical operand in all the scalar processors 110.

  The operation of the processor 120 configured as described above will be described below. In the following description, it is assumed that the broadcast unit 77 broadcasts vector data representing one of a vector command and an operand, and the element unit 66 reads a data element representing the other of the operands.

  In the first clock cycle, the scalar processor 110_1 receives the vector instruction and vector data broadcast from the broadcast unit 77 and the first data element read from the element unit 66_1 as inputs. The scalar processor 110_1 processes a process based on the input instruction and data in the second clock cycle after the first clock cycle.

  Similarly, in the first clock cycle, the scalar processors 110_2 to 110_m respectively receive the vector instruction and vector data broadcast from the broadcast unit 77 and the data elements read from the element units 66_2 to 66m as inputs. The scalar processors 110_2 to 110_m process the processing based on the input instruction and data in the second clock cycle after one clock cycle.

  In the second clock cycle, the scalar processors 110_1 to 110_m respectively receive the vector command and vector data broadcast from the broadcast unit 77 and the data elements read from the element units 66_1 to 66m as inputs. The scalar processors 110_1 to 110_m process a process based on the input instruction and data in the third clock cycle after one clock cycle.

  Thereafter, the processor 120 repeats the same operation.

  Next, effects of the twelfth embodiment of the present invention will be described.

  The processor according to the twelfth embodiment of the present invention can efficiently execute a plurality of operations with the same instruction or operand when realizing performance equal to or better than that of the pipeline while avoiding problems in the pipeline. And

  The reason is that the vector register unit has an element unit and a broadcast unit, the arithmetic unit has the same number of scalar processors as the eleventh embodiment of the present invention, and each scalar processor broadcasts. This is because a series of processing is executed in one stage using a vector command or vector data broadcast from the unit and a command element or data element read from the element unit. As a result, this embodiment can prevent the throughput with the memory from becoming a performance bottleneck when the same instruction is to be executed in all the arithmetic units or the same operand is to be used in all the arithmetic units. .

  In the second to seventh embodiments of the present invention described above, the floating point arithmetic operation performed by each arithmetic unit in the vector processor has been described mainly with four stages. However, the arithmetic operation performed by each arithmetic unit is described. The type and the number of stages are not limited.

  Further, in the above-described second embodiment of the present invention, the example in which the series of processing executed by each arithmetic unit in the vector processor is floating point addition has been mainly described, but the type of arithmetic is not limited. .

  Further, in the above-described third to seventh embodiments of the present invention, each arithmetic unit has been described mainly with respect to an example in which either a floating point addition or a floating point multiplication can be selected and executed. It does not limit the types and number of types of operations that can be performed.

  Further, in the above-described eighth to eleventh embodiments of the present invention, description has been made centering on an example in which the instruction executed by each arithmetic unit in the scalar processor is composed of five stages. The number is not limited.

  Moreover, each embodiment mentioned above can be implemented in combination as appropriate.

  The present invention is not limited to the above-described embodiments, and can be implemented in various modes.

A part or all of each of the above-described embodiments can be described as in the following supplementary notes, but is not limited thereto.
(Appendix 1)
A data holding unit for holding each data read from the main storage device;
An arithmetic unit that executes a series of processes based on each data in parallel using a plurality of arithmetic units that start the series of processes based on the next data after finishing a series of processes based on the data;
With processor.
(Appendix 2)
The processor according to appendix 1, wherein the arithmetic unit further includes an interleaving unit that interleaves each data held in the data holding unit with respect to the plurality of arithmetic units.
(Appendix 3)
The data holding unit is divided into the number of the computing units, and each divided part is associated with each computing unit,
The processor according to appendix 1, wherein each of the arithmetic units executes the series of processing based on data held in the corresponding divided portion.
(Appendix 4)
The arithmetic unit includes N arithmetic units of N (N is an integer of 1 or more) times n when the series of processes includes n (n is an integer of 1 or more) stages. To 4. The processor according to any one of appendix 3.
(Appendix 5)
The data holding unit further holds data broadcast to the respective computing units,
The processor according to any one of Supplementary Note 1 to Supplementary Note 4, wherein each of the arithmetic units executes the series of processes based on the broadcast data.
(Appendix 6)
Any one of appendix 1 to appendix 5, wherein the computing unit includes a forwarding path between the computing units for inputting data generated in the series of processes in each computing unit to another computing unit. Processor described in 1.
(Appendix 7)
The data holding unit is configured by a vector register that holds vector data composed of data elements,
The processor according to any one of Supplementary Note 1 to Supplementary Note 5, wherein each of the computing units executes computation on the data element as the series of processes.
(Appendix 8)
The data holding unit further holds a vector instruction composed of instruction elements representing the contents of an operation on each data element,
The processor according to appendix 7, wherein each of the arithmetic units executes an operation indicated by the instruction element corresponding to each data element as the series of processes.
(Appendix 9)
The computing unit has the same number of computing units as the number of elements of the vector register,
9. The processor according to appendix 7 or appendix 8, wherein each of the arithmetic units executes the series of processes on the corresponding data element.
(Appendix 10)
The data holding unit holds information representing an instruction for each arithmetic unit,
The processor according to any one of appendix 1 to appendix 5, wherein each arithmetic unit ends a series of processes based on the instruction and then starts a series of processes based on a next instruction.
(Appendix 11)
Using a plurality of arithmetic units that start the series of processes based on the next data after completing a series of processes based on the data read from the main storage device and held in the data holding unit, A processing method of a processor that executes a series of processes based on parallel processing.
(Appendix 12)
The processor processing according to appendix 11, wherein a series of processing based on each data is executed in parallel by interleaving each data held in the data holding unit with respect to the plurality of arithmetic units. Method.

1, 120 Processor 2, 3, 4, 5, 6, 7, Vector processor 8, 9, 100, 110 Scalar processor 11 Data holding unit 12, 22, 32, 42, 52, 62, 72, 82, 92, 102 , 112, 122 arithmetic unit 13, 23, 33, 53, 63, 73, 83, 103, 113 arithmetic unit 21, 31, 51, 61, 71 vector register unit 24, 34, 44, 84, 94 interleave unit 55, 105 Dividing unit 66 Element unit 77 Broadcasting unit 81, 101 Instruction cache unit 111 Instruction register 800 Main storage device 801 Memory 802 Memory interleaving unit 900 Processor 901 Logic circuit

Claims (7)

An operation on one or more vector data to be calculated, read from the main storage device, and an i-th data element (i is an integer equal to or more than 1 and equal to or less than the number of elements of the vector data) A data holding unit for holding a vector command composed of command elements representing the contents of
Using a plurality of arithmetic units that start the series of processes for the next data element after completing a series of processes for the operation indicated by the instruction element corresponding to the data element, An arithmetic unit that executes processing in parallel;
With processor. The arithmetic unit, the is held in the data holding unit, one or more of said vector data to be the arithmetic, and further comprising a interleaving unit for interleaving with respect to the plurality of arithmetic units The processor of claim 1. The data holding unit is divided into the number of the computing units, and each divided part is associated with each computing unit,
Wherein each operation unit, based on the data elements held in the divided portion corresponding processor of claim 1, characterized in that executing the series of processes.   The arithmetic unit includes, when the series of processes includes n (n is an integer equal to or greater than 1) stages, N arithmetic units of N (N is an integer equal to or greater than 1) times. The processor according to any one of claims 1 to 3. The data holding unit further holds the vector data that is the broadcast for each calculator,
Wherein each operation unit is further based on the vector data that is the broadcast, the processor according to any one of claims 1 to 4, characterized in that executing the series of processes. One or more vector data to be calculated, read from the main storage device and held in the data holding unit, and the i-th vector in each of the vector data (i is 1 or more and the number of elements of the vector data or less And a vector instruction consisting of instruction elements representing the contents of the operation on the data element of
Using a plurality of arithmetic units that start the series of processes for the next data element after completing a series of processes for the operation indicated by the instruction element corresponding to the data element, A processor processing method that executes processing in parallel. The series of processes are executed in parallel by interleaving the one or more vector data and the vector instruction to be subjected to the operation held in the data holding unit with respect to the plurality of computing units. The processor processing method according to claim 6 .

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