JP6056243B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  In the following, embodiments of the semiconductor device and the manufacturing method thereof will be described.

  In recent years, high-voltage elements and low-voltage elements are mixedly mounted in system LSIs and the like. Examples of such a high voltage element include a semiconductor element for power supply and a semiconductor element for high surge used in a motor drive circuit for automobile applications. Examples of the low voltage element include a logic semiconductor element. Is mentioned.

JP 2004-363136 A JP-A-10-116895 Japanese Patent Laid-Open No. 10-50948 JP-A-9-321135

  A system LSI in which a high voltage diode and a low voltage logic circuit are mixedly mounted has been studied.

  In a semiconductor integrated circuit, when the applied voltage to the wiring layer is about 40 V, for example, the conductivity type of the surface of the semiconductor substrate or the well included in the element region is reversed, and a conductive channel is formed. is there. As a result, for example, even if a diode is configured as an element on the semiconductor substrate, a current may flow through the conductive channel, causing a problem that the element does not function as a diode.

  Therefore, when such a high voltage diode is incorporated in a system LSI, a multilayer wiring structure is used, and the wiring to the high voltage diode is separated from the surface of the semiconductor substrate so that the upper layer or the uppermost layer of the multilayer wiring structure is separated. A countermeasure for making a connection between the wiring layer and the diode by a deep via plug has been studied. However, the upper or uppermost wiring layer has a problem that the degree of freedom of the wiring layout is small, and even if such measures are taken, it cannot be avoided that destruction occurs at the diode junction when a surge occurs. The problem remains.

  That is, in a high breakdown voltage diode, in order to ensure a reverse breakdown voltage, the impurity concentration of the p-type well constituting the anode is made lower than that of a normal diode, and therefore a voltage exceeding the rating is applied by, for example, a surge or the like. In some cases, the joint is destroyed. When the junction is destroyed, the diode is disconnected or remains conductive, and does not function as a diode. Further, the joint portion destroyed in this way does not recover even after the high voltage is released.

  Therefore, in the case of such a high voltage diode, if it is to have surge voltage tolerance, it can have a withstand voltage higher than the rated voltage by design, and measures such as reducing the impurity concentration and increasing the element size. In addition, special measures are required to deepen the bonding, which causes a significant cost increase.

A semiconductor device according to an embodiment includes a semiconductor substrate, a first diffusion region of a first conductivity type formed in the semiconductor substrate, and the first conductivity formed in the first diffusion region. A second diffusion region of a second conductivity type opposite to the mold, a third diffusion region of the first conductivity type formed in the second diffusion region, and the semiconductor substrate is formed on the first wiring pattern in which the first voltage is connected to said second diffusion region is supplied, the formed on a semiconductor substrate, wherein the higher than first voltage second voltage is supplied anda second wiring pattern that will be connected to the third diffusion region, said second and third diffusion regions form a diode by pn junction, the said second diffusion region first Between the second wiring pattern and the second wiring pattern in plan view. First voltage is provided a conductive pattern to be supplied.

  According to the above embodiment, a high breakdown voltage diode having a high breakdown voltage and capable of avoiding the breakdown of the pn junction even when a surge voltage exceeding the rating comes in is obtained.

It is sectional drawing and a top view which show the structure of the high voltage | pressure-resistant diode by 1st Embodiment. It is a graph which shows the relationship between a shielding electrode width and the proof pressure of the high voltage | pressure-resistant diode of FIG. It is sectional drawing which shows the structure of the high voltage | pressure-resistant diode by a comparative example. FIG. 2 is a diagram (part 1) for explaining a manufacturing process of the high voltage diode in FIG. 1; FIG. 3 is a diagram (No. 2) for explaining a production process of the high voltage diode in FIG. 1; FIG. 8 is a diagram (No. 3) for explaining a production process of the high voltage diode in FIG. 1; FIG. 4 is a diagram (No. 4) for explaining a production process of the high voltage diode in FIG. 1; FIG. 7 is a diagram (No. 5) for explaining a production process of the high voltage diode in FIG. 1; FIG. 6 is a view (No. 6) for explaining a production process of the high voltage diode in FIG. 1; FIG. 7 is a view (No. 7) for explaining a production process of the high voltage diode in FIG. 1; FIG. 8 is a view (No. 8) for explaining a production process of the high voltage diode in FIG. 1; FIG. 9 is a diagram (No. 9) for explaining a production process of the high voltage diode in FIG. 1; FIG. 10 is a diagram (No. 10) for explaining a production process of the high voltage diode in FIG. 1; FIG. 11 is a diagram (No. 11) for explaining a production process of the high voltage diode in FIG. 1; FIG. 12 is a diagram (No. 12) for explaining the production process of the high voltage diode in FIG. 1; FIG. 13 is a view (No. 13) for explaining a production process of the high voltage diode in FIG. 1; FIG. 14 is a view (No. 14) for explaining the production process of the high voltage diode in FIG. 1; FIG. 15 is a view (No. 15) for explaining a production process of the high voltage diode in FIG. 1; FIG. 16 is a view (No. 16) for explaining a production step of the high voltage diode in FIG. 1; It is FIG. (17) explaining the manufacturing process of the high voltage | pressure-resistant diode of FIG. It is FIG. (18) explaining the manufacturing process of the high voltage | pressure-resistant diode of FIG. FIG. 19 is a view (No. 19) for explaining a production step of the high voltage diode of FIG. 1; FIG. 20 is a view (No. 20) for explaining the production process of the high voltage diode in FIG. 1; FIG. 22 is a view (No. 21) for explaining a production step of the high voltage diode in FIG. 1; FIG. 22 is a view (No. 22) for explaining the production process of the high voltage diode in FIG. 1; It is sectional drawing and a top view which show the structure of the high voltage | pressure-resistant diode by 2nd Embodiment. FIG. 27 is a diagram (No. 1) for explaining a production process of the high voltage diode in FIG. 26; FIG. 27 is a second diagram for explaining the manufacturing process of the high voltage diode in FIG. 26; FIG. 27 is a diagram (No. 3) for explaining a production process of the high voltage diode in FIG. 26; FIG. 27 is a diagram (No. 4) for explaining the production process of the high voltage diode in FIG. 26; FIG. 27 is a diagram (No. 5) for explaining a manufacturing process of the high voltage diode in FIG. 26; FIG. 27 is a diagram (No. 6) for explaining a production process of the high voltage diode in FIG. 26; FIG. 27 is a view (No. 7) for explaining a production step of the high voltage diode in FIG. 26; FIG. 27 is a diagram (No. 8) for explaining a production process of the high voltage diode in FIG. 26; FIG. 27 is a diagram (No. 9) for explaining a manufacturing process of the high voltage diode in FIG. 26; FIG. 27 is a view (No. 10) for explaining a production process of the high voltage diode in FIG. 26; FIG. 27 is a diagram (No. 11) for explaining a production process of the high voltage diode in FIG. 26; FIG. 27 is a view (No. 12) for explaining a production step of the high voltage diode in FIG. 26; FIG. 27 is a view (No. 13) for explaining a production step of the high voltage diode in FIG. 26; It is a circuit diagram which shows the structure of the drive circuit by 3rd Embodiment. It is sectional drawing and a top view which show the structure of the high voltage | pressure-resistant diode by 4th Embodiment.

[First Embodiment]
1A (hereinafter referred to as FIG. 1A) is a cross-sectional view showing the configuration of the semiconductor device 20 according to the first embodiment, and FIG. 1B is a diagram (hereinafter referred to as FIG. 1B). Is a plan view corresponding to the cross-sectional view of FIG. The cross-sectional view of FIG. 1A shows a cross section taken along line 1-1 ′ in the plan view of FIG.

  The semiconductor device 20 is a high breakdown voltage diode, and has a reverse breakdown voltage of 42 V in the illustrated example. However, the present invention is not limited to such specific standards and operating voltages.

  1A and 1B, the semiconductor device 20 is formed on a silicon substrate 21, and includes an n-type first diffusion region 21A and the first diffusion region 21A in plan view. P-type second diffusion region 21B formed so as to be included in the region, and n-type third diffusion region 21C formed so as to be included in the second diffusion region 21B in plan view. .

In the illustrated example, the first diffusion region 21A has, for example, a square having a side of 35 μm in a plan view, a depth of 6 μm in a cross-sectional view, and 6 × 10 ¹⁶ cm ⁻³ by P (phosphorus). It is doped with an impurity concentration of. On the other hand, the second diffusion region 21B has, for example, a square having a side of 23 μm in a plan view, a depth of 2.3 μm in a sectional view, and 1 × 10 ¹⁷ cm ⁻³ by B (boron). It is doped with an impurity concentration of. Further, the third diffusion region 21C has, for example, a square having a side of 15 μm in a plan view, a depth of 0.35 μm in a sectional view, and 1.2 × 10 ¹⁷ cm ⁻ by P (phosphorus). Doped to ³ impurity concentration. Here, the second diffusion region 21 </ b> B constitutes the anode of the high voltage diode 20, and the third diffusion region 21 </ b> C constitutes the cathode of the high voltage diode 20. The diffusion region 21 </ b> A forms a shielding layer surrounding the high voltage diode 20.

  On the surface of the silicon substrate 21, an STI type element isolation region 21I is formed to a thickness of, for example, 0.38 μm so as to cover the first and second diffusion regions 21A and 21B. The diffusion region 21C is formed in an opening formed in the element isolation region 21I.

  An interlayer insulating film 23 including a first wiring layer M1 is formed on the silicon substrate 21 via an interlayer insulating film 22, and the first wiring layer M1 has, for example, a ground voltage (0 V). Is provided, wiring patterns 23B and 23G to which an anode voltage is supplied, and connection pads 23C to which a high cathode voltage is supplied. As will be described later, the wiring patterns 23A and 23B may be short-circuited.

The wiring pattern 23A is connected through the via plug 22V _A in a first opening formed in the device isolation region 21I in the first diffusion region 21A, wherein the surface of the first diffusion region 21A, the for electrical connection to the via plug 22V _a, and the ^{n +} -type contact region 21A _C and the silicide layer 21A _S are sequentially formed. As can be seen from the plan view of FIG. 1B, a large number of via plugs 22V _A are arranged in the first diffusion region 21A so as to surround the second diffusion region 21B, thereby reducing the contact resistance. . Accordingly, the silicide layer 21As is also formed so as to surround the second diffusion region 21B. In the plan view of FIG. 1B, the element isolation region 21I and the silicide layer 21As are not shown for simplicity. The voltage applied to the wiring pattern 23A is not limited to the ground voltage. For example, the same anode voltage as that of the wiring pattern 23B can be supplied by short-circuiting the wiring pattern 23B.

Further, the wiring pattern 23B is connected to the second diffusion region 21B via a via plug 22V _B in a second opening formed in the element isolation region 21I. On the surface of the second diffusion region 21B, the via plug 22V _B and for electrical connection, and a ^{p +} -type contact region 21B _C and the silicide layer 21B _S are sequentially formed. The via plug 22V _B is the second diffusion region 21B as seen from a plan view in FIG. 1 (B), the third is arranged numerous so as to surround the diffusion region 21C, the reduction of the contact resistance is achieved . Also, the silicide layer 21B _S Along with this is also formed to include a substantially U-shaped portion surrounding said third diffusion region 21C. The device isolation region 21I and the silicide layer 21B _S also in the plan view of FIG. 1 (B), not shown for simplicity.

It is further connected the connection pad 23C via the via plug 22V _C in the third opening that is formed in the device isolation region 21I in the third diffusion region 21C, the surface of the second diffusion region 21C is the via plug 22V _C and for electrical connection, and the ^{n +} -type contact region 21C _C and the silicide layer 21C _S are sequentially formed. The contact region 21C _C and the silicide layer 21Cs are formed by being surrounded by a sidewall insulating film 21SW _A surrounding the cathode 21C, and are separated from the surrounding element isolation region 21I by the sidewall insulating film 21SW _A. .

As can be seen from the plan view of FIG. 1B, a large number of the via plugs 22V _C are arranged in the third diffusion region 21C, for example, in a lattice shape to reduce the contact resistance. In the plan view of FIG. 1B, the element isolation region 21I and the silicide layer 21Cs are not shown for simplicity.

  Further, the wiring layer M1 is formed in the interlayer insulating film 23 with the element isolation region 21I and the first-layer interlayer insulating film 22 separated from the second diffusion region 21B, as seen from the plan view of FIG. As can be seen, a conductive pattern 23G branched from the wiring pattern 23B is included. In the example shown in the figure, the conductive pattern 23G includes three sides surrounded by the U-shaped portion of the wiring pattern 23B among the four sides of the third diffusion region 21C. The U-shaped part of the U-shaped wiring pattern 23B is bridged so as to close the remaining one side.

  Further, an interlayer insulating film 24 is formed on the interlayer insulating film 23, and a second wiring layer M2 including a power supply wiring pattern 24A supplied with a high voltage of, for example, + 42V is formed in the interlayer insulating film 24. Is formed.

Said power supply wiring patterns 24A to the connection pad 23C, the interlayer insulating film are electrically connected by a plurality of via plugs 24V _A formed in 23, as shown in the sectional view of that time Figure 1 (A) It should be noted that the wiring pattern 24A extends across the conductive pattern 23G. In the illustrated example, as shown in the plan view of FIG. 1B, the wiring pattern 24A extends in parallel between the wiring pattern 23A and the wiring pattern 23B from the third diffusion region 21C in plan view. And crosses over the conductive pattern 23G.

In the diode 20 of FIG. 1, the impurity concentration of the second diffusion region 21B is suppressed to 1 × 10 ¹⁷ cm ⁻³ or less, so that a high voltage is applied between the third diffusion region 21C and the third diffusion region 21C. As a result of an increase in the thickness of the depletion layer formed, a reverse breakdown voltage against the power supply voltage of, for example, + 42V is ensured. Accordingly, the second diffusion region 21B has a sufficient thickness corresponding to the spread of the depletion layer.

  On the other hand, in the high voltage diode 20 according to the present embodiment, an inversion region INV can be formed along the wiring pattern 24A on the surface of the second diffusion region by an electric field accompanying a high voltage on the wiring pattern 24A. It should be noted that there is sex. In the high breakdown voltage diode 20 according to the present embodiment, the inversion region INV is suppressed from being formed because the electric field of the wiring pattern 24A is shielded immediately below the conductive pattern 23G. As a result, the conductive pattern 23G Note that it is divided into two parts. For this reason, even if a high voltage is applied to the wiring pattern 24A in the high breakdown voltage diode 20 of the present embodiment, the n-type diffusion region 21C is outside through the inversion region INV as long as the high voltage is within the rating of the diode. There is no short circuit to the n-type diffusion region 21A.

  On the other hand, the shield electrode pattern 23G constitutes a parasitic MOS transistor together with the n-type diffusion regions 21A and 21C and the p-type diffusion region 21B, and the wiring pattern 24A is set by appropriately setting the width of the conductive pattern 23G. The parasitic MOS transistor can be set to be conductive when the voltage applied to the voltage exceeds a predetermined value due to, for example, a surge. The high breakdown voltage diode 20 configured in this way can form a discharge path by conducting the parasitic MOS transistor in this way even when a high voltage exceeding the standard value is applied, and the diffusion region 21B and the diffusion region can be formed. It is possible to avoid irreparable breakdown of the pn junction with the region 21C. The discharge current flowing through the first diffusion region 21A is grounded via the ground electrode pattern 23A or absorbed by an external power source.

  FIG. 2 is a graph showing the relationship between the width of the conductive pattern 23G and its breakdown voltage in the high breakdown voltage diode 20 of FIG.

  Referring to FIG. 2, the diode 20 has a rated voltage of 42V. When the conductive pattern 23G having a width L of 0.3 μm is provided, the element breakdown voltage at which the pn junction is broken is about 46V. As can be seen, when the width L is increased to 1.9 μm, the device breakdown voltage increases to about 67V.

  In contrast, FIG. 3 is a cross-sectional view showing an example of a high voltage diode 30 according to a comparative example of the present embodiment. For comparison, the same reference numerals in FIG. 3 denote parts corresponding to those in FIG.

Referring to FIG. 3, in the present comparative example, the conductive pattern 23G is omitted from the high breakdown voltage diode 20 of FIG. 1, and when the high voltage is applied to the wiring pattern 24A of FIG. In order to avoid the problem that the inversion layer INV is formed on the surface of the diffusion region 21B and the discharge current flows, a wiring pattern 25A to which a high voltage is applied is formed in the third wiring layer M3. . Connection pads 24B are provided in place of the wiring pattern 24A in the wiring layer M2 of the for the second layer, the interlayer insulating film 23 interlayer insulating film 24 via plug 24V _A is formed on is formed, said wiring The pattern 25 A is formed in the interlayer insulating film 25 next to the interlayer insulating film 24. The wiring pattern 25A is in contact with the connection pads 25B through the via plug 24V _A. However, such a configuration requires a multilayer wiring structure in which a large number of interlayer insulating films are laminated in order to form the wiring pattern 25A away from the surface of the substrate 21, and the size of the diode 30 increases, There are problems such as a low degree of freedom and difficulty in design.

  Further, in such a configuration, since a discharge current path via the inversion layer INV formed on the surface of the second diffusion region 21B is not formed in this way, when a surge enters the wiring pattern 25A, the second diffusion is performed. A very large electric field is generated in the region 21B and the third diffusion region 21C, causing a problem that the pn junction is easily broken. For this reason, in the comparative example of FIG. 3, in order to reduce the electric field of the depletion layer formed in the vicinity of the pn junction, the impurity concentration of the diffusion regions 21B and 21C is decreased to increase the thickness of the depletion layer and to accommodate the depletion layer. In addition, the thickness of the diffusion regions 21B and 21C is increased. However, such a configuration has a problem that the size of the diode 30 further increases and the cost increases. In such a configuration, since the thickness of the diffusion regions 21B and 21C increases, the parasitic resistance of the diode also increases.

  On the other hand, in the high breakdown voltage diode 20 of FIG. 1, by disposing the conductive pattern 23G near the surface of the second diffusion region, the discharge current path by the inversion layer INV in a normal state without increasing the element size. However, when a high voltage exceeding the rated voltage such as surge comes in, this discharge path is closed and the discharge current flows. This protects the pn junction formed by the second and third diffusion regions 21B and 21C. That is, according to the present embodiment, it is possible to configure a high voltage diode having high reliability and low parasitic resistance while being small and inexpensive.

  Hereinafter, a method for manufacturing a semiconductor device including the high voltage diode 20 of FIG. 1 will be described with reference to FIGS. However, in each of FIGS. 1-19, (B) represents a plan view, and (A) represents a cross-sectional view along line LL ′ in the plan view of (B).

  4A and 4B, first, a p-type silicon substrate having a specific resistance of 10 Ωcm, for example, is prepared as the silicon substrate 21, and the surface thereof is thermally oxidized to form a protective oxide film 21Ox. A surface of the silicon substrate 21 is covered and formed to a thickness of about 10 nm, for example. In the illustrated example, a substrate region 20A for the high breakdown voltage diode 20 to be formed is formed on the silicon substrate 21. The substrate region 20B for the n-channel MOS transistor 20NMOS and the p-channel MOS transistor 20PMOS that are formed simultaneously. It is secured together with 20C.

Next FIG. 5 (A), the patterned by the protective covering oxide film 21Ox to form a resist pattern R _1, which photolithography on the silicon substrate 21 in the step of (B), in the substrate region 20A A resist opening R ₁ A exposing the protective oxide film 21Ox is formed. Other substrate areas 20B, the resist pattern _{R 1} in 20C covers the surface of the silicon substrate 21. According to an example, the resist opening R ₁ A has a square shape with a side of 35 μm, for example. In yet a plan view of FIG. 5 (B), illustration of the resist pattern R ₁ and the protective oxide film 21Ox should be noted that it is omitted.

Further, in the steps of FIGS. 5A and 5B, an acceleration voltage of, for example, 2 MeV corresponding to the resist opening R ₁ A in the silicon substrate 21 with P + (phosphorus ions) using the resist pattern R ₁ as a mask. Below, ions are implanted at a dose of 2.43 × 10 ¹³ cm ⁻² . As a result, in the silicon substrate 21, when the phosphorus ions are activated, an n-type well as the first diffusion region 21A has a substantially square planar shape with a side of, for example, about 35 μm and a depth of about 6 nm. Formed.

Next FIG. 6 (A), the patterned by the protective covering oxide film 21Ox to form a resist pattern R _2, which photolithography on the silicon substrate 21 in the step of (B), in the substrate region 20A A resist opening R ₂ A exposing the protective oxide film 21Ox is formed inside the first diffusion region 21A previously formed in plan view. Still other substrate areas 20B, the resist pattern _{R 2} in 20C, like the resist pattern _{R 1,} covering the surface of the silicon substrate 21. For example, the resist opening R ₂ A has a square shape with a side of 23 μm, for example. Note also in plan view in FIG. 6 (B), illustration of the resist pattern R ₂ and the protective oxide film 21Ox should be noted that it is omitted.

Furthermore FIG. 6 (A), the a mask the resist pattern _{R 2} is in the process of (B) B + (boron ions) into the silicon substrate 21, in correspondence to the resist opening portion _{R 2} A, for example 1.6MeV Under an acceleration voltage of 1.3 × 10 ¹³ cm ⁻² , under an acceleration voltage of 800 keV, at a dose of 5 × 10 ¹² cm ⁻² and under an acceleration voltage of 120 keV, 9.0 × 10 Ions are implanted at a dose of ¹² cm ⁻² , and P + (phosphorus ions) are further implanted at a dose of 6.0 × 10 ¹² cm ⁻² under an acceleration voltage of 40 keV, for example. As a result, in the silicon substrate 21, when the boron ions and phosphorus ions are activated, a p-type diffusion region having a substantially square planar shape having a side of about 23 μm and a depth of about 2.3 μm is formed. An n-type third diffusion region 21C formed as the second diffusion region 21B and having the same planar shape as the diffusion region 21B is formed at a depth of about 0.35 μm above the diffusion region 21B. The As described above, the diffusion region 21 </ b> B constitutes the anode of the high voltage diode 20, while the diffusion region 21 </ b> C constitutes the cathode of the high voltage diode 20. In the plan view of FIG. 6B, the lower diffusion region 21B overlaps with the upper diffusion region 12C and is not visible.

  Next, in the steps of FIGS. 7A and 7B, the protective oxide film 21Ox is removed by wet etching, and a new protective oxide film 21POx is formed on the surface of the silicon substrate 21 by thermal oxidation at 900 ° C. For example, it is formed to a film thickness of 15 nm. Also in the plan view of FIG. 7B, the protective oxide film 21POx is not shown.

Next, in the steps of FIGS. 8A and 8B, a silicon nitride film (not shown) is formed on the protective oxide film 21POx by a vapor deposition method, and this is patterned by a photolithography process. on the protective oxide film 21POx, silicon nitride film pattern 21PN _a ~21PN _G serving as a mask is formed in the step of forming the next element isolation region. Wherein the silicon nitride layer pattern 21PN _A is formed corresponding to the cathode 21C of the high voltage diode 20 in Fig. 1, whereas the silicon nitride film pattern 21PN _B and 21PNC the anode contact region 21B _C of each of the high-voltage diode 20 and it corresponds to the contact region 21A _C. Further nitride pattern 21PN _D corresponds to the element region of the n-channel MOS transistor formed in the substrate region 20B, the nitride film pattern 21PN _E corresponds to the well contact region of the n-channel MOS transistor. Further nitride pattern 21PN _F corresponds to the device region of the p-channel MOS transistor formed in the substrate region 20C, the nitride film pattern 21PN _G corresponds to the well contact region of the p-channel MOS transistor. In the plan view of FIG. 8B, the protective oxide film 21POx is not shown.

Next FIG. 9 (A), the forming an isolation trench in the silicon nitride layer pattern 21PN _A ~21PN _G etching the silicon substrate 21 as a mask to a depth, for example, about 350μm in the step (B). At this time, since the depth of the element isolation trench to be formed is deeper than the depth of the third diffusion region 21C serving as the cathode, the diffusion region 21C is patterned along with the formation of the element isolation trench, and the silicon nitride only the portion covered by the film 21PN _A and 21PN _B is left.

Thereafter, in the steps of FIGS. 9A and 9B, heat treatment is performed at 1100 ° C. in an oxidizing atmosphere to oxidize the silicon surface exposed on the side wall surface and the bottom surface of the element isolation trench, and the thickness is increased. For example, a 40 nm silicon oxide film is formed, and a high density silicon oxide film is further deposited to a thickness of, for example, about 700 nm by a high density plasma CVD method or the like, and the element isolation trench is filled with the silicon oxide film. Further the silicon oxide film, by the silicon nitride layer pattern 21PN _A ~21PN _G is chemical mechanical polishing to expose, to form an element isolation region 21I STI-type on the silicon substrate 21.

Next, in the steps of FIGS. 10A and 10B, the silicon nitride film patterns 21PN _{A to} 21PN _G are removed by wet etching using hot phosphoric acid, and the silicon oxide remaining on the silicon substrate is removed. The film is wet etched to a depth of, for example, 15 nm with an HF aqueous solution to expose the surface of the silicon substrate 21. Thereafter, the silicon nitride film pattern 21PN _A ~21PN _G is removed by wet etching. As a result, the patterned in correspondence with the silicon nitride film pattern 21PN _A third diffusion region 21C is exposed as a cathode and as an anode contact region 21B _C, the first diffusion region 21A is, the cathode It is exposed in a substantially U-shape. In the steps of FIGS. 10A and 10B, the n-type third diffusion region 21C is still exposed in the anode contact region 21BC, but this region is made p-type in a later step. The type changes. The first diffusion region 21A patterned in correspondence to the silicon nitride film pattern 21PN _C is exposed as the contact region 21A _C surrounds the second diffusion region.

Also, the substrate region silicon substrate 21 in corresponding to the device region 20NMOS of the n-channel MOS transistor 21B is exposed, further silicon substrate corresponding to the well contact region 21PW _C of the p-type well formed in the device region 20NMOS 21 is exposed.

Likewise the silicon substrate 21 substrate region 21C in corresponding to the device region 20PMOS of the p-channel MOS transistor is exposed, further in response to the well contact region 21NW _C of the n-type well formed in the element region 20PMOS silicon The substrate 21 is exposed.

Next, in the steps of FIGS. 11A and 11B, a protective oxide film 21POxx is formed on the silicon substrate 21 by a thermal oxidation process at 900 ° C., and further on the silicon substrate 21 corresponding to the substrate region 20B. A resist pattern R ₃ having a resist opening R ₃ A is formed. Further, the resist pattern _{R 3} under the acceleration voltage of 420keV boron (B +) as a mask, 2.0 × 10 ¹³ cm dose ^-2 and an acceleration voltage of an 15keV, 4.0 × 10 ¹² dose of cm ^-2 Then, phosphorus (P +) is ion-implanted at a dose amount of 2.0 × 10 ¹³ cm ⁻² under an acceleration voltage of 2 MeV to form an n-channel MOS transistor formed in the substrate region 20B. A p-type well 21PW is formed corresponding to the element region 21NMOS and the well contact region 21PWc.

Next FIG. 12 (A), the step wherein the resist pattern _{R 3} is removed in the (B), the substrate region 20A, 20C covered by new resist pattern _{R 4,} phosphorus substrate region 20C which is exposed (P + ) At a dose of 2.0 × 10 ¹² cm ⁻² at an acceleration voltage of 600 keV, and boron (B +) at a dose of 4.9 × 10 ¹² cm ⁻² at an acceleration voltage of 60 keV. ion implantation, the n-type well 21NW for p-channel MOS transistor formed in the substrate region 20C, are formed in correspondence to the device regions 21PMOS and the well contact region 21NW _C.

  Further, the structure shown in FIGS. 12A and 12B is heat-treated at 1000 ° C. for 10 seconds in a nitrogen atmosphere to activate the impurity element, whereby the substrate region 20B has a p-type for an n-channel MOS transistor. A well 21PW is formed, and an n-type well 21NW for a p-channel MOS transistor is formed in the substrate region 20C.

11A and 11B correspond to the stage before the thermal activation process as a process, and the p-type well 21PW has not yet been formed. The state where the formed p-type well 21PW is formed is illustrated. FIG. 11 (A), the order is intended to cover only the resist pattern _{R 3} substrate region 20A and 20C as seen from (B), the p-type well 21PW is towards the bottom of the device isolation region 21I in the high-voltage diode The channel cut region 21ChC is formed under the element isolation region 21I between the substrate region 20A and the element region 21NMOS, and extends in contact with the n-type region 21A outside the high breakdown voltage diode. Has been.

  Although not shown, in this step, a well for a horizontal DMOS (double-diffuse MOS) transistor may be additionally formed on the silicon substrate, and the high breakdown voltage transistor may be formed in the well.

After FIG. 12 (A), the of the step (B), the resist pattern _{R 4} is removed, further the silicon oxide film 21POxx is removed by wet etching using HF solution.

  Further, in the steps of FIGS. 13A and 13B, a gate insulating film 21Gox is formed on the exposed portion of the silicon substrate 21 in a wet atmosphere by thermal oxidation at, for example, 800 ° C. to a thickness of, for example, 15 nm to 20 nm. .

14A and 14B, a polysilicon film (not shown) is deposited to a thickness of about 200 nm on the silicon substrate 21 via the gate insulating film 21Gox and patterned. it allows the device region 21NMOS the gate electrode 21G _B, also respectively form the gate electrode 21G _C in the element region 21PMOS.

Next, in the steps of FIGS. 15A and 15B, on the silicon substrate 21, the element region 21NMOS of the n-channel MOS transistor, the cathode 21C of the high breakdown voltage diode 20, and the contact of the first diffusion region 21A. Resist having resist openings R ₄ A, R ₄ B, R ₄ C, and R ₄ D exposing the region 21 A _C , the element region 21 NMOS of the n-channel MOS transistor, and the well contact region 21 NWc of the n-type well 21 NW, respectively. forming a pattern _{R 4,} the resist pattern _{R 4} under the acceleration voltage of the P +, for example, from about 20keV to mask, ions are implanted at a dose of eg 5 × 10 ¹⁵ cm- ^2. Further, the impurity element is activated by performing a heat treatment at 1000 ° C. for 10 seconds in a nitrogen atmosphere, whereby the low resistance region 21C + is formed on the surface portion of the diffusion region 21C constituting the cathode, and the diffusion region 21B is first formed. It was enclosing further increase the impurity concentration of the surface portion of the low-resistance contact region 21A _C formed to form a low-resistance region 21A +. The formed n-type source extension region 21a and a drain extension region 21b are simultaneously in the device region 21NMOS of the substrate region 20B, in yet a substrate region 20C low resistance contact region 21NW _C surface portion of the n-type well 21NW Region 21NW _C + is formed.

Next, in the steps of FIGS. 16A and 16B, the resist pattern R ₄ is removed, and the anode contact region 21 B _C of the high breakdown voltage diode 20 and the n-channel MOS transistor are further formed on the silicon substrate 21. well contact region 21PWc, further the p-channel MOS transistor resist opening portion _R 5 _a to an element region 21PMOS exposed each, R 5 B, a resist pattern _{R 5} with _{R 5} C, masking the resist pattern _{R 5 BF} ^{2 +,} for example, under the acceleration voltage of about 80 keV, ions are implanted at a dose of 5 × 10 ¹⁵ cm- ^2, for example, in. Thus, forming the contact region 21B p-type low resistance region 21B + on the surface of the n-type diffusion region 21C constituting the _C, also of p-type in the device region 21PMOS source extension region 21c and a drain extension region 21d To do. Also in the substrate region 20B at the same time the low-resistance region 21P + is formed in the contact region 21PW _C of the p-type well 21PW.

Next, FIG. 17 (A), the resist pattern _{R 5} is removed in the step of (B), the more uniformly the silicon oxide film (not shown) of a CVD method, a uniform, for example, 100nm film thickness And formed in conformity with the base shape. Further, the square region including the cathode 21C having a side of 5 μm and the device regions 21NMOS and 21PMOS are protected by a resist film (not shown), and the silicon oxide film is removed from the substrate 21. After further removing the resist film, said by remaining silicon oxide film is etched back, the sidewall insulating films 22SW _B surrounds the gate electrode 21G _B in the device region 21NMOS is said in the device region 21PMOS surrounds the gate electrode 21G _C sidewall insulating films 22SW _C is formed and said in the cathode 21C, the central sidewall insulation inclined toward the membrane of the cathode region 21C the cathode 21C from the edge of the device isolation region 21I surrounding 21SW _A is formed. The sidewall insulating film 21SW _A acts to separate a silicide or high concentration region formed in a later step on the cathode from the edge of the element isolation region 21I.

Further FIG. 18 (A), the in the step of (B), under the acceleration voltage of the contact area 21B _C and the element region 21PMOS the resist pattern while protected (no shown) ^{P +} example 15 keV, 2.0 × Ions are implanted at a dose of 10 ¹⁵ cm ⁻² . Further, in the substrate region 20A, an n ⁺ type high concentration region 21C _C is formed so as to overlap the n type high concentration region 21C ⁺ previously formed in the cathode 21C, and in the substrate region 20B, the substrate region 20B is formed first. Deeper n ⁺ -type source regions 21e and 21f are formed so as to partially overlap with the n-type source extension region 21a and the drain extension region 21b.

18A and 18B, the cathode 21C and the element region 21NMOS of the n-channel MOS transistor are covered with a resist pattern, and B ⁺ is applied to the element region 21PMOS under an acceleration voltage of, for example, 5 keV. a dose of .0 × 10 ¹⁵ cm ^-2, also under the acceleration voltage of 8keV iron ^{(F +),} ion-implanted at a dose of 4.0 × 10 ¹⁴ cm ^-2, in the contact region 21B _C is As a result of further deeper ion implantation of B + having a higher concentration superimposed on the previously formed low-resistance region 21B ⁺ , the n-type diffusion region 21C in the contact region 21BC is converted to p-type, and p + -type low resistance contact region 21B _C is formed. At the same time, in the element region 21PMOS, a p + type source region 21g and a drain region 21h are formed so as to partially overlap with the previously formed p type source extension region 21c and drain extension region 21d. Here since the contact area 21C _C is formed with the sidewall insulation films 21SW _A as a mask, the contact region 21C _C whereas around the device isolation structure 21I, corresponding to the thickness of the sidewall insulation films 21SW _A They are separated by a distance.

  Further, a heat treatment is performed at 1000 ° C. for 10 seconds in a nitrogen atmosphere to activate each impurity element implanted.

19A and 19B, the silicide layers 21C _S , 21B _S , and 21A _S are formed corresponding to the contact regions 21C _C , 21B _C, and 21A _C , respectively, and the source region 21e and the drain region are formed. 21f, the source region 21g and the drain region 12h, further gate electrode _21G B, respectively silicide layer 21S also on 21G _C is formed.

  Reference is now made to the cross-sectional view of FIG. 20 and the plan view of FIG. Here, the cross-sectional view of FIG. 20 shows a cross section along line LL ′ in the plan view of FIG. 21. In the plan view of FIG. 21 and the following similar plan views, various silicide layers formed on the silicon substrate 21 are not shown for simplicity.

20 and 21, an interlayer insulating film 22 is formed on the structure shown in FIGS. 19A and 19B. In the interlayer insulating film 22, the contact region 21C _{C of} the cathode 21C and the anode are respectively formed. contact region 21B of 21B _C and the contact region 21A _C shielding layer 21A, further the source region 21e and the drain region 21f, the contact area of the well 21PW _C, and the source region 21g and the drain region 21h, a further contact region 21NW _C wells Corresponding via plugs 22V _C , 22V _B , 22V _A , 22VB _A , 22VB _B , 22VC _A , 22VC _B , and 22VC _C are formed and contacted via corresponding silicide layers. However, FIG. 23 is a sectional view taken along line LL ′ in the plan view of FIG.

Via plug 22V _B As can be seen from the plan view of FIG. 21 are formed a large number along the contact area 21B _C of substantially U-shaped in plan view, similarly via plug 22V _A even number along the contact region 21A _C Is formed. Also it illustrates a single plug 22V _C for simplicity in cross-sectional view of FIG. 20, and four of the via plug 22V _C is formed in the cathode contact region 21C _C As can be seen from the plan view of FIG. 21 Yes.

Similar multiple via plugs _{22V BA} are formed on the source region 21e, a plurality of via plugs 22VB _B is formed in the drain region 21f, s drain region 22V _h more via plugs _{22V CA} is formed in the source region 21g Via plug 22V _CB is formed.

  Reference is now made to the cross-sectional view of FIG. 22 and the plan view of FIG. Here, the sectional view of FIG. 22 shows a section taken along line LL ′ in the plan view of FIG. 23. In the plan view of FIG. 23, various silicide layers formed on the silicon substrate 21 are not shown for simplicity.

Referring to FIG. 22, the first layer (M1) wiring patterns 23A, 23B, and 23C are formed on the interlayer insulating film 22 corresponding to the high breakdown voltage diode 20, and the wiring pattern 23A is by connecting the plurality of the via plug 22V _a, extends so as to surround the diffusion region 21B in plan view. The wiring pattern 23B is also tied to the number of the via plug 22V _B, and extends in a substantially U-shaped configuration so as to surround the diffusion region 21C in a plan view. The wiring patterns 23A and 23B further extend in parallel with each other, the wiring pattern 23A is grounded, and a predetermined anode voltage is applied to the wiring pattern 23B. The via plug 22V _C is connected to the connection pad 23V _C.

  Further, a conductive pattern 23G branches off from the substantially U-shaped wiring pattern 23B, and the conductive pattern 23G surrounds the connection pad 23C together with the U-shaped portion of the wiring pattern 23B. Form a pattern. Since the conductive pattern 23G is branched from the wiring pattern 23B, the anode voltage applied to the wiring pattern 23B is also applied to the conductive pattern 23G.

On the other hand, in the element region 21NMOS, wiring patterns 23V _BA , 23V _BB and 23V _BC are formed as wiring patterns of the wiring layer M1 corresponding to the via plugs 22V _BA , 22V _BB and 22V _BC , respectively. In the element region 21PMOS, wiring patterns 23V _CA , 23V _CB and 23V _CC are formed as wiring patterns of the wiring layer M1 corresponding to the via plugs 22V _CA , 22V _CB and 22V _CC , respectively. Furthermore said gate electrode 21G _B and 23G on _C wiring pattern 23G _B and 23G _C are respectively formed as a wiring pattern of the wiring layer M1, the wiring pattern 23G _B is formed in the interlayer insulating film 22 on the gate electrode 21G _B via plugs 22VG _B, also the wiring pattern 23G _C via a plug 22VG _C formed in the interlayer insulating film 22 on the gate electrode 21G _C, are connected.

  Reference is now made to the cross-sectional view of FIG. 24 and the plan view of FIG. Here, FIG. 24 is a plan view similar to FIG. 22, and FIG. 24 shows a cross section along line LL ′ in the plan view of FIG. In the plan view of FIG. 25, various silicide layers formed on the silicon substrate 21 are omitted, while the wiring pattern of the lower wiring layer M1 is shown together with the wiring pattern of the upper wiring layer M2. Yes.

24 and 25, on the interlayer insulating film 22, the wiring patterns 23A to 23C, the conductive pattern 23G, and the wiring patterns 23 _BA , 23 _BB , 23 _BC , 23 _GB , 23 _CA , 23 _CB , 23 _The next interlayer insulating film 23 is formed covering the _CC and 23 _GC , and a wiring pattern 24A is formed on the interlayer insulating film 23 in contact with the connection pad 23C through a via plug 23V.

  In the illustrated example, the wiring pattern 24A extends across the conductive pattern 23G in parallel with the extending direction of the wiring patterns 23A and 23B.

  A high voltage including a surge voltage is applied to the wiring pattern 24A, but the conductive pattern 23G is interposed between the wiring pattern 24A and the anode 21B, and an electric field due to the high voltage on the wiring pattern 24A. Shield. For this reason, as described above, the formation of the inversion layer in the portion of the anode 21B immediately below the conductive pattern 23G is suppressed, and the high breakdown voltage diode 20 does not leak during normal operation. As described above, the conductive pattern 23G forms a diode-connected parasitic MOS transistor together with the inversion layer formed on the anode 21B, and is conductive when a voltage surge occurs in the wiring pattern 24A. Thus, a discharge current path is formed, and destruction of the pn junction between the anode 21B and the cathode 21C due to application of an excessive voltage is prevented.

[Second Embodiment]
26A (hereinafter referred to as FIG. 26A) is a cross-sectional view showing a configuration of the semiconductor device 40 according to the second embodiment, and FIG. 26B (hereinafter referred to as FIG. 26B). Is a plan view corresponding to the cross-sectional view of FIG. The cross-sectional view of FIG. 26A shows a cross-section along line 2-2 ′ in the plan view of FIG. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.

  Referring to FIGS. 26A and 26B, the semiconductor device 40 is a high breakdown voltage diode as in the previous embodiment, and an n-type first diffusion region serving as a shielding region similar to the previous embodiment. 21A, a p-type second diffusion region 21B serving as an anode formed so as to be included in the first diffusion region 21A in plan view, and so as to be included in the second diffusion region 21B in plan view. And an n-type third diffusion region 21 </ b> C serving as a cathode.

Wherein the first diffusion region 21A contact region 21A _C of the ^{n +} -type so as to surround the second diffusion region 21B is formed, the contact region 21A _C is defined by the device isolation region 21I of the STI type. Wherein the contact region 21A _C silicide layer 21A _S is formed, a number of via plugs 22V _A in said first interlayer insulating film 22 is connected through the silicide layer 21A _S on the contact region 21A _C ing. Ground wiring pattern 23A is formed on the interlayer insulating film 22, the along the shape of the contact region 21A _C extends so as to surround the diffusion region 21B, the contact region 21A by the via plug 22V _A and the silicide layer 21A _S Electrically connected to _C.

Also the the second diffusion region 21B and the third diffusion region 21C, i.e. p + -type contact region 21B _C so as to surround the substantially U-shaped cathode of the high-voltage diode 40 is formed, the contact area 21B _C Is also defined by the STI type element isolation region 21I. Connecting said on the contact area 21B _C silicide layer 21B _S is formed, the the contact area 21B _C number of plugs 22B _A in the first-layer interlayer insulating film 22, through the silicide layer 21B _S Has been. Further on the interlayer insulating film 22 is the anode wiring pattern 23B is formed comprising a substantially U-shaped portion which surrounds the diffusion region 21B of the contact area 21B _C along the eggplant substantially U-shaped configuration at the tip portion, the anode wiring pattern 23B is electrically connected to the contact region 21B _C by the via plug 22V _B and the silicide layer 21B _S in the U-shaped portion. The anode wiring pattern 23B shifts from the U-shaped tip portion to a linear portion extending in parallel with the wiring pattern 23A.

Furthermore the cathode and the third diffusion region 21C are also defined by the device isolation region 21I made, low-resistance contact region 21C _C of the n ⁺ type in the cathode are formed. Also in the contact region on the 21C _C are low-resistance silicide layer 21C _S is formed. The contact region 21C _C in plug 22V _C in the interlayer insulating film 22, are electrically connected through the silicide layer 21C _S.

Said on the first layer interlayer insulating film 22 is formed in contact with the respective ground wiring pattern 23A and the anode wiring pattern 23B via plug 22V _A and 22V _B, wherein the diffusion region 21A is the ground voltage GND In addition, an anode voltage is supplied to each diffusion region 21B. Alternatively, as in the example of the later embodiment, the diffusion region 21A may be short-circuited to the diffusion region 21B by the wiring pattern 23A and the wiring pattern 23B.

In the present embodiment, a high voltage wiring pattern 23H to which a high voltage possibly including a surge is applied is further provided on the first interlayer insulating film 22, and one end of the high voltage wiring pattern 23H is connected to the via plug. It is electrically connected to the third diffusion region 21C by 21V _C , and further extends on the interlayer insulating film 22 in parallel with the wiring patterns 23A and 23B in the illustrated example. At this time, the high-voltage wiring pattern 23H becomes a second diffusion region 21B serving as an anode and a shielding region outward from the third diffusion region 21C positioned substantially at the center of the high-voltage diode 40 in plan view. It extends across the third diffusion region 21C.

Since the high-voltage wiring pattern 23H passes near the surface of the second diffusion region 21B serving as an anode, an inversion layer is formed on the surface of the second diffusion region 21B by the electric field accompanying the high voltage. There is a possibility. Therefore, in this embodiment, a polysilicon pattern 22G similar to the polysilicon gate electrode of another semiconductor element formed on the silicon substrate 21 is formed on the element isolation region 21I on the diffusion region 21B. formed to it passes through the bottom of the wiring pattern 23H, at least one end of the polysilicon pattern 22G, preferably both ends, by via plugs 22G _C and 22G _D, is electrically connected to the wiring pattern 23B is the anode wiring pattern.

  The polysilicon pattern 22G is highly doped and has conductivity, and acts as a shielding pattern for the high voltage wiring pattern 23H. That is, according to this configuration, as in the previous embodiment, the conductive polysilicon pattern 22G in which the electric field generated by the high-voltage wiring pattern 23H is maintained at the anode voltage level on the surface of the second diffusion region 21B. Therefore, the formation of the inversion region that may be formed along the high-voltage wiring pattern 23H is suppressed.

  In the present embodiment, since the shielding pattern 22G is formed directly on the element isolation region 21I, the high-voltage wiring pattern 23H can be formed in the first wiring layer M1, and the operational effects of the previous embodiment. In addition, it is possible to obtain exceptional effects that increase the degree of freedom in semiconductor design.

  Hereinafter, the manufacturing process of the semiconductor device including the high voltage diode 40 of FIG. 26 will be described with reference to FIGS. In the figure, the same reference numerals are given to the parts described above, and the description thereof will be omitted.

FIGS. 27A and 27B are steps that are executed subsequent to the steps of FIGS. 10A and 10B in the previous embodiment. The exposed surface of the silicon substrate 21 has a film thickness, for example, by thermal oxidation. after the formation of the protective oxide film 21POxx of 15 nm, on the silicon substrate 21, the forming a resist pattern _{R 11} having the resist opening _{R 11} a to expose the annular region including the contact region 21BC, B +, for example 230keV of Ions are implanted at a dose of 3.0 × 10 ¹³ cm ⁻² under an accelerating voltage, and the contact region 21BC is doped p-type.

Further the resist pattern to _{R 11} are resist opening R11B exposing formation between the substrate region 20A and the substrate region 20B, the contact region 21BC doped simultaneously with the resist opening the isolation region in R11B 21I A p-type channel cut region 21ChC is formed immediately below the region.

  Thereafter, by performing the same steps as those shown in FIGS. 11A, 11B, 12A, and 12B, the substrate region 20B is p-typed as shown in FIGS. A type well 21PW is formed, and an n-type well 21NW is formed in the substrate region 20C.

Further, in the steps of FIGS. 29A and 29B, the protective insulating film 21POxx is removed from the structure of FIGS. 28A and 28B, and the exposed silicon surface is thermally oxidized, whereby the gate insulating film 21Gox. Is formed to a thickness of 2 nm, for example. Further, a polysilicon film 21Poly is deposited to a thickness of, for example, 200 nm on the structure on which the gate insulating film 21Gox is formed, and this is further patterned to form the substrate region 20B as shown in FIGS. 30 (A) and 30 (B). a polysilicon gate electrode 21G _B across the element regions 21NMOS in, also the polysilicon gate electrode 21G _C across the device region 21PMOS in the substrate region 20C, are formed respectively. At this time, in this embodiment, as shown in FIGS. 30A and 30B, another polysilicon pattern 22G is formed above the second diffusion region 21B serving as an anode on the element isolation region 21I. Form. In the illustrated example, the polysilicon pattern 22G is disposed to close the mouth 21B _CO an open contact region 21BC in a substantially U-shape surrounding the third diffusion region 21C as the cathode, the contact region 21B _C and the polysilicon pattern 22G are configured to surround the third diffusion region 21C as a whole. At this time, in this embodiment, the depth d on the plan view of the U-shaped contact region 21BC is set so that the polysilicon pattern 22G can be formed on the second diffusion region 21B. Compared to

Further, in the steps of FIGS. 31A and 31B, the n channel formed in the third diffusion region 21C, the contact region 21A _C , and the substrate region 20B on the structure of FIGS. 30A and 30B. A resist pattern R ₁₂ having resist openings R ₁₂ A, R ₁₂ B, R ₁₂ C, and R ₁₂ D exposing the element region 21 NMOS of the MOS transistor and the well contact region 21 NWC formed in the substrate region 20 _C , respectively. formed, the resist pattern _{R 12} and the gate electrode 21G the mask of P + a _B Figure 15 (a), by ion implantation under the same conditions (B), and said third low-resistance region in the diffusion region 21C of 21C + is, the low-resistance region 21A + is in the contact region 21A _C in the first diffusion region 21A, the element In pass 21NMOS n-type source extension region 21a and a drain extension region 21b is further in the substrate region 20C has the low-resistance region 21NW _C + to the well contact regions 21NW _C, are formed, respectively.

Next, in the steps of FIGS. 32A and 32B, the contact region 21B _{C of} the second diffusion region 21B and the substrate region 20B are formed on the structure of FIGS. 31A and 31B. Resist pattern having resist openings R ₁₃ A, R ₁₃ B, and R ₁₃ C exposing the well contact region 21PW _C of the p-type well 21PW and the device region 21PMOS of the p-channel MOS transistor formed in the substrate region 20C, respectively. forming a R _13, FIG 16, the resist pattern _{R 13} and the gate electrode 21G _C to mask (a), by ion implantation of B + under the same conditions (B), and the resistance in the contact region 21B _C further reduced to form a low resistance region 21PW _C + in the well contact region 21PW _C, the p tea Respectively forming a p-type source extension region 21c and a drain extension region 21d in the element region 21PMOS Le MOS transistor.

Next, FIG. 33 (A), (B) the polysilicon pattern 22G and the gate electrode _21G B in the process of the Figure 17 to _{21G C (A), (B} ) a sidewall insulating each film by the same process as 22SW _A, 22SW _B and 22SW _C are formed. At this time, a sidewall insulating film 21SW _A is also formed around the third diffusion region 21C serving as a cathode so as to expose the low resistance region 21C + corresponding to the step portion of the interlayer insulating film 21I. .

Further, in the steps of FIGS. 34 (A) and (B), the same process as in the steps of FIGS. 18 (A) and (B) is executed, so that the sidewall insulating film 21SW _A is formed in the diffusion region 21C. low-resistance region of the n ⁺ -type surrounded by region is formed as a contact region 21C _C, the low-resistance region of the p ⁺ -type contact region 21B _C in the diffusion region 21B is formed. The low-resistance region of the ^{n +} -type contact region 21A _C in the diffusion region 21A is formed.

Further elements outside the region 21NMOS in the sidewall insulation films 22SW _B of the ^{n +} -type source region 21e and the drain region 21f, further _{p +} -type well contact region 21PW _C is formed. Furthermore the element region 21PMOS the sidewall insulating films 22SW of ^{p +} -type on the outside of the _C source region 21g and the drain region 21h is also ^{n +} -type well contact region 21NW _C is formed.

Figure 34 (A), in the step of (B), when the contact region _21C C, P + ion implantation into the source region 21e and the drain region 21f of 21A _C and n-channel MOS transistor, the polysilicon pattern 22G and the gate polysilicon pattern constituting the electrode 21G _B are imparted conductivity is n ⁺ doped. Further, FIG. 34 (A), when the source region 21g of the contact region 21BC and p-channel MOS transistor, B + ion implantation into the drain region 21h is in the step of (B), the polysilicon pattern constituting the gate electrode 21G _C Is doped into p ⁺ type to impart conductivity.

  It is also possible to dope the polysilicon pattern 22G into the p + type by performing the doping at the time of forming the source and drain regions of the p-channel MOS transistor.

Next, in the steps of FIGS. 35A and 35B, silicide layers 21AS, 21BS, and 21CS are formed in the contact regions 21AC, 21BC, and 21CC, respectively, by the salicide method. the polysilicon pattern 22, the source region 21e, a gate electrode 21G _B, the drain region 21f, the source region 21g, on the surface of the gate electrode 21G _C and a drain region 21h, is formed a silicide layer 21S. However, the silicide layer 21S is not shown in the plan view of FIG. 35B for simplicity.

  Reference is now made to the cross-sectional view of FIG. 36 and the plan view of FIG. Here, the cross-sectional view of FIG. 36 is a cross-sectional view taken along line LL ′ in the plan view of FIG. 37.

Referring to FIG. 36 and 37, an interlayer insulating film 22 on the silicon substrate 21, the polysilicon pattern 22G, a gate electrode 21G _B, is formed so as to cover the gate electrode 21G _C, in the interlayer insulation film 22 the contact region _{21A C,} 21B _C, 21C C in contact with the via plug _{22V a, 22V B,} the 22V _C, also the source region 21e, the drain region 21f, well contact region 21PW _C, the source region 21g, a drain region 21h and and contact each of the well contact region 21NW _C, to form the via plug _{22V BA, 22V BB, 22V BC} , 22V CA, 22V CB, the _{22V CC.} Although not shown in the sectional view of FIG. 36, both ends to form a via plug 22G _C and 22G _D of the polysilicon pattern 22 as shown in the plan view of FIG. 37, further gate electrode pattern _21G B, via plugs to 21G _C 22V _GB and 22V _GC are formed, respectively.

  Reference is now made to the cross-sectional view of FIG. 38 and the plan view of FIG. Here, the cross-sectional view of FIG. 38 is a cross-sectional view taken along line LL ′ in the plan view of FIG. 39.

38 and 39, on the interlayer insulating film 22, the wiring patterns 23A, 23B, and 23H of FIG. 26 and the wiring patterns 23 _BA , 23 _BB , 23 _BC , 23 _{GB of} the n-channel MOS transistor, is further formed a wiring pattern _{23 CA, 23 CB, 23 CC} , 23 GC of p-channel MOS transistors, the wiring pattern 23A is formed along the contact region 21A _C so as to surround the second diffusion region 21B U includes shaped portion, said U-shaped portion is connected to the contact region 21A _C by the via plug 22V _a. On the other hand, as shown in the plan view of FIG. 39, the wiring pattern 23B has a smaller U-shaped portion surrounding the third diffusion region 21C at the tip, and the polysilicon pattern 22G is formed by the wiring pattern 23B. The U-shaped open portion is closed, that is, the diffusion region 21C is completely surrounded by the U-shaped portion and the polysilicon pattern 22G in a plan view, and the wiring is formed by the via plugs 22V _GB and 22V _GC. It is electrically connected to the pattern 23B. Also the wiring pattern 23H extends in a linear shape as shown in plan view in FIG. 39, the third diffusion region 21C, contact with the via plug 22V _C in the contact region 21C _C. In the illustrated example, the wiring patterns 23A and 23B have straight portions connected to the respective U-shaped portions, and each straight portion extends in parallel on both sides of the wiring pattern 23H.

The wiring patterns _{23V BA} corresponding to the source region 21e of the n-channel MOS transistor in the substrate region 22B is formed, the wiring pattern _{23V BA} is electrically connected to the source region 21e by the via plug _{22V BA} . Also, the wiring pattern _{23V BB} corresponding to the drain region 21f of the n-channel MOS transistor is formed, the wiring pattern _{23V BB} are electrically connected to the drain region 21f by the via plug _{22V BB.}

Similarly the in substrate region 22C wherein corresponding to the source region 21g of the p-channel MOS transistor wiring patterns _{23V CA} is formed, the wiring pattern _{23V CA} is electrically connected to the source region 21g by the via plug _{22V CA} The Also, the wiring pattern _{23V CB} corresponding to the drain region 21h of the n-channel MOS transistor is formed, the wiring pattern _{23V CB} is electrically connected to the drain region 21h by the via plug _{22V CB.}

Further the gate electrode 21G _B is connected to the wiring pattern 23G _B by plugs _{22V GB,} the gate electrode 21G _C is connected to the wiring pattern 23G _C by a via plug _{22V GC.} Also, the well contact region 21PW _C is connected to the wiring pattern _{23V BC} by plugs _{22V BC,} well contact region 21NW _C is connected to the wiring pattern _{23V CC} by plugs _{22V CC.}

  According to this configuration, since the polysilicon pattern 22G is held at the same potential as the anode wiring pattern 22B, even if a high voltage including a surge voltage is applied to the wiring pattern 23H, the high voltage on the wiring pattern 23H The electric field is shielded, and the formation of the inversion layer in the portion of the anode 23B immediately below the conductive pattern 23G is suppressed. For this reason, the high breakdown voltage diode 40 does not leak in normal operation. Further, as described above, the shielding pattern 22G forms a diode-connected parasitic MOS transistor together with the inversion layer formed on the anode 21B, and becomes conductive when a voltage surge occurs in the wiring pattern 23H. Thus, a discharge current path is formed, and destruction of the pn junction between the anode 21B and the cathode 21C due to application of an excessive voltage is prevented.

[Third Embodiment]
FIG. 40 is a circuit diagram showing an example of a drive circuit using the high voltage diode according to the first or second embodiment as the third embodiment.

  When used in this example, the diffusion region 21A and the diffusion region 21B are short-circuited in the high voltage diode in the previous embodiment.

  Referring to FIG. 40, a dotted line region represents a part constituting the semiconductor integrated circuit 51, and external switching FETs 52 and 53 for driving a motor 54 are connected to the semiconductor integrated circuit 51. As shown in FIG. 40, a semiconductor integrated circuit 51A having the same configuration as that of the semiconductor integrated circuit 51 is connected to the motor 54, and the motor 54 is driven by the semiconductor integrated circuit 51 and the semiconductor integrated circuit 51A. In the following description, the description of the semiconductor integrated circuit 51A is omitted.

  The semiconductor integrated circuit 51 is supplied with a power supply voltage of 5V for driving the logic circuit and a power supply voltage of 12V for high voltage, and the external switching FETs 52 and 53 are provided with a motor 54 and the like. A power supply voltage HV of 40V for driving is supplied.

  The semiconductor integrated circuit 51 includes a logic circuit 61 driven by a power supply voltage of 5V, a first low voltage level shifter 62 supplied with an output of the logic circuit 61, and an output of the first low voltage level shifter 62. The low-side drive circuit 64 outputs a drive voltage for driving the low-side switching FET 53 to the terminal LD.

  The semiconductor integrated circuit 51 includes a second low voltage level shifter 65 to which the output of the logic circuit is supplied, a high voltage level shifter 66 to which the output of the second low voltage level shifter 65 is supplied, and the high voltage level shifter. A high side driving circuit 67 supplied with 66 outputs is included.

  The semiconductor integrated circuit 51 further includes a power protection circuit 71 to which a power supply voltage of 12V is supplied. The power supply voltage of 12V is stored in the capacitor 73 via the diode 72 formed of the high voltage diode 20 or 40 of the previous embodiment, The high side driving circuit 67 is supplied with a high voltage generated at the node (2) by the capacitor 73 and outputs a driving voltage for driving the high side switching FET 52 to the terminal HD. Here, the high breakdown voltage diode 72 is used as a bootstrap diode for opening the gate of the external FET 52 connected to the HD terminal on the high side. That is, in order to completely turn on the FET 52 on the high side, the voltage at the terminal HD needs to output a voltage higher than the power supply voltage of 40 V supplied to the HV terminal. Used to generate a high voltage for this.

  In principle, when the external FET 53 on the low side is turned on, a forward current flows through the high breakdown voltage diode 72 and the charge of the capacitor 73 between the nodes (1) and (2) is accumulated. For example, the node (1 ) Is 12V-0.7V = 11.3V. However, this 0.7 V corresponds to a forward voltage drop in the diode 72.

  Next, when the high-side FET 52 is operated, the low-side external FET 53 is turned off and the high-side external FET 52 is turned on. Therefore, the voltage Vs of the intermediate node N between the FETs 52 and 53 and the node (1) Is finally raised to 40V.

  At that time, the voltage of the terminal HD is the sum of the voltage of 40V at the node (1) and the voltage of 11.3V due to the charge stored in the capacitor 73, and the voltage at the node (1) is about 40V + 11.3V = A voltage of 51.3V appears. That is, even when the voltage on the source side of the FET 52 is 40 V, the gate voltage is kept higher by the voltage at the terminal HD, and the high-side FET 52 can continue to be driven.

  At this time, a voltage of 51.3V-12V = 39.3V is applied to the diode 72 between the nodes (2) and (3). However, since the reverse breakdown voltage of the diode 72 is 42V or more, The voltage at the terminal HD can be maintained.

  However, when a voltage such as a surge is generated due to some trouble in the power supply that supplies the high voltage HV when the motor is driven, and a voltage of 55 V or more is instantaneously applied between the nodes (2) and (3), In a normal high voltage diode, the junction is destroyed, so the HV voltage flows to the 12V power supply all at once.

  As a result, even if the protection circuit 71 is provided on the 12V power supply side, the destruction of the diode caused by such a cause is not a temporary phenomenon, and thus there is a possibility that a large damage is caused on the 12V power supply side. . Further, the FET drive circuit does not operate because the diode 72 is destroyed.

  On the other hand, when the high-breakdown-voltage diode 20 or 40 described in the previous embodiment is used as the diode 72, since the protective element that operates, for example, 47V is built in the element, the surge voltage is increased on the HV power supply side. Even if it occurs, the destruction of the diode junction can be prevented.

  Even if the surge voltage is temporarily supplied to the 12V power supply side, the surge is a transient phenomenon, so the 12V power supply is protected by the protection circuit 71 and does not suffer a fatal damage. .

  In addition, since the diode 72 is not destroyed, the drive circuit can operate normally after the abnormal surge is converged.

[Fourth Embodiment]
41A and 41B are a cross-sectional view and a plan view showing a high voltage diode according to the fourth embodiment. Here, the cross-sectional view of FIG. 41A shows a cross section taken along line 1-1 ′ in the plan view of FIG. 41B. The high voltage diode of the present embodiment is a modification of the high voltage diode 20 of FIG. In the figure, the same reference numerals are given to the parts described above, and the description thereof is omitted.

  Referring to FIG. 41, in this embodiment, the element isolation region 21I in the configuration of FIG. 1 is omitted, and the interlayer insulating film 22 is formed directly on the silicon substrate 21.

Such a configuration can be formed, for example, by forming the diffusion regions 21A, 21B, and 21C and the low resistance regions 21A _C , 21B _C , and 21C _C using the respective ion implantation masks. . The silicide layers 21A _S , 21B _S , and 21C _S can be formed using, for example, a silicon oxide film mask.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
A semiconductor substrate;
A first diffusion region of a first conductivity type formed in the semiconductor substrate;
A second diffusion region of a second conductivity type formed in the first diffusion region and having a conductivity type opposite to that of the first conductivity type;
A third diffusion region of the first conductivity type formed in the second diffusion region;
A first wiring pattern formed on the semiconductor substrate and connected to the second diffusion region by being supplied with a first voltage;
A second wiring pattern formed on the semiconductor substrate and supplied with a second voltage higher than the first voltage;
Including
The second and third diffusion regions form a diode with a pn junction,

A semiconductor having a conductive pattern that crosses the second wiring pattern in plan view and that is supplied with the first voltage is provided between the second diffusion region and the second wiring pattern. apparatus.
(Appendix 2)
2. The semiconductor device according to claim 1, further comprising an element isolation region defining the third diffusion region on the semiconductor substrate, wherein the conductive pattern is formed on the element isolation region.
(Appendix 3)
The semiconductor device according to claim 2, wherein the first and second wiring patterns are formed on an interlayer insulating film formed on the semiconductor substrate.
(Appendix 4)
4. The semiconductor device according to appendix 2 or 3, wherein the conductive pattern is a polysilicon pattern formed on the element isolation region.
(Appendix 5)
The first wiring pattern is formed on a first interlayer insulating film formed on the semiconductor substrate, and the second wiring pattern is formed on the first interlayer insulating film. 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed on a second interlayer insulating film formed to cover the pattern, and the conductive pattern is formed on the first interlayer insulating film.
(Appendix 6)
Supplementary notes 1 to 3 including a third wiring pattern connected to the first diffusion region and provided on the first interlayer insulating film and below the second interlayer insulating film. 5. The semiconductor device according to claim 1.
(Appendix 7)
The semiconductor device according to appendix 6, wherein the third wiring pattern is connected to a third voltage source that is lower than the second voltage.
(Appendix 8)
The semiconductor device according to appendix 6, wherein the third wiring pattern is short-circuited with the first wiring pattern and supplied with the first voltage.
(Appendix 9)
8. The semiconductor device according to appendix 6 or 7, wherein the third wiring pattern is grounded.
(Appendix 10)
10. The semiconductor device according to claim 1, wherein the first diffusion region has an impurity concentration lower than that of the third diffusion region.
(Appendix 11)
11. The semiconductor device according to claim 1, further comprising a transistor that operates on a second voltage lower than the first voltage on the semiconductor substrate.
(Appendix 12)
Forming a first conductivity type first diffusion region on a semiconductor substrate;
Forming a second diffusion region to be included in the first diffusion region;
Forming a third diffusion region of the first conductivity type so as to be included in the second diffusion region, and forming a pn junction constituting a diode by the second diffusion region and the third diffusion region; When,
Forming a first wiring pattern in the second diffusion region;
Forming a second wiring pattern in the third diffusion region;
Providing a conductive pattern that intersects the second wiring pattern in plan view and is supplied with the first voltage between the second diffusion region and the second wiring pattern;
A method for manufacturing a semiconductor device, comprising:
(Appendix 13)
The step of forming the third diffusion region includes the step of forming a third diffusion region over the entire surface of the second diffusion region in a plan view above the second diffusion region, Forming a device isolation region deeper than the third diffusion region in the third diffusion region, and leaving the third diffusion region so as to be included in the second diffusion region in plan view. 14. A method of manufacturing a semiconductor device according to appendix 12.
(Appendix 14)
The step of forming the conductive pattern includes a step of forming a polysilicon film in the element isolation region and a step of patterning the polysilicon film, and the conductive pattern is formed on the element isolation region. A method for manufacturing a semiconductor device according to appendix 13.
(Appendix 15)
After the step of forming the conductive pattern, the method includes a step of forming an interlayer insulating film on the semiconductor substrate so as to cover the element isolation region and the conductive pattern, and the first and second wiring patterns include the interlayer insulation 15. The method of manufacturing a semiconductor device according to appendix 14, wherein the method is formed on a film.
(Appendix 16)
And a step of sequentially forming a first interlayer insulating film and a second interlayer insulating film on the semiconductor substrate, wherein the first wiring pattern and the conductive pattern are formed on the first interlayer insulating film, 13. The method of manufacturing a semiconductor device according to appendix 12, wherein the second conductive pattern is formed on the second interlayer insulating film.

20, 40 High voltage diodes 20A, 20B, 20C Substrate region 21 Silicon substrate 21A First diffusion region 21B Second diffusion region 21C Third diffusion region 21A _C , 21B _C , 21C _C Low resistance contact region 21A _S , 21B _{S, 21C S,} 21S silicide layer 21A +, 21B + 21C +, 21NWC +, 21NWC ++, 21PWC +, 21PWC ++ low-resistance region 21ChC channel cut region _21G B, 21G _C gate electrode 21Gox gate oxide film 21I isolation region 21Ox, 21POx, 21POxx protective oxide film 21PMOS , 21 NMOS device region 21PW p-type well 21NW n-type well 21PW _C , 21NW _C well contact 21a, 21c source extension region 21b, 21d drain extension Region 21e, 21g source region 21f, 21h drain region 22, 23, 24 interlayer insulating film 22G, 23G conductive pattern 21SW _A , 22SW _A , 22SW _B , 22SW _C sidewall insulating film 22V _A , 22V _B , 22V _C , 22V _{BA , 22V BB, 22V BC, 22V} CA, 22V CB, 22V CC, 22V GB, 22V GC, 24V A via plugs _{23A, 23B, 23H, 23G B} , 23G C, 24A wiring pattern _R 1 _{~R 5, R} 11 _{~R 13} resist patterns

Claims (8)

A semiconductor substrate;
A first diffusion region of a first conductivity type formed in the semiconductor substrate;
A second diffusion region of a second conductivity type formed in the first diffusion region and having a conductivity type opposite to that of the first conductivity type;
A third diffusion region of the first conductivity type formed in the second diffusion region;
A first wiring pattern formed on the semiconductor substrate and connected to the second diffusion region by being supplied with a first voltage;
Said formed on a semiconductor substrate, said first voltage said supplied with a second voltage higher than the third diffusion region connected to Ru second wiring pattern,
Including
The second and third diffusion regions form a diode with a pn junction,
A semiconductor having a conductive pattern that crosses the second wiring pattern in plan view and that is supplied with the first voltage is provided between the second diffusion region and the second wiring pattern. apparatus.   The semiconductor device according to claim 1, further comprising an element isolation region defining the third diffusion region on the semiconductor substrate, wherein the conductive pattern is formed on the element isolation region.   3. The semiconductor device according to claim 2, wherein the first and second wiring patterns are formed on an interlayer insulating film formed on the semiconductor substrate.   4. The semiconductor device according to claim 2, wherein the conductive pattern is a polysilicon pattern formed on the element isolation region. The first wiring pattern, the is formed on the first interlayer insulating film formed on a semiconductor substrate, said second wiring pattern, the first on the first interlayer insulating film 2. The semiconductor device according to claim 1, wherein the semiconductor device is formed on a second interlayer insulating film formed so as to cover the wiring pattern, and the conductive pattern is formed on the first interlayer insulating film. . 6. The semiconductor device according to claim 5 , further comprising a third wiring pattern connected to the first diffusion region and provided on the first interlayer insulating film and below the second interlayer insulating film. serial mounting semiconductor device.   The semiconductor device according to claim 6, wherein the third wiring pattern is connected to a third voltage source lower than the second voltage. Forming a first conductivity type first diffusion region on a semiconductor substrate;
Forming a second diffusion region to be included in the first diffusion region;
Forming a third diffusion region of the first conductivity type so as to be included in the second diffusion region, and forming a pn junction constituting a diode by the second diffusion region and the third diffusion region; When,
Forming a first wiring pattern so as to contact the second diffusion region;
Forming a second wiring pattern so as to contact the third diffusion region;
Between the said second diffusion region a second wiring pattern intersect with the second wiring pattern in plan view, the steps of the first voltage provided conductive patterns supplied,
A method for manufacturing a semiconductor device, comprising: