JP6054856B2 - Method for forming insulating region - Google Patents

Description

  The present invention relates to a method for forming an insulating region.

  Various semiconductor elements are formed on the surface of the semiconductor substrate, and regions for insulating the elements are formed. As a method for forming an insulating region, for example, Patent Document 1 discloses a shallow trench isolation process. In the shallow trench isolation process, a composition including an insulating material is applied to a substrate having a trench formed on the surface. Next, an insulating layer is formed on the surface of the substrate by baking the insulating material. Next, excess insulator is removed by polishing and wet etching, and an insulating region is formed for each trench.

JP2011-9985A

  In the above method, the height of the insulating region may vary depending on the formation position. When this variation becomes large, the height of the insulating region may be partially insufficient.

  In view of the above, an object of the present invention is to provide a method capable of suppressing variations in the height of the insulating region depending on the formation position when the insulating region is formed for each recess on the surface of the substrate.

  As a result of detailed investigation and research on the phenomenon in which the height of the insulating region varies depending on the formation position, the present inventors have found a tendency that the height of the insulating region varies depending on the width of the recess. Specifically, the height of the insulating region tends to be lower in a narrow recess than in a wide recess. As this factor, it can be considered that as the width of the concave portion becomes narrower, the stress generated in the insulating material at the time of firing increases, and the resistance of the insulator to the etching solution decreases.

  Therefore, in the method for forming an insulating region according to the present invention, a silicon-based insulating material solution is applied to a substrate having a recess on the surface, the insulating material solution applied to the substrate is dried, and the insulating material solution is applied. After drying, an etching solution is supplied to the substrate to remove the excess of the insulating material, and after removing the excess of the insulating material, the insulating material remaining on the substrate is baked to insulate the silicon oxide. Forming a body in the recess.

  In this method for forming an insulating region, etching (excess removal by supplying an etching solution) is performed before baking the insulating material. For this reason, the height of the insulating material is adjusted in a state where variation in resistance to the etching solution is suppressed. Thereby, the variation in the height of the insulating material after etching is suppressed, and the variation in the height of the insulator after baking is also suppressed. Therefore, variation in the height of the insulating region according to the formation position can be suppressed.

  An insulating material containing polysilazane may be used, or an alkaline etching solution may be used. As the alkaline etching solution, any one of an aqueous ammonium hydroxide solution, an aqueous potassium hydroxide solution, and ammonia perwater may be used.

  The method may further include polishing the insulating material attached to the substrate after the solution of the insulating material applied to the substrate is dried and before supplying the etching solution to the substrate. In this case, before the etching solution is supplied, the surface of the insulating material is smoothed by polishing, whereby the variation in the height of the insulating material before firing is further suppressed. Therefore, variation in the height of the insulating region according to the formation position can be further suppressed.

  The insulating material may be removed with an etching solution so that the side edge portion of the surface of the insulating material remaining in the recess is in a depressed state as compared with the central portion. In this case, the contact area between the inner surface of the recess and the insulating material is smaller than when the side edge portion and the central portion of the surface of the insulating material have the same height. Thereby, since the force which acts on an insulating material from the inner surface of a recessed part at the time of baking is reduced, the intensity | strength of the insulating area | region after baking can be raised.

  You may further include laminating | stacking an insulator by chemical vapor deposition on the insulator formed in the recessed part. The strength of an insulator laminated by chemical vapor deposition tends to be higher than the strength of an insulator formed by firing an insulating material. On the other hand, in chemical vapor deposition, there is a tendency that it is difficult to fill the insulator on the bottom side of the recess compared to applying and baking an insulating material. By combining firing of the insulating material and chemical vapor deposition, it is possible to achieve both the filling property and strength of the insulator.

  According to the present invention, when the insulating region is formed for each concave portion on the surface of the substrate, variation in the height of the insulating region according to the formation position can be suppressed.

It is a flowchart which shows the formation procedure which concerns on 1st Embodiment. It is a schematic diagram which shows the formation process of the insulation area | region according to the formation procedure which concerns on 1st Embodiment. 1 is a perspective view showing a schematic configuration of a substrate processing system according to a first embodiment. It is sectional drawing which follows the IV-IV line in FIG. It is sectional drawing which follows the VV line in FIG. It is sectional drawing which follows the VI-VI line in FIG. It is a flowchart which shows the formation procedure which concerns on 2nd Embodiment. It is a schematic diagram which shows the formation process of the insulation area | region according to the formation procedure which concerns on 2nd Embodiment. It is sectional drawing of the coating / etching apparatus which concerns on 2nd Embodiment. It is a flowchart which shows the formation procedure which concerns on 3rd Embodiment. It is a schematic diagram which shows the formation process of the insulation area | region according to the formation procedure which concerns on 3rd Embodiment. It is a perspective view which shows schematic structure of the substrate processing system which concerns on 3rd Embodiment. It is an electron micrograph of the insulation area | region which concerns on a comparative example. It is an electron micrograph of the insulation area | region which concerns on an Example. It is an electron micrograph of the insulation area | region which concerns on an Example and a comparative example.

  Hereinafter, embodiments will be described in detail with reference to the drawings. In the description, the same elements or elements having the same functions are denoted by the same reference numerals, and redundant description is omitted.

[First Embodiment]
(Method of forming insulating region)
The insulating region forming method according to the first embodiment is a method of forming an insulating region in a trench (concave portion) Wt formed on a surface Wa of a semiconductor wafer (substrate) W. In this method, first, a wafer W having a trench Wt formed on the surface Wa is prepared, and a solution of a silicon-based insulating material is applied to the surface Wa (Step S01). Examples of the silicon-based insulating material include polysilazane. Moreover, as a coating method, a solution is supplied on the surface Wa while rotating the wafer W installed horizontally.

  Next, the wafer W is heated to volatilize the solvent of the solution of the insulating material IM. That is, the solution of the insulating material IM applied to the wafer W is dried (step S02). As heating conditions, for example, placing on a hot plate at 100 to 250 ° C. for 60 to 180 seconds can be mentioned. The insulating material IM remaining on the surface Wa after drying enters the trench Wt and forms a film on the surface Wa (see FIG. 2A).

  Next, an etching solution is supplied onto the surface Wa, and excess of the insulating material IM is removed by the erosion action of the etching solution (step S03). Hereinafter, excess removal by supplying the etching solution is referred to as “etching”. By continuing the etching, at least the insulating material IM outside the trench Wt is removed. Specific examples of the etching solution include an alkaline liquid such as an ammonium hydroxide aqueous solution, a potassium hydroxide aqueous solution, or ammonia perwater. Ammonia hydrogen peroxide is a mixture of an aqueous ammonium hydroxide solution and a hydrogen peroxide solution. As a method for supplying the etching solution, an etching solution may be supplied onto the surface Wa while rotating the horizontally installed wafer W.

  Next, a rinsing liquid is supplied onto the surface Wa to wash away the etching liquid and the dissolved matter from the etching liquid (step S04). Examples of the rinsing liquid include pure water and DIW (Deionized Water). As a method for supplying the rinsing liquid, it is possible to supply the rinsing liquid on the surface Wa while rotating the wafer W placed horizontally.

  Next, the rinse liquid is volatilized by heating and the wafer W is dried (step S02). As heating conditions, for example, placing on a hot plate at 80 to 120 ° C. for 20 to 40 minutes can be mentioned.

  After drying, the insulating material IM remains only in the trench Wt (see FIG. 2B). In the etching, after the etching solution reaches the insulating material IM in the trench Wt, the insulating material IM tends to dissolve faster in the peripheral portion in the trench Wt than in the central portion in the trench Wt. Using this property, etching may be performed so that the side edge portion F2 of the surface F of the insulating material IM is depressed as compared with the central portion F1.

  Next, the wafer W is placed in a firing furnace and heated to fire the insulating material IM (step S06). As heating conditions, for example, leaving in a furnace at 200 to 600 ° C. for 2 to 5 minutes can be mentioned. The insulating material IM becomes an insulator IB1 containing silicon oxide (for example, silicon dioxide) by firing. The insulator IB1 forms an insulating region IA. This completes the formation of the insulating region IA.

  If the etching is performed after the insulating material IM is baked, the height of the insulating region IA tends to vary depending on the width of the trench Wt. Specifically, the height of the insulating region IA tends to be lower in the narrow trench Wt than in the wide trench Wt. As this factor, it is considered that as the width of the trench Wt becomes narrower, the stress generated in the insulating material IM at the time of firing increases, and the resistance of the insulator IB1 to the etching solution decreases.

  On the other hand, in the above-described forming method, etching is performed before firing the insulating material IM. For this reason, the height of the insulating material IM is adjusted in a state where variations in resistance to the etching solution are suppressed. Thereby, the variation in the height of the insulating material IM after etching is suppressed, and the variation in the height of the insulator IB1 after baking is also suppressed. Therefore, variation in the height of the insulating region IA according to the formation position can be suppressed.

  As described above, the etching may be performed so that the side edge portion F2 of the surface F of the insulating material IM remaining in the trench Wt is depressed as compared with the central portion F1. In this case, the contact area between the inner surface of the trench Wt and the insulating material IM is larger than when the side edge portion F2 and the central portion F1 of the surface F are equal in height (see the two-dot chain line in FIG. 2B). Get smaller. Thereby, the force acting on the insulating material IM from the inner surface of the trench Wt during firing is reduced, so that the strength of the insulating region IA after firing can be increased.

(Substrate processing system)
The substrate processing system shown in FIG. 3 is an example of a system that executes the above-described insulating region forming method, and includes a coating / etching apparatus 2 and a baking furnace 3. The firing furnace 3 is an apparatus for firing the insulating material IM in the method for forming the insulating region IA described above, and accommodates and heats the wafer W.

  The coating / etching apparatus (substrate processing apparatus) 2 is an apparatus for performing all procedures other than baking of the insulating material IM in the above-described method for forming the insulating region IA. As shown in FIGS. 4 to 6, the coating / etching apparatus (substrate processing apparatus) 2 includes a carrier block P <b> 1 and a processing block P <b> 2.

  The carrier block P <b> 1 includes a carrier station 20 and a carry-in / carry-out unit 21. The carrier station 20 supports a plurality of carriers 10. The carrier 10 contains a plurality of wafers W in a sealed state, and has an open / close door (not shown) for taking in and out the wafers W on the side surface 10a side. The carrier 10 is installed on the carrier station 20 so that the side surface 10a faces the loading / unloading unit 21 side.

  The loading / unloading unit 21 is adjacent to the carrier station 20. The carry-in / carry-out unit 21 has a plurality of opening / closing doors 21 a respectively corresponding to the carriers 10 on the carrier station 20. By opening the open / close door and the open / close door 21a of the side surface 10a at the same time, the inside of the carrier 10 and the inside of the carry-in / out unit 21 are communicated. The carry-in / carry-out unit 21 incorporates an arm A1. The arm A1 takes out the wafer W from the carrier 10 and passes it to the processing block P2, and receives the wafer W from the processing block P2 and returns it into the carrier 10.

  The processing block P <b> 2 has a coating part 22 and an etching part 23 arranged vertically, and is adjacent to the carry-in / carry-out part 21. The coating unit 22 includes a coating unit U1, a heat treatment unit U2, and an arm A2 for transporting the wafer W to these units. The coating unit U1 applies a solution of the insulating material IM onto the surface Wa of the wafer W. The heat treatment unit U2 includes a hot plate and a cooling plate. The hot plate heats the wafer W in order to dry the solution of the insulating material IM applied to the wafer W. The cooling plate cools the heated wafer W.

  The etching unit 23 includes an etching unit U3, a heat treatment unit U4, and an arm A3 that transfers the wafer W to these units. The etching unit U3 sequentially supplies an etching solution and a rinsing solution onto the surface Wa of the wafer W. The heat treatment unit U4 has a hot plate and a cooling plate. The hot plate heats the wafer W in order to volatilize the rinse liquid. The cooling plate cools the heated wafer W.

  In the processing block P2, a shelf unit U10 is provided on the loading / unloading unit 21 side. The shelf unit U10 is provided from the floor surface to the application unit 22, and is partitioned into a plurality of cells arranged in the vertical direction. An arm A4 is provided in the vicinity of the shelf unit U10. The arm A4 transports the wafer W between the plurality of cells of the shelf unit U10.

  As described above, the coating / etching apparatus 2 dries the coating unit U1 that applies the solution of the silicon-based insulating material IM to the wafer W having the trench Wt on the surface Wa and the solution of the insulating material IM applied to the wafer W. And an etching unit U3 that supplies an etchant to the wafer W to remove excess of the insulating material IM before firing the insulating material IM.

  The coating / etching apparatus 2 is used as follows. First, the carrier 10 containing a plurality of wafers W is installed on the carrier station 20 with the side surface 10a facing the loading / unloading unit 21 side. A trench Wt is formed in advance on the surface Wa of the wafer W in the carrier 10. Next, both the open / close door and the open / close door 21a of the carrier 10 are opened, and the wafer W in the carrier 10 is taken out by the arm A1 and sequentially transferred to any cell of the shelf unit U10.

  The wafer W transferred to any cell of the shelf unit U10 is transferred to the cell corresponding to the coating unit 22 by the arm A4. The wafer W is transferred to the coating unit U1 by the arm A2. In the coating unit U1, a coating process for coating the surface Wa of the wafer W with the solution of the insulating material IM is performed. The wafer W subjected to the coating process is transferred to the heat treatment unit U2 by the arm A2. In the heat treatment unit U2, a heat treatment for drying the solution of the insulating material IM by heating the wafer W and cooling the heated wafer W is performed. The heat-treated wafer W is returned to the cell of the shelf unit U10 by the arm A2.

  The wafer W returned to the cell of the shelf unit U10 is transferred to the cell corresponding to the etching unit 23 by the arm A4. The wafer W is transferred to the etching unit U3 by the arm A3. In the etching unit U3, an etching process for supplying an etching liquid to the surface Wa of the wafer W and a rinsing process for supplying a rinsing liquid to the surface Wa are sequentially performed. The wafer W that has been subjected to the etching process and the rinsing process is transferred to the heat treatment unit U4 by the arm A3. In the heat treatment unit U4, heat treatment for drying the wafer W by heating and cooling the wafer W after heating is performed. The heat-treated wafer W is returned to the cell of the shelf unit U10 by the arm A3.

  The wafer W returned to the cell of the shelf unit U10 is transferred to the cell accessible by the arm A1 by the arm A4 and then returned to the carrier 10 by the arm A1.

  According to the substrate processing system 1, all processes up to immediately before firing the insulating material IM can be executed only by the coating / etching apparatus 2. For this reason, the formation method of the insulating region IA described above can be executed with high efficiency.

  The configuration of the substrate processing system 1 is merely an example, and various changes can be made. For example, the layout of each unit of the coating / etching apparatus 2 can be changed as appropriate. Further, the coating / etching apparatus 2 and the baking furnace 3 may be integrated, or the functions of the coating / etching apparatus 2 may be distributed to a plurality of apparatuses.

[Second Embodiment]
The insulating region forming method according to the second embodiment is different from the insulating region forming method according to the first embodiment in that a step of polishing the insulating material IM attached to the wafer W is added.

  As shown in FIG. 7, in the insulating region forming method according to the second embodiment, first, a solution of a silicon-based insulating material is applied to the surface Wa of the wafer W in the same manner as in steps S01 and S02 of the first embodiment. (Step S11), and the solution is dried (Step S12). As a result, a film of the insulating material IM is formed on the surface Wa of the wafer W (see FIG. 8A).

  Next, the insulating material IM adhered on the surface Wa of the wafer W is polished by, for example, CMP (Chemical Mechanical Polishing) (step S13). Thereby, the surface of the film of the insulating material IM is smoothed (see FIG. 8B). A known method can be used for CMP.

  Next, similarly to steps S03 to S05 of the first embodiment, the etching solution is supplied (step S14), the rinse solution is supplied (step S15), and the wafer W is dried (step S16). As a result, the insulating material IM remains only in the trench Wt (see FIG. 8C).

  Next, as in step S06 of the first embodiment, the insulating material IM is baked (step S17). Thereby, the insulator IB1 containing silicon oxide is formed in the trench Wt (see FIG. 8D). The insulator IB1 forms an insulating region IA.

  As described above, the insulating region forming method according to the second embodiment adheres to the wafer W after the solution of the insulating material IM applied to the wafer W is dried and before the etching solution is supplied to the wafer W. It further includes polishing the insulating material.

  In the method for forming an insulating region according to the second embodiment, the surface of the insulating material IM is smoothed by polishing before supplying the etching solution, thereby further suppressing the variation in the height of the insulating material IM before firing. The Therefore, the variation in the height of the insulating region IA according to the formation position can be further suppressed.

  In addition, as a substrate processing system that executes the insulating region forming method according to the second embodiment, for example, in the substrate processing system 1, a known CMP unit U 5 for performing CMP is used as the coating unit 22 of the coating / etching apparatus 2. (See FIG. 9). The CMP unit U5 may be added to the etching unit 23.

[Third Embodiment]
The method for forming an insulating region according to the third embodiment is that a step of laminating an insulator by CVD (Chemical Vapor Deposition) on the insulator IB1 formed in the trench Wt is added. This is different from the insulating region forming method according to the first embodiment.

  As shown in FIG. 10, in the method for forming an insulating region according to the third embodiment, first, as in steps S01 to S06 of the first embodiment, application of a solution of an insulating material (step S21), and drying of the solution ( Step S22), supplying an etching solution (Step S23), supplying a rinsing solution (Step S24), drying the wafer W (Step S25), and baking the insulating material IM (Step S26). Thereby, the insulator IB1 containing silicon oxide is formed in the trench Wt (see FIGS. 11A to 11C). Next, a CVD process is performed (step S27), and the insulator IB2 is stacked on the insulator IB1 (see FIG. 11D). For the CVD, for example, a known high density plasma (HDP) CVD can be used. Further, as the insulator IB2 stacked by CVD, a material containing silicon oxide (for example, silicon dioxide) can be used as in the case of the insulator IB1. The insulator IB1 and the insulator IB2 are integrated to form the insulating region IA.

  The strength of the insulator IB2 stacked by CVD tends to be higher than the strength of the insulator IB1 formed by firing the insulating material IM. On the other hand, in the CVD, it is difficult to fill the insulator on the bottom surface side of the trench Wt as compared with the case where the insulating material IM is applied and baked. By combining the baking of the insulating material IM and the CVD, it is possible to achieve both the filling property and strength of the insulating region IA.

  As a substrate processing system for executing the insulating region forming method according to the third embodiment, as shown in FIG. 12, for example, a known CVD for performing CVD in addition to the coating / etching apparatus 2 and the baking furnace 3. An example of the substrate processing system 1 </ b> A further includes the apparatus 4.

  Although the embodiment has been described above, the present invention is not necessarily limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. For example, the insulating material is not limited to polysilazane as long as it forms silicon oxide by firing. The etching solution is not limited to an aqueous ammonium hydroxide solution, an aqueous potassium hydroxide solution, or ammonia overwater as long as it can dissolve a silicon-based insulating material.

  Hereinafter, although an example and a comparative example are explained, the present invention is not limited to these.

[Preparation of sample]
Example 1
A wafer was prepared in which a plurality of types of trenches having different widths were formed on the surface. The depth of each trench is about 300 nm. A polysilazane solution was applied to the surface of the wafer and dried. The thickness of the polysilazane adhering to the wafer after drying was about 350 nm based on the bottom of the trench. Next, an aqueous ammonium hydroxide solution containing ammonia at a concentration of about 29% was supplied for 20 minutes to remove excess polysilazane. Next, the polysilazane was baked by leaving the wafer in a furnace at about 300 ° C. for about 2 minutes to form an insulator containing silicon oxide in the trench.

(Example 2)
A wafer having a plurality of trenches with a width of about 80 nm and a depth of about 300 nm formed on the surface was prepared. A polysilazane solution was applied to the surface of the wafer and dried. The thickness of the polysilazane adhering to the wafer after drying was about 350 nm based on the bottom of the trench. Next, etching was performed using an aqueous ammonium hydroxide solution containing ammonia at a concentration of about 29% to remove excess polysilazane. In the etching, the supply time of the etching solution was adjusted so that the side edge portion of the surface of the insulating material remaining in the trench was depressed as compared with the central portion. The supply time of the etching solution was about 30 seconds. Next, the polysilazane was baked by leaving the wafer in a furnace at about 300 ° C. for about 2 minutes to form an insulator containing silicon oxide in the trench.

(Comparative Example 1)
A wafer was prepared in which a plurality of types of trenches having different widths were formed on the surface. The depth of each trench is about 300 nm. A polysilazane solution was applied to the surface of the wafer and dried. The thickness of the polysilazane adhering to the wafer after drying was about 350 nm based on the bottom of the trench. Next, the polysilazane was baked by leaving the wafer in a furnace at about 300 ° C. for about 2 minutes to form an insulator containing silicon oxide. Next, an etching solution containing hydrofluoric acid as a main component was supplied for about 30 seconds to remove excess of the insulator.

(Comparative Example 2)
A wafer having a plurality of trenches with a width of about 80 nm and a depth of about 300 nm formed on the surface was prepared. A polysilazane solution was applied to the surface of the wafer and dried. The thickness of the polysilazane adhering to the wafer after drying was about 350 nm based on the bottom of the trench. Next, the polysilazane was baked by leaving the wafer in a furnace at about 300 ° C. for about 2 minutes to form an insulator containing silicon oxide. Next, etching was performed by supplying an etchant containing hydrofluoric acid as a main component, and excess of the insulator was removed. In etching, the supply time of the etching solution was adjusted so that the height of the insulator remaining in the trench was equal to the height of the insulator formed in Example 2. The supply time of the etching solution was about 30 seconds.

[Comparison of insulation area height]
For each of Example 1 and Comparative Example 1, the height of the insulating region formed in the trench was measured. In Comparative Example 1, as shown in FIG. 13, the height of the insulating region IA1 formed in the trench Wt1 having a width of about 200 nm is about 310 nm, and the insulating region IA2 formed in the trench Wt2 having a width of about 150 nm. Was about 280 nm, and the height of the insulating region IA3 formed in the trench Wt3 having a width of about 100 nm was about 150 nm. That is, it was clear that the height of the insulating region was decreased as the width of the trench was reduced.

  For Example 1, as shown in FIG. 14, the height of the insulating region IA4 formed in the trench Wt4 having a width of about 70 nm is about 190 nm, and the insulating region IA5 formed in the trench Wt5 having a width of about 80 nm. The height of was about 185 nm. That is, there was almost no difference in the height of the insulating regions formed in the trenches having a width of 70 nm and 80 nm, respectively. Further, the height of the insulating region IA6 formed in the trench Wt6 having a width of about 700 nm, which is larger than the width of the trenches Wt4 and Wt5, is about 131 nm, and the insulation formed in the trenches Wt4 and Wt5. It was lower than the height of areas IA4 and IA5. From these facts, there was no tendency for the height of the insulating region to decrease as the width of the trench narrowed. From this result, it is estimated that the variation in the height of the insulating region according to the formation position can be suppressed by performing the etching before firing the insulating material.

[Comparison of insulation area resistance]
An etching solution containing hydrofluoric acid as a main component was supplied to each of the insulator of Example 2 and the insulator of Comparative Example 2 over the same time, and the state of the insulating region remaining in the trench was confirmed. As shown in FIG. 15, the average value of the height of the insulating region IA7 remaining in the trench Wt7 of Comparative Example 2 is about 120 nm, whereas the average value of the insulating region IA8 remaining in the trench Wt8 of Example 2 is high. The average value was about 150 nm. That is, the residual amount of the insulating region IA8 is larger than the residual amount of the insulating region IA7. In addition, the height of the insulating region IA7 varies from trench to trench, whereas the height of the insulating region IA8 hardly varies from trench to trench. Therefore, in addition to performing the etching before firing the insulating material, the etching is performed so that the side edge portion of the surface of the insulating material remaining in the trench is depressed compared to the central portion. It was confirmed that the strength of the region could be increased. Furthermore, it was confirmed that variation in the strength of the insulating region according to the formation position can be suppressed.

  F ... surface, F1 ... center portion, F2 ... side edge portion, IA ... insulating region, IB1 ... insulator, IB2 ... insulator, IM ... insulating material, W ... wafer, Wa ... surface, Wt ... trench.

Claims (6)

Applying a solution of a silicon-based insulating material to a substrate having a recess on the surface;
Drying the solution of the insulating material applied to the substrate;
After drying the solution of the insulating material, supplying an etchant to the substrate to remove excess of the insulating material;
After removing the excess of said insulating material, by firing the insulating material remaining on the substrate, forming an insulator containing silicon oxide in the recess, only including,
The insulating material is removed with the etchant so that the side edge portion of the surface of the insulating material remaining in the recess is depressed as compared with the central portion, and the insulating material is baked in this state. And a method of forming an insulating region.   The method for forming an insulating region according to claim 1, wherein the insulating material containing polysilazane is used.   The method for forming an insulating region according to claim 1, wherein the alkaline etching solution is used.   The method for forming an insulating region according to claim 3, wherein any one of an aqueous ammonium hydroxide solution, an aqueous potassium hydroxide solution, and ammonia perwater is used as the alkaline etching solution.   The method further comprises polishing the insulating material adhered to the substrate after drying the solution of the insulating material applied to the substrate and before supplying the etching solution to the substrate. The method for forming an insulating region according to any one of the above. Wherein on the insulator formed in the recess by chemical vapor deposition further includes laminating the insulator, the method of forming the insulating region of any one of claims 1-5.