JP6051986B2 - Liquid crystal display device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly to a liquid crystal display device such as a fringe field switching mode and a manufacturing method thereof.

  An in-plane-switching (IPS) (registered trademark) mode liquid crystal display device is a display method in which a horizontal electric field is applied to a liquid crystal layer sandwiched between opposing substrates to perform display. The IPS mode is considered to be a display method that is superior in viewing angle characteristics as compared with a TN (Twisted Nematic) mode and can satisfy the demand for higher image quality.

  In an IPS mode liquid crystal display device, a pixel electrode and a counter electrode made of opaque metal films facing each other are generally formed on the same layer of the same substrate. The liquid crystal display device having such a structure has a drawback that it is difficult to increase the pixel aperture ratio as compared with the normal TN mode, and thus the light use efficiency is low.

  In order to improve the aperture ratio and the transmittance in the IPS mode liquid crystal display device, a fringe field switching (FFS) mode has been proposed (for example, Patent Documents 1 and 2). In the FFS mode liquid crystal display device, since the pixel electrode and the counter electrode are formed of a transparent conductive film, the aperture ratio and the transmittance are improved compared to the IPS mode. Further, in the FFS mode liquid crystal display device, the capacity between the transparent conductive films can be increased without forming the storage capacitor forming portion, and thus the transmittance loss due to the storage capacitor forming portion does not occur.

  In the FFS mode liquid crystal display device as described above, configurations and manufacturing methods for further improving the aperture ratio and the transmittance have been proposed (for example, Patent Documents 3 and 4). In addition, in the FFS mode reflective and transflective liquid crystal display devices, a method and a manufacturing method for improving contrast reduction due to variations in the thickness of the liquid crystal layer have been proposed (for example, Patent Document 4).

JP 2001-235863 A JP 2002-182230 A JP 2009-36947 A JP 2009-128397 A

  The FFS mode liquid crystal display device is different from the IPS mode liquid crystal display device in that it includes a counter electrode having a slit provided in an upper layer and a lower electrode provided in a lower layer via an insulating film. It is done. According to such a configuration, by applying different potentials to the counter electrode and the lower electrode, the upper part of the lower electrode, the slit of the counter electrode, the liquid crystal layer, and the upper part of the counter electrode are arranged in this order (or in reverse order). Then, an electric field (hereinafter referred to as “fringe field”) is generated in the lateral direction in the liquid crystal layer. In the FFS mode liquid crystal display device, it is possible to drive the liquid crystal using this fringe electric field.

  However, the fringe electric field of the conventional FFS mode liquid crystal display device is oriented in the horizontal direction at the boundary between the counter electrode and the slit, but in the vicinity of the center portion of the counter electrode and the vicinity of the center portion of the slit. There is a problem that it is oriented in the direction (stacking direction of the counter electrode and the lower electrode). As a result, in both the counter electrode and the vicinity of the center of the slit, the liquid crystal molecules are arranged along the electric field, and a sufficient phase difference cannot be obtained (insufficient) when the electric field is applied. It falls locally within the pixel. For this reason, there is a problem that the transmittance in one pixel becomes non-uniform and the average transmittance of one whole pixel is lowered, resulting in a reduction in display quality.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of improving display quality in a liquid crystal display device using a fringe electric field.

The liquid crystal display device according to the present invention includes a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer sandwiched between the first and second substrates. The first substrate has a first electrode having a top surface on which irregularities in the shape of a sine wave or cosine wave are arranged in a predetermined direction in a cross-sectional view, and an interelectrode insulating film on the first electrode. formed Te comprises a slit, said second electrode having a partial electrode is a portion between the two said slit adjacent in a predetermined direction, is divided by a plurality of bottom of front Symbol irregularities The partial electrodes and the slits of the second electrode are alternately arranged above the plurality of projections arranged in the predetermined direction so as to correspond to the projections in the order of the arrangement of the plurality of projections. It is arranged. The top surface of the partial electrode of the second electrode and the top surface of the interelectrode insulating film exposed from the slit of the second electrode reflect the unevenness in the shape of a sine wave or cosine wave of the first electrode. Concavities and convexities are provided.

  According to the present invention, the entire upper portion of the first convex portion of the first electrode is configured to be exposed from the slit of the second electrode in a predetermined direction in plan view. Thereby, since the 1st convex part can be arranged in the horizontal direction as much as possible with respect to the 2nd electrode, the fringe electric field can be directed in the horizontal direction as much as possible. Therefore, display quality can be improved in a liquid crystal display device using a fringe electric field.

It is a top view which shows the structure of the TFT array substrate used for a liquid crystal display device. 2 is a plan view showing a pixel configuration of a TFT array substrate according to Embodiment 1. FIG. 2 is a cross-sectional view showing a pixel configuration of a TFT array substrate according to Embodiment 1. FIG. FIG. 6 is a diagram for explaining an effect of the liquid crystal display device according to the first embodiment. FIG. 6 is a diagram for explaining an effect of the liquid crystal display device according to the first embodiment. FIG. 6 is a cross-sectional view for illustrating the method for manufacturing the liquid crystal display device according to the first embodiment. FIG. 6 is a cross-sectional view for illustrating the method for manufacturing the liquid crystal display device according to the first embodiment. 6 is a cross-sectional view showing a pixel configuration of a TFT array substrate according to Embodiment 2. FIG. FIG. 10 is a cross-sectional view for explaining the effect of the liquid crystal display device according to the second embodiment. 6 is a cross-sectional view showing a pixel configuration of a TFT array substrate according to Embodiment 3. FIG. FIG. 11 is a cross-sectional view for explaining the method for manufacturing the liquid crystal display device according to the third embodiment. FIG. 10 is a cross-sectional view for explaining an effect of the liquid crystal display device according to the third embodiment. 6 is a plan view showing a pixel configuration of a TFT array substrate according to Embodiment 4. FIG. 6 is a cross-sectional view showing a pixel configuration of a TFT array substrate according to Embodiment 4. FIG. It is sectional drawing which shows the pixel structure of the TFT array substrate which concerns on a modification.

<Embodiment 1>
<Configuration>
FIG. 1 is a plan view showing a configuration of a substrate 10 (first substrate) used in the liquid crystal display device according to Embodiment 1 of the present invention. This substrate 10 is applied to, for example, an array substrate in which switching elements are formed in an array. In the following description, it is assumed that the substrate 10 is an array substrate of thin film transistors (TFTs), that is, a TFT array substrate (hereinafter referred to as “TFT array substrate 10”).

  Although not shown, the liquid crystal display device according to the first embodiment includes not only the TFT array substrate 10 (first substrate) but also a counter substrate (second substrate), a liquid crystal layer, a backlight unit, and the like. Configured.

  The counter substrate is a substrate (for example, a color filter substrate) disposed to face the TFT array substrate 10, and is disposed on the viewing side (the front side of the TFT array substrate 10 shown in FIG. 1). A color filter, a black matrix (BM), an alignment film, and the like are formed on the counter substrate.

  The liquid crystal layer is sandwiched between the TFT array substrate 10 and the counter substrate. That is, liquid crystal is introduced between the TFT array substrate 10 and the counter substrate. Furthermore, a polarizing plate, a retardation plate, and the like are provided on the surfaces of the TFT array substrate 10 and the counter substrate on the side opposite to the liquid crystal layer.

  The TFT array substrate 10, the counter substrate, and the liquid crystal layer form a liquid crystal display panel, and the backlight unit is disposed on the non-viewing side of the liquid crystal display panel.

  Here, it is assumed that a lower electrode and a counter electrode (pixel electrode) capable of generating a fringe electric field are formed on the TFT array substrate 10. That is, the liquid crystal display device according to the first embodiment is an FFS mode liquid crystal display device. The overall configuration of this liquid crystal display device is common to the first to fourth embodiments described below.

  Next, the configuration of the TFT array substrate 10 will be described in detail.

  As shown in FIG. 1, the TFT array substrate 10 is provided with a display area 41 and a frame area 42 provided so as to surround the display area 41.

  In the display area 41, a plurality of gate lines (scanning signal lines) 43 and a plurality of source lines (display signal lines) 44 are formed. The plurality of gate lines 43 are arranged in parallel, and the plurality of source lines 44 are arranged in parallel. On the other hand, the gate wiring 43 and the source wiring 44 are formed so as to cross each other in a plan view, but are insulated by a gate insulating film in a sectional view as will be described later. A region surrounded by two adjacent gate lines 43 and two adjacent source lines 44 is a pixel 47. Therefore, in the TFT array substrate 10, the pixels 47 are arranged in a matrix.

  In the frame area 42, a scanning signal driving circuit 45 and a display signal driving circuit 46 are provided. The gate line 43 extends from the display area 41 to the frame area 42 and is connected to the scanning signal drive circuit 45 at the end of the TFT array substrate 10. Similarly, the source line 44 extends from the display area 41 to the frame area 42 and is connected to the display signal drive circuit 46 at the end of the TFT array substrate 10. An external wiring 48 electrically connected to the scanning signal driving circuit 45 is provided in a region near the scanning signal driving circuit 45 on the TFT array substrate 10. Further, an external wiring 49 electrically connected to the display signal drive circuit 46 is provided in a region near the display signal drive circuit 46 on the TFT array substrate 10. For the external wirings 48 and 49, for example, a wiring board such as FPC (Flexible Printed Circuit) is used.

  Various external signals are supplied to the scanning signal driving circuit 45 and the display signal driving circuit 46 through the external wirings 48 and 49. The scanning signal drive circuit 45 sequentially selects the gate wiring 43 based on a control signal from the outside, and supplies a gate signal (scanning signal) to the selected gate wiring 43. The display signal driving circuit 46 supplies a display signal to the source wiring 44 based on an external control signal or display data. Thereby, a display voltage corresponding to the display data can be sequentially supplied to each pixel 47.

  In the pixel 47, at least one TFT 50 is formed. The TFT 50 is disposed in the vicinity of the intersection between the source wiring 44 and the gate wiring 43. The TFT 50 is turned on or off according to the gate signal from the gate wiring 43. When the display voltage is supplied from the source line 44 in the ON state, the TFT 50 applies the display voltage to the counter electrode connected to the drain electrode.

  Next, the configuration of the pixel 47 of the liquid crystal display device according to the first embodiment will be described. FIG. 2 is a plan view showing a pixel configuration of the TFT array substrate 10 according to the first embodiment. FIG. 3 is a cross-sectional view showing a pixel configuration of the TFT array substrate 10 according to the first embodiment. 2 shows one of the pixels 47 of the TFT array substrate 10, and FIG. 3 is a cross-sectional view taken along the line AA of FIG. Here, a case where a channel etch type TFT 50 is formed will be described as an example.

  Here, before describing the pixel configuration in detail, an outline of the pixel configuration will be described. The counter electrode 8 has a slit 8s, and is opposed to the lower electrode 7 with the interelectrode insulating film 14 interposed therebetween (FIG. 3). The lower electrode 7 and the counter electrode 8 are electrodes for generating the above-described fringe electric field, and the magnitude of the fringe electric field corresponds to the magnitude of the display voltage applied to the counter electrode 8. An alignment film (not shown) is formed on the surface of the TFT array substrate 10.

  The liquid crystal in the liquid crystal layer between the TFT array substrate 10 and the counter substrate (the liquid crystal layer above the TFT array substrate 10 in FIG. 3) is driven by a fringe electric field corresponding to the display voltage, and the alignment direction of the liquid crystal changes. Along with this, the polarization state of light passing through the liquid crystal layer changes. That is, the polarization state of the light passing through the liquid crystal layer can be changed according to the display voltage.

  Here, when the light from the backlight unit passes through the polarizing plate on the TFT array substrate 10 side, it becomes linearly polarized light, and when the light passing through the polarizing plate passes through the liquid crystal layer, the polarization state changes as described above. . The amount of light that has passed through the liquid crystal layer passes through the polarizing plate on the counter substrate side depends on the change in the polarization state in the liquid crystal layer.

  That is, the amount of light that passes through the polarizing plate on the viewing side (the polarizing plate on the counter substrate) among the transmitted light that passes through the liquid crystal display panel from the backlight unit is based on the display voltage applied to the counter electrode 8. It is possible to change. Thus, by controlling the display voltage applied to the counter electrode 8, the amount of light passing through the viewing side can be changed. In other words, a desired image can be displayed in the display area 41 by changing the display voltage for each pixel 47.

  Next, the configuration of such a pixel 47 will be described in detail. 2 and 3, a gate wiring 43 and a common wiring 9, part of which forms the gate electrode 1, are formed on a transparent insulating transparent substrate 10 a such as glass. The gate wiring 43 is arranged so as to extend linearly in one direction on the transparent substrate 10a. The gate electrode 1, the gate wiring 43, and the common wiring 9 are made of, for example, Cr, Al, Ta, Ti, Mo, W, Ni, Cu, Au, Ag, an alloy film containing these as a main component, or a laminated film thereof. Is formed by.

  A gate insulating film 11 is provided so as to cover the gate electrode 1, the gate wiring 43, and the common wiring 9. The gate insulating film 11 is formed of an insulating film such as silicon nitride or silicon oxide. In the region where the TFT 50 is formed, the semiconductor layer 2 is provided on the gate wiring 43 via the gate insulating film 11. Here, the semiconductor layer 2 is formed on the gate insulating film 11 so as to overlap with the gate wiring 43 in plan view, and the gate wiring 43 in a region substantially overlapping with the semiconductor layer 2 becomes the gate electrode 1. The semiconductor layer 2 is formed of, for example, amorphous silicon, polycrystalline silicon, metal oxide, or the like. Hereinafter, a case where the semiconductor layer 2 is formed of amorphous silicon will be described as an example.

  In addition, the semiconductor layer 2 includes an ohmic contact film 3 doped with a conductive impurity on each of both ends of the semiconductor layer 2. The region of the semiconductor layer 2 corresponding to the ohmic contact film 3 becomes a source / drain region. Specifically, the region of the semiconductor layer 2 corresponding to the left ohmic contact film 3 in FIG. 3 becomes the source region. A region of the semiconductor layer 2 corresponding to the right ohmic contact film 3 in FIG. 3 becomes a drain region. Thus, source / drain regions are formed at both ends of the semiconductor layer 2. Then, a region sandwiched between the source / drain regions of the semiconductor layer 2 in a plan view becomes a channel region. The ohmic contact film 3 is not formed on the channel region of the semiconductor layer 2. The ohmic contact film 3 is made of, for example, n-type amorphous silicon or n-type polycrystalline silicon doped with an impurity such as phosphorus (P) at a high concentration.

  A part of the source electrode 4 is formed on the ohmic contact film 3 in the source region. Specifically, a source electrode 4 extending from the ohmic contact film 3 in the source region to the opposite side to the channel region is formed. Similarly, a part of the drain electrode 5 is formed on the ohmic contact film 3 in the drain region. Specifically, a drain electrode 5 extending from the ohmic contact film 3 in the drain region to the opposite side to the channel region is formed. That is, the source electrode 4 and the drain electrode 5 are not formed on the channel region of the semiconductor layer 2 like the ohmic contact film 3.

  As described above, in the liquid crystal display device according to the first embodiment, the channel etch type TFT 50 is formed on the transparent substrate 10a.

  A portion of the source electrode 4 that extends to the opposite side of the channel region of the semiconductor layer 2 is connected to the source wiring 44. In a cross-sectional view, the source wiring 44 is formed on the gate insulating film 11. In plan view, the source wiring 44 has a main body portion linearly extending in a direction intersecting the gate wiring 43 and a branching from the main body portion in the vicinity of the intersection and extending in the same direction as the extending direction of the gate wiring 43. Existing branching portions. This branch portion corresponds to the source electrode 4.

  The drain electrode 5 has an extending portion that extends on the opposite side to the channel region of the semiconductor layer 2. The extending portion of the drain electrode 5 is electrically connected to the counter electrode 8 via a connection wiring 19 (FIG. 2). The connection wiring 19 is made of the same material (here, the same metal film) as the lower electrode 7, but is separated from the lower electrode 7 and insulated from the lower electrode 7.

  The source electrode 4, the source wiring 44, and the drain electrode 5 are, for example, Cr, Al, Ta, Ti, Mo, W, Ni, Cu, Au, Ag, an alloy film containing these as a main component, or a laminated film thereof. Is formed by.

  A first interlayer insulating film 12 is provided so as to cover the semiconductor layer 2, the source electrode 4, the source wiring 44, and the drain electrode 5. The first interlayer insulating film 12 is formed of an insulating film such as silicon nitride or silicon oxide.

  A second interlayer insulating film 13 (interlayer insulating film) is provided so as to cover the first interlayer insulating film 12. Here, the second interlayer insulating film 13 has an upper surface on which irregularities are arranged in a predetermined direction (X direction shown in FIG. 2) as shown in FIGS. 2 and 3. The second interlayer insulating film 13 is formed of a resin film such as acrylic, epoxy, polyimide, polyolefin, for example.

  In the first and second interlayer insulating films 12 and 13, a first contact hole 15 is provided on a part of the drain electrode 5. Further, a third contact hole 17 is provided on a part of the common wiring 9 in the gate insulating film 11 and the first and second interlayer insulating films 12 and 13. The second contact hole 16 will be described later.

  The lower electrode 7 (first electrode) is formed on the upper surface of the second interlayer insulating film 13 where the irregularities are disposed, and is electrically connected to the common wiring 9 in the third contact hole 17. . In the first embodiment, the unevenness of the second interlayer insulating film 13 is reflected on the upper surface of the lower electrode 7, that is, the unevenness is raised and transferred. Thus, the lower electrode 7 has an upper surface on which unevenness similar to the unevenness of the second interlayer insulating film 13 is arranged in the X direction. According to such a configuration, it is possible to form irregularities on the upper surface of the lower electrode 7 by a simple process. In the following description, the unevenness of the lower electrode 7 will be described as including the convex portion 7a (7a1, 7a2) and the concave portion 7b.

  The connection wiring 19 is formed on the second interlayer insulating film 13 around the first contact hole 15 and is electrically connected to the drain electrode 5 in the first contact hole 15. The lower electrode 7 and the connection wiring 19 are formed of a transparent conductive film (metal oxide) such as ITO or IZO. As described above, the connection wiring 19 is separated from the lower electrode 7 and insulated from the lower electrode 7.

  An interelectrode insulating film 14 is provided so as to cover the second interlayer insulating film 13, the lower electrode 7, and the connection wiring 19. In the first embodiment, the unevenness of the lower electrode 7 is reflected on the upper surface of the interelectrode insulating film 14, that is, the unevenness is raised and transferred. As described above, the interelectrode insulating film 14 has an upper surface on which unevenness similar to the unevenness of the lower electrode 7 is arranged in the X direction. The interelectrode insulating film 14 is formed of an insulating film such as silicon nitride or silicon oxide. The interelectrode insulating film 14 is provided with a second contact hole 16 on a part of the connection wiring 19.

  The counter electrode 8 (second electrode) is formed on the upper surface of the interelectrode insulating film 14 where the unevenness is disposed, and is electrically connected to the connection wiring 19 in the second contact hole 16. Thereby, the TFT 50 included in the TFT array substrate 10 can control the display voltage (voltage) applied to the counter electrode 8. Further, unevenness of the interelectrode insulating film 14 is reflected on the upper surface of the counter electrode 8, that is, the unevenness is raised and transferred. The counter electrode 8 is formed of a transparent conductive film (metal oxide) such as ITO or IZO.

  Further, the counter electrode 8 has a slit 8s. Hereinafter, the portion between the two slits 8s adjacent in the X direction in the counter electrode 8 is referred to as a “partial electrode 8p”. As described above, since the unevenness of the interelectrode insulating film 14 is reflected on the counter electrode 8, the upper surface of the partial electrode 8p is inclined so as to protrude convexly from the end of the partial electrode 8p toward the center. It includes surface 8f (FIG. 3).

  Now, in FIG. 2, the upper part of the convex part 7a of the lower electrode 7 is indicated by a thick line. As shown in FIG. 2, in the first embodiment, when attention is paid to one convex portion 7a1 (first convex portion) of the lower electrode 7 in the X direction in plan view, the entire upper portion is one It is exposed from the slit 8s.

  Here, as an example of the configuration, in the X direction, the position of the upper portion of the convex portion 7a1 of the lower electrode 7, the position of the central portion of the slit 8s, and the position of the upper portion of the convex portion of the second interlayer insulating film 13 are Almost aligned. Further, in the X direction, the position of the upper part of the convex part 7a2 adjacent to the convex part 7a1 of the lower electrode 7, the position of the central part of the partial electrode 8p, and the position of the upper part of the convex part of the second interlayer insulating film 13 are Almost aligned. Further, in the X direction, the position of the lower portion of the recess 7b of the lower electrode 7, the position of the boundary between the slit 8s and the partial electrode 8p (that is, the position of each end of the slit 8s and the partial electrode 8p), the second interlayer The position of the lower portion of the concave portion of the insulating film 13 is substantially aligned.

<Effect>
The effect of the liquid crystal display device according to the first embodiment configured as described above will be described with reference to FIGS. FIG. 4 is a diagram showing the pixel structure and the operation of the liquid crystal molecules in the FFS mode liquid crystal display device (hereinafter referred to as “related liquid crystal display device”) related to the liquid crystal display device according to the first embodiment. FIG. 5 is a diagram showing the pixel structure and the operation of the liquid crystal molecules in the liquid crystal display device according to the first embodiment. 4A and 5A are plan views thereof, and FIG. 4B and FIG. 5B are cross-sectional views thereof.

  4 and 5 indicates an OFF state in which the fringe electric field 34 is not applied to the lower electrode 7 and the counter electrode 8, and ON in FIGS. 4 and 5 indicates a fringe to the lower electrode 7 and the counter electrode 8. An ON state in which an electric field 34 is applied to operate the liquid crystal molecules 32 is shown. Specifically, the liquid crystal molecules 32 have a rod shape, and in the OFF state where the fringe electric field 34 is not generated, the liquid crystal molecules 32 are long as shown in FIGS. 4 (a) and 5 (a). In the ON state where the fringe electric field 34 is generated, the longitudinal direction is the direction of the fringe electric field 34 as shown in FIGS. 4 (b) and 5 (b). It shall operate to point to. In the configuration that operates as described above, in the ON state, it is preferable that the longitudinal direction of many liquid crystal molecules 32 be as much as possible in the second lateral direction 35b.

  Here, as shown in FIG. 4B, the fringe electric field 34 generated in the ON state in the related liquid crystal display device is near the boundary between the partial electrode 8p and the slit 8s (each end of the partial electrode 8p and the slit 8s). Part) in the second horizontal direction 35b, but in the vicinity of the central part of each of the partial electrode 8p and the slit 8s, in the vertical direction 35c. For this reason, in the center part of each of the partial electrode 8p and the slit 8s, the longitudinal direction of the liquid crystal molecules 32 is not directed to the second lateral direction 35b but is directed to the longitudinal direction 35c. Therefore, since a sufficient phase difference cannot be obtained (is insufficient), the transmittance is unintentionally lowered.

  On the other hand, in the liquid crystal display device according to the first embodiment, in the X direction (predetermined direction) in plan view, the entire upper portion of the first convex portion 7a1 of the lower electrode 7 is It is configured to be exposed from the slit 8s. Thereby, since the 1st convex part 7a1 can be arrange | positioned in the 2nd horizontal direction 35b as much as possible with respect to the counter electrode 8, the fringe electric field 34 between the counter electrode 8 and the 1st convex part 7a1 is made as much as possible. 2 can be directed in the horizontal direction 35b. Thereby, in the center part of the slit 8s of the counter electrode 8, the longitudinal direction of the liquid crystal molecules 32 is suppressed from being directed to the longitudinal direction 35c, and can be directed to the second lateral direction 35b as much as possible. Accordingly, since it is possible to suppress the local decrease in the transmittance in one pixel 47 in the ON state, the transmittance in the one pixel 47 can be made uniform and the average transmittance of the entire one pixel 47 can be achieved. The rate can be improved. Therefore, display quality can be improved in a liquid crystal display device using a fringe electric field.

  In the liquid crystal display device according to the first embodiment, the upper surface of the partial electrode 8p (counter electrode 8) includes an inclined surface 8f that is inclined in a convex shape from the end of the partial electrode 8p toward the center. . As a result, the upper surface of the partial electrode 8p can be directed to the first convex portion 7a1 side as much as possible. Therefore, the fringe electric field 34 between the counter electrode 8 and the first convex portion 7a1 is further directed in the second lateral direction 35b. be able to. Therefore, the transmittance within one pixel 47 can be further uniformed, and the average transmittance of the entire one pixel 47 can be further improved, so that the display quality is further improved in a liquid crystal display device using a fringe electric field. be able to.

<Manufacturing method>
Next, a method for manufacturing the liquid crystal display device according to the first embodiment will be described.

  First, Cr, Al, Ta, Ti, Mo, W, Ni, Cu, Au, Ag, or an alloy film containing these as a main component, or these films are formed on the entire upper surface of a transparent insulating transparent substrate 10a such as glass. A laminated film is formed. For example, a film is formed on the entire upper surface of the transparent substrate 10a by using a sputtering method, a vapor deposition method, or the like. Thereafter, a resist is applied, the applied resist is exposed from above the photomask, and the resist is exposed. Next, the exposed resist is developed to pattern the resist. Hereinafter, these series of steps are called photoengraving. Thereafter, using the resist pattern as a mask, the above-described film formation (here, metal film) is etched to remove the photoresist pattern. Hereinafter, such a process is referred to as a fine processing technique. Thereby, the gate electrode 1, the gate wiring 43, and the common wiring 9 are patterned.

  Next, the gate insulating film 11 is formed using, for example, plasma CVD, atmospheric pressure CVD, reduced pressure CVD or the like so as to cover the entire upper surface (gate electrode 1, gate wiring 43, common wiring 9 and the like) of the transparent substrate 10a. The first insulating film, the semiconductor layer 2 and the ohmic contact film 3 are formed in this order. Silicon nitride, silicon oxide, or the like can be used for the first insulating film. The gate insulating film 11 is preferably formed in a plurality of times in order to prevent a short circuit due to the occurrence of film defects such as pinholes.

  As a material for the semiconductor layer 2, amorphous silicon, polycrystalline silicon, metal oxide, or the like can be used. As a material for the ohmic contact film 3, n-type amorphous silicon, n-type polycrystalline silicon, or the like in which an impurity such as high concentration phosphorus (P) is added to the semiconductor layer 2 can be used. Thereafter, the above-described film formation that becomes the semiconductor layer 2 and the ohmic contact film 3 is patterned by the photoengraving and fine processing techniques up to the stage before the semiconductor layer 2 and the ohmic contact film 3 are formed. Here, as an example, the above-described film formation to be the semiconductor layer 2 and the ohmic contact film 3 is patterned on the gate electrode 1 in an island shape.

  Next, Cr, Al, Ta, Ti, Mo, W, Ni, Cu, Au, Ag, an alloy film containing these as a main component, or a laminated film thereof is formed so as to cover the ohmic contact film 3 and the like. To do. For example, the film is formed by using a sputtering method or a vapor deposition method. Thereafter, patterning is performed by photolithography and microfabrication technology to form the source electrode 4, the source wiring 44, and the drain electrode 5.

  Subsequently, the film to be the ohmic contact film 3 is etched using the source electrode 4 and the drain electrode 5 as a mask. That is, the exposed portion of the ohmic contact film 3 patterned in an island shape without being covered by the source electrode 4 or the drain electrode 5 is removed by etching. Thereby, the semiconductor layer 2 and the ohmic contact film 3 in which the channel region is provided between the source electrode 4 and the drain electrode 5 are formed. In the above description, the etching is performed using the source electrode 4 and the drain electrode 5 as a mask. However, the ohmic contact film 3 is etched using the resist pattern used for patterning the source electrode 4 and the drain electrode 5 as a mask. May be. In that case, the ohmic contact film 3 is etched before removing the resist pattern on the source electrode 4 and the drain electrode 5. Through the above manufacturing process, an array of TFTs 50 is formed on the transparent substrate 10a.

  The subsequent manufacturing steps will be described with reference to FIGS. 6 and 7 are cross-sectional views showing a method of manufacturing the liquid crystal display device (particularly the TFT array substrate 10) according to the first embodiment.

  After the TFT 50 is formed by the above-described process, as shown in FIG. 6A, the entire upper surface (the source electrode 4, the drain electrode 5 and the source wiring 44, the gate insulating film 11 and the like) of the transparent substrate 10a is covered. A first interlayer insulating film 12 is formed. For example, an inorganic insulating film such as silicon nitride or silicon oxide to be the first interlayer insulating film 12 is formed on the entire upper surface of the transparent substrate 10a by using a CVD method or the like. As a result, the channel region and the like of the semiconductor layer 2 are covered with the first interlayer insulating film 12.

  Next, a second interlayer insulating film 13 is formed so as to cover the first interlayer insulating film 12. For example, a photosensitive resin film such as acrylic, epoxy, polyimide, polyolefin, or the like, which becomes the second interlayer insulating film 13 (interlayer insulating film) by using a spin coat method or a slit coat method is shown in FIG. It is applied to the entire top surface of the transparent substrate 10a. Here, the coating film thickness is set so that the thickness of the second interlayer insulating film 13 is 2.0 μm or more in the thinnest portion (portion on the TFT 50). Thereafter, the uneven pattern and the patterns of the first and third contact holes 15 and 17 are formed on the resin film by photolithography. At this time, for example, the exposure is performed with an exposure amount at which the unevenness depth becomes 0.5 μm, and the contact hole pattern is exposed with an exposure amount that can completely remove the resin film.

  Thereafter, the entire surface of the second interlayer insulating film 13 was irradiated with ultraviolet rays, and then baked by performing a heat treatment at 100 ° C., followed by a heat treatment at 230 ° C. As a result, the structure shown in FIG. 6B is formed. Note that a resin film having photosensitivity (for example, a resin film having positive photosensitivity) is preferably used for the second interlayer insulating film 13. This is because the depth of the unevenness 13c of the second interlayer insulating film 13 can be arbitrarily controlled by the exposure amount. Moreover, it is preferable that the pitch of the unevenness | corrugation 13c is 3-5 micrometers, and the depth of the unevenness | corrugation 13c is 0.1-0.5 micrometer. This is because when the depth of the unevenness 13c is deeper than 0.5 μm, the contrast reduction due to the variation in the thickness of the liquid crystal layer cannot be ignored, and the display performance is deteriorated.

  Next, the first and third contact holes 15 and 17 are formed by patterning the first interlayer insulating film 12 using a fine processing technique using the second interlayer insulating film 13 as a mask. Thereby, the structure shown in FIG. 6C is formed. That is, the first insulating film (here, the first and second interlayer insulating films 12, 13) having the first contact hole 15 on the transparent substrate 10a and the TFT 50 and having an upper surface on which the unevenness 13c is disposed. The whole insulating film) is formed.

  In the frame region 42, terminals (not shown) for connecting the gate wiring 43 and the source wiring 44 to the scanning signal driving circuit 45 and the display signal driving circuit 46 are the same as the gate wiring 43 or the source wiring 44. Formed by layers. Then, the hole that becomes the gate terminal contact hole 21 (FIG. 2) exposing the gate terminal is patterned in the same manner as the third contact hole 17, whereby the gate insulating film 11, the first and second interlayer insulating films 12 are formed. , 13. In addition, a hole to be the source terminal contact hole 22 (FIG. 2) exposing the source terminal is formed in the first and second interlayer insulating films 12 and 13 by patterning in the same manner as the first contact hole 15. The

  Subsequently, a transparent conductive film such as ITO or IZO is formed on the entire upper surface of the transparent substrate 10a shown in FIG. 6C (the second interlayer insulating film 13 and the first and third contact holes by, for example, sputtering. 15 and 17). At this time, unevenness reflecting the unevenness 13c (following the unevenness 13c) is formed on the upper surface of the transparent conductive film formed on the unevenness 13c of the second interlayer insulating film 13.

  Then, this transparent conductive film is patterned by photolithography and fine processing techniques. As a result, the structure shown in FIG. 7A is formed. That is, on the upper surface of the first insulating film (here, the insulating film composed of the entire first and second interlayer insulating films 12 and 13), the unevenness 7c (the protruding portion 7a and the recessed portion 7b) similar to the unevenness 13 is disposed. A lower electrode 7 having an upper surface and a connection wiring 19 insulated from the lower electrode 7 are formed.

  When forming a transparent conductive film such as the lower electrode 7, in the hole serving as the gate terminal contact hole 21 (FIG. 2) in the frame region 42 and the hole serving as the source terminal contact hole 22. Also, the transparent conductive film is formed. The transparent conductive film formed in these holes becomes the gate terminal pad 23 (FIG. 2) and the source terminal pad 24 in a later step.

  Next, an interelectrode insulating film 14 is formed so as to cover the entire upper surface (second interlayer insulating film 13, lower electrode 7, connection wiring 19 and the like) of the transparent substrate 10a shown in FIG. . For example, an inorganic insulating film such as silicon nitride or silicon oxide to be the interelectrode insulating film 14 is formed on the entire upper surface of the transparent substrate 10a by using a CVD method or the like. At this time, unevenness reflecting the unevenness 7c (following the unevenness 7c) is formed on the upper surface of the inter-electrode insulating film 14 formed on the unevenness 7c of the second interlayer insulating film 13 and the lower electrode 7. .

  When the temperature in forming the interelectrode insulating film 14 is set to be equal to or higher than the temperature at which the second interlayer insulating film 13 is baked, the gas is released from the second interlayer insulating film 13 and the interelectrode insulating film 14 As a result of the gas being taken into the film, the insulating properties and clothing of the interelectrode insulating film 14 are lowered. Therefore, it is preferable that the temperature in forming the interelectrode insulating film 14 is equal to or lower than the temperature at which the second interlayer insulating film 13 is baked. In the present embodiment, a silicon nitride film to be the interelectrode insulating film 14 is formed with a thickness of 300 nm in a state where the film forming temperature is set to a temperature lower than the firing temperature of the second interlayer insulating film 13 (for example, 220 ° C.). .

  Next, the second contact hole 16 is formed in the interelectrode insulating film 14 by photolithography and microfabrication technology. As a result, the structure shown in FIG. 7B is formed. That is, the interelectrode insulating film 14 (second insulating film) having the second contact hole 16 and the unevenness 14 c similar to the unevenness 7 c of the lower electrode 7 is formed. In the frame region 42, the gate terminal contact hole 21 (FIG. 2) and the source terminal contact hole 22 are completed.

  Next, a transparent conductive film such as ITO or IZO is applied to the entire upper surface of the transparent substrate 10a shown in FIG. 7B (on the interelectrode insulating film 14 and in the second contact hole 16) by, for example, sputtering. Form a film. Then, the transparent conductive film is patterned by photolithography and fine processing technology to form the counter electrode 8 having the slits 8s.

  Here, in the first embodiment, the slit 8s is formed in the counter electrode 8 so that the entire upper part of one convex portion 7a1 of the lower electrode 7 is exposed from one slit 8s in the X direction in plan view. Is done. Here, as a result of the unevenness 14c of the interelectrode insulating film 14 being reflected in the counter electrode 8, the upper surface of the partial electrode 8p has an inclined surface 8f inclined in a convex shape from the end of the partial electrode 8p toward the center. It is included. The specific positional relationship between the slits 8s and the partial electrode 8p of the counter electrode 8 and the unevenness of the lower electrode 7 is as described above.

  Thus, the structure shown in FIG. 7C is formed. That is, the counter electrode 8 having the slit 8 s electrically connected to the TFT 50 through the first and second contact holes 15 and 16 is formed on the interelectrode insulating film 14.

  When forming the transparent conductive film to be the counter electrode 8, the transparent conductive film is also formed in the gate terminal contact hole 21 (FIG. 2) and the source terminal contact hole 22 in the frame region 42. Is done. The transparent conductive films formed in the gate terminal contact hole 21 (FIG. 2) and the source terminal contact hole 22 are patterned into the gate terminal pad 23 and the source terminal pad 24, respectively. Through the above steps, the TFT array substrate 10 included in the liquid crystal display device according to the first embodiment is completed.

  On the TFT array substrate 10 manufactured as described above, an alignment film is formed in the subsequent cell process. In addition, an alignment film is similarly formed on a counter substrate manufactured separately. And this alignment film is subjected to an alignment treatment (rubbing treatment) for making micro scratches in one direction on the contact surface with the liquid crystal. Next, a sealing material is applied between the TFT array substrate 10 and the counter substrate, and the TFT array substrate 10 and the counter substrate are formed so that a closed space except for the liquid crystal injection port is formed between the substrates. Bonding is performed by fixing with a sealing material. After the TFT array substrate 10 and the counter substrate are bonded together, liquid crystal is injected into the space from the liquid crystal injection port using a vacuum injection method or the like. Then, the liquid crystal injection port is sealed. After attaching polarizing plates on both sides of the liquid crystal cell thus formed and connecting the drive circuit, the backlight unit is attached. In this way, the liquid crystal display device according to the first embodiment is completed.

  According to the liquid crystal display device according to the first embodiment configured as described above, in the X direction (predetermined direction) in plan view, the entire upper portion of the first convex portion 7a1 of the lower electrode 7 is It is configured to be exposed from the slit 8s of the counter electrode 8. Thereby, since the 1st convex part 7a1 can be arrange | positioned in the horizontal direction as much as possible with respect to the counter electrode 8, a fringe electric field can be directed in the horizontal direction as much as possible. Therefore, display quality can be improved in a liquid crystal display device using a fringe electric field.

<Embodiment 2>
A configuration of the pixel 47 of the liquid crystal display device according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 8 is a cross-sectional view showing the pixel configuration of the TFT array substrate 10 according to the second embodiment in the same manner as FIG. In the liquid crystal display device according to the second embodiment, the same or similar components as those described in the first embodiment are denoted by the same reference numerals, and different points will be mainly described below.

  In the first embodiment, the positions of the recesses 7b of the lower electrode 7 and the positions of the respective ends of the slit 8s and the partial electrode 8p are substantially aligned in the X direction in plan view. On the other hand, in the second embodiment, in the X direction in plan view, the end of the slit 8s is formed by the convex portion 7a2 and the concave portion 7b1 (the concave portion 7b between the convex portion 7a1 and the convex portion 7a2). Located between. That is, the end of the partial electrode 8p according to the second embodiment is set back from the end of the partial electrode 8p according to the first embodiment toward the center of the partial electrode 8p.

  In addition, as a manufacturing method of the TFT array substrate 10 according to the second embodiment, in the manufacturing method described in the first embodiment, the pattern of the photoengraving that forms the unevenness in the second interlayer insulating film 13 is adjusted, What is necessary is just to adjust the pattern of the photoengraving which forms the slit 8s in the counter electrode 8. FIG. The other steps are the same as those in the first embodiment, and thus description thereof is omitted.

  The effect of the liquid crystal display device according to the second embodiment configured as described above will be described with reference to FIG. Temporarily, in the first embodiment, a positional shift as shown by a two-dot chain line in FIG. 9 occurs between the recess 7b of the lower electrode 7 and the end of the slit 8s (end of the partial electrode 8p). In this case, the upper surface of the end portion of the partial electrode 8p is directed to the opposite side to the convex portion 7a1 of the lower electrode 7. In this case, the direction of the fringe electric field 34 is directed to the longitudinal direction 35c side of the original fringe electric field 34.

  On the other hand, in the second embodiment, even if the positional deviation occurs to some extent, it is possible to suppress the upper surface of the end portion of the partial electrode 8p from being directed to the opposite side to the convex portion 7a1 of the lower electrode 7. That is, even if the positional deviation occurs to some extent, it is possible to maintain the effect of directing the fringe electric field 34 in the second horizontal direction 35b as much as possible, and thus the display quality of the liquid crystal display device.

<Embodiment 3>
The configuration of the pixel 47 of the liquid crystal display device according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 10 is a cross-sectional view showing the pixel configuration of the TFT array substrate 10 according to the third embodiment in the same manner as FIG. In the liquid crystal display device according to the third embodiment, the same or similar components as those described in the first embodiment are denoted by the same reference numerals, and different points will be mainly described below.

  In the third embodiment, the partial electrode 8p is formed flat. The specific positional relationship between the slits 8 s and partial electrodes 8 p of the counter electrode 8 and the unevenness of the lower electrode 7 is the same as in the first embodiment. That is, when the cross-sectional configuration shown in FIG. 10 is viewed in plan, in the X direction, the position of the upper portion of the convex portion 7a1 of the lower electrode 7, the position of the central portion of the slit 8s, and the second interlayer insulating film 13 The position of the upper part of the convex part is substantially aligned. In the X direction, the position of the upper portion of the convex portion 7a2 of the lower electrode 7, the position of the central portion of the partial electrode 8p, and the position of the upper portion of the convex portion of the second interlayer insulating film 13 are substantially aligned. . Furthermore, in the X direction, the position below the recess 7b of the lower electrode 7, the position of the boundary between the slit 8s and the partial electrode 8p, and the position below the recess of the second interlayer insulating film 13 are substantially aligned. .

  Here, in Embodiment 3, a coating type insulating film is used for the interelectrode insulating film 14. Note that the coating-type insulating film has a lower relative dielectric constant than the insulating film formed by CVD or the like when compared with the same film thickness. However, even when a coating-type insulating film is used for the interelectrode insulating film 14, the relative dielectric constant equivalent to that of an insulating film such as CVD and thus the driving voltage can be reduced by reducing the thickness of the portion that generates the fringe electric field. Can be obtained. Since other configurations are the same as those in the first embodiment, description thereof is omitted.

  Next, a manufacturing method of the TFT array substrate 10 according to the third embodiment will be described with reference to FIG. Since the manufacturing method of the third embodiment is the same as that of the first embodiment up to the step of forming the lower electrode 7 (FIG. 7A), the description of the manufacturing method up to that step is omitted. The step of forming the gate terminal contact hole 21 (FIG. 2), the source terminal contact hole 22, the gate terminal pad 23, and the source terminal pad 24 in the manufacturing method according to the third embodiment is also described in the embodiment. 1 is omitted here.

  An interelectrode insulating film 14 is formed by coating so as to cover the entire upper surface (second interlayer insulating film 13, lower electrode 7, connection wiring 19 and the like) of the transparent substrate 10a shown in FIG. Here, the interelectrode insulating film 14 according to the first embodiment is formed in an uneven shape reflecting the unevenness of the second interlayer insulating film 13 and the lower electrode 7. In contrast, the interelectrode insulating film 14 according to the third embodiment is planarized.

  In addition, as a coating type insulating film to be the interelectrode insulating film 14, acrylic, epoxy, polyimide, polyolefin, organic SOG, or the like may be used. Since the interelectrode insulating film 14 is formed thin, it is desirable to select a material having excellent insulating properties, and a non-photosensitive organic insulating film is preferable. In the third embodiment, an organic SOG film having excellent insulating properties, flatness, and high transmittance is used for the interelectrode insulating film 14, and the interelectrode insulating film 14 is the thinnest part (on the convex portion of the lower electrode 7). The film thickness of the portion is 200 nm, and the baking temperature is 230 ° C.

  Next, the second contact hole 16 is formed in the interelectrode insulating film 14 by photolithography and microfabrication technology. As a result, the structure shown in FIG. 11A is formed.

  Next, a transparent conductive film such as ITO or IZO is applied to the entire upper surface of the transparent substrate 10a shown in FIG. 11A (on the interelectrode insulating film 14 and in the second contact hole 16) by, for example, sputtering. Form a film. Then, the transparent conductive film is patterned by photolithography and fine processing technology to form the counter electrode 8 having the slits 8s. Here, the specific positional relationship between the slits 8s and partial electrodes 8p of the counter electrode 8 and the unevenness of the lower electrode 7 is as described above.

  Thus, the structure shown in FIG. 11B is formed. That is, the counter electrode 8 having the slit 8 s electrically connected to the TFT 50 through the first and second contact holes 15 and 16 is formed on the interelectrode insulating film 14.

  The effect of the liquid crystal display device according to the third embodiment configured as described above will be described with reference to FIG. FIG. 12 is a diagram showing the pixel structure of the TFT array substrate 10 and the operation of the liquid crystal molecules in the liquid crystal display device according to the third embodiment, as in FIG.

  According to the third embodiment, the convex portion 7a1 of the lower electrode 7 is formed in the vicinity of the center portion of the slit 8s of the counter electrode 8 so that the interelectrode insulating film 14 is thin. Moreover, since the 1st convex part 7a1 can be arrange | positioned in the 2nd horizontal direction 35b as much as possible with respect to the counter electrode 8, similarly to Embodiment 1, between the counter electrode 8 and the 1st convex part 7a1. The fringe electric field 34 can be directed in the second lateral direction 35b as much as possible. Therefore, as in the first embodiment, the transmittance in one pixel 47 can be made uniform and the average transmittance of the entire one pixel 47 can be improved, so that the display quality of the liquid crystal display device is improved. be able to.

  Further, according to the third embodiment, the recess 7b1 of the lower electrode 7 is formed so that the interelectrode insulating film 14 is thick in the vicinity of the end of the slit 8s. For this reason, the charge to the interelectrode insulating film 14 due to the electric field concentration at the end of the slit 8s is reduced, and an effect of suppressing the image sticking phenomenon is obtained. Further, in the third embodiment, the counter electrode 8 is formed flat. For this reason, even when the concave / convex depth of the lower electrode 7 is increased in order to extend the fringe electric field 34 in the lateral direction, the thickness of the liquid crystal layer does not need to be affected by the concave / convex portions. It is possible to suppress a decrease in contrast due to variations in the image quality.

  In the above description of the third embodiment, an example in which a non-photosensitive coating type insulating film is used for the interelectrode insulating film 14 has been described. However, a photosensitive organic insulating film may be used. In this case, a material having high flatness is desirable. Further, the material is not necessarily a liquid coating material as long as it has a high leveling property, and may be, for example, polysilazane.

<Embodiment 4>
The configuration of the pixel 47 of the liquid crystal display device according to Embodiment 4 of the present invention will be described with reference to FIGS. FIG. 13 is a plan view showing a pixel configuration of the TFT array substrate 10 according to the fourth embodiment. FIG. 14 is a cross-sectional view illustrating a pixel configuration of the TFT array substrate 10 according to the fourth embodiment. FIG. 13 shows one of the pixels 47 of the TFT array substrate 10, and FIG. 14 is a cross-sectional view taken along the line AA of FIG. In the liquid crystal display device according to the fourth embodiment, the same or similar components as those described in the third embodiment are denoted by the same reference numerals, and different points will be mainly described below.

  In the fourth embodiment, both ends of one partial electrode 8p are located between the upper part of the convex part 7a1 and the upper part of the convex part 7a2 in plan view. That is, in the third embodiment, the convex portion 7a of the lower electrode 7 is provided below the central portion of the partial electrode 8p (FIG. 10), whereas in the fourth embodiment, the convex portion of the lower electrode 7 is provided. The part 7a is configured not to be provided below the central part of the partial electrode 8p (FIG. 14).

  In addition, as a manufacturing method of the TFT array substrate 10 according to the fourth embodiment, in the manufacturing method described in the third embodiment, the pattern of the photoengraving that forms the unevenness in the second interlayer insulating film 13 is adjusted, What is necessary is just to adjust the pattern of the photoengraving which forms the slit 8s in the counter electrode 8. FIG. The other steps are the same as those in the third embodiment, and thus description thereof is omitted.

  Since the liquid crystal display device according to the fourth embodiment configured as described above is configured in substantially the same manner as the liquid crystal display device according to the third embodiment, the liquid crystal display is the same as in the third embodiment. The display quality of the device can be improved.

  Furthermore, according to the fourth embodiment, both end portions of one partial electrode 8p are located between the upper part of the convex part 7a1 and the upper part of the convex part 7a2. Therefore, the interelectrode insulating film 14 is formed thick in the central portion of the partial electrode 8p, and the charge on the interelectrode insulating film 14 due to the electric field concentration at the slit opening end is reduced. Therefore, the image sticking phenomenon can be suppressed. In addition, since the Cs retention capacity formed by the counter electrode 8 and the lower electrode 7 can be reduced, it is possible to reduce the driving load of the TFT 50 that writes charges in the Cs retention capacity. As a result, the TFT 50 Can be miniaturized.

  In addition, although the case where this Embodiment 4 was applied to Embodiment 3 was demonstrated in the above description, it is not restricted to this, It can apply similarly to Embodiment 1,2.

  In the first to fourth embodiments, a liquid crystal display device in which the lower electrode 7 is connected to the common wiring 9 and the drain electrode 5 is connected to the counter electrode 8 (that is, a liquid crystal display device having the counter electrode 8 as a pixel electrode) will be described. did. However, the present invention is not limited to this, and is a liquid crystal display device in which the lower electrode 7 is connected to the drain electrode 5 and the common wiring 9 is connected to the counter electrode 8 (that is, a liquid crystal display device having the lower electrode 7 as a pixel electrode). May be.

  In the first to fourth embodiments, the configuration in which the first interlayer insulating film 12 is provided in the lower layer of the second interlayer insulating film 13 forming the unevenness is described. However, the first interlayer insulating film 12 is omitted and the second interlayer insulating film 12 is omitted. You may comprise only the interlayer insulation film 13.

  In the first to fourth embodiments, an example in which a photosensitive resin film is used for the second interlayer insulating film 13 has been described. However, a non-photosensitive resin film may be used if irregularities are formed. In that case, after applying and baking a non-photosensitive resin film, a similar concavo-convex pattern may be formed with a resist, and the concavo-convex pattern may be transferred to the resin film by an existing dry etching technique.

  In the first to fourth embodiments, the liquid crystal display device in which a channel etch type TFT is formed as the TFT 50 has been described. However, another TFT such as a top gate type may be formed as the TFT 50.

  In the first to fourth embodiments, the case where the direction of the slit 8s of the counter electrode 8 is parallel to the source wiring 44 has been described as an example, but the present invention is not limited to this. The direction of the slit of the counter electrode 8 is not limited to the direction parallel to the source wiring 44 but may be any direction or a combination of any different directions. In addition, the said Embodiment 1-4 can be implemented in combination as appropriate.

  In the first to fourth embodiments, the case where the pitch of the slits 8s of the counter electrode 8 is the same in the pixel has been described as an example. However, the present invention is not limited to this. As long as the positional relationship between the slit 8s and the unevenness of the counter electrode 8 satisfies the first to fourth embodiments, any pitch or any different pitch may be combined in one pixel. In addition, the said Embodiment 1-4 can be implemented in combination as appropriate.

  In addition, the above description demonstrates embodiment of this invention and this invention is not limited to the above embodiment. Within the scope of the present invention, the present invention can be freely combined with each other, or can be appropriately modified or omitted.

  DESCRIPTION OF SYMBOLS 10 TFT array substrate, 7 Lower electrode, 7a, 7a1, 7a2 Convex part, 7b Concave part, 8 Counter electrode, 8p Partial electrode, 8s Slit, 10a Transparent substrate, 12 1st interlayer insulation film, 13 2nd interlayer insulation film, 14 Interelectrode insulating film, 15 first contact hole, 16 second contact hole, 50 TFT.

Claims (7)

A first substrate;
A second substrate disposed opposite to the first substrate;
A liquid crystal layer sandwiched between the first and second substrates,
The first substrate is
A first electrode having an upper surface on which irregularities in the shape of a sine wave or cosine wave are arranged in a predetermined direction in a cross-sectional view;
A second electrode having a slit formed on the first electrode via an inter-electrode insulating film and a partial electrode that is a portion between the two slits adjacent in the predetermined direction; Including
Is divided by a plurality of bottom of front Symbol irregularities, the advance into a plurality of protrusion upper arranged in the direction defined, the second electrode in correspondence with each of the convex portions in the order of arrangement of the plurality of protrusions The partial electrodes and the slits are alternately arranged ,
The top surface of the partial electrode of the second electrode and the top surface of the interelectrode insulating film exposed from the slit of the second electrode reflect the unevenness in the shape of a sine wave or cosine wave of the first electrode. A liquid crystal display device provided with unevenness . The liquid crystal display device according to claim 1,
The upper surface of the partial electrode is a liquid crystal display device including an inclined surface inclined in a convex shape from an end portion of the partial electrode toward a central portion. The liquid crystal display device according to claim 1 or 2,
The first substrate is
Further comprising an interlayer insulating film formed under the first electrode and having an upper surface on which irregularities similar to the irregularities are disposed in the predetermined direction;
The liquid crystal display device, wherein the unevenness of the first electrode reflects the unevenness of the interlayer insulating film. The liquid crystal display device according to claim 3,
The liquid crystal display device, wherein the interlayer insulating film is made of a photosensitive resin film. The liquid crystal display device according to claim 1,
The pitch of the said unevenness | corrugation of the said 1st electrode is 3-5 micrometers, The depth of the said unevenness | corrugation is 0.1-0.5 micrometer. A liquid crystal display device according to any one of claims 1 to 5,
The first substrate is
A liquid crystal display device further comprising a thin film transistor for controlling a voltage applied to the second electrode. (A) forming a thin film transistor on a substrate;
(B) A first surface having a first contact hole on the substrate and the thin film transistor, and having a sine wave or cosine wave shape unevenness arranged in a predetermined direction in a sectional view. 1 forming an insulating film;
(C) forming a first electrode having an upper surface provided with unevenness reflecting the unevenness on the upper surface of the first insulating film;
(D) forming a second insulating film having a second contact hole on the upper surface of the first electrode;
(E) a slit electrically connected to the thin film transistor through the first and second contact holes on the second insulating film, and two slits adjacent in the predetermined direction. Forming a second electrode having a partial electrode that is a portion in between,
Wherein in step (e), is divided by a plurality of bottom of front Symbol irregularities, the plurality of the protrusion upper arranged in a predetermined direction, in correspondence to each of said convex portions in the order of the plurality of protrusions The slits are formed in the second electrode so that the partial electrodes and the slits of the second electrode are alternately arranged , and the upper surface of the partial electrode of the second electrode, and the second wherein the upper surface of the second insulating film, unevenness reflecting the unevenness of the sine wave or cosine wave shape of the first electrode Ru is disposed, a method of manufacturing a liquid crystal display device which is exposed from the slit of the electrode.

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