JP6047732B2 - Amusement stand - Google Patents

Description

  The present invention relates to a game machine represented by a spinning machine (slot machine) and a ball game machine (pachinko machine).

  Conventional game machines (for example, slot machines, pachinko machines) are configured so that a player can obtain a predetermined profit by stopping and displaying a predetermined combination of symbols along an effective winning line of a symbol display unit. Or by allowing a player to obtain a predetermined profit by allowing a game ball to enter a predetermined winning opening provided in the game area (see, for example, Patent Document 1).

JP 2008-200302 A

  However, the conventional game machine has room for improvement in the CPU register and the program using the register.

  An object of the present invention is to provide a gaming machine characterized by a CPU register and a program using the register.

  The present invention is a game machine including a microcomputer including a CPU, a ROM storing at least a control program, and a RAM capable of temporarily storing data, wherein the game machine is a pachinko machine or a slot machine. The CPU has at least a first register, the CPU has at least a second register, and the first register sets a value by any one of a plurality of methods. At least one of the plurality of methods is a first method, the first method is a method of setting a value by a direct value, and the CPU Among the functions for setting a value in the register, the function performed based on the receipt of the LD instruction has only the function for setting a value by the first method. The register is a flag register, one bit of the second register is a bit that functions as a first flag, and one bit of the second register is a bit that functions as a second flag And the control program is a program including a command for changing the first flag.

  According to the gaming machine according to the present invention, it is possible to provide a gaming machine characterized by a CPU register and a program using the register.

It is the external appearance perspective view which looked at the pachinko machine from the front side (player side). It is the external view which looked at the pachinko machine from the back side. It is the schematic front view which looked at the game board from the front. The circuit block diagram of a control part is shown. (A) An example of the stop symbol form of the special figure is shown. (B) An example of a stop symbol form of a decorative symbol is shown. (C) An example of a usual stop display symbol is shown. FIG. 3 is a diagram showing only a main part of a basic circuit 302 extracted from a main control part 300. (A) It is the figure which showed the memory map of CPU304. (B) It is the figure which showed the detail of the RWM area | region of the memory map shown to (a). (C) It is the figure which showed the I / O map of CPU304. It is a flowchart which shows the flow of the initialization process. It is a time chart of the starting process after a system reset. It is a flowchart which shows the flow of a main control part main process. (A) It is a flowchart which shows the flow of the T-registration check process performed by the initial setting 1. FIG. (B) It is an example of the program list of T cash register check processing. (A) It is a flowchart which shows the flow of the T cash register check process which concerns on a modification. (B) It is an example of the program list of the T cash register check process concerning a modification. It is the figure which extracted and showed only the LD command from the program list of FIG.11 (b). It is a flowchart which shows the flow of a main control part timer interruption process. (A) It is a flowchart of the main process which CPU of a 1st sub control part performs. (B) It is a flowchart of the command reception interruption process of a 1st sub control part. (C) It is a flowchart of the timer interruption process of a 1st sub control part. (D) It is a flowchart of the image control process of a 1st sub control part. (A) It is a flowchart of the main process which CPU504 of the 2nd sub control part 500 performs. (B) It is a flowchart of the command reception interruption process of the 2nd sub control part 500. FIG. (C) It is a flowchart of the timer interruption process of the 2nd sub control part 500. FIG. 6 is a diagram illustrating an example of data stored in a ROM 306. FIG. 3 is a diagram illustrating an example of a configuration of instruction data of a main control unit 300. FIG. (A) It is the figure which showed the high-order bit and the low-order bit of the instruction data of the main control part 300. (B) It is the figure which showed an example of the instruction data table. An example of the movement of the address by the CALL instruction is shown conceptually. It is the figure which showed an example of the command data and supplementary data of a CALL command. (A) It is the figure which showed an example of the structure of the EXESUB instruction. FIG. 20B is a diagram showing an instruction data table in which an EXESUB instruction is assigned to the empty area in FIG. It is the figure which showed notionally an example of the movement of the address by an EXESUB instruction. It shows an example of calling of the top address of a subroutine by the EXESUB instruction. It is the figure which showed an example of the instruction data and the supplementary data of the EXESUB instruction. It is the program list which showed an example of the control program of the main control part timer interruption process. It is the figure which showed the case where the ROM area was comprised so that the ROM control area in which the control program data was memorize | stored might become larger than the area | region which can be called by the EXESUB instruction. (A) (b) It is the figure which showed an example at the time of expanding the area | region of the top address of the subroutine which can be called by the EXESUB instruction (EXESUBmn). (A) A part of the control program of the special figure 2 state update process and the special figure 1 state update process is extracted. (B) A part of the control program for the normal state update process is extracted. (C) A part of a conventional memory read process is extracted. (D) It is the figure which showed a part of variable area | region provided in RAM area (RWM area | region). (E) A part of the memory read processing according to the present embodiment is extracted. It is the figure which compared the machine language of the conventional memory reading process shown in FIG.29 (c), and the machine language of the memory reading process which concerns on this embodiment shown in FIG.29 (e). It is a flowchart which shows the flow of a special figure 1 related lottery process. (A) It is the figure which showed an example of the table for table selection. (B) It is the figure which showed an example of the 1st fluctuation pattern selection table. (C) It is the figure which showed an example of the 2nd fluctuation pattern selection table. (D) It is the figure which showed the reservation number storage area, the random number 1 storage area, and the random number 2 storage area which are provided in the storage area of the RAM 308 corresponding to the addresses F040H to F042H of the RWM area. 3 is an example of a program list showing a part of a definition of a data table stored in a ROM 306 of the main control unit 300 and a part of a definition of a variable storage area provided in a RAM 308. It is a flowchart which shows the flow of a special symbol fluctuation | variation time lottery process. It is an example of a program list of special symbol variation time lottery processing. It is the figure which showed a part of command with which the control part 300 (CPU304) is provided, and its description. (A) It is the figure which showed the high-order bit and the low-order bit of the instruction data of the main control part 300. (B) It is the figure which showed an example of the instruction data table. It is the figure which showed the modification of the table for table selection, the 1st fluctuation pattern selection table, and the 2nd fluctuation pattern selection table. It is a flowchart which shows the flow of the special symbol fluctuation | variation time lottery process which concerns on a modification. (A) It is the figure which showed an example of the initial setting data table memorize | stored in ROM306. (B) It is the figure which showed a part of storage area of RAM308 after the initialization process. (C) It is a flowchart which shows the flow of an initial setting process. It is an example of the program list of an initialization process. (A) It is the figure which showed a part of 2nd special command with which the main-control part 300 is provided. (B) It is the figure which showed the state of the flag register before and behind performing a 2nd special instruction. It is a figure showing an example of processing using a CPJR instruction. (A) It is the figure which showed an example of the program using the conventional command. (B) An example of a program using a CPJR instruction. It is a figure showing an example of other processing using a CPJR instruction. FIG. 10 is a diagram illustrating an example of another process using a CPJR instruction including a process V. It is a figure showing an example of processing using a CPRT instruction. (A) An example of a program using a CPRT instruction. (B) It is the figure which showed an example of the program using the conventional command. FIG. 10 is a diagram illustrating a part of a third special instruction included in the main control unit 300. FIG. 10 is a diagram illustrating a specific example of a “RESmZ n, r” instruction. FIG. 10 is a diagram illustrating a specific example of a “RESmZ n, (rr)” instruction. It is the figure which extracted and showed the part applicable to a RES command from the command map of the main control part. FIG. 10 is a diagram showing a RES instruction according to Modification 1. FIG. 10 is a diagram illustrating a specific example of a RES instruction according to Modification 1. FIG. 10 is a diagram illustrating an example of a program using a RES instruction according to Modification 1. FIG. 10 is a diagram illustrating a RES instruction according to Modification 2. FIG. 10 is a diagram illustrating a specific example of a RES instruction according to Modification 2. FIG. 10 is a diagram illustrating a specific example of a RES instruction according to Modification 2. It is the figure which extracted and showed the part applicable to the RES command which concerns on the modification 2 from the command map of the main control part. It is the figure which showed the other modification of the RES instruction. (A) It is the figure which showed the instruction map at the time of providing the RES instruction which prohibits the access of a predetermined bit, and the instruction map when provided with the RES instruction which prohibits the access of a predetermined bit. (B) It is the figure which showed the example which made the magnitude of the numerical value of the 1st operand of a RES instruction differ, and the arrangement | sequence order of the instruction map of a RES instruction. (A) It is the figure which showed an example of the program starting setting process which is a part of user program. (B) It is the figure which showed an example of the power-on setting process which is a part of user program. It is the figure which showed a part of user program equivalent to a main control part timer interruption process. FIG. 6 is a diagram illustrating the contents of a fourth special instruction included in the main control unit 300 and the ROM area of the main control unit 300. It is the figure which extracted and showed the part applicable to the RST command which concerns on a 4th special command from the command map of the main control part. FIG. 3 is an external perspective view of the slot machine as viewed from the front side (player side). It is a front view showing the slot machine in a state where the front door is opened. The circuit block diagram of a control part is shown. (A) It is the figure which expanded and showed the arrangement | sequence of the symbol given to each reel (left reel, middle reel, right reel) planarly. (B) It is the figure which showed the kind of winning combination (including an operating combination), the symbol combination corresponding to each winning combination, and the operation or payout of each winning combination. It is a flowchart which shows the flow of a main control part main process. It is a flowchart which shows the flow of a main control part timer interruption process. (A) It is a flowchart of the main process which CPU1404 of a 1st sub control part performs. (B) It is a flowchart of the command reception interruption process of a 1st sub control part. (C) It is a flowchart of the timer interruption process of a 1st sub control part. (A) It is a flowchart of the main process which CPU1504 of a 2nd sub control part performs. (B) It is a flowchart of the command reception interruption process of a 2nd sub control part. (C) It is a flowchart of the timer interruption process of a 2nd sub control part. (D) It is a flowchart of the image control process of a 2nd sub control part. It is the figure which showed the other example of application of this invention. FIG. 11 is a diagram illustrating a configuration example of a basic circuit 302 when a microprocessor 3000 is used. It is a flowchart which shows the flow of reset. FIG. 76 is an internal configuration diagram of a random number generation circuit 318 shown in FIG. 75. FIG. 78 is a diagram illustrating an example of processing by a noise filter 3185 illustrated in FIG. 77. FIG. 78 is a diagram showing details of a random number update circuit 3183 shown in FIG. 77. It is a figure which shows the range of the random number output when the maximum value of the random number generation range is not set. It is a figure which shows the range of the random number output when the maximum value different from FIG. 80 is set. It is a figure which shows the range which can acquire a random number in the random number generation range which set the maximum value and the minimum value. It is a figure which shows the derivation source of the random number used with the game machine of this embodiment with a table | surface. 5 is a diagram for explaining a first internal information register prepared in an internal register 3101 of an interrupt control circuit 3100. FIG. 10 is a diagram illustrating an example of abnormality detection in a frequency monitoring circuit 3182. FIG. It is a figure which shows the example of detection of abnormality in the random number monitoring circuit 3184. It is the figure which compared the cycle in which a random number makes a round, and the cycle of a timer interruption. It is a flowchart which shows the flow of a main control part main process. It is a flowchart which shows the flow of the initial setting 2 in a main control part main process. It is a flowchart which shows the flow of the random number generation circuit initial setting process in step S1053. It is a flowchart which shows the flow of a main control part timer interruption process. (A) It is a flowchart which shows the flow of a common drawing relevant lottery process. (B) It is a figure which shows a common drawing lottery table. It is a flowchart which shows the flow of a special figure related lottery process. (A) It is a figure which shows a special drawing lottery table. (B) It is a figure which shows a stop symbol lottery table. It is a flowchart which shows the flow of a device monitoring process. It is the figure which showed the flow of the process which acquires a special figure winning random number and a common winning random number among winning prize reception processes in step S217. (A) It is a figure which shows the operation | movement in the case of power-off. (B) It is a figure which shows the operation | movement in the case of a momentary interruption. It is a figure which shows the problem of a random number generation range. FIG. 80 is a diagram showing a modification of the random number update circuit 3183 described in FIG. 79. It is a flowchart which shows the flow of a payout control part main process. It is a flowchart which shows the flow of a payout control part timer interruption process. 6 is a diagram for explaining a second internal information register prepared in the internal register 3101 of the interrupt control circuit 3100. FIG. FIG. 10 is a diagram for explaining a third internal information register prepared in the internal register 3101 of the interrupt control circuit 3100. FIG. 10 is a diagram for explaining a fourth internal information register prepared in the internal register 3101 of the interrupt control circuit 3100. It is a figure which shows the flow of a system reset including the relationship with random number update. (A) It is the figure which showed typically the process performed by the initial setting of a game control program. (B) It is a figure for demonstrating the concept of the process of (a). 76 is a diagram showing a modification of the reset control circuit 314 of the microprocessor 3000 shown in FIG. 75. FIG. 10 is a timing chart showing an example when a timeout of WDT 3141 occurs only in main control unit 300 out of main control unit 300 and first sub control unit 400. (A) It is the figure which showed the 1st modification of the structure of the main control part. (B) It is the figure which showed the 2nd modification of the structure of the main control part. (C) It is the figure which showed the structural example of the reset circuit comprised including the random delay circuit 317, the voltage monitoring circuit 338, and WDT314. (A) It is the figure which showed the 1st modification of FIG. 109 (c). (B) It is the figure which showed the 2nd modification of FIG. 109 (c). (A) It is the figure which showed the 3rd modification of the reset circuit shown in FIG.109 (c). (B) It is the figure which showed a part of various IC connected to CPU304. It is the figure which showed the 1st modification of the connection of the reset signal output terminal XRST shown in FIG.111 (b). FIG. 5 is a diagram illustrating a basic circuit 302 described with reference to FIG. 4 and a part of various ICs connected to the basic circuit 302; (A) An example of setting a fixed extension time is shown. (B) A setting example of the random extension time is shown. An example of setting the timeout time of WDT 314 is shown. (A)-(d) It is the figure which showed the change of the output signal of a reset output terminal XSRSTO terminal, and the state change of a security mode. (A), (b) It is the figure which showed the example from which the end timing of a fixed extension process and the timing which outputs the signal of H level from reset output terminal XRSTO correspond, but differ in random extension time. (C), (d) It is the figure which showed the example which the completion | finish timing of a fixed extension process and the timing which outputs the signal of H level from reset output terminal XRSTO correspond, but fixed extension time differs. It is the figure which showed the example which changes a reset output signal on the occasion of a fixed extension process. It is the figure which showed the change of the state of an address signal, a data signal, a control signal, and a reset output signal, and a security mode. (A) It is the figure which showed the state change of the other output signal after an external reset. (B) It is the figure which showed the state change of the other output signal after internal reset. (A) It is the figure which showed the other example of the state change of the other output signal after an external reset. (B) It is the figure which showed the other example of the state change of the other output signal after internal reset. (A) It is the figure which showed the example of the start timing of the security mode after an external reset. (B) It is the figure which showed the example of the start timing of the security mode after internal reset. It is the figure which showed the basic concept of this invention. (A) It is the figure which showed the example of a connection of the power supply board | substrate 182 demonstrated using FIG. 2, the payout board | substrate 170, and the main board | substrate 156. FIG. (B) It is the figure which showed the conventional connection aspect corresponding to (a). It is a flowchart which shows the flow of the main control part main process which concerns on a modification, and is a flowchart corresponding to the said FIG. It is a flowchart which shows the flow of the initial setting 2 in a main control part main process. It is a figure for demonstrating an example of the signal output of the predetermined | prescribed output terminal which concerns on this invention. It is a figure for demonstrating an example of the signal output of the predetermined | prescribed output terminal which concerns on this invention. It is the figure which showed the change of the system clock signal at the time of a user reset, a data signal, a control signal, and a reset output signal.

  <Embodiment 1>

Hereinafter, the gaming machine (pachinko machine 100) according to Embodiment 1 of the present invention will be described in detail with reference to the drawings.
<Overall configuration>

  First, the overall configuration of the pachinko machine 100 according to the first embodiment of the present invention will be described with reference to FIG. In addition, the figure is the external appearance perspective view which looked at the pachinko machine 100 from the front side (player side).

  As an external structure, the pachinko machine 100 includes an outer frame 102, a main body 104, a front frame door 106, a door 108 with a ball storage tray, a launching device 110, and a game board 200 on the front surface.

  The outer frame 102 is a wooden frame member having a vertical rectangular shape for fixing to an installation location (island facilities or the like) provided in a gaming machine installation sales shop. The main body 104 is referred to as an inner frame, and is a member that is provided inside the outer frame 102 and serves as a longitudinal rectangular gaming machine base body that is rotatably attached to the outer frame 102 via a hinge portion 112. The main body 104 is formed in a frame shape and has a space 114 inside. In addition, when the main body 104 is opened, an inner frame opening sensor (not shown) that detects the opening of the main body 104 is provided.

  The front frame door 106 is attached to the front surface of the main body 104 on the front side of the pachinko machine 100 so as to be openable and closable with a lock function, and is configured in a frame shape so that the inner side of the front frame door 106 can be opened and closed. Is a door member having an opening. The front frame door 106 is provided with a transparent plate member 118 made of glass or resin at the opening, and a speaker 120 and a frame lamp 122 are attached to the front side. A game area 124 is defined by the rear surface of the front frame door 106 and the front surface of the game board 200. Further, a front frame door opening sensor (not shown) that detects opening of the front frame door 106 when the front frame door 106 is opened is provided.

  The door 108 with a ball storage tray is a door member attached to the lower side of the main body 104 on the front surface of the pachinko machine 100 so as to have a lock function and be openable and closable. The ball storage tray-equipped door 108 is capable of storing a plurality of game balls (hereinafter simply referred to as “balls”), and an upper plate 126 provided with a passage for guiding the game balls to the launching device 110. A lower plate 128 that stores game balls that cannot be stored in the upper plate 126, a ball removal button 130 that discharges the game balls stored in the upper plate 126 to the lower plate 128 by the player's operation, A ball discharge lever 132 that discharges game balls stored in the lower plate 128 to a game ball collection container (common name, dollar box) by operation, and a game ball guided to the launching device 110 by operation of the player 200 ball launching handles 134 for launching into the game area 124, chance buttons 136 for changing the effects of the various effects devices 206 by the player's operation, and the chance button 136 to emit light. Sub button lamp 138, ball lending operation button 140 for instructing ball lending to a card unit (CR unit) installed in the game store, and return operation button for instructing the card unit to return the player's balance 142, and a ball rental display unit 144 for displaying the balance of the player and the state of the card unit. In addition, a lower plate full tank sensor (not shown) that detects that the lower plate 128 is full is provided.

  The launching device 110 is attached to the lower side of the main body 104, and a launching rod 146 that rotates when the ball launching handle 134 is operated by the player, and a launching rod 148 that strikes the game ball at the tip of the launching rod 146. .

  The game board 200 has a game area 124 on the front surface, and is detachably attached to the main body 104 using a predetermined fixing member so as to face the space 114 of the main body 104. The game area 124 can be observed from the opening after the game board 200 is mounted on the main body 104.

  FIG. 2 is an external view of the pachinko machine 100 of FIG. The upper part of the back surface of the pachinko machine 100 has an opening that opens upward, a ball tank 150 for temporarily storing game balls, and a lower part of the ball tank 150 that is positioned below the ball tank 150. A tank rail 154 is provided for guiding a ball passing through the formed communication hole and dropping to the dispensing device 152 located on the right side of the back surface.

  The payout device 152 is formed of a cylindrical member, and includes a payout motor, a sprocket, and a payout sensor (not shown) inside. The sprocket is configured to be rotatable by a payout motor. The sprocket that temporarily passes through the tank rail 154 and flows down into the payout device 152 is temporarily retained, and the payout motor is driven to rotate by a predetermined angle. Thus, the temporarily accumulated game balls are sent one by one downward to the payout device 152.

  The payout sensor is a sensor for detecting the passage of the game ball sent out by the sprocket. When the game ball is passing, either a high signal or a low signal is passed. Either the high signal or the low signal is output to the dispensing control unit 600. The game ball that has passed through the payout sensor passes through a ball rail (not shown) and reaches the upper plate 126 disposed on the front side of the pachinko machine 100. The pachinko machine 100 has this configuration. To pay out the ball to the player.

  On the left side of the payout device 152 in the figure, a main board case 158 that houses the main board 156 that constitutes the main control section 300 that performs control processing for the entire game, and control related to effects based on the processing information generated by the main control section 300 The first sub-board case 162 that houses the first sub-board 160 that constitutes the first sub-control unit 400 that performs processing, and the second sub-board that performs control processing related to effects based on processing information generated by the first sub-control unit 400 An error release switch that constitutes a second sub-board case 166 that houses the second sub-board 164 that constitutes the control unit 500, a payout control unit 600 that performs control processing related to the payout of game balls, and that releases an error by the operation of a game clerk Discharge board case 172 storing the payout board 170 having 168, launch base constituting the launch control unit 630 that performs control processing relating to the launch of the game ball A launch board case 176 that houses 174, a power control unit 660 that supplies power to various electrical gaming machines, and a power switch 178 that turns the power on and off by the operation of a game store clerk and an RWM clear by being operated when the power is turned on A power board case 184 that houses a power board 182 that includes an RWM clear switch 180 that outputs a signal to the main controller 300, and a CR interface 186 that transmits and receives signals between the payout controller 600 and the card unit are provided. ing.

  FIG. 3 is a schematic front view of the game board 200 as viewed from the front. In the game board 200, an outer rail 202 and an inner rail 204 are arranged, and a game area 124 in which a game ball can roll is defined.

  An effect device 206 is disposed in the approximate center of the game area 124. The effect device 206 is provided with a decorative symbol display device 208 substantially in the center, and around the normal symbol display device 210, the first special symbol display device 212, the second special symbol display device 214, and the ordinary device. A symbol holding lamp 216, a first special symbol holding lamp 218, a second special symbol holding lamp 220, and a high-probability medium lamp 222 are provided. Hereinafter, the normal symbol may be referred to as “general symbol” and the special symbol may be referred to as “special symbol”.

  The effect device 206 performs the effect by operating the effect movable body 224, and details thereof will be described later. The decorative symbol display device 208 is a display device for performing various displays used for decorative symbols and effects. In this embodiment, the decorative symbol display device 208 is constituted by a liquid crystal display device (Liquid Crystal Display). The decorative symbol display device 208 is divided into four display areas, a left symbol display area 208a, a middle symbol display area 208b, a right symbol display area 208c, and an effect display area 208d, and the left symbol display area 208a and the middle symbol display area 208b. The right symbol display area 208c displays different decorative symbols, and the effect display area 208d displays an image used for the effect. Furthermore, the position and size of each display area 208a, 208b, 208c, 208d can be freely changed within the display screen of the decorative symbol display device 208. In addition, although the liquid crystal display device is employ | adopted as the decoration symbol display apparatus 208, it is not a liquid crystal display device, What is necessary is just the structure which can display various effects and various game information, for example, a dot matrix display device Other display devices including a 7-segment display device, an organic EL (ElectroLuminescence) display device, a reel (drum) display device, a leaf display device, a plasma display, and a projector may be adopted.

  The general map display device 210 is a display device for displaying a general map, and is configured by a 7-segment LED in this embodiment. The first special figure display device 212 and the second special figure display device 214 are display devices for displaying a special figure, and are configured by 7 segment LEDs in this embodiment.

  The multi-purpose hold lamp 216 is a lamp for indicating the number of general-purpose variable games (details will be described later) that are on hold. It is possible to do. The first special figure hold lamp 218 and the second special figure hold lamp 220 are lamps for indicating the number of special figure variable games (details will be described later) that are being held. In this embodiment, the special figure variable games are displayed. It is possible to hold up to a predetermined number (for example, four). The high-probability medium lamp 222 is a lamp for indicating that the gaming state is a high probability state in which a big hit is likely to occur or a high probability state, and the gaming state is changed from a low probability state in which a big hit is unlikely to occur. Turns on when switching to the probability state, and turns off when switching from the high probability state to the low probability state.

  In addition, there are predetermined ball entrances, for example, a general prize opening 226, a general start port 228, a first special view start port 230, a second special view start port 232, around the effect device 206. A variable winning opening 234 is provided.

  In this embodiment, a plurality of general winning holes 226 are arranged on the game board 200. When a predetermined ball detecting sensor (not shown) detects a ball entering the general winning holes 226 (in the general winning holes 226). In the case of winning, the payout device 152 is driven, and a predetermined number (for example, 10 balls) of balls are discharged to the upper plate 126 as prize balls. The player can freely take out the balls discharged to the upper plate 126. With these configurations, the player can pay out the winning balls to the player based on winning. The ball that has entered the general winning opening 226 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side. In this embodiment, a ball to be paid out to a player as a consideration for winning is sometimes referred to as a “prize ball”, and a ball lent to a player is sometimes referred to as “rental ball”. They are called “balls (game balls)”.

  The normal start port 228 is constituted by a device called a gate or a through chucker for determining whether or not a ball has passed a predetermined area of the game area 124. In this embodiment, the left side of the game board 200 is used. One is arranged. Unlike the ball that has entered the general winning opening 226, the ball that has passed through the usual starting port 228 is not discharged to the amusement island side. When a predetermined ball detection sensor detects that a ball has passed through the general map starting port 228, the pachinko machine 100 starts a general map variable game by the general map display device 210.

  In the present embodiment, only one first special figure starting port 230 is disposed at the center of the game board 200. When a predetermined ball detection sensor detects a ball entering the first special figure starting port 230, a payout device 152, which will be described later, is driven, and a predetermined number (for example, three) of balls is used as a prize ball for the upper plate 126. The special figure changing game by the first special figure display device 212 is started. The ball that has entered the first special figure starting port 230 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side.

  The second special figure starting port 232 is called an electric tulip (electric Chu). In the present embodiment, only one second special figure starting port 232 is disposed directly below the first special figure starting port 230. The second special figure starting port 232 includes a wing member 232a that can be opened and closed to the left and right. When the wing member 232a is closed, it is impossible to enter a ball. When 210 hits and stops and displays the symbol, the blade member 232a opens and closes at a predetermined time interval and a predetermined number of times. When a predetermined ball detection sensor detects a ball entering the second special figure starting port 232, the payout device 152 is driven and a predetermined number (for example, four) of balls is discharged to the upper plate 126 as prize balls. At the same time, the special figure variation game by the second special figure display device 214 is started. The ball that has entered the second special figure starting port 232 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side.

  The variable winning opening 234 is called a large winning opening or an attacker, and in the present embodiment, only one variable winning opening 234 is disposed below the center of the game board 200. The variable winning opening 234 includes a door member 234a that can be opened and closed. When the door member 234a is closed, it is impossible to enter a ball, and the special figure display device stops the jackpot symbol when the special figure variable game is won. When displayed, the door member 234a opens and closes at a predetermined time interval (for example, an opening time of 29 seconds and a closing time of 1.5 seconds) and at a predetermined number of times (for example, 15 times). When a predetermined ball detection sensor detects a ball entering the variable winning opening 234, the payout device 152 is driven to discharge a predetermined number (for example, 15 balls) of balls to the upper plate 126 as prize balls. The ball that entered the variable winning opening 234 is guided to the back side of the pachinko machine 100 and then discharged to the amusement island side.

  Further, a plurality of disc-shaped hitting direction changing members 236 called a windmill and a plurality of game nails 238 are arranged in the vicinity of these winning openings and start openings, and at the bottom of the inner rail 204, After guiding a ball that has not won any prize opening or start opening to the back side of the pachinko machine 100, an out opening is provided for discharging to the game island side.

This pachinko machine 100 supplies the ball stored in the upper plate 126 by the player to the launch position of the launch rail, drives the launch motor with strength according to the operation amount of the player's operation handle, and launches 146 Further, the outer rail 202 and the inner rail 204 are passed by the launcher 148 and driven into the game area 124. Then, the ball that has reached the upper part of the game area 124 falls downward while changing the advancing direction by the hitting direction changing member 236, the game nail 238, etc. (Outside the first special figure starting port 230, the second special figure starting port 232), winning out any winning port or starting port, or just passing through the normal start port 228, the out port 240 To reach.
<Directing device 206>
Next, the rendering device 206 of the pachinko machine 100 will be described.

  On the front side of the effect device 206, a warp device 242 and a stage 244 are arranged in an area where the game ball can roll, and an effect movable body 224 is arranged in an area where the game ball cannot roll. . In addition, a decorative symbol display device 208 and a shielding device 246 (hereinafter sometimes referred to as a door) are disposed on the back side of the effect device 206. That is, in the effect device 206, the decorative symbol display device 208 and the shielding means are located behind the warp device 242, the stage 244, and the effect movable body 224.

  The warp device 242 discharges the game balls that have entered the warp inlet 242a provided at the upper left of the effect device 206 to the stage 244 below the front surface of the effect device 206 from the warp outlet 242b.

The stage 244 can roll a ball discharged from the warp outlet 242b, a ball carried on by a nail of the game board 200, or the like, and the passed ball is a first special figure starting port 230 at the center of the stage 244. A special route 244a is provided to facilitate entry into the golf course.

  In this embodiment, the effect movable body 224 includes an upper arm portion 224a and a forearm portion 224b simulating the upper arm and forearm of a human right arm. A forearm motor (not shown) that rotates the forearm 224b at a position is provided. The effect movable body 224 moves in front of the decorative symbol display device 208 by the upper arm motor and the forearm motor.

The shielding device 246 includes a lattice-like left door 246a and right door 246b, and is disposed between the decorative symbol display device 208 and the front stage 244. Belts wound around two pulleys (not shown) are fixed to the upper portions of the left door 246a and the right door 246b, respectively. That is, the left door 246a and the right door 246b move to the left and right as the belt driven by the motor through the pulley moves. When the left door 246a and the right door 246b are closed, the shielding means shields the inner end portions thereof so that it is difficult for the player to visually recognize the decorative symbol display device 208. In the state where the left door 246a and the right door 246b are opened, each inner end portion slightly overlaps the outer end portion of the display screen of the decorative symbol display device 208, but the player can visually recognize all of the display of the decorative symbol display device 208. It is. In addition, the left door 246a and the right door 246b can be stopped at arbitrary positions, respectively, for example, only a part of the decorative design so that the player can identify which decorative design the displayed decorative design is. Can be shielded. In addition, the left door 246a and the right door 246b may be configured so that a part of the decorative symbol display device 208 behind the lattice hole can be visually recognized, or the shoji part of the lattice hole is closed with a translucent lens body. The display by the decorative symbol display device 208 may be made vaguely visible to the player, or the shoji part of the holes in the lattice is completely blocked (shielded), and the decorative symbol display device 208 behind is made completely invisible. Also good.
<Control unit>

  Next, the circuit configuration of the control unit of the pachinko machine 100 will be described in detail with reference to FIG. This figure shows a circuit block diagram of the control unit.

The control unit of the pachinko machine 100 is roughly divided into a main control unit 300 that mainly controls the progress of a game (for example, detection of an operation by a player, transition of a game state, game medium payout control, determination of success / failure, etc.) In response to a command signal transmitted by the main control unit 300 (hereinafter simply referred to as “command”), the first sub control unit 400 that mainly controls the production and the command transmitted from the first sub control unit 400 A second sub-control unit 500 that controls various devices based on it, a payout control unit 600 that mainly performs control related to payout of game balls in accordance with a command transmitted by the main control unit 300, and a launch that controls the launch of game balls A control unit 630 and a power control unit 660 that controls the power supplied to the pachinko machine 100 are configured.
<Main control unit>
First, the main control unit 300 of the pachinko machine 100 will be described.

  The main control unit 300 includes a basic circuit 302 that controls the entire main control unit 300. The basic circuit 302 includes a CPU 304, a ROM 306 for storing control programs and various data, and temporary data. RAM 308 for storing data, I / O 310 for controlling input / output of various devices, counter timer 312 for measuring time and frequency, and WDT 314 for monitoring abnormalities in program processing are mounted. . Note that other storage devices may be used for the ROM 306 and the RAM 308, and this is the same for the first sub-control unit 400 described later. The CPU 304 of the basic circuit 302 operates by inputting a clock signal of a predetermined period output from the crystal oscillator 316b as a system clock.

  In addition, the basic circuit 302 includes a counter circuit 318 used as a hardware random number counter that changes a numerical value in the range of 0 to 65535 each time a clock signal output from the crystal oscillator 316a is received (this circuit includes two circuits). And a predetermined ball detection sensor, for example, a sensor that detects a game ball passing through each start port, winning port, variable winning port, front frame door opening sensor, and inner frame opening sensor. And a sensor circuit 322 for receiving signals output from various sensors 320 including a lower plate full sensor and outputting a comparison result with an amplification result or a reference voltage to the counter circuit 318 and the basic circuit 302, and a predetermined symbol display device For example, a drive circuit 324 for performing display control of the first special figure display device 212 and the second special figure display device 214, a predetermined symbol display device, A drive circuit 326 for performing display control of the general-purpose display device 210, and various status display units 328 (for example, a general-purpose reservation lamp 216, a first special figure reservation lamp 218, a second special figure reservation lamp 220, a high-probability medium) A drive circuit 330 for performing display control of the lamp 222 and the like, and various solenoids 332 for opening and closing a predetermined movable member, for example, a blade member 232a of the second special figure starting port 232, a door member 234a of the variable winning port 234, and the like. A drive circuit 334 for controlling the above is connected.

  When the ball detection sensor 320 detects that a ball has won the first special figure starting port 230, the sensor circuit 322 outputs a signal indicating that the ball has been detected to the counter circuit 318. Upon receiving this signal, the counter circuit 318 latches the value of the counter corresponding to the first special figure starting port 230 at that timing, and stores the latched value in the built-in counter value corresponding to the first special figure starting port 230. Store in the register. Similarly, when the counter circuit 318 receives a signal indicating that the second special figure starting port 232 has won a ball, the counter circuit 318 latches the value at the timing of the counter corresponding to the second special figure starting port 232. The latched value is stored in a built-in counter value storage register corresponding to the second special figure starting port 232.

  Further, an information output circuit 336 is connected to the basic circuit 302, and the main control unit 300 is connected to an information input circuit 350 provided in an external hall computer (not shown) or the like via this information output circuit 336. The game information (for example, game state) of the machine 100 is output.

  In addition, the main control unit 300 is provided with a voltage monitoring circuit 338 that monitors the voltage value of the power source supplied from the power source control unit 660 to the main control unit 300. The voltage monitoring circuit 338 is a voltage value of the power source. Is less than a predetermined value (9v in this embodiment), a low voltage signal indicating that the voltage has dropped is output to the basic circuit 302.

  In addition, the main control unit 300 is provided with a start signal output circuit (reset signal output circuit) 340 that outputs a start signal (reset signal) when the power is turned on. When an activation signal is input, game control is started (details will be described later).

The main control unit 300 includes an output interface for transmitting a command to the first sub-control unit 400 and an output interface for transmitting a command to the payout control unit 600. With this configuration, the first control unit 300 Communication with the sub-control unit 400 and the payout control unit 600 is enabled. Information communication between the main control unit 300 and the first sub-control unit 400 and the payout control unit 600 is one-way communication. The main control unit 300 sends commands and the like to the first sub-control unit 400 and the payout control unit 600. The first sub control unit 400 and the payout control unit 600 are configured such that signals such as commands cannot be transmitted to the main control unit 300.
<Sub control unit>

  Next, the first sub control unit 400 of the pachinko machine 100 will be described. The first sub-control unit 400 includes a basic circuit 402 that controls the entire first sub-control unit 400 mainly based on commands transmitted from the main control unit 300. The basic circuit 402 includes a CPU 404 and ROM 406 for storing control programs and various effects data, RAM 408 for temporarily storing data, I / O 410 for controlling input / output of various devices, and for measuring time, frequency, etc. The counter timer 412 is mounted. The CPU 404 of the basic circuit 402 operates by inputting a clock signal of a predetermined period output from the crystal oscillator 414 as a system clock. The ROM 406 may store the control program and various effect data in separate ROMs.

  The basic circuit 402 includes a sound source IC 416 for controlling the speaker 120 (and amplifier), a drive circuit 420 for controlling various lamps 418 (for example, the chance button lamp 138), and a shielding device 246. A drive circuit 432 for performing drive control, a shielding device sensor 430 that detects the current position of the shielding device 246, a chance button detection sensor 426 that detects pressing of the chance button 136, a shielding device sensor 430, and a chance button detection sensor The sensor circuit 428 that outputs the detection signal from the 426 to the basic circuit 402, and the image data stored in the ROM 406 based on the signal from the CPU 404 are read, and the display image is generated using the work area of the VRAM 436 to decorate VDP 434 (image) for displaying an image on the symbol display device Are connected Oh and display processor), the.

  Next, the second sub control unit 500 of the pachinko machine 100 will be described. The second sub-control unit 500 includes a basic circuit 502 that receives the control command transmitted from the first sub-control unit 400 via the input interface and controls the entire second sub-control unit 500 based on the control command. The basic circuit 502 includes a CPU 504, a RAM 508 for temporarily storing data, an I / O 510 for controlling input / output of various devices, and a counter timer for measuring time and frequency 512 is installed. The CPU 504 of the basic circuit 502 operates by inputting a clock signal of a predetermined period output from the crystal oscillator 514 as a system clock, and controls a control program and data for controlling the entire second sub-control unit 500, and an image display A ROM 506 storing data and the like is provided.

The basic circuit 502 includes a drive circuit 516 for controlling the drive of the effect movable body 224, an effect movable body sensor 424 that detects the current position of the effect movable body 224, and a detection signal from the effect movable body sensor 424. Is output to the basic circuit 502, a game board lamp drive circuit 530 for controlling the game board lamp 532, and a game table frame lamp drive for controlling the game table frame lamp 542 The circuit 540 is connected to a serial communication control circuit 520 that performs lighting control by serial communication between the game board lamp drive circuit 530 and the game stand frame lamp drive circuit 540.
<Discharge control unit, launch control unit, power supply control unit>

  Next, the payout control unit 600, the launch control unit 630, and the power supply control unit 660 of the pachinko machine 100 will be described.

  The payout control unit 600 controls the payout motor 602 of the payout device 152 mainly based on a command signal or the like transmitted from the main control unit 300, and a prize ball or a rental ball based on a control signal output from the payout sensor 604 It is detected whether or not the payout has been completed, and communication with a card unit 608 provided separately from the pachinko machine 100 is performed via the interface unit 606.

  The launch control unit 630 outputs a control signal output from the payout control unit 600 to permit or stop the launch, or a launch intensity output circuit provided in the ball launch handle 134 to operate the ball launch handle 134 by the player. Based on a control signal instructing the launch intensity according to the amount, control of the launch motor 632 that drives the launcher 146 and launcher 148, and control of the ball feeder 634 that supplies the ball from the upper plate 126 to the launcher 110 I do.

The power control unit 660 converts the AC power supplied from the outside to the pachinko machine 100 into a DC voltage, converts it to a predetermined voltage, and controls each control unit such as the main control unit 300 and the first sub control unit 400, the payout device 152, etc. Supply to each device. Further, the power supply control unit 660 supplies a power storage circuit (for example, a power supply circuit) for supplying power to a predetermined part (for example, the RAM 308 of the main control unit 300) for a predetermined period (for example, 10 days) even after the external power supply is cut off. , Capacitor). In the present embodiment, a predetermined voltage is supplied from the power supply control unit 660 to the payout control unit 600 and the second sub control unit 500, and the main control unit 300, the second sub control unit 500, and the launch control unit are supplied from the payout control unit 600. Although the predetermined voltage is supplied to 630, the predetermined voltage may be supplied to each control unit and each device through another power supply path.
<Type of design>

  Next, using FIGS. 5A to 5C, the first special symbol display device 212, the second special symbol display device 214, the decorative symbol display device 208, and the normal symbol display device 210 of the pachinko machine 100 are stopped and displayed. The types of special maps and general maps to be described will be described. FIG. 4A shows an example of the stop symbol form of the special figure.

  The special figure 1 variable game is started on the condition that the first start port sensor detects that the ball has entered the first special figure start port 230, and the ball has entered the second special figure start port 232 The special figure 2 variable game is started on the condition that the second start port sensor has detected. When the special figure 1 variable game is started, the first special symbol display device 212 performs “variable display of special figure 1” by repeating all lighting of seven segments and lighting of one central segment. In addition, when the special figure 2 variable game is started, the second special symbol display device 214 displays “fluctuation display of special figure 2” which repeats lighting of all seven segments and lighting of one central segment. Do. These “variation display of special figure 1” and “variation display of special figure 2” correspond to an example of the symbol fluctuation display according to the present invention. Then, when the variation time determined before the variation start of the special figure 1 (corresponding to the variation time referred to in the present invention) elapses, the first special symbol display device 212 stops and displays the special symbol form of the special figure 1. When the variation time determined before the start of variation 2 (this also corresponds to the variation time according to the present invention) has elapsed, the second special symbol display device 214 stops and displays the stop symbol form of the special diagram 2. Therefore, from the start of “figure display of special figure 1” until the stop symbol form of special figure 1 is stopped, or after the start of “fluctuation display of special figure 2”, the stop symbol form of special figure 2 is displayed. Until stop display corresponds to an example of the symbol variation stop display referred to in the present invention, hereinafter, after the “variable display of special figure 1 or 2” is started, the stop symbol form of special figure 1 or 2 is stopped and displayed. The series of displays up to is referred to as symbol variation stop display. As will be described later, the symbol variation stop display may be continuously performed a plurality of times. FIG. 10A shows 10 types of special drawings from “Special Figure A” to “Special Figure J” as stop symbol forms in the symbol variation stop display, and the white portions in the figure are turned off. The location of the segment to be displayed is shown, and the black portion indicates the location of the segment to be lit.

  “Special Figure A” is a 15 round (15R) special jackpot symbol, and “Special Figure B” is a 15R jackpot symbol. In the pachinko machine 100 according to the present embodiment, as will be described later, the determination as to whether or not the big hit in the special figure variable game is made by lottery of hardware random numbers, and the decision as to whether or not it is a special big hit is made by lottery of software random numbers. The difference between the jackpot and the special jackpot is the difference in whether the probability of winning the jackpot is high (special jackpot) or low (jackpot) in the next special figure variation game. Hereinafter, a state having a high probability of winning the jackpot is referred to as a special figure high probability state, and a state having a low probability is referred to as a special figure low probability state. Moreover, after the 15R special jackpot game ends and after the 15R jackpot game ends, both shift to the time-saving state. Although the time reduction will be described in detail later, the state that shifts to the time reduction state is referred to as a normal high probability state, and the state that does not shift to the time reduction state is referred to as a normal low probability state. “Special figure A”, which is a 15R special jackpot symbol, is a special figure high probability normal figure high probability state, and “Special figure B”, which is a 15R jackpot symbol, is a special figure low probability ordinary figure high probability state. These “special chart A” and “special chart B” are symbols that give a relatively large profit amount to the player.

  “Special figure C” is a 2R jackpot symbol called sudden probability change, and is a special figure high probability normal figure high probability state. That is, “Special Figure C” is 2R compared to “Special Figure A” which is 15R. "Special figure D" is a 2R jackpot symbol called sudden time reduction, and is a special figure low probability normal figure high probability state. That is, “Special Figure D” is 2R compared to “Special Figure B” which is 15R.

  “Special figure E” is a 2R jackpot symbol called hidden probability change, and is a special figure high probability normal figure low probability state. "Special figure F" is a 2R jackpot symbol suddenly called normal, and is a special figure low probability normal figure low probability state. These “special drawing E” and “special drawing F” are both 2R and are in a state in which they do not shift to the time-saving state.

  "Special figure G" is a first small hit symbol, and "Special figure H" is a second small hit symbol, both of which are in a special figure low probability normal figure low probability state. The small hit here is equivalent to the same short hit big hit with 2R. That is, “Special Figure G” and “Special Figure H” are in the same state as “Special Figure F”, but the effects displayed on the decorative symbol display device 208 are different in both cases. By providing “G”, “Special Figure H”, and “Special Figure F”, the interest of the game is enhanced.

  In addition, “Special Figure I” is a first off symbol, and “Special Figure J” is a second off symbol, and the profit amount given to the player is a relatively small profit amount.

  In the pachinko machine 100 of the present embodiment, symbols other than “Special Figure A” are prepared as 15R special jackpot symbols, and the same applies to other symbols such as 15R jackpot symbols.

  FIG. 5B shows an example of a decorative design. There are 10 types of decoration patterns of the present embodiment: “Decoration 1” to “Decoration 10”. The first start port sensor detects that a ball has won the first special figure start port 230 or the second special view start port 232, that is, the ball has entered the first special view start port 230; or On the condition that the second start port sensor detects that a ball has entered the second special symbol start port 232, the left symbol display area 208a, the middle symbol display area 208b, and the right symbol display of the decorative symbol display device 208 are displayed. Displayed in the order of “decoration 1” → “decoration 2” → “decoration 3” →... “Decoration 9” → “decoration 10” → “decoration 1” →... “Decoration display of decorative pattern” is performed. When the 15R jackpot of “Special Figure B” is notified, a symbol combination (for example, “decoration 1—decoration 1—decoration”) corresponding to the 15R jackpot corresponding to the 15R jackpot is displayed in the symbol display areas 208a to 208c. 1 ”or“ decoration 2—decoration 2—decoration 2 ”). When the 15R special jackpot of “special drawing A” is notified, a combination of three symbols of the same odd number of decorative symbols (for example, “decoration 3—decoration 3—decoration 3” or “decoration 7—decoration 7—decoration 7”). Etc.) is stopped and displayed.

  In addition, the 2R jackpot called “hidden probability change” of “Special Figure E”, the 2R jackpot called “Special Figure F” suddenly, or the first small hit of “Special Figure G”, “Special Figure H” When notifying the second small hit, “decoration 1-decoration 2—decoration 3” is stopped and displayed. Furthermore, in order to notify the 2R jackpot called “sudden change” of “special drawing C” or the 2R jackpot called “sudden time reduction” of “special drawing D”, “decoration 1-decoration 3—decoration 5” is displayed. Stop display. On the other hand, when notifying the first deviation of “Special Figure I” and the second deviation of “Special Figure J”, the symbol combination other than the symbol combination shown in FIG. 5B is stopped in the symbol display areas 208a to 208c. indicate.

FIG.5 (c) shows an example of the usual stop display symbol. In the present embodiment, there are two types of stoppage display modes for ordinary maps: “general diagram A” which is a winning symbol and “general symbol B” which is a missed symbol. Based on the fact that the above-mentioned gate sensor has detected that a sphere has passed through the general-purpose start opening 228, the normal symbol display device 210 repeats all lighting of the seven segments and lighting of the central one segment. Perform a “normal change display”. Then, when notifying the winning of the common figure variable game, the “normal figure A” is stopped and displayed, and when notifying the usual figure variable game, the “normal figure B” is stopped and displayed. In FIG. 5C, the white portions in the figure indicate the segment locations where the light is turned off, and the black portions indicate the location where the segments are turned on.
<Basic circuit of main control unit>

  Next, the basic circuit 302 of the main controller 300 will be described in detail. FIG. 6 is a diagram showing only the main part of the basic circuit 302 extracted from the main control part 300.

The basic circuit 302 of the main control unit 300 includes a CPU 304 that controls the entire main control unit 300, a ROM 306 that stores a control program executed by the CPU 304 and various data referred to by the CPU 304, and the CPU 304 temporarily stores data. RAM 308 for storing.
<Built-in register of CPU of main control unit>

  The CPU 304 is a control register for controlling a counter circuit, a timer circuit, a serial communication circuit, a random number circuit, an arithmetic circuit, a reset / interrupt controller, and the like, and a built-in register such as a register used when the CPU 304 executes a control program Is provided. The built-in registers include a T register (special register), a general purpose register, a program counter (PC), an instruction register, etc., which are one of the features of the present invention. The type of general-purpose register is not particularly limited, but in this embodiment, an 8-bit register including an I register, an A register, an F register, a B register, a C register, a D register, an E register, an H register, and an L register is provided. The B and C registers, the D and E registers, and the H and L registers also function as 16-bit registers (pair registers) of the BC, DE, and HL registers that can perform 16-bit operations, respectively. It is configured.

  In this embodiment, the value of the interrupt vector (interrupt vector read from a predetermined device) output from the built-in device is the lower 8 bits, and the content of the I register (interrupt vector register, interrupt register) is the upper 8 bits. A 16-bit address is read as an interrupt processing address, and is branched (jumped) to an interrupt processing to be described later. For example, when an interrupt processing request is generated when the value of the I register is 00H and the value of the interrupt vector is 60H, this is indicated by 0060H (the upper byte is 00H of the I register and the lower byte is 60H of the interrupt vector). A 2-byte address (for example, 0412H) is loaded to the PC with the value (for example, 12H) stored at the address to be stored as the lower byte, and the value (for example, 04H) stored at the address indicated by 0061H as the upper byte. Thus, a branch (jump) is made to an interrupt process using this address as the head address.

  When an instruction is executed, the F register sequentially executes the S flag (sign flag), Z flag (zero flag), SZ flag (second zero flag), H flag (half carry flag) from bit 7 in the F register according to the execution result. , Bit 3 (empty bit), P / V flag (parity / overflow flag), N flag (subtract flag), and C flag (carry flag) change to 1 or 0 or do not change Or The SZ flag changes in the same way as the Z flag for instructions that change the Z flag, and all LD instructions of Z80 compatible instructions, all 16-bit arithmetic operation instructions (including INC instructions and DEC instructions), and RLCA of rotate shift instructions. It changes with an instruction, an RLA instruction, an RRCA instruction, an RRA instruction, and an “INA, (n)” instruction.

  Note that the 16-bit arithmetic instruction ADC instruction and SBC instruction change the Z flag, the other instructions do not change the Z flag, and the 16-bit arithmetic instruction changes the SZ flag. In addition, in the “INA, (n)” instruction, the SZ flag changes and the Z flag does not change. The position of the SZ flag or empty bit in the F register may be a bit other than the above-described bits. Note that the SZ flag may not be changed in the case of a special instruction described later.

  In the present embodiment, A ′, F ′, B ′, A ′, F ′, B ′, A ′, F ′, B ′, A, F, B, C, D, E, H, and L are used as auxiliary registers (back registers) corresponding to the general-purpose registers (main registers). Each of the general-purpose registers C ′, D ′, E ′, H ′, and L ′ is provided, but only the T register that is a special register is not provided with an auxiliary register. Therefore, the usage of the T register is limited, and the usage frequency of the T register is lower than that of the general-purpose register. Therefore, a situation in which the value of the T register is inadvertently rewritten (the contents of the T register are destroyed). Situation) can be prevented in advance. Note that the value of the auxiliary register cannot be directly read / written by various instructions, and only the value of the main register and the value of the auxiliary register are allowed to be exchanged by a special exchange instruction (EX instruction, EXX instruction). Here, for convenience of explanation, a register whose register value can be easily changed by an instruction such as a PUSH instruction or a POP instruction is a general-purpose register. It is not necessary to include a register having a special role in the general-purpose register.

Although an example in which the T register is built in the CPU 304 is shown here, for example, the T register may be provided outside the CPU 304 or may be provided in a part of the RAM 308 separate from the CPU 304. That is, it is preferable that the T register is provided at a location physically different from storage means (ROM 306 in the present embodiment) for storing the control program. Furthermore, it is preferable that a control unit that performs a process of writing a specific value (described later) in the T register is different from a control unit that reads a control program from the ROM 306 and performs game control. This is because it is possible to make it difficult to perform both modification of the control program and illegal acquisition of a specific value by making the control unit different.
<Memory space and I / O space of CPU of main controller>

  Next, the memory space and I / O space of the CPU 304 of the main control unit 300 will be described with reference to FIG. 2A is a diagram showing a memory map of the CPU 304, and FIG. 2B is a diagram showing an I / O map of the CPU 304.

  The CPU 304 of the main control unit 300 has a memory space for accessing the above-described built-in registers, ROM 306, RAM 308, etc., and an I / O space for inputting / outputting control signals to / from the above-mentioned I / O 310. doing. Specifically, as shown in the memory map of FIG. 6A, the address / data signal line of the ROM 306 of the main control unit 300 is the ROM area of the memory space (0000H to 2FFFH (H is 16 in this embodiment)). 0000H to 2FBFH, 2FC0H to 2FFFH are assigned to the program management area), and the CPU 304 reads the data from the ROM 306 by designating this ROM area. In the present embodiment, the ROM area is divided into eight areas from the first area to the eighth area for management, and the first area is an area starting from 0000H.

  The address / data signal line of the built-in register is assigned to a register area in the memory space (in this embodiment, FE00H to FEBFH), and the CPU 304 reads data from the built-in register to this register area and sends it to the register. Write the data.

  Further, the address / data signal line of the RAM 308 is assigned to the RWM area (F000H to F3FFH in this embodiment) of the memory space, and the CPU 304 designates this RWM area and reads data from the RAM 308 and sends it to the RAM 308. Write data. Note that other areas of the memory space (in the present embodiment, 3000H to EFFFH, F4000H to FDFFH, FEC0H to FFFFH) are unused areas.

Also, as shown in the I / O map of FIG. 10B, the I / O 310 of the main control unit 300 is assigned to the work area of the I / O space (in this embodiment, 00H to BFH). The control signal is input / output to / from the I / O 310 via the I / O space. In addition, the other area | region (0C0H-FFH in this embodiment) of I / O space is made into the non-use area | region.
<Initialization process>

  Next, the initialization process of the main control unit 300 will be described with reference to FIG. This figure is a flowchart showing the flow of initialization processing.

  As described above, the main control unit 300 is provided with the start signal output circuit (reset signal output circuit) 340 that outputs the start signal (system reset signal) when the power is turned on. The CPU 304 of the basic circuit 302 to which this activation signal is input executes this initialization process before shifting to a security mode or a user mode described later.

  Specifically, in step S51, a specific value (in this embodiment, F0H which is the upper byte of the start address 7E00H of the RWM area described above) is stored in the T register built in the CPU 304. In step S52, an initial value is set in a register other than the T register, and then the process proceeds to step S53 to execute a main control unit main process described later.

  Needless to say, the specific value stored in the T register is not limited to F0H. For example, 20H, which is the upper byte of the start address of the register area (2000H in the present embodiment), is stored in the T register. If configured, the access efficiency to the built-in register may be improved by the same principle as the access to the RAM 308 described later. At the first timing, the upper byte of the head address of the RWM area is set in the T register, and the upper byte of the head address of the register area is set in the T register at the second timing thereafter (or before). You may comprise. In addition, when a predetermined condition is satisfied (for example, when an L level signal is input to a predetermined terminal), the upper byte of the leading address of the RWM area is set in the T register, and the predetermined condition is satisfied. If not, the upper byte of the start address of the register area may be set in the T register.

  In this initialization process, the upper byte of the start address of the RWM area is set in the T register (or / and the upper byte of the start address of the register area is set in the T register) without depending on the control program. Then, after this initialization processing, the start address of the register area in the T register (manually) by a control program (for example, initial setting 1 processing in step S101 described later, initial setting 2 processing in step S107, initialization processing in step S113, etc.) May be configured (or / and / or the upper byte of the start address of the RWM area is set in the T register).

  Here, the above-mentioned reset interrupt includes a system reset interrupt (a reset interrupt caused by an external event such as inputting a reset signal for a certain period to the system reset terminal) and a user reset interrupt (a user reset terminal). There are two types of reset interrupts that are triggered by an external event, such as inputting a reset signal for a certain period, and reset interrupts that are triggered by an internal event, such as a WDT timeout or access outside a specified area) There is an interrupt. In a reset by a system reset interrupt, all internal circuits including a control register and a general-purpose register are initialized (for example, an initial value corresponding to the register (for example, 00H is set in the I register)). A part of the internal circuit is initialized.

  FIG. 9 is a time chart of the startup process after system reset. After executing an initialization process by a system reset (when an H level signal is input after an L level signal is input to the XSRST terminal for a predetermined period (for example, a period of four cycles of the system clock)) When the predetermined condition is satisfied (for example, when an L level signal is input to a predetermined terminal), the process shifts to the security mode, and when the predetermined condition is not satisfied, the process shifts to the user mode. Here, the security mode is a mode for authenticating the user program. Specifically, when the system reset is input, re-calculate whether the authentication code calculated based on the user program is correct. If the result (security check result) is OK (no abnormality), this mode is terminated. When the security check result is NG (abnormal), the CPU 304 is configured to stop. The authentication code is written in the ROM 306 together with the user program (hereinafter sometimes referred to as “control program”) when writing into the ROM.

  After the security check is finished in this security mode, when the fixed extension process (hereinafter also referred to as “fixed delay function”) waiting for a certain period of time is finished, an H level reset output is output from the XRSTO terminal, and thereafter When the random extension process (hereinafter also referred to as “random delay function”) that waits for the passage of a random period is completed, it is configured to shift to the user mode (a combination of the fixed extension process and the random extension process) Security mode extension processing ”or“ security mode extension function ”). The user mode is a mode in which the user program is executed from the reset address of the ROM (0000H, which is the first address of the first area of the ROM area described above), and main control unit main processing described later is started. In this embodiment, when the CPU 304 executes the user program, the byte length of data read into the instruction register in one process (one state) is 1 byte (8 bits). The data length is not particularly limited, and may be 16 bits or 32 bits, for example.

  In the present embodiment, the above-described initialization process is configured to be executed (automatically (regardless of the control program)) before shifting to the security mode or the user mode. You may comprise so that it may be performed after transfering to user mode. Further, the initialization processing execution timing may be different depending on the type of reset (the type of interrupt factor in the case of a user reset interrupt).

  Specifically, referring to a register (one of the built-in registers) for managing the reset factor that occurred immediately before, whether or not the reset factor that occurred immediately before is (1) a system reset. (2) It is determined whether or not a user reset is caused by a timeout of WDT, and (3) whether or not a user reset is caused by access outside the designated area, and the execution timing of the initialization process is determined according to the determination result. You may comprise. In addition, the specific value and the initial value set in the initialization process may be configured to be different depending on the type of reset and the type of register (for example, a general-purpose register has 00H as an initial value in both system reset and user reset). The T register is set such that F0H is set as a specific value at the time of system reset, but may not be initialized at the time of user reset).

The security mode time can be extended by a set time or can be extended by a random time. By extending by a random amount of time, it may be difficult for the fraudster to aim at the start timing of the user program. Moreover, it is good also as a structure which can set the time from user reset (for example, reset by timeout of WDT) to the start of execution of a user program to random time. With such a configuration, there is a case where fraud aimed at the start timing of the user program can be prevented in advance.
<Main control unit main processing>

  Next, main control unit main processing executed by the CPU 304 of the main control unit 300 will be described with reference to FIG. This figure is a flowchart showing the flow of main processing of the main control unit.

  In step S101, initial setting 1 is performed. In this initial setting 1, setting of a stack initial value (temporary setting) to the stack pointer (SP) of the CPU 304, setting of an interrupt mask, initial setting of the I / O 310, initial setting of various variables stored in the RAM 308, and setting of the WDT 314 Start-up, timer out time setting, T-registration check processing (details will be described later), and the like are performed. In the present embodiment, a numerical value corresponding to 32.8 ms is set as an initial value as the timeout time of the WDT 314. In this example, the WDT 314 is activated and the time-out time is set immediately before entering the main loop of the main control unit main process. May be. In step S103, the counter value of WDT 314 is cleared, and the time measurement by WDT 314 is restarted. In addition, although the example which performs clear & restart of WDT314 immediately after a main loop start was shown, you may perform regularly in the main control part timer interruption process mentioned later, for example.

  Although not shown, the basic circuit 302 includes a start register and a clear register as registers for controlling the WDT 314. The start register is an 8-bit register for controlling the start / stop of the WDT 314. When starting the WDT 314, a value (for example, CCh) instructing the start is set (written) and stopped when the WDT 314 is stopped. Is set so as to set a value (for example, 33h).

  This start register is valid when “start by software” is set (selected) in the program management area at the time of reset. In this case, a stop instruction value (for example, 33h) is set as an initial value. Is set. Therefore, in order to activate WDT 314 when “activation by software” is set (selected), it is necessary to set a value (for example, CCh) instructing activation by the game control program (manually). On the other hand, when “activation by software” is not set (selected) at the time of resetting, a value instructing activation (for example, CCh) is an initial value (automatically) regardless of the game control program. The WDT 314 is activated (automatically) regardless of the game control program.

  The clear register is an 8-bit register for controlling clearing and restarting of the WDT 314, and after setting a predetermined first value (for example, 55h), a predetermined second value (for example, AAh) Is set, WDT 314 is cleared and restarted immediately after. When the value of the clear register is read, a predetermined fixed value (for example, FFh) is read. Although details will be described later, in the present embodiment, the time-out time of the WDT 314 can be freely set by presetting any of the 4-bit length setting value data 0000B to 1000B in the predetermined storage area of the CPU 304. (See FIG. 115).

  In step S105, whether or not the low voltage signal is on, that is, the voltage value of the power supply that the voltage monitoring circuit 338 supplies from the power supply control unit 660 to the main control unit 300 is a predetermined value (in this embodiment, 9v), it is monitored whether or not a low voltage signal indicating that the voltage has dropped is output. Then, when the low voltage signal is on (when the CPU 304 detects that the power supply is cut off), the process returns to step S103, and when the low voltage signal is off (when the CPU 304 does not detect that the power supply is cut off), the step is performed. The process proceeds to S107. Even when the predetermined value (9 V) is not yet reached immediately after the power is turned on, the process returns to step S103, and step S105 is repeatedly executed until the supply voltage becomes equal to or higher than the predetermined value.

  In step S107, initial setting 2 is performed. In this initial setting 2, a process for setting a numerical value for determining a cycle for executing a main control unit timer interrupt process, which will be described later, in the counter timer 312 and a predetermined port of the I / O 310 (for example, a test output port, A process of outputting a clear signal from the output port to the first sub control unit 400, a setting for permitting writing to the RAM 308, and the like are performed.

  In step S109, it is determined whether or not to return to the state before power interruption (before power interruption), and the state before power interruption is not restored (when the basic circuit 302 of the main control unit 300 is set to the initial state). ) Proceeds to an initialization process (step S113).

  Specifically, first, a RAM clear signal transmitted when a store clerk or the like of an amusement store operates the RWM clear switch 180 provided on the power supply board is turned on (indicates that there has been an operation). That is, it is determined whether or not the RAM clear is necessary. If the RAM clear signal is on (when the RAM clear is necessary), the process proceeds to step S113 to set the basic circuit 302 to the initial state. On the other hand, when the RAM clear signal is OFF (when the RAM clear is not necessary), the power status information stored in the power status storage area provided in the RAM 308 is read, and the power status information is information indicating suspend. It is determined whether or not. If the power status information is not information indicating suspend, the process proceeds to step S113 to set the basic circuit 302 to an initial state. If the power status information is information indicating suspend, a predetermined area of the RAM 308 is set. A checksum is calculated by adding all the 1-byte data stored in (for example, all areas) to a 1-byte register whose initial value is 0, and the calculated checksum results in a specific value (for example, 0) (whether or not the checksum result is normal). When the checksum result is a specific value (eg, 0) (when the checksum result is normal), the process proceeds to step S111 to return to the state before the power interruption, and the checksum result is a specific value. If the value is other than 0 (for example, 0) (if the result of the checksum is abnormal), the process proceeds to step S113 to set the pachinko machine 100 to the initial state. Similarly, when the power status information indicates information other than “suspend”, the process proceeds to step S113.

  In step S111, power recovery processing is performed. In this power recovery process, the value of the stack pointer stored in the stack area provided in the RAM 308 at the time of power interruption is read and reset to the stack pointer (this setting). Also, as will be described later, the values of predetermined registers stored in the register save area provided in the RAM 308 at the time of power interruption are read out, reset to these registers, and then the interrupt permission (EI) is set. Do. Thereafter, as a result of the CPU 304 executing the control program based on the reset stack pointer and registers, the pachinko machine 100 returns to the state when the power is turned off. That is, the processing is resumed from the instruction next to the instruction (predetermined in step S115) performed immediately before branching to the timer interrupt process (described later) immediately before the power interruption.

The CPU 304 according to the present embodiment includes a “PUSH TI” instruction, a “PUSH ALL” instruction, and a “PUSH GRP” instruction as PUSH instructions. The “PUSH TI” instruction is an instruction for saving the values stored in the T and I registers to the above-described stack area. Specifically, when the stack pointer at the time of executing the PUSH instruction is SP, the PUSH instruction is executed. Sometimes the value stored in the T register is saved to the address indicated by (SP-1), and the value stored in the I register when the PUSH instruction is executed is saved to the address indicated by (SP-2). . Further, "PUSH ALL" instruction, T at PUSH instruction is executed, I, A, F, B , C, D, E, H, L, IX H, IX L, IY H, stored in the IY _L register This is an instruction to save values in the stack area in this order. The “PUSH GRP” instruction is an instruction for saving the values stored in the A, F, B, C, D, E, H, and L registers in the stack area in this order when the PUSH instruction is executed.

In addition, the CPU 304 includes a “POP TI” command, a “POP ALL” command, and a “POP GRP” command as POP commands. The “POP TI” instruction is an instruction that restores the value stored in the stack area to the T and I registers (loads data from the storage area of the RAM 308 to the T and I registers). When the stack pointer at the time of execution is SP, the value stored at the address indicated by (SP-1) is restored to the T register when the POP instruction is executed, and the address indicated by (SP-2) when the POP instruction is executed. The value stored in is returned to the I register. In addition, the “POP ALL” instruction uses the values stored in the stack area when the POP instruction is executed as T, I, A, F, B, C, D, E, H, L, IX _H , IX _L , IY. _This is an instruction to restore the _H and IY _L registers. Further, the “PUSH GRP” instruction is an instruction for returning the value stored in the stack area to the A, F, B, C, D, E, H, and L registers when the POP instruction is executed.

  In order to restore the T register from the stack area, it is necessary to use the “POP TI” instruction. However, even if the I register is not used, the value of the stack area is also restored to the I register. Become. In this way, by eliminating the generality of the instruction using the T register as an operand (making it difficult to use), it is possible to prevent the instruction using the T register as an operand from being frequently used. May be rewritten inadvertently (a situation where the contents of the T register are destroyed).

  The CPU 304 includes an instruction that permits acceptance of an interrupt request (EI instruction) and an instruction that prohibits acceptance of an interrupt request (DI instruction). The above-described “POP TI” instruction is an interrupt request by a DI instruction. It is configured to execute only when reception of the request is prohibited, and is configured not to execute when reception of the interrupt request is permitted by the EI instruction. As described above, if the “POP TI” instruction is not executed when the acceptance of the interrupt request is permitted, the execution of the “POP TI” instruction causes the interrupt register to function as an interrupt vector register or an interrupt register. In some cases, an unexpected value may not be restored from the stack area, and reliable game control can be performed by reliably executing the interrupt processing.

  In addition to the above-described instructions, the CPU 304 also loads an 8-bit load (transfer) instruction, a 16-bit load (transfer) instruction, a stack operation instruction, an 8-bit arithmetic logic operation instruction, a 16-bit arithmetic logic operation instruction, multiplication / division Instruction, accumulator operation instruction, MPU control instruction, exchange instruction, block transfer instruction, block search instruction, bit operation instruction, rotate / shift instruction, unconditional jump instruction / conditional jump instruction, call instruction / return instruction, input / output instruction, It has compound instructions.

  In this embodiment, when power is interrupted, the values of the A, F, B, C, D, E, H, and L registers that do not include the T and I registers are saved (stored) in the stack area by the “PUSH GRP” instruction. When power is restored, the “POP GRP” instruction is used to restore the values of the A, F, B, C, D, E, H, and L registers from the stack area, not including the T and I registers. The T register is configured so that both saving by the “PUSH GRP” instruction and restoration by the “POP GRP” instruction cannot be performed (the T register cannot be specified as an operand of these instructions). In this embodiment, the T register cannot be specified as an operand of an addition instruction (INC instruction) or a subtraction instruction (DEC instruction). As will be described later, the T register is a special register that plays an important role in accessing the RAM 308. However, a situation in which an unexpected value is set in the T register due to a coding error or the like can be surely avoided. Stable game control is possible. In addition, since the T register is not both saved by the PUSH instruction and restored by the POP instruction, the processing at the time of power interruption or restoration may be accelerated.

  The RAM 308 mounted on the basic circuit 302 in the main control unit 300 is provided with a transmission information storage area. In step S111, a power recovery command is set in the transmission information storage area. This power recovery command is a command indicating that the power has been restored to the state at the time of power-off, and is transmitted to the first sub-control unit 400 in step S233 in the timer interrupt process of the main control unit 300 described later. In step S116, if the RAM is cleared, the RAM is cleared. If not, the WDT 314 is started after the data is restored to each register.

  In step S113, initialization processing is performed. In this initialization processing, interrupt prohibition (DI) setting, stack initial value setting to the stack pointer (this setting), initialization of all storage areas of the RAM 308, and the like are performed. Further, here, a normal return command is set in the transmission information storage area provided in the RAM 308 of the main control unit 300. This normal return command is a command indicating that the initialization process (step S113) of the main control unit 300 has been performed, and in the same way as the power recovery command, in step S233 in the timer interrupt process of the main control unit 300, 1 is transmitted to the sub-control unit 400. In step S114, if the RAM is cleared, the RAM is cleared. If not, the WDT 314 is started after the data is restored to each register.

In step S115, after setting for prohibition of interruption, a basic random number initial value update process is performed. In this basic random number initial value update process, two initial value generation random number counters for generating the initial values of the ordinary figure winning random number counter and the special figure random value counter, the ordinary figure timer random number value, and the special figure timer, respectively. Two random number counters for generating each random value are updated. For example, if the range of values that can be taken as a normal timer random number value is 0 to 100, a value is acquired from a random number counter storage area for generating a normal timer random value provided in the RAM 308, and 1 is added to the acquired value. Then, it is stored in the original random number counter storage area. At this time, if the result of adding 1 to the acquired value is 101, 0 is stored in the original random number counter storage area. Other initial value generation random number counters and random number counters are similarly updated. Note that the initial value generation random number counter is also updated in step S207 described later. The main control unit 300 repeatedly executes the process of step S115 except during a timer interrupt process that starts every predetermined period.
<T cash register check processing>

  FIG. 11A is a flowchart showing the flow of the T registration check process performed in the initial setting 1, and FIG. 11B is an example of a program list of the T registration check process.

  In step S131 of the T registration check process, the value of the T register is set in the A register (LD A, T). In the next step S132, whether or not the value of the A register matches a specific value (F0H). (SUB F0H, JP Z, SEIJYOU) If they do not match (in case of abnormality; the value obtained by subtracting a specific value (F0H) from the value in register A becomes a value other than 0 and the Z flag becomes 0) ) Proceeds to step S133, and if they match (if normal; the value obtained by subtracting a specific value (F0H) from the value of the A register becomes 0 and the Z flag becomes 1), the value of the T register Is determined to be normal, the T registration check process is terminated, and the process proceeds to the subsequent process. In step S133, after determining that the value of the T register is abnormal and setting a specific value (F0H) in the T register (LD T, F0H), the T registration check process is terminated and the process proceeds to the subsequent process.

  Note that the T-registration check process is not limited to the process shown in FIG. 11, and may be, for example, a process shown in FIG. FIG. 11A is a flowchart showing a flow of a T-registration check process according to the modification, and FIG. 11B is an example of a program list of the T-registration check process according to the modification.

In the T-registration check process according to this modification, the error process in step S135 is performed instead of the process in step S133. Specifically, when it is determined in step S132 that the value of the A register does not match the specific value (F0H) (in case of abnormality; the value obtained by subtracting the specific value (F0H) from the value of the A register is other than 0) If the value becomes Z and the Z flag becomes 0), the process proceeds to step S135 and error processing is performed (SUB F0H, JP NZ, moError). The content of this error processing is not particularly limited. For example, the error processing is configured not to enter the infinite loop and execute the subsequent main control unit main processing, or to use a liquid crystal display device or a speaker in the subsequent main control unit main processing. It may be possible to report an error.
<LD instruction>

  Next, the LD command provided in the main control unit 300 will be described. The LD instruction (LD OP1, OP2) is stored in the register indicated by the first operand OP1, the value stored in the register indicated by the second operand OP2 (or the immediate value (immediate value or immediate value) indicated by the second operand OP2. For example, when the instruction “LD A, T” is executed in a state where F0H is stored in the T register before the execution of the T-registration check process described above. The value stored in the T register indicated by the second operand, that is, F0H is stored in the A register, and when the instruction “LD A, F0H” is executed, the second operand is also stored in the A register. Is stored, that is, F0H is stored.

  On the other hand, in the LD instruction using the first operand OP1 as a T register, the second operand is limited to an immediate value, and setting a register in the second operand is prohibited (in the process of being assembled into a machine language). Error and cannot be assembled). Therefore, as described in the above-described T-registration check process, programming (coding) of an LD instruction (“LD T, F0H” in the above example) having the second operand as an immediate value is permitted, but the second operand Programming (coding) of an LD instruction (eg, “LD T, A”) that sets a register is not allowed. As described above, the LD instruction using the first operand OP1 as the T register is configured to transfer data as a direct value to the T register, so that the set data may be easily confirmed. Further, since data is not transferred to the T register via another register, the value of the T register cannot be inadvertently changed, thereby reducing the occurrence of coding errors. There are cases where it is possible.

  FIG. 13 shows only the LD command extracted from the program list. In this example, five LD instructions are used. For example, let us consider a case in which tracing is performed by debugging with respect to a value stored in the B register after execution of the LD instruction “LD B, A” in (4). In this case, it is necessary to trace back the program list for the A register which is the second operand of the LD instruction “LD B, A”. For example, the search of the program list can be performed using the search key “LD A”. If this is done, the LD instruction “LD A, H” in (3) will be hit in addition to the LD instruction “LD A, B” in (1). That is, the LD instruction with the A register set to the first operand is frequently used because it is permitted to set the register to the second operand and to set the second operand to an immediate value. This can contribute to a reduction in the efficiency of review work and debugging (for example, tracing of the A register). Although the A register having the highest use frequency has been described here, the same can be said when other registers other than the T register are used.

On the other hand, the LD instruction in which the T register is set in the first operand is prohibited from setting the register in the second operand, and only the second operand is allowed to have an immediate value. The frequency of use is relatively lower than that of the LD instruction, and it becomes possible to increase the efficiency of coding review work and debugging (for example, T register tracing), and the control program development efficiency may be improved.
<Main control unit timer interrupt processing>

  Next, a main control unit timer interrupt process executed by the CPU 304 of the main control unit 300 will be described with reference to FIG. This figure is a flowchart showing the flow of the main control unit timer interrupt process.

  The main control unit 300 includes a counter timer 312 that generates a timer interrupt signal at a predetermined cycle (in this embodiment, about once every 2 ms), and the main control unit timer interrupt is triggered by this timer interrupt signal. The process is started at a predetermined cycle.

  In step S201, a timer interrupt start process is performed. In this timer interrupt start process, a process of temporarily saving each register value of the CPU 304 to the stack area is performed.

  In step S203, the WDT is periodically updated (so that the count value of the WDT 314 exceeds the initial setting value (32.8 ms in the present embodiment) and no WDT interruption occurs (so as not to detect a processing abnormality). In the embodiment, the restart is performed once every about 2 ms, which is the period of the main control unit timer interrupt.

  In step S205, input port state update processing is performed. In this input port state update process, the detection signals of various sensors 320 including the above-mentioned front frame door open sensor, inner frame open sensor, lower pan full sensor, and various ball detection sensors are input via the input port of the I / O 310. The input is monitored for the presence or absence of a detection signal, and stored in a signal state storage area provided for each of the various sensors 320 in the RAM 308. If the detection signal of the sphere detection sensor is described as an example, information on the presence / absence of the detection signal of each sphere detection sensor detected in the timer interruption process (about 4 ms before) is stored in the RAM 308 for each sphere detection sensor. This information is read out from the previous detection signal storage area partitioned and stored in the RAM 308 in the previous detection signal storage area partitioned for each sphere detection sensor, and the previous timer interrupt processing (about 2 ms before) ) Is read from the current detection signal storage area provided for each sphere detection sensor in the RAM 308, and this information is read out from the previous detection signal storage area described above. To remember. Further, the detection signal of each sphere detection sensor detected this time is stored in the above-described current detection signal storage area.

  Further, in step S205, the information on the presence or absence of the detection signal of each sphere detection sensor stored in each storage area of the above-mentioned detection signal storage area, the previous detection signal storage area, and the current detection signal storage area is compared. It is determined whether or not the information on the presence or absence of detection signals for the past three times in the ball detection sensor matches the winning determination pattern information. This main control unit timer interruption process that is repeatedly started at a very short interval of about 2 ms is started several times while one game ball passes through one ball detection sensor. For this reason, every time the main control unit timer interrupt process is activated, in step S205 described above, a detection signal indicating that the same game ball has passed the same ball detection sensor is confirmed. As a result, a detection signal indicating that the same game ball has passed the same ball detection sensor is stored in each of the detection signal storage area, the previous detection signal storage area, and the current detection signal storage area. That is, when the game ball starts to pass through the ball detection sensor, there is no detection signal before, a previous detection signal, and a current detection signal. In the present embodiment, in consideration of erroneous detection of the sphere detection sensor and noise, it is determined that there is a prize when the detection signal is stored twice continuously after no detection signal. The ROM 306 of the main control unit 300 shown in FIG. 4 stores winning determination pattern information (in this embodiment, information indicating that there is no previous detection signal, that there is a previous detection signal, and that there is a current detection signal). In this step S205, information on the presence or absence of detection signals for the past three times in each sphere detection sensor is predetermined winning determination pattern information (in this embodiment, no previous detection signal, previous detection signal, current detection signal present). In the case of the general winning port 226, the variable winning port 234, the first special figure starting port 230, and the second special figure starting port 232, or the ordinary drawing starting port 228. Is determined to have passed. In other words, it is determined that a prize has been awarded to the winning ports 226 and 234 and the starting ports 230, 232, and 228. For example, when the information on the presence / absence of the detection signals for the past three matches with the above-described winning determination pattern information in the general winning opening sensor for detecting the winning at the general winning opening 226, there is a winning at the general winning opening 226. If the information on the presence / absence of detection signals for the past three times does not match the above-described winning determination pattern information, the subsequent general winnings are performed. The process branches to the subsequent process without performing the process associated with winning the prize to the mouth 226. Note that the ROM 306 of the main control unit 300 stores winning determination clear pattern information (in this embodiment, information indicating that there is a detection signal before the previous time, no previous detection signal, and no current detection signal). After it is determined that there has been a single win, it is not determined that there has been a win until the information on the presence or absence of detection signals for the past three times matches the winning determination clear pattern information in each ball detection sensor, and the winning determination is cleared. If it matches the pattern information, it is next determined whether or not it matches the winning determination pattern information.

  In step S207 and step S209, basic random number initial value update processing and basic random number update processing are performed. In these basic random number initial value update processing and basic random number update processing, the value of the initial value generation random number counter performed in step S115 is updated, and then the normal winning random number value used in the main control unit 300, Two random number counters for generating the special figure 1 random value and the special figure 2 random value are updated. For example, if the range of values that can be taken as a random number value for a normal winning number is 0 to 100, a value is acquired from a random number counter storage area for generating a normal winning random number value provided in the RAM 308, and 1 is added to the acquired value. Then, it is stored in the original random number counter storage area. At this time, if the result of adding 1 to the acquired value is 101, 0 is stored in the original random number counter storage area. If it is determined that the random number counter has made one round as a result of adding 1 to the acquired value, the value of the initial value generating random number counter corresponding to each random number counter is acquired and stored in the storage area of the random number counter. set. For example, a value is acquired from a random number counter for generating a regular winning random number that fluctuates in a numerical range of 0 to 100, and a result obtained by adding 1 to the acquired value is stored in a predetermined initial value storage area provided in the RAM 308. If the value is equal to the previously set initial value (for example, 7), the value is acquired as an initial value from the initial value generation random number counter corresponding to the random number counter for generating the random number for winning the normal number, The initial value set this time is stored in the above-described initial value storage area in order to determine that the random number counter for generating the winning random number value has made one round next time, in addition to setting it in the random number counter for generating the winning random value Keep it. Further, apart from the above-described initial value storage area for determining that the random number counter for generating the random number for winning the normal signal has made one round next, it is determined that the random number counter for generating the special figure random number has made one round. An initial value storage area is provided in the RAM 308. In the present embodiment, the counter for acquiring the random number value of FIG. 1 and the counter for acquiring the random value of FIG. 2 are separately provided, but the same counter may be used.

  In step S211, effect random number update processing is performed. In this effect random number update process, a random number counter for generating an effect random number used by the main control unit 300 is updated.

  In step S213, timer update processing is performed. In this timer update process, the normal symbol display symbol update timer for timing the time for the symbol to be changed / stopped on the normal symbol display device 210, and the time for the symbol to be changed / stopped to be displayed on the first special symbol display device 212 are timed. Special symbol 1 display symbol update timer for performing, special symbol 2 display symbol update timer for measuring the time for the symbol to be changed and stopped on the second special symbol display device 214, a predetermined winning effect time, a predetermined opening time Various timers including a timer for measuring a predetermined closing time, a predetermined end effect period, and the like are updated.

  In step S215, winning prize counter update processing is performed. In this winning opening counter updating process, when winning holes 226, 234 and starting holes 230, 232, 228 are won, the RAM 308 stores the winning ball number storage area provided for each winning hole or for each starting hole. The value is read out, 1 is added, and the original prize ball number storage area is set.

  In step S217, a winning acceptance process is performed. In this winning acceptance process, it is determined whether or not there has been a winning at the first special figure starting port 230, the second special figure starting port 232, the ordinary drawing starting port 228, and the variable winning port 234. Here, the determination is made using the determination result of whether or not it matches the winning determination pattern information in step S203. When a winning is made at the first special figure starting port 230 and the corresponding reserved number storage area provided in the RAM 308 is not full, the value is stored in the special counter value storage register of the counter circuit 318. And a value from the random number counter for generating the special figure 1 random value as a special figure 1 random value and storing it in the corresponding random value storage area. When a winning is made to the second special figure starting port 232 and the corresponding reserved number storage area provided in the RAM 308 is not full, the value is sent from the winning counter value storage register of the counter circuit 318 to the special figure 2 winning random number value. And a value from the random number counter for generating the special figure 2 random value as a special figure 2 random value and storing it in the corresponding random value storage area. If there is a win at the general figure starting port 228 and the corresponding reserved number storage area provided in the RAM 308 is not full, the value is obtained as a normal figure winning random number value from the random number counter for generating the normal figure winning random number value. Store in the corresponding random value storage area. When there is a winning at the variable winning opening 234, information indicating that a ball has entered the variable winning opening 234 is stored in the winning storage area for the variable winning opening.

  In step S219, a payout request number transmission process is performed. Note that the output schedule information and the payout request information output to the payout control unit 600 are composed of, for example, 1 byte, strobe information (indicating that data is set when ON), bit 6 Power-on information (if turned on, indicates that this is the first command transmission after power-on), bits 4-5 indicate the current processing type for encryption (0-3), and bits 0-3 indicate encryption The number of payout requests after processing is shown.

  In step S221, a normal state update process is performed. This normal state update process performs one of a plurality of processes corresponding to the normal state. For example, in the normal state update process in the middle of the normal symbol display (the above-described general symbol display symbol update timer value is 1 or more), the 7-segment LED constituting the normal symbol display device 210 is repeatedly turned on and off. Turns off drive control. By performing this control, the normal symbol display device 210 performs a usual fluctuation display (ordinary figure fluctuation game).

  Also, in the normal state update process at the timing when the normal symbol change display time has elapsed (the timing when the value of the general symbol display symbol update timer has changed from 1 to 0), if the hit flag is on, the win symbol is displayed. The normal symbol display device 210 is controlled so that the 7-segment LED constituting the normal symbol display device 210 is turned on / off, and when the hit flag is off, the normal symbol display device 210 is configured to be in the off symbol display mode. 7 segment LED on / off drive control is performed. Further, the RAM 308 of the main control unit 300 is provided with a setting area for performing various settings in various processes, not limited to the normal state update process. Here, the above-described lighting / extinguishing drive control is performed, and the setting area is set to indicate that the normal stop display is being performed. By performing this control, the normal symbol display device 210 determines the symbol of either the winning symbol (the common symbol A shown in FIG. 5C) or the off symbol (the common symbol B shown in FIG. 5C). Display. Thereafter, information indicating the stop period is set in a storage area of a normal stop time management timer provided in the RAM 308 in order to maintain the display for a predetermined stop display period (for example, 500 msec). With this setting, the symbol that has been confirmed and displayed is stopped and displayed for a predetermined period, and the player is notified of the result of the normal game.

  Further, if the result of the usual figure variable game is a hit, the usual figure hit flag is turned on as will be described later. When the usual figure hit flag is on, in the usual figure state update process at the timing when the predetermined stop display period ends (when the value of the usual figure stop time management timer is changed from 1 to 0), The normal operation is set in the setting area, and the blade member 232a is opened to a solenoid (332) for opening and closing the blade member 232a of the second special figure starting port 232 for a predetermined opening period (for example, 2 seconds). And a signal indicating the open period is set in the storage area of the blade open time management timer provided in the RAM 308.

  In the usual state update process that starts at the timing when the predetermined opening period ends (the timing when the value of the blade opening time management timer is changed from 1 to 0), the blade member has a predetermined closing period (for example, 500 milliseconds). A signal for holding the blade member in the closed state is output to the opening / closing drive solenoid 332, and information indicating the closing period is set in the storage area of the blade closing time management timer provided in the RAM 308.

  Further, in the normal state update process that starts at the timing when the predetermined closing period ends (the timing when the value of the blade closing time management timer changes from 1 to 0), in the setting area of the RAM 308, the normal state is not operating is set. To do. Furthermore, if the result of the usual figure fluctuation game is out, the usual figure out flag is turned on as will be described later. When the off-normal flag is on, the normal state update process at the timing when the predetermined stop display period described above ends (the timing at which the normal stop time management timer value changes from 1 to 0) In the setting area of the RAM 308, normal operation inactive is set. In the general state update process in the case where the general map is not operating, nothing is done and the process proceeds to the next step S223.

  In step S223, a general drawing related lottery process is performed. In this general map-related lottery process, the open / close control of the general map variable game and the second special map start port 232 is not performed (the state of the general map is not in operation), and the pending general map variable game is not held. When the number is 1 or more, it is decided whether to win or not to win the result of the variable figure game by random lottery based on the random number value stored in the random number value storage area. When the winning judgment is made and the winning is made, the winning flag provided in the RAM 308 is set to ON. If unsuccessful, turn off the winning flag. Regardless of the result of the hit determination, next, the value of the random number counter for generating the normal figure timer random value is acquired as the normal figure timer random number value, and a plurality of fluctuation times are obtained based on the acquired general figure timer random number value. One time is selected for variably displaying the normal map on the general map display device 210, and this variable display time is stored as a normal map variable display time in a general map variable time storage area provided in the RAM 308. In addition, the number of pending general figure variable games is stored in the usual figure pending number storage area provided in the RAM 308, and from the number of pending custom figure variable games each time a hit determination is made. The value obtained by subtracting 1 is re-stored in the usual figure number-of-holds storage area. Also, the random number value used for the hit determination is deleted.

  Next, the special figure state update process for each of the special figure 1 and the special figure 2 is performed. First, the special figure state update process (the special figure 2 state update process) for the special figure 2 is performed (step S225). In the special figure 2 state update process, one of the following eight processes is performed in accordance with the state of the special figure 2. For example, in the special figure 2 state update process in the middle of the special figure 2 fluctuation display (the value of the above-mentioned special figure 2 display symbol update timer is 1 or more), Performs lighting / extinguishing drive control that repeatedly turns off. By performing this control, the second special symbol display device 214 performs the variable display of the special figure 2 (special figure 2 variable game).

In addition, predetermined transmission information indicating that the rotation start setting transmission process is to be executed in the command setting transmission process (step S233) is additionally stored in the above-described transmission information storage area, and the process ends.

  In addition, in the RAM 308 determination result storage area of the main control unit 300, a 15R big hit flag, 2R big hit flag, first small hit flag, second small hit flag, first off flag, second off flag, special figure probability A flag for each of a variation flag and an ordinary probability variation flag is prepared. In the special figure 2 state update process starting at the timing when the special figure 2 fluctuation display time has elapsed (the timing when the special figure 2 display symbol update timer value has changed from 1 to 0), the 15R big hit flag is on, and the special figure probability fluctuation When the flag is also on and the normal figure probability fluctuation flag is on, the special figure A, 15R jackpot flag shown in FIG. 5A is on, the special figure probability fluctuation flag is off, and the common figure probability fluctuation flag is on. When the special figure B, 2R big hit flag is on, the special figure probability fluctuation flag is on, and the general figure probability fluctuation flag is also on, the special figure C, 2R big hit flag is on, the special figure probability fluctuation flag is off, When the probability fluctuation flag is on, the special figure D, 2R jackpot flag is on, the special figure probability fluctuation flag is on, and when the common figure probability fluctuation flag is on, the special figure E, 2R jackpot flag is on, special chart Probability flag is off, normal When the rate fluctuation flag is also off, the special figure F, when the first small hit flag is on, the special figure G, when the second small hit flag is on, the special figure H, and the first off flag are on. In such a case, the 7-segment LED constituting the second special symbol display device 214 is controlled to be turned on / off so that the special figure I and the second off flag are turned on, respectively, so that the special figure I is in the respective mode. A setting indicating that the special figure 2 stop display is in progress is made in the setting area of the RAM 308. By performing this control, the second special symbol display device 214 has a 15R special jackpot symbol (special symbol A), a 15R jackpot symbol (special symbol B), a sudden probability variation symbol (special symbol C), and a sudden time-short symbol symbol (special symbol). D), hidden probability variation (special E), suddenly normal (special F), first small hit (special G), second small hit (special H), first off symbol (special) Any one of the symbols I) and the second off-set symbol (special symbol J) is confirmed and displayed. After that, information indicating the stop period is set in the storage area of the special figure 2 stop time management timer provided in the RAM 308 in order to maintain the display for a predetermined stop display period (for example, 500 milliseconds). With this setting, the specially displayed special figure 2 is stopped and displayed for a predetermined period, and the result of the special figure 2 variable game is notified to the player. In addition, if the time reduction number stored in the time reduction number storage unit provided in the RAM 308 is 1 or more, 1 is subtracted from the time reduction number, and if the subtraction result becomes 1 to 0, the special figure probability is changing. If not (details will be described later), the time reduction flag is turned off. Further, the hourly flag is also turned off during the big hit game (in the special game state).

  Further, the special transmission information indicating that the rotation stop setting transmission process is executed in the command setting transmission process (step S233) is additionally stored in the above-described transmission information storage area, and the design for stopping the variable display is shown in FIG. The special figure 2 identification information indicating the presence is additionally stored in the RAM 308 as information to be included in command data, which will be described later, and the processing is terminated.

  If the result of the special figure 2 variable game is a big hit, the big hit flag is turned on as will be described later. When the jackpot flag is on, in the special figure 2 state update process at the timing when the predetermined stop display period ends (the timing when the special figure 2 stop time management timer value changes from 1 to 0), the RAM 308 In the setting area, the special figure 2 is in operation and waits for a predetermined winning effect period (for example, 3 seconds), that is, a period during which an image for notifying the player that the big win by the decorative symbol display device 208 is started is displayed. Therefore, information indicating the winning effect period is set in the storage area of the special figure 2 standby time management timer provided in the RAM 308. Further, predetermined transmission information indicating that the winning effect setting transmission process is executed in the command setting transmission process (step S233) is additionally stored in the transmission information storage area.

  Further, in the special figure 2 state update process that starts at the timing when the predetermined winning effect period ends (the timing when the value of the special figure 2 standby time management timer changes from 1 to 0), a predetermined release period (for example, 29 seconds) Alternatively, the door member 234a is opened to the solenoid (332) for opening and closing the door member 234a of the variable prize opening 234 until a winning of a predetermined number of balls (for example, 10 balls) is detected at the variable prize opening 234. In addition to outputting a signal to be held at the same time, information indicating the opening period is set in the storage area of the door opening time management timer provided in the RAM 308. In addition, predetermined transmission information indicating that the special winning opening release setting transmission process is executed in the command setting transmission process (step S233) is additionally stored in the transmission information storage area.

  In the special figure 2 state update process that starts at the timing when the predetermined opening period ends (the timing when the door opening time management timer value changes from 1 to 0), the predetermined closing period (for example, 1.5 seconds) A signal for holding the door member 234a in a closed state is output to a solenoid (332) for opening and closing the door member 234a of the variable prize opening 234, and a closing period is stored in a storage area of a door closing time management timer provided in the RAM 308. Set the information indicating. In addition, predetermined transmission information indicating that the special winning opening closing setting transmission process is executed in the command setting transmission process (step S233) is additionally stored in the transmission information storage area.

  In addition, in the special figure 2 state update process that starts at the timing when the door member opening / closing control is repeated a predetermined number of times (15 rounds or 2 rounds in this embodiment) and finished, a predetermined end effect period (for example, 3 seconds) In other words, the effect standby period is stored in the storage area of the effect standby time management timer provided in the RAM 308 in order to set to wait for a period during which an image for informing the player that the big hit by the decorative symbol display device 208 is to be ended is displayed. Set the information indicating. Also, if the normal probability fluctuation flag is set to ON, at the same time as the end of the jackpot game, the time reduction number 100 is set in the time reduction number storage unit provided in the RAM 308, and the time reduction flag provided in the RAM 308 is set. Turn on. If the usual time probability variation flag is set to OFF, the time reduction number is not set in the time reduction number storage unit, and the time reduction flag is not turned ON. The short time here means that the pachinko machine is in an advantageous state for the player in order to shorten the time from the end of the big hit in the special figure variable game to the start of the next big hit. If the short time flag is set to ON at this time, it is a normal high probability state. There is a higher probability of hitting a general-purpose variable game in the high-probability state than in the low-probability state. In addition, the fluctuation time of the normal figure variable game and the fluctuation time of the special figure variable game are shorter in the normal figure high probability state than in the normal figure low probability state. Further, in the normal high probability state, the opening time in one opening of the pair of blade members 232a of the second special start port 232 tends to be longer than in the normal low probability state. In addition, the pair of blade members 232a are more likely to open in the normal high probability state than in the normal low probability state. In addition, as described above, the hourly flag is set to off during the big hit game (in the special game state). Therefore, the normal low probability state is maintained during the jackpot game. This is because, if the game is in a high probability state during a jackpot game, a large number of games will be placed in the second special figure start port 232 until a predetermined number of game balls are entered during the jackpot game. There is a problem that a ball enters and the number of game balls that can be acquired during the jackpot increases, resulting in an increase in euphoria. This is to solve this problem.

  Further, predetermined transmission information indicating that the end effect setting transmission process is executed in the command setting transmission process (step S233) is additionally stored in the transmission information storage area.

  Also, in the special figure 2 state update process that starts at the timing when the predetermined end production period ends (when the production standby time management timer value changes from 1 to 0), the special figure 2 is not activated in the setting area of the RAM 308. Set medium. Further, if the result of the special figure 2 variable game is out of the way, the off flag is turned on as will be described later. In the case where the miss flag is on, even in the special figure 2 state update process at the timing when the predetermined stop display period described above ends (the timing when the special figure 2 stop time management timer value changes from 1 to 0), In the setting area of the RAM 308, special figure 2 inactive is set. In the special figure 2 state update process when the special figure 2 is not in operation, nothing is done and the process proceeds to the next step S227.

  Subsequently, special figure state update processing (special figure 1 state update process) for special figure 1 is performed (step S227). In the special figure 1 state update process, each process described in the special figure 2 state update process is performed according to the state of the special figure 1. Each process performed in the special figure 1 state update process is the same as the process in which “special figure 2” in the contents described in the special figure 2 state update process is replaced with “special figure 1”. Omitted. The order of the special figure 2 state update process and the special figure 1 state update process may be reversed.

  When the special figure state update process in step S225 and step S227 is completed, a special figure related lottery process for each of special figure 1 and special figure 2 is performed. Also here, first, a special drawing related lottery process for special figure 2 (a special drawing 2 related lottery process) is performed (step S229), and then a special drawing related lottery process for special figure 1 (a special drawing 1 related lottery process). ) Is performed (step S231). Also for these special drawing related lottery processes, the main control unit 300 performs the special figure 2 related lottery processing before the special figure 1 related lottery processing, so that the special figure 2 variable game start condition and the special figure 1 fluctuation Even if the game start conditions are satisfied at the same time, since the special figure 2 variable game is changing first, the special figure 1 variable game does not start changing. Further, the notification of the result of the jackpot determination of the special figure variable game by the decorative symbol display device 208 is performed by the first sub-control unit 400, and the lottery result of the lottery based on the winning at the second special figure starting port 232 is notified. However, it is performed in preference to the notification of the lottery result of the lottery based on the winning at the first special figure starting port 230.

  In step S233, command setting transmission processing is performed, and various commands are transmitted to the first sub-control unit 400. The output schedule information to be transmitted to the first sub-control unit 400 is composed of 16 bits, for example, bit 15 is strobe information (indicating that data is set when ON), bits 11 to 14 are Command type (in this embodiment, information that can specify the type of command, such as basic command, symbol variation start command, symbol variation stop command, winning effect start command, end effect start command, jackpot round number designation command, power recovery command) Bits 0 to 10 are composed of command data (predetermined information corresponding to the command type).

  Specifically, the strobe information is turned on and off in the command transmission process described above. If the command type is a symbol variation start command, information indicating the value of the 15R jackpot flag or 2R jackpot flag, the value of the special figure probability variation flag, the timer number selected in the special figure related lottery process, etc. is included in the command data. In the case of the symbol variation stop command, the value of the 15R jackpot flag, 2R jackpot flag, the value of the special figure probability variation flag, etc. are included. In the case of a jackpot round number designation command, the value of the special variation probability flag, the number of jackpot rounds, and the like are included. When the command type indicates a basic command, device information in the command data, presence / absence of winning at the first special figure starting port 230, presence / absence of winning at the second special figure starting port 232, winning of the variable winning port 234 Includes presence or absence.

  In the rotation start setting transmission process described above, the 15R jackpot flag or 2R jackpot flag value, the special figure probability variation flag value, the special figure 1 related lottery process, and the special figure 2 relation stored in the RAM 308 as command data. Information indicating the timer number selected in the lottery process, the number of the first special figure variable game or the second special figure variable game held, etc. is set. In the rotation stop setting transmission process described above, information indicating the value of the 15R jackpot flag, the 2R jackpot flag, the value of the special figure probability variation flag, etc. stored in the RAM 308 is set in the command data. In the winning effect setting transmission process described above, the command control data stored in the RAM 308, the effect control information output to the decorative symbol display device 208, various lamps 418, and the speaker 120 during the winning effect period, the special figure probability variation flag Information indicating the value, the number of the first special figure variable game or the second special figure variable game being held, etc. is set. In the above-described end effect setting transmission process, the command control data stored in the RAM 308, the effect control information output to the decorative symbol display device 208, various lamps 418, and the speaker 120 during the effect standby period, the special figure probability variation flag Information indicating the value, the number of the first special figure variable game or the second special figure variable game being held, etc. is set. In the above-described large winning opening release setting transmission process, the number of big hits stored in the RAM 308 in the command data, the value of the special figure probability variation flag, the pending first special figure variation game or the second special figure variation game is stored. Set information such as number. In the above-mentioned big winning opening closing setting transmission process, the number of big hits stored in the RAM 308 in the command data, the value of the special figure probability variation flag, the pending first special figure variation game or the second special figure variation game is stored. Set information such as number. In step S233, general command special figure hold increase processing is also performed. In this general command special figure pending increase process, special figure identification information (information showing special figure 1 or special figure 2) stored in the transmission information storage area of the RAM 308, command notice information (preliminary notice information, false) Set either advance notice information or no advance notice information).

  In the first sub-control unit 400, it is possible to determine the production control according to the change of the game control in the main control unit 300 by the command type included in the received output schedule information, and it is included in the output schedule information. Based on the information of the command data, the contents of effect control can be determined.

  In step S235, an external output signal setting process is performed. In this external output signal setting process, the game information stored in the RAM 308 is output to the information input circuit 350 separate from the pachinko machine 100 via the information output circuit 336.

  In step S237, device monitoring processing is performed. In this device monitoring process, the signal states of the various sensors stored in the signal state storage area in step S205 are read, and the presence or absence of a predetermined error, for example, the presence or absence of a front frame door opening error or the presence or absence of a full tray error is monitored. When the front frame door opening error or the lower pan full error is detected, the transmission information to be transmitted to the first sub-control unit 400 includes device information indicating the presence or absence of the front frame door opening error or the lower pan full error. Set. Further, various solenoids 332 are driven to control the opening and closing of the second special figure starting port 232 and the variable prize opening 234, and the normal symbol display device 210 and the first special symbol display via the display circuits 324, 326 and 330. Display data to be output to the device 212, the second special symbol display device 214, the various status display units 328, and the like is set in the output port of the I / O 310. Further, the output schedule information set in the payout request number transmission process (step S219) is output to the first sub-control unit 400 via the output port (I / O 310).

  In step S239, it is monitored whether or not the low voltage signal is on. Then, when the low voltage signal is on (when power supply cutoff is detected), the process proceeds to step S243, and when the low voltage signal is off (when power supply cutoff is not detected), the process proceeds to step S241.

  In step S241, timer interrupt end processing is performed. In this timer interrupt end process, the value of each register temporarily saved in step S201 is set in each original register, interrupt permission is set, and the like, and then the process returns to the main process of the main control unit.

On the other hand, in step S243, a specific variable or stack pointer for returning to the power-off state at the time of power recovery is saved in a predetermined area of the RAM 308 as return data, and power-off processing such as initialization of input / output ports is performed. After that, the process returns to the main process of the main control unit.
<Processing of First Sub-Control Unit 400>

  Next, processing of the first sub control unit 400 will be described with reference to FIG. FIG. 5A is a flowchart of main processing executed by the CPU 404 of the first sub control unit 400. FIG. 5B is a flowchart of the strobe interrupt process of the first sub control unit 400. FIG. 6C is a flowchart of the timer variable update interrupt process of the first sub control unit 400. FIG. 4D is a flowchart of the image control process of the first sub control unit 400.

  First, in step S301 in FIG. 9A, various initial settings are performed. When power is turned on, an initialization process is first executed in S301. In this initialization processing, initialization of input / output ports, initialization processing of a storage area in the RAM 408, and the like are performed.

  In step S303, it is determined whether or not the timer variable is 10 or more. This process is repeated until the timer variable becomes 10, and when the timer variable becomes 10 or more, the process proceeds to step S305. In step S305, 0 is substituted into the timer variable.

  In step S307, command processing is performed. The CPU 404 of the first sub control unit 400 determines whether a command has been received from the main control unit 300.

  In step S309, effect control processing is performed. For example, when there is a new command in S307, processing such as reading effect data corresponding to the command from the ROM 406 is performed, and when update of the effect data is necessary, effect data update processing is performed.

  If it is detected in step S311 that the chance button has been pressed, the effect data updated in step S309 is changed to effect data corresponding to the press of the chance button. In step S313, if there is a command to VDP 434 in the effect data read in S309, this command is output to VDP 434 (details will be described later).

  In step S315, if there is a command to the sound source IC 416 in the effect data read out in S309, this command is output to the sound source IC 416. In step S317, if there is a command to the various lamps 418 in the effect data read in S309, this command is output to the drive circuit 420.

  In step S <b> 319, if there is a command to the shielding device 246 in the effect data read in S <b> 309, this command is output to the drive circuit 432. In step S321, if there is a control command to be transmitted to the second sub-control unit 500 in the effect data read in S309, the control command is set to be output, and the process returns to S303.

  Next, the command reception interrupt process of the first sub-control unit 400 will be described using FIG. This command reception interrupt process is a process executed when the first sub-control unit 400 detects a strobe signal output from the main control unit 300. In step S401 of the command reception interrupt process, the command output from the main control unit 300 is stored as an unprocessed command in a command storage area provided in the RAM 408.

  Next, the first sub control unit timer interrupt process executed by the CPU 404 of the first sub control unit 400 will be described with reference to FIG. The first sub-control unit 400 includes a hardware timer that generates a timer interrupt at a predetermined cycle (in this embodiment, once every 2 ms). Execute in the cycle.

  In step S501 of the first sub-control unit timer interrupt process, 1 is added to the value of the timer variable storage area of the RAM 408 described in step S303 in the first sub-control unit main process, and the original timer variable storage area is stored. To do. Therefore, in step S303, the value of the timer variable is determined to be 10 or more every 20 ms (2 ms × 10).

  In step S503 of the first sub control unit timer interrupt process, a control command is transmitted to the second sub control unit 500 set in step S319, an effect random number value is updated, and the like.

  Next, the image control process in step S313 in the main process of the first sub control unit 400 will be described with reference to FIG. FIG. 5 is a flowchart showing the flow of image control processing.

  In step S601, an instruction to transfer image data is issued. Here, the CPU 404 first swaps the designation of the display areas A and B in the VRAM 436. As a result, an image of one frame stored in the display area not designated as the drawing area is displayed on the decorative design display device 208. Next, the CPU 404 sets ROM coordinates (transfer source address of the ROM 406), VRAM coordinates (transfer destination address of the VRAM 436) and the like in the attribute register of the VDP 434 based on the position information table and the like, and then the image from the ROM 406 to the VRAM 436. Sets an instruction to start data transfer The VDP 434 transfers the image data from the ROM 406 to the VRAM 436 based on the command set in the attribute register. Thereafter, the VDP 436 outputs a transfer end interrupt signal to the CPU 404.

  In step S603, it is determined whether or not a transfer end interrupt signal from the VDP 434 is input. If a transfer end interrupt signal is input, the process proceeds to step S605. If not, a transfer end interrupt signal is input. Wait for it. In step S605, parameters are set based on the production scenario configuration table and attribute data. Here, in order to form a display image in the display area A or B of the VRAM 436 based on the image data transferred to the VRAM 436 in step S601, the CPU 404 has information on the image data constituting the display image (coordinate axis and image size of the VRAM 436). , VRAM coordinates (arrangement coordinates, etc.) are instructed to the VDP 434. The VDP 434 sets parameters according to attributes based on instructions stored in the attribute register.

  In step S607, a drawing instruction is performed. In this drawing instruction, the CPU 404 instructs the VDP 434 to start drawing an image. The VDP 434 starts drawing an image in the frame buffer in accordance with an instruction from the CPU 404.

In step S609, it is determined whether or not a generation end interrupt signal from the VDP 434 based on the end of image drawing is input. If a generation end interrupt signal is input, the process proceeds to step S611. If not, the generation end interrupt signal is determined. Wait for input. In step S611, a scene display counter that is set in a predetermined area of the RAM 408 and counts how many scene images have been generated is incremented (+1), and the process ends.
<Processing of Second Sub-Control Unit 500>

  Next, the processing of the second sub control unit 500 will be described with reference to FIG. FIG. 6A is a flowchart of main processing executed by the CPU 504 of the second sub-control unit 500. FIG. 7B is a flowchart of command reception interrupt processing of the second sub control unit 500. FIG. 8C is a flowchart of the timer interrupt process of the second sub control unit 500.

  First, in step S701 in FIG. 9A, various initial settings are performed. When the power is turned on, first, initialization processing is executed in S701. In this initialization processing, initial setting of input / output ports, initialization processing of a storage area in the RAM 508, and the like are performed.

  In step S703, it is determined whether or not the timer variable is 10 or more, and this process is repeated until the timer variable becomes 10. When the timer variable becomes 10 or more, the process proceeds to step S705.

  In step S705, 0 is assigned to the timer variable. In step S707, command processing is performed. The CPU 504 of the second sub control unit 500 determines whether a command has been received from the CPU 404 of the first sub control unit 400. In step S709, an effect control process is performed. For example, when there is a new command in S707, the effect data corresponding to this command is read from the ROM 506, and when the effect data needs to be updated, the effect data is updated.

  In step S <b> 711, if there is a command from the first sub-control unit 400 to the game board lamp 532 or the game table frame lamp 542, this command is output to the serial communication control circuit 520.

  In step S713, if there is a command from the first sub-control unit 400 to the effect movable body 224, this command is output to the drive circuit 516, and the process returns to S703.

Next, the command reception interrupt process of the second sub control unit 500 will be described with reference to FIG. This command reception interrupt process is a process executed when the second sub control unit 500 detects the strobe signal output from the first sub control unit 400. In step S801 of the command reception interrupt process, the command output from the first sub control unit 400 is stored as an unprocessed command in a command storage area provided in the RAM 508.

  Next, the second sub control unit timer interrupt process executed by the CPU 504 of the second sub control unit 500 will be described with reference to FIG. The second sub-control unit 500 includes a hardware timer that generates a timer interrupt at a predetermined cycle (in this embodiment, once every 2 ms), and a timer interrupt process is performed in response to this timer interrupt. Execute in the cycle.

In step S901 of the second sub control unit timer interrupt process, 1 is added to the value of the timer variable storage area of the RAM 508 described in step S703 in the second sub control unit main process, and the result is stored in the original timer variable storage area. To do. Therefore, in step S703, the value of the timer variable is determined to be 10 or more every 20 ms (2 ms × 10). In step S903 of the second sub-control unit timer interrupt process, an effect random number update process is performed.
<ROM of main controller>

  Next, the types of data stored in the ROM 306 of the main control unit 300 will be described with reference to FIG. The figure shows an example of data stored in the ROM 306 described above.

  The ROM area corresponding to the storage area of the ROM 306 (in this embodiment, a 16 Kbyte area from 0000H to 2FFFH) is a ROM control area (in this embodiment, 0000H to 0BB0H), a non-use area (in this embodiment, 0BB1H to 0FFFH), ROM data area (1FFFH to 18FDH in this embodiment), and other areas (18FEH to 2FFFH in this embodiment). The storage area of the ROM 306 corresponding to this ROM control area contains instruction data (opcode) corresponding to each of a plurality of types of instructions executed by the CPU 304 and supplementary data (operands) necessary for the CPU 304 to execute each instruction. Data for the configured control program (sometimes simply referred to as control program data) is stored, and a specific value (00H in this embodiment) is uniformly set in the storage area of the ROM 306 corresponding to the non-use area. In the storage area of the ROM 306 that is stored and corresponds to the ROM data area, reference data (for example, the above-mentioned various lottery data) referred to by the control program is stored. Also, management data for managing the control program (for example, data indicating the final address of the control program data) is stored in the storage area of the ROM 306 corresponding to the other area. In this embodiment, 1-byte (8-bit) data can be stored in the storage area of the ROM 306 corresponding to each address in the ROM area, and each of the above-described data (command data, supplemental data, reference data) , Management data) is data having a number of bytes exceeding 1 byte (for example, 2 bytes), the data is divided and stored for each byte in the storage area of the ROM 306 corresponding to a plurality of consecutive addresses in the ROM control area. doing.

  Further, the control program is composed of a plurality of subroutines, and it is possible to move to the top address of the subroutine by a CALL instruction, an EXESUB (EXECUTE SUBBROUTINE) instruction, which will be described later, and execute the subroutine sequentially. .

  By the way, in the field of gaming machines, it is necessary to limit the storage area for storing control program data from the viewpoint of improving the inspection efficiency of the control program. In this embodiment, the ROM control area is limited to 0000H to 0BB0H as described above. doing. In addition, from the viewpoint of preventing unauthorized modification, it is necessary to store control program data in a young address in the ROM control area so that no unused area or unused data is provided between control program data. In order to fill the storage area of the control program data that is not used at the stage, work such as dividing and assigning another control program data occurs, and as a result, a lot of control program data for calling a subroutine is required. Furthermore, since subroutines are frequently used to improve control program development efficiency and to simplify maintenance work such as control program debugging, a large amount of control program data is required to call the subroutines. .

  In order to enhance the interest of the game in such a development environment, conventional control program data stored in the storage area of the ROM 306 corresponding to the ROM control area (for example, calling the above subroutine) It is necessary to secure a storage area where new control program data can be added to the storage area of the ROM 306 corresponding to the ROM control area.

  In particular, a control program for executing a timer interrupt process for executing a predetermined process at a predetermined period (for example, 10 ms) includes a plurality of external information randomly generated from a plurality of game control processes (for each sensor). Control for invoking many subroutines, such as processing for detecting changes (for example, input port state update processing (step S205)) and processing based on detection results of external information (for example, device monitoring processing (step S237)) Since the program data is included, it is necessary to compress the control program data for calling a subroutine included in the control program for executing the timer interrupt process.

In addition, in order to be able to perform stable game control, the above-described timer interrupt process must be focused and stabilized. Specifically, it is indispensable to suppress coding mistakes and to improve processing speed in order to execute predetermined processing at predetermined intervals (for example, 10 ms) (to ensure real-time performance). Therefore, it is necessary to devise a control program for calling a subroutine (details will be described later).
<Command data of main control unit>

  Next, the command data of the main control unit 300 will be described. FIG. 18 is a diagram illustrating an example of a configuration of instruction data of the main control unit 300. FIG. 19A is a diagram showing upper and lower bits of instruction data of the main control unit 300, and FIG. 19B is a diagram showing an example of an instruction data table.

  For example, when the instruction data is composed of 1-byte (8-bit) data, the instruction data of the main control unit 300 can be defined up to 256 patterns. Note that the defined instruction data is not stored in the ROM 306 but is incorporated in the CPU 304 in hardware. Further, when the 1-byte instruction data is classified according to the upper 4 bits and the lower 4 bits, the relationship between the pattern and the instruction data is as shown in FIG. For example, INC (instruction data) used for “INC BC (instruction for adding one BC register)” is assigned to upper bit 0H (0000B) and lower bit 3H (0011B), and “DEC B (B register DEC (instruction data) used for “an instruction for subtracting 1 from” is assigned to the upper bit 0H (0000B) and the lower bit 5H (0101B).

  In addition, as a method of allocating instruction data having a pattern number exceeding 256 patterns of instruction data that can be defined by 1 byte length, for example, a new one byte is added to one pattern among the 256 patterns defined by 1 byte. There is a method of defining instruction data of up to 511 patterns (255 patterns (1 byte instruction data) +256 patterns (2 bytes instruction data)) by associating 256 patterns to be defined. Since this instruction is used because it is composed of byte data, the storage area of the ROM 306 corresponding to the ROM control area is compressed rather than using the above-described one-byte instruction data.

  Therefore, in this embodiment, the region surrounded by the thick line in FIG. 19B, that is, the combination of the upper bit 1H (0001B) and the lower bits 8H (1000B) to FH (1111B), and the upper bit 3H (0011B) An area formed by a combination of the lower bits 8H (1000B) to FH (1111B) is set as a special area for assigning an EXESUB instruction to be described later. As described above, a limited hardware resource (for example, 1 byte) can be used by using, as a special area, an empty area from which instruction data has not been allocated or the allocated instruction data has been deleted. A definable pattern (256 patterns)) can be used effectively, and compression of the storage area of the ROM 306 corresponding to the ROM control area by instruction data can be suppressed.

Also, the instruction data is grouped by role (an area consisting of a combination of a plurality of lower bits consecutive to one upper bit or one lower bit for easy checking of the machine language after assembly. An instruction data having the same system role is assigned to an area composed of a combination of a plurality of consecutive upper bits with respect to a bit and assigned to an instruction data table (for example, upper bit 8H (1000B) and lower bit 0H (ADD instruction in a part defined by a combination of (0000B) to 7H (0111B)). In recent years, in order to reduce the development burden of the chip, the instruction data allocated to the conventional instruction data table has been reduced, or new instruction data has been added to the part to which the reduced instruction data has been allocated. Develop. For this reason, it is necessary to assign the instruction data of the same system to be added as a group when newly adding instruction data for data compression while simplifying checking the machine language after assembly. In the present embodiment, the problem is solved by allocating the EXESUB instruction as a group to a special area. Furthermore, in order to efficiently allocate new instruction data to the subdivided special area, it is necessary to allocate the instruction data group to be added as a subdivided group. In this embodiment, the EXESUB is further allocated. The problem is solved by assigning instructions to sub-groups and assigning them to special sub-regions.
<CALL instruction>

  Next, a CALL instruction which is one of the above control programs will be described. FIG. 20 conceptually shows an example of address movement by the CALL instruction, and FIG. 21 shows an example of instruction data and supplementary data of the CALL instruction.

  For example, when the address of the control program being executed is 0700H and the start address of the transfer destination subroutine is 03FFH, the relative addresses of the two (the transfer source address and the transfer destination address) are indicated by the symbol X in FIG. The address difference is 0301H (= 0700H-03FFH), and this relative address can be expressed by 2-byte data. Here, when this control program is expressed by a CALL instruction, as shown in FIG. 21A, a total of 3 bytes of control is performed with 1 byte of instruction data indicating the CALL instruction and 2 bytes of supplementary data indicating the destination address. Program data is required.

  Further, when the address of the control program being executed is 0700H and the start address of the destination subroutine is 075FH, the relative address of both is 005FH (= 075FH-03FFH), as indicated by the symbol Y in FIG. The relative address can be expressed by 1-byte data. Even in this case, if this control program is expressed by a CALL instruction, as shown in FIG. 21B, a total of 1 byte of instruction data indicating the CALL instruction and 2 bytes of supplementary data indicating the destination address is added. 3-byte control program data is required.

  That is, the control program for executing the CALL instruction requires 3 bytes of control program data regardless of the destination address (any address in the storage area (0000H to FFFFH) that can be defined by 2 bytes). Become.

When executing the CALL instruction, the CPU 304 specifically executes the CALL instruction after executing the process of storing the data (2 bytes) stored in the PC register (program counter) in the stack area. Subroutine can be called by executing a process (moving to the start address of the subroutine) that stores the supplementary data (data indicating the start address of the transfer destination subroutine (2 bytes)) in the PC register (program counter) It becomes.
<EXESUB instruction>

  Next, the EXESUB instruction, which is one of the above control programs, will be described. FIG. 22A is a diagram showing an example of the configuration of the EXESUB instruction, and FIG. 22B is a diagram showing an instruction data table in which the EXESUB instruction is assigned to the free area of FIG. 19B. It is.

The EXESUB instruction is the same as the above CALL instruction in that it can call a subroutine, but the structure of instruction data / supplementary data and the storage capacity required for control program data are different (details will be described later) ).
<EXESUB instruction / instruction data>

  In the present embodiment, the instruction data of the EXESUB instruction includes 0 (fixed value) of bit 7, 0 (fixed value) of bit 6, bit, in order from the most significant bit 7 (MSB) to the least significant bit 0 (LSB). 5 for α (variable value), 1 for bit 4 (fixed value), 1 for bit 3 (fixed value), β for bit 2 (variable value), γ for bit 1 (variable value), δ for bit 0 (variable) Value) is a total of 8 bits (1 byte). That is, the EXESUB instruction becomes instruction data of a pattern (2 4 = 16 patterns) defined by changing the above-described variable value. Note that m, which is a total of 4 bits of data of α of bit 5, β of bit 2, γ of bit 1, and δ of bit 0, can represent a numerical range of 0H to FH, and represents the start address of the subroutine to be called It is a part of identification information (binary format) that can be identified.

  Further, as described above, the instruction data of the EXESUB instruction is an area surrounded by a thick line in the instruction data table shown in FIG. 5B, that is, the upper bit 1H (0001B) and the lower bits 8H (1000B) to FH ( 1111B) and a free space consisting of a combination of the upper bit 3H (0011B) and the lower bits 8H (0111B) to FH (1111B) (in the past, no instruction data has been assigned or assigned instruction data Allocated to the deleted area).

  As described above, the instruction data of the EXESUB instruction is configured such that a fixed value bit is inserted between the variable value bit and the variable value bit, thereby grouping the instruction data of the EXESUB instruction. , It becomes possible to allocate to the above-mentioned free space. Therefore, the machine language of the EXESUB instruction data can be easily checked and coding errors can be suppressed.

  Furthermore, as described above, the instruction data of the EXESUB instruction has a variable value bit number (for example, 1 (above 1) described above) with one or more fixed value bits (for example, the above bit 4 and bit 3) interposed therebetween. Compared with bit 5)), the number of lower-order variable values (for example, 3 (bit 2, bit 1, bit 0 above)) across the fixed value bit is increased (the storage capacity is increased). ), The instruction data of the EXESUB instruction can be grouped and finely allocated to the above-described free area. Therefore, limited hardware resources (for example, patterns that can be defined by 1 byte (256 patterns)) can be used effectively and stored in the storage area of the ROM 306 corresponding to the ROM control area by compressing instruction data. The conventional control program data can be compressed. It should be noted that the number of bits of the upper variable value across the fixed value is larger than the number of bits of the lower variable value across the one or more fixed value bits (the storage capacity is increased). Even if it is comprised, it has the above-mentioned effect.

  Note that the correspondence relationship between the above-described variable values α, β, γ, and δ and the bit 7 to 0 of the instruction data of the EXESUB instruction is not limited to the above-described correspondence relationship. , Bit 2 may be associated with variable value β, bit 1 may be associated with variable ground γ, and bit 0 may be associated with variable value δ.

Furthermore, the order of the variable values α, β, γ, and δ constituting the instruction data may be any order, but the above-described order (α, β, γ, δ in order from the upper bit), that is, an address described later. By setting m in mn to an order that can be defined by arranging α, β, γ, and δ in order from the upper bits, it is possible to easily check the machine language of the EXESUB instruction data and suppress coding errors.
<EXESUB instruction / supplementary data>

  In the present embodiment, supplementary data for the EXESUB instruction is composed of n that is 8-bit data indicating a numerical range of 00H to FFH.

Therefore, the EXESUB instruction has a total of 12 bits configured by arranging m, which is 4-bit data included in the instruction data, and n, which is 8-bit supplemental data, in this order (m is a higher order and n is a lower order). This is an instruction that can call a subroutine having a head address in an address area (0000H to 0FFF) definable by the address mn. That is, n is at least a part of information obtained by removing a part (m) of the identification information from the identification information (binary format) that can identify the head address of the subroutine to be called.
<EXESUB instruction / subroutine call>

  FIG. 23 is a diagram conceptually showing an example of address movement by the EXESUB instruction. In this embodiment, m (4-bit data) indicates the lower 4 bits (0H to FH) of the upper 1 byte among the addresses 0000H to 0FFFH in the ROM area, as shown in FIG. (8-bit data), as shown in FIG. 4B, when the storage area of 100H units (0m00H to 0mFFH: m = 0H to FH) expressed by the upper address m is one block, This is a value indicating an address (00H to FFH) in one block.

  Note that even if the address area where the destination address can be set is defined as either n or m data as upper address data, the effect of reducing the control program data described later can be obtained. By defining m included in the instruction data as upper address data, the instruction data of the EXESUB instruction can be grouped and associated with the address area as shown in FIG. can do.

  In addition, since the instruction data of the EXESUB instruction is configured to include m which is a part of the head address of the subroutine to be called, even if the destination address data is wrong, If erroneous data is included in the instruction data, execution of the control program is stopped, so that coding errors can be suppressed.

  FIG. 24 shows an example of calling the top address of a subroutine by the EXESUB instruction, and FIG. 25 shows an example of instruction data and supplement data of the EXESUB instruction.

  For example, suppose that the address of the control program being executed is 0700H and the start address of the transfer destination subroutine is 03FFH. When this control program is expressed by a CALL instruction, as described above, the relative address (the difference between the source address and the destination address) indicated by the symbol X ′ in FIG. 24 is 0301H (= 0700H-03FFH). This relative address can be expressed by 2 bytes of data, and requires 1 byte of instruction data and 2 bytes of supplementary data for a total of 3 bytes of control program data.

  On the other hand, when this control program is expressed by an EXESUB instruction, the movement to the destination address is conceptually indicated by X ″, and this relative address is 00FFH (= 03FFH-0300H) that can be expressed by 1-byte data. ) That is, as shown in FIG. 25 (a), the EXESUB instruction requires 1 byte of instruction data represented by 0101101B and 1 byte of supplementary data represented by 11111111B, which requires 2 bytes of control program data. .

  Further, a case where the address of the control program being executed is 0700H and the start address of the subroutine to be called is 075FH will be described. In this case, even if this control program is expressed by either a CALL instruction or an EXESUB instruction, as shown above, the relative address of both can be expressed by 1 byte, as indicated by the symbol Y ′ in FIG. 005FH (= 0C5FH-0C00H), and this relative address can be expressed by 1-byte data. However, when this control program is expressed by a CALL instruction, a total of 3 bytes of 1-byte instruction data and 2 bytes of supplementary data are provided. Byte control program data is required.

  On the other hand, when this control program is expressed by an EXESUB instruction, as shown in FIG. 25 (b), a total of 2 bytes of control including 1-byte instruction data represented by 00001111B and 1-byte supplement data represented by 0101111B. Program data is required, and the data per instruction can be reduced by 1 byte compared to the CALL instruction described above.

  Therefore, the control program for executing the EXESUB instruction requires control program data of 2 bytes regardless of the destination address (any address in the storage area (0000H to 0FFFH) that can be defined by 12 bits). As compared with the above CALL instruction, the control program data per instruction can be reduced by 1 byte.

  That is, by using the above EXESUB instruction for a control program for calling a subroutine, a control program (for example, a CALL instruction) for calling a conventional subroutine can be compressed and stored in the storage area of the ROM 306 corresponding to the ROM control area. The conventional control program data can be compressed.

  Note that when executing the EXESUB instruction, the CPU 304 specifically executes the EXEBUS instruction after executing the process of storing the data (2 bytes) stored in the PC register (program counter) in the stack area. Subroutine can be called by executing a process (moving to the start address of the subroutine) that stores the supplementary data (data indicating the start address of the transfer destination subroutine (2 bytes)) in the PC register (program counter) It becomes.

  Further, by using the above EXESUB instruction for the control program for calling the subroutine, the processing speed of the control program for calling the subroutine is improved (the number of states is reduced) than the conventional (for example, CALL instruction) due to the compression of the control program. Less).

  Further, as described above, the ROM area stores all control program data in the storage area of the ROM 306 corresponding to the area (0000H to 0FFFH in the present embodiment) that can be called by the above-described EXEBUS instruction. ROM control area (0000H to 0BB1H in this embodiment) is provided, and at least a ROM in which control program data is stored from an area (0000H to 0FFFH in this embodiment) that can be called by the above-described EXEBUS instruction The area (0BB1H to 0FFFH in this embodiment) excluding the control area (0000H to 0BB1H in this embodiment) is configured to be a non-use area, and the ROM data area follows the non-use area. It is configured as follows.

In the gaming machine having the ROM area as described above, the CPU 304 is used by using the EXESUB instruction described above as a control program for calling a subroutine (the control program data of the EXESUB instruction is stored in the storage area of the ROM 306 corresponding to the ROM control area). However, since data other than control program data and non-use data is not directly read as instruction data, malfunctioning of the CPU 304 due to a coding error in supplementary data may be prevented.
<Example of control program>

  FIG. 26 is a program list showing an example of a control program for the above-described main control unit timer interrupt process. “**” indicates supplementary data for the EXESUB instruction.

  When starting the timer interrupt process, the CPU 304 first executes a process for restarting the WDT, executes a predetermined process (details omitted), and then uses the EXEBUS instructions (1) to (19), respectively. The following subroutine is read out. Input port status update processing, basic random number initial value update processing, basic random number update processing, production random number update processing, timer update processing, winning a prize counter update processing, winning acceptance processing, payout request number transmission processing, general drawing state update processing, Figure-related lottery process special figure prefetch control process, special figure 2 state update process, special figure 1 state update process, special figure 2 related lottery process, special figure 1 related lottery process, command setting transmission process, external output signal setting process, device Monitoring processing is executed, and other processing (details are omitted) is executed. Although not described in detail, the start address of the subroutine called by the above-described EXESUB instructions (1) to (19) is included in the ROM control area (0000H to 0BB0H in this embodiment).

  In this way, the above EXEBUS instruction is used for the control program that calls the subroutine in the timer interrupt processing (the control program data of the EXESUB instruction is stored in the storage area of the ROM 306 corresponding to the timer interrupt processing area in the ROM control area). Thus, timer interrupt processing can be stabilized.

  By the way, in the development of a gaming machine, a new gaming machine is generally developed by changing (deleting or adding) a part of a conventional control program. In particular, it is desirable to avoid changing the control program as much as possible in order to stabilize game control.

  Therefore, it is not necessary to use the above EXEBUS instruction for all the control programs that call subroutines in the ROM area (for example, the timer interrupt processing area), depending on necessity (for example, whether or not the above-described control program data is requested to be compressed). May be used as appropriate.

Furthermore, the above-described EXESUB instruction is a conventional 3-byte instruction control program data (for example, CALL instruction) composed of 1-byte instruction data and 2-byte supplement data, and 1-byte instruction data and 1-byte supplement. Although the control program is compressed into control program data of 2-byte instructions composed of data, any control program that compresses the control program composed of instruction data and supplemental data may be used. In other words, the EXESUB instruction includes instruction data including a part of identification information (binary format) that can identify the start address of a subroutine to be called, and the identification information included in the instruction data is excluded from the identification information. The control program is composed of supplemental data composed of at least a part of information, and more specifically, each of the above-described instruction data and supplemental data has a data length (for example, read by the CPU 304 in one process). It may be an integer multiple of 8 bits).
<Modification of ROM control area>

  FIG. 27 shows a ROM control area (in this embodiment) in which control program data is stored rather than an area (0000H to 0FFFH in this embodiment) in which the ROM area can be called by the above-described EXEBUS instruction (EXESUBmn). , 0000H to 11B8H) is a diagram showing a case where it is configured to be wide. FIGS. 28A and 28B are diagrams showing an example in which the area of the top address of a subroutine that can be called by the EXESUB instruction (EXESUBmn) is expanded.

  For example, as shown in FIG. 27, the ROM control area (0000H to 11B8H in this embodiment) is the area of the top address of a subroutine (0000H to 0FFFH in this embodiment) that can be called with the EXEBUS instruction (EXESUBmn). When the area is wider, the ROM control area is composed of an EXESUB target area (0000H to 0FFFH in the present embodiment) and an EXESUB non-target area (for example, 1000H to 11B8H).

  In this case, even if the above-mentioned CALL instruction is used to supplement the instruction for calling the subroutine having the address corresponding to the EXESUB non-target area with the above-mentioned CALL instruction, as described above, it is possible to improve the fun of the game while being stable. It is possible to realize game control.

  However, as shown in FIG. 28, the above effect can be further enhanced by expanding the area of the top address of the subroutine that can be called by the EXESUB instruction (EXESUBmn).

  As specific means, as shown in FIGS. 28A and 28B, a variable value σ, which will be described later, is used to maintain the storage capacity required for the EXESUB instruction (EXESUBmn) and to execute the EXEBUS instruction (EXESUBMn). The command data is expanded. In the following, the variable value σ newly added to the figure will be described.

  The variable value σ is used to extend the EXESUB instruction (EXESUBm′n described later), and as shown in FIG. 28A, the instruction data of the EXESUB instruction (EXESUBm′n described later) (in this embodiment, 8 bits), which changes according to the value of m ′ of the address m′n indicating the start address of the subroutine to be called.

  In the instruction data table, as shown in FIG. 28 (b), the EXESUB instruction (EXESUBm'n) expanded by the variable value σ is an area surrounded by a bold line shown in FIG. It is allocated to an empty area consisting of a combination of bit 5H (0101B) and lower bits 8H (1000B) and 9H (1001B).

  Here, m ′ is data having the same role as m shown in FIG. 22A, where m is α of bit 5, β of bit 2, γ of bit 1, and δ of bit 0. In this case, m ′ is a total of 5 bits of data of σ of bit 6, α of bit 5, β of bit 2, γ of bit 1 and δ of bit 0. However, m ′ is data that can express a numerical range of 00H to 11H, and is a part of identification information (binary format) that can identify the head address of a subroutine to be called.

  As described above, the address area (000H to FFF) definable by the address mn is expanded using the EXESUB instruction (EXESUBm'n) in which the variable value σ is provided in the bit 6 of the instruction data of the above EXEBUS instruction (EXESUBmn). (By making the address area definable by the address m′n into 0000H to 11FFH), the subroutine having the address corresponding to the above-mentioned EXESUB non-target area at the top address is called using the EXESUB instruction (EXESUBm′n) Can do.

  The correspondence relationship between the above-described variable values σ, α, β, γ, and δ and the bits 7 to 0 of the instruction data of the EXESUB instruction (EXESUBm'n) is not limited to the above-described correspondence relationship. Similarly, the variable value α may correspond to the bit 4, the variable value β to the bit 2, the variable value γ to the bit 1, the variable value δ to the bit 0, and the variable value δ to the bit 0, and the correspondence described with reference to FIG. It may be the same as the relationship.

  Furthermore, the order of the variable values σ, α, β, γ, and δ constituting the instruction data may be any order, but the above-described order (σ, α, β, γ, δ in order from the upper bit), that is, By setting m ′ of address m′n, which will be described later, in order that can be defined by arranging σ, α, β, γ, and δ from the upper bits in order, it is possible to easily check the machine language of the EXESUB instruction data. Coding mistakes can be suppressed.

  In this way, by providing the above-mentioned EXESUB instruction (EXESUBm'n) corresponding to the above-described ROM control area (for example, 0000H to 11B8H), the data is stored in the storage area of the ROM 306 corresponding to the ROM control area. The conventional control program data can be compressed.

  Further, as described above, the ROM area is a ROM control area in which control program data is stored rather than an area (0000H to 11FFH in this embodiment) that can be called by the above-described EXEBUS instruction (EXESUBm'n). The area excluding (in this embodiment

  By the way, as shown in FIG. 17 and FIG. 27, the ROM control area provided for each developed game machine may be different among the limited ROM control areas. In addition, it is wasteful from the viewpoint of development man-hours and costs, and development of a stable game control that uses a CPU that includes each of the above-mentioned EXESUBmn or EXESUBmn'n as instruction data is unnecessary from the viewpoint of development man-hours and costs. It will be difficult to realize. Therefore, even in the gaming machine having the ROM control area shown in FIG. 17, it is desirable to use EXESUBm′n for the EXESUB instruction.

Even in this case, the ROM control area (0000H to 0BB1H in this embodiment) stores control program data rather than the area (0000H to 11FFH in this embodiment) that can be called by EXESUBm'n. Therefore, at least an area that can be called by the above-described EXESUBm'n, excluding a ROM control area in which control program data is stored (in this embodiment, 0BB1H to 11FFH) ) In the non-use area, and the ROM data area may follow the non-use area.
<Special drawing state update processing, general drawing state update processing>

  Next, a part of the control program for the above-described special figure 2 state update process (step S225), special figure 1 state update process (step S227), and general figure state update process (step S221) will be described with reference to FIG. To do. FIG. 8A shows a part of the control program for the special figure 2 state update process and the special figure 1 state update process, and FIG. The part is extracted.

  For example, in the special figure state update process shown in FIG. 6A, first, by executing the instruction “LD L, Low.vbTokuzuStatus”, the address defined as vbTokuzuStatus in FIG. In the example, the lower byte (60H in this example) of F060H which is an address indicating the special figure status storage area provided in the RAM 308 is stored in the L register.

  Subsequently, by executing the instruction “JP moReadMemory”, the process moves to moReadMemory (memory reading process) shown in FIG. In this memory read processing, F0H is first stored in the H register by executing the instruction “LD H, F0H”, and then indicated by the HL register by executing the instruction “LD A, (HL)”. The content (in this example, F060H) of the address (in this example, F060H) is stored in the A register. Subsequently, after executing the instruction “AND A”, the process returns to the special figure state update process of the reading source. It should be noted that the common figure status update process shown in FIG. 6B also uses the common subroutine moReadMemory (memory read process) to read the common figure status stored in the common figure status storage area of the RAM 308. I do,

  As described above, when the conventional memory reading process shown in FIG. 5C is used, an instruction “LD H, F0H” causes the upper address of the special figure status storage area or the general figure status storage area to be higher. (F0H) is analyzed, and there is a risk of causing fraud. For this reason, in the present embodiment, the memory read process shown in FIG. 5E is adopted instead of the conventional memory read process shown in FIG.

  In the memory read processing according to this embodiment, the value of the T register is stored in the A register by executing the instruction “LD A, T”. As described above, a specific value ( Since F0H) is stored, F0H is stored in the A register. The subsequent processing is the same as the conventional processing, but since the T register is used instead of using the immediate value, the upper address (F0H) of the address of the special status status storage area or the normal status storage area is In some cases, there is little risk of analysis and fraud can be prevented. Further, when the immediate value is used, the possibility of a coding error increases, for example, when F0H is mistakenly input as F1H. However, if the T register is used, the coding error may be prevented in advance.

FIG. 30 is a diagram comparing the machine language of the conventional memory reading process shown in FIG. 29C and the machine language of the memory reading process according to the present embodiment shown in FIG. When the “LD H, F0H” instruction on the first line in the conventional memory read processing is assembled, the machine language is “26F0H” and includes “F0H”. Therefore, in the conventional memory read processing, There is a risk that the upper address (F0H) of the address in the storage area for the normal status is analyzed. On the other hand, when the “LD A, T” instruction on the first line in the memory read processing of the present embodiment is assembled, the machine language is “ED01H” and does not include “F0H”. Therefore, in the memory read processing of the present embodiment, There is a very low possibility that the upper address (F0H) of the special figure status storage area and the general figure status storage area will be analyzed, and it may be possible to prevent fraud.
<Special drawing 1 related lottery processing>

  Next, the special figure 1 related lottery process in the above-mentioned main control part timer interruption process is demonstrated using FIG. In addition, the figure is a flowchart which shows the flow of a special figure 1 related lottery process.

  In step S1001, special symbol random number transfer processing is performed. In this special symbol random number transfer process, the random value stored in the primary is transferred (stored) to the special symbol related lottery random number storage area provided in the RAM 308. In step S1002, a special symbol per lottery process is performed. In the lottery processing per special symbol, the above-mentioned special symbol random value (the special symbol 1 random value, the special symbol 2 random value) is compared with the special symbol lottery data stored in the ROM 306 in advance, and the lottery result The 15R big hit flag, the 2R big hit flag, the first small hit flag, the second small hit flag, the first off flag, the second off flag, the special figure probability fluctuation flag, the normal figure probability fluctuation flag, etc. Set and set the special symbol gaming state while fluctuating.

  In step S1003, a display symbol lottery process is performed. In this display symbol lottery process, a lottery for comparing the display symbol determination random number stored in the RAM 308 with the display symbol lottery data stored in advance in the ROM 306 is performed, and according to the lottery result, the 15R special jackpot symbol (special Figure A), 15R jackpot symbol (Special Figure B), Sudden Probability Variation (Special Figure C), Sudden Short-Time Design (Special Figure D), Hidden Probability Variation (Special Figure E), Sudden Normal Design (Special Figure F), No. One small symbol (Special G), second small symbol (Special H), first off symbol (Special I), and second off symbol (Special J) are set. .

  In step S1004, a special symbol variation time lottery process is performed (details will be described later). In step S1005, a special symbol variation time setting process is performed. In this special symbol variation time setting process, a timer corresponding to the variation pattern (pattern number) acquired in the special symbol variation time lottery process in step S1004 is set (stored) as a special symbol variation timer. In step S1006, special symbol on-hold information migration processing is performed. In this special symbol hold information transfer process, the special symbol hold information is transferred (stored) to the previous storage area in the order of change, and then the process ends.

Here, as an example, the special figure 1 related lottery process (step S231) in the above-described main control unit timer interrupt process has been described. For example, the special figure 2 related lottery process (step S229) and the common figure related lottery process Similar processing can be applied to (step S223).
<Data table and variable storage area of main controller>

Next, a part of the data table stored in the ROM 306 of the main control unit 300 and a part of the variable storage area provided in the RAM 308 will be described with reference to FIGS. 32 and 33.
<Table selection table>

  FIG. 32A shows an example of the table selection table. FIG. 33 shows a part of the definition of the data table stored in the ROM 306 of the main control unit 300 and the variable storage area provided in the RAM 308. It is an example of the program list which showed a part of definition of.

In the table selection table shown in FIG. 32 (a), the destination address indicating the address of the ROM 306 in which the first variation pattern selection table (to be described later) is stored is 0 for each number of special figure variation games held. It is divided and stored in four for individual use. Specifically, 174FH is stored in the 2-byte storage area of the ROM 306 corresponding to the addresses 1600H to 1601H of the ROM data area as the destination address of the first variation pattern selection table to be referred to when the number of holds is 0. (1600 DEFB 174FH). In addition, 174FH is stored in the 2-byte storage area of the ROM 306 corresponding to the addresses 1602H to 1603H of the ROM data area as the destination address of the first variation pattern selection table to be referred to when the number of holds is 1 ( 1602 DEFB 174FH). Further, 174FH is stored in the 2-byte storage area of the ROM 306 corresponding to the addresses 1604H to 1605H of the ROM data area as the destination address of the first variation pattern selection table to be referred to when the number of holds is 2 ( 1604 DEFB 174FH). In addition, 1755H is stored in the 2-byte storage area of the ROM 306 corresponding to the addresses 1606H to 1607H of the ROM data area as the destination address of the first variation pattern selection table to be referred to when the number of holds is 3 ( 1606 DEFB 1755H).
<First variation pattern selection table>

FIG. 32B is a diagram showing an example of the first variation pattern selection table. This first variation pattern selection table stores the difference (offset) between the address of the table and the address where the second variation pattern selection table described later is stored, and the number of random numbers. Specifically, AEH is stored as an offset in the 1-byte storage area of the ROM 306 corresponding to the address 1750H of the ROM data area, and the 1-byte storage area of the ROM 306 corresponding to 1751H that is continuous with this address. 32 stores 20 as the number of random numbers (1750H DEFB AEH, 20), and the storage area of the ROM 306 corresponding to the addresses 1752H to 1759H of the subsequent ROM data area is as shown in FIGS. 32 (b) and 33. In addition, an offset of 1 byte length and the number of random numbers of 1 byte length are alternately and continuously stored. In the first variation pattern selection table, the number of random numbers is indicated by a decimal number.
<Second variation pattern selection table>

FIG. 32C is a diagram showing an example of the second variation pattern selection table. The second variation pattern selection table stores a pattern number and the number of random numbers. Specifically, 01H is stored as a pattern number in the 1-byte storage area of the ROM 306 corresponding to the address 1800H in the ROM data area, and the 1-byte area indicated by 1801H that is continuous with this address is stored in the 1-byte area. , 255 is stored as the number of random numbers (1800H DEFB 01H, 255), and the storage area of the ROM 306 corresponding to the addresses 1802H to 180FH of the subsequent ROM data area is as shown in FIG. 32 (c) and FIG. A pattern number of 1 byte length and the number of random numbers of 1 byte length are stored alternately and continuously. In the second variation pattern selection table, the number of random numbers is indicated by a decimal number.
<Variable storage area>

FIG. 32D is a diagram showing a reserved number storage area, a random number 1 storage area, and a random number 2 storage area provided in the storage area of the RAM 308 corresponding to the addresses F040H to F042H of the RWM area. A 1-byte storage area of the RAM 308 corresponding to the RWM area address F040H has a reserved number storage area (F040 vbHoryuuSP1 DEFS 1), and the reserved number storage area stores the reserved number. A random number 1 storage area is provided in the 1-byte storage area of the RAM 308 corresponding to the address F041H (F041 vbRndHendou1 DEFS 1), and the random number 1 is stored in the random number 1 storage area. A random number 2 storage area is provided in the 1-byte storage area of the RAM 308 corresponding to the address F042H (F042 vbRndHendou2 DEFS 1), and the random number 2 is stored in the random number 2 storage area.
<Special symbol variation time lottery processing>

  Next, the special symbol variation time lottery process in the special figure 1 related lottery process described above will be described with reference to FIGS. 34 and 35. FIG. 34 is a flowchart showing the flow of the special symbol variation time lottery process, and FIG. 35 is an example of a program list of the special symbol variation time lottery process.

  In step S1101, effect random number acquisition processing is performed. In this effect random number acquisition process, the special figure 1 random value (0 to 255) acquired in the special figure 1 related lottery process is stored in the random value 1 storage area (RWM area address F041H). The special figure 2 random value (0 to 255) acquired in the special figure 2 related lottery process is stored in the random value 2 storage area (address F042H of the RWM area).

  In the next step S1102, the start address (1600H in this embodiment) of the table selection table (FIG. 32A) is transferred to the HL register (LD HL, tableSelectTable). As a result, 1600H is stored in the HL register.

  In the next step S1103, the number of reservations stored in the above-mentioned reservation number storage area (address R040H of the RWM area) is transferred to the A register (LDT A, (40H)). Here, as shown in FIG. 36, the “LDT A, (n: immediate value)” instruction is an instruction for loading data at an address indicating the T register in the upper order and the immediate value in the lower order into the A register. In this embodiment, since F0H is stored in the T register, when the “LDT A, (40H)” instruction is executed, an address (F040H) indicating the T register (F0H) as the higher order and the immediate value (40H) as the lower order. ), That is, the number of holds stored in the hold number storage area is loaded (transferred) to the A register. For example, when the hold number stored in the hold number storage area is 2, 02H is loaded (transferred) to the A register.

  In the next step S1104, the value of the A register is added to the value of the A register (ADD A, A). In the above example, 04H is stored in the A register by adding the value (02H) of the A register to the value (02H) of the A register. In the next step S1105, the value of the A register is added to the HL register (ADDTWOONE HL, A). Although details will be described later, the ADDTWOONE instruction (ADDTWOONE HL, A) is an instruction for adding the 1-byte length value stored in the A register to the 2-byte length value stored in the HL register. In the previous example, 1604H is stored in the HL register by adding the value (04H) of the A register to the HL register (1600H).

  In the next step S1106, the value of the address indicated by the HL register is transferred to the DE register (LDTWO DE, (HL)). Here, as shown in FIG. 36, the “LDTWO DE, (HL)” instruction is an instruction for loading data at the address indicated by the HL register into the DE register. In the above example, 174FH is stored in the DE register by transferring the value (174FH) of the address (1604H) indicated by the HL register to the DE register.

  In the next step S1107, the value of the DE register and the value of the HL register are exchanged (EX DE, HL). In the above example, 174FH is stored in the HL register and 1604H is stored in the DE register by exchanging the value (174FH) of the DE register with the value (1604H) of the HL register.

  In the next step S1108, the random number 1 (special symbol variation time determination random number 1) stored in the random number 1 storage area is transferred to the A register (LDT A, (41H)). In this embodiment, since F0H is stored in the T register, when the “LDT A, (41H)” instruction is executed, an address (7E41H) indicating the T register (F0H) as the higher order and the immediate value (41H) as the lower order. ), That is, random number 1 stored in the random number 1 storage area is loaded (transferred) to the A register. For example, when the random number 1 stored in the random number 1 storage area is 250, 250 is stored in the A register.

  In the next step S1109, the values stored in the two consecutive addresses next to the address indicated by the value of the HL register are transferred to the BC register (INCTENSOU BC, (HL)). As will be described in detail later, the “INCENSOUBC, (HL)” instruction adds 1 to the 2-byte length value stored in the HL register, and 1 stored in the address indicated by the value of the HL register after the addition. After the byte length value is stored in the lower C register of the BC register, 1 is further added to the 2-byte length value stored in the HL register, and the address indicated by the value of the HL register after the addition is added. This is an instruction for storing the stored 1-byte value in the upper B register of the BC registers. In the above example, 1 is added to the 2-byte length value (174FH) stored in the HL register, and the 1-byte length value (AEH) stored at the address indicated by the HL register value (1750H) after the addition. ) Is stored in the lower C register of the BC register, 1 is further added to the 2-byte length value stored in the HL register, and the address indicated by the value (1751H) of the HL register after the addition is added. The stored 1-byte value (20) is stored in the upper B register of the BC registers.

  In the next step S1110, the value of the B register is subtracted from the value of the A register (SUB B). In the above example, the value (20) of the B register is subtracted from the value (250) of the A register. In the next step S1111, it is determined whether or not a carry has occurred as a result of the subtraction in step S1110, that is, whether or not the result of the subtraction has become a negative value. If applicable, the process proceeds to step S1112. Are repeatedly executed until the condition is satisfied (JP NC, LOOP01). In the previous example, a carry is generated by repeating the processing of steps S1109 to S1111 three times, and when proceeding to step S1112, the value of the B register is 8, the value of the C register is B0H, and the value of the HL register is 1755H. Become.

  In the next step S1112, the value of the C register is added to the value of the HL register (ADDTWOONE). In the above example, 1805H is stored in the HL register by adding the value (B0H) of the C register to the value (1755H) of the HL register. In the next step S1113, the random number 2 (special symbol variation time determination random number 2) stored in the random number 2 storage area (F042H in the present embodiment) is transferred to the A register (LDT A, (42H)). In this embodiment, since F0H is stored in the T register, when the “LDT A, (42H)” instruction is executed, an address (7E42H) indicating the T register (F0H) as the higher order and the immediate value (42H) as the lower order. ), That is, random number 2 stored in the random number 2 storage area is loaded (transferred) to the A register. For example, when the random number 2 is 148, 148 is stored in the A register.

  In the next step S1114, the values stored in the two consecutive addresses next to the address indicated by the value of the HL register are transferred to the BC register (INCTENSOU BC, (HL)). In the previous example, 1 is added to the 2-byte length value (1805H) stored in the HL register, and the 1-byte length value (04H) stored at the address indicated by the HL register value (1806H) after the addition. ) Is stored in the lower C register of the BC register, 1 is further added to the 2-byte length value stored in the HL register, and the address indicated by the value (1807H) of the HL register after the addition is added. The stored 1-byte value (128) is stored in the upper B register of the BC registers.

In the next step S1115, the value of the B register is subtracted from the value of the A register (SUB B). In the above example, the value (128) of the B register is subtracted from the value (148) of the A register. In the next step S1116, it is determined whether or not a carry has occurred as a result of the subtraction in step S1115, that is, whether or not the result of the subtraction has become a negative value. If so, the process proceeds to step S1117. The processing of steps S1114 to S1116 is repeatedly executed until it corresponds (JP NC, LOOP02). In the previous example, a carry is generated by repeating the processing of steps S1114 to S1116 twice, and when proceeding to step S1117, the value of the B register is 32, the value of the C register is 05H, and the value of the HL register is 1809H. become. In step S1117, the process ends after other processes are performed. Here, as an example, the processing related to special figure 1 and special figure 2 has been described, but the same processing can be applied to, for example, the number of reserved figures and random numbers in a normal figure.
<Special instruction of main control unit>

Next, a special command provided in the main control unit 300 will be described with reference to FIGS. FIG. 36 is a diagram illustrating a part of the commands included in the main control unit 300 and a description thereof. FIG. 37A is a diagram showing the upper and lower bits of the instruction data of the main control unit 300, and FIG. 37B is a diagram showing an example of the instruction data table.
<Special instruction / LDT instruction>

  The “LDT A, (n: immediate value)” instruction, which is one of the special instructions, is an instruction for loading data at an address indicating the T register in the higher order and the immediate value in the lower order as described above. In step S1103 of the special symbol variation time lottery process described above, by executing the “LDT A, (40H)” instruction, the address (F040H) indicating the T register (F0H) as the higher order and the immediate value (40H) as the lower order. Data, that is, the hold count stored in the hold count storage area is loaded (transferred) to the A register.

  Although not shown, the main control unit 300 further uses “LDT (n: immediate value),” for loading the data stored in the A register into an address indicating the T register as the upper and the immediate value as the lower. A "instruction. On the other hand, an instruction (for example, an instruction such as “LDT A, H”) for loading data at an address indicating the T register as a higher order and a general-purpose register (for example, an H register) as a lower order is stored in the A register. An instruction (for example, an instruction such as “LDTH H, A”) for loading the data into an address indicating the T register as the higher order and the general-purpose register (for example, the H register) as the lower order is not provided.

That is, the lower byte of the address that can be specified by the LDT instruction is limited to an immediate value, and it is prohibited to specify a general-purpose register (an error occurs during the assembly into the machine language and the assembly cannot be performed). . For this reason, the LDT instruction makes it easy to check the address when checking the program list and the like, and the value of the T register (the upper byte of the address) cannot be changed carelessly. And the occurrence of malfunctions may be reduced.
<Special instructions / LDTWO instructions>

  As described above, the “LDTWO OP1, (OP2)” instruction, which is one of the special instructions, loads the data at the addresses indicated by the two registers indicated by the second operand OP2 into the two registers indicated by the first operand OP1. The “LDTWO (OP2), OP1” instruction is an instruction to load the data of the two registers indicated by the first operand OP1 to the address indicated by the two registers indicated by the second operand OP2, for example, In step S1106 of the special symbol variation time lottery process described above, by executing the “LDTWO DE, (HL)” instruction, the value (174FH) of the address (1604H) indicated by the HL register is loaded (transferred) to the DE register. Thus, 174FH is stored in the DE register. When OP2 is a BC register or DE register that is not an HL register, OP1 becomes a BC register, DE register, HL register, IX register, and IY register, and only when OP2 is an HL register, OP1 becomes a BC register, DE register, HL register, AC register, AE register, BD register, IX register, IY register. The LDTWO instruction is suitable for protecting the A register and the HL register.

In the LDTWO instruction, the required number of states is 14 and the required number of bytes is 2 bytes. On the other hand, when the same processing as the LDTWO instruction is performed by the conventional instruction, as shown in FIG. 36, the required number of states is 14 (= 4 + 6 + 4) and the required number of bytes is 3 (= 1 + 1 + 1). . Therefore, if the LDTWO instruction is used when the address data indicated by the HL register is loaded into the DE register, the processing time of the control program can be shortened and the control burden can be reduced, and the amount of program code can be reduced. In some cases, the storage area of the ROM having a limited memory capacity can be used effectively. Further, even if the program code is increased in order to improve game play, an increase in program capacity and a decrease in processing speed may be suppressed. Also, by reducing the program capacity, it is possible to reduce developer coding errors and check mistakes, facilitate debugging, increase development efficiency, and whether or not it has an appropriate function as a game machine. Even when an external organization confirms, there may be a case where it is possible to provide a gaming table that can prevent mistakes in confirmation work and allow a player to play a game with peace of mind.
<Special instruction / ADDTWOONE instruction>

  The ADDTWOONE instruction (ADDTWONE OP1, OP2), which is one of the special instructions, is stored in the register indicated by the second operand OP2 into a 2-byte length value stored in the two registers indicated by the first operand OP1. This is an instruction for adding a 1-byte value (or a 1-byte immediate value indicated by the second operand OP2). The upper 1 byte of the instruction code of the ADDTWOONE instruction is a fixed value (EDH in this example), and the lower byte is a combination of the upper bit 4H (0100B) and the lower bits 0H (0000B) to 2H (0010B) of the instruction data table. It is assigned to a combination of the upper bit 4H (0100B) and the lower bits 4H (0100B) to 7H (0001B), 9H (1001H) of the instruction data table. In this way, by using an instruction area that has been considered as a free area in the past, it is possible to effectively use limited hardware resources and to embed an illegal instruction (hidden instruction) in the free area. In some cases, it is possible to prevent illegal acts and to ensure the fairness of the game. In this embodiment, the instruction code of the special instruction is 2 bytes long, but the byte length of the instruction code is not particularly limited, and may be 1 byte, for example. Further, only a specific instruction (for example, “ADDTWOONE HL, A” instruction) among the ADDTWOONE instructions may have a shorter instruction code (for example, 1 byte length) than other ADDTWOONE instructions. Further, only a specific instruction (for example, “ADDTWOONE HL, A” instruction) in the “ADDTWOONE OP1, A” instruction may have a shorter instruction code (for example, 1 byte length) than other ADDTWOONE instructions. In this case, the convenience of the command can be improved.

  Taking the “ADDTWOONE HL, C” instruction as an example, a value of 1 byte length stored in the C register indicated by the second operand is added to a value of 2 bytes length stored in the pair register HL indicated by the first operand. For example, in step S1112 of the special symbol variation time lottery process described above, by executing “ADDTWOONE HL, C”, a 2-byte length value stored in the HL register The value of the HL register is updated to 1805H by adding the 1-byte length value (B0H) stored in the C register to (1755H). It should be noted that the ADDTWOONE instruction (ADDTWOONE OP1, OP2) is less likely to carry, but the 2-byte length value (for example, FF01H) stored in the HL register is a 1-byte length value (for example, FF01H). When adding (FFH), carry occurs. That is, when a carry occurs after execution of the ADDTWONE instruction (ADDTWOONE OP1, OP2), it can be determined that the H register is FFH.

  Further, in the “ADDTWOONE HL, C” instruction, the required number of states is 8 and the required number of bytes is 2 bytes. On the other hand, when processing similar to that of the “ADDTWOONE HL, C” instruction is performed using a conventional instruction, as shown in FIG. 36, the required number of states is 22 (= 4 + 4 + 10 + 4), and the required number of bytes is 6 bytes ( = 1 + 1 + 3 + 1). Therefore, if the “ADDTWOONE HL, C” instruction is used to add the 1-byte length value stored in the C register to the 2-byte length value stored in the HL register, the processing time of the control program can be shortened. In addition, the control burden can be reduced and the amount of program code can be reduced, so that the storage area of the ROM having a limited memory capacity can be used effectively. Further, even if the program code is increased in order to improve game play, an increase in program capacity and a decrease in processing speed may be suppressed. Also, by reducing the program capacity, it is possible to reduce developer coding errors and check mistakes, facilitate debugging, increase development efficiency, and whether or not it has an appropriate function as a game machine. Even when an external organization confirms, there may be a case where it is possible to provide a gaming table that can prevent mistakes in confirmation work and allow a player to play a game with peace of mind.

  Further, in the case of an 8-bit arithmetic instruction that is conventionally provided in the CPU, the addition result (subtraction result in the case of the “SUB A, E” instruction) is input to the A register as in the case of the “ADD A, E” instruction. However, by executing the ADDTWOONE instruction and changing it to the “ADDTWOONE HL, E” instruction, “ADD L, E” is enabled, and it can be preserved without using the A register. As a result of using a wide A register for other instructions, the program capacity may be reduced). In addition, after executing “LD H, 00H” instruction and transferring 00H to the H register, “ADDTWONE HL, E” instruction is executed, the value of the E register is added to the L register, and the “SRL H” instruction is issued. Executing and checking whether or not the L register has overflowed can be saved without using the A register by checking whether or not the carry flag is set (use the A register which is widely used for other instructions) As a result, the program capacity may be reduced.

  In other words, the “ADD A, L” instruction can be executed, the “ADD L, A” instruction cannot be executed, but the “ADDTWONE HL, A” instruction can be executed. By increasing the number of instructions in the instruction set by one, it is possible to increase the number of registers that can store the addition results of 8-bit operations and also enable 16-bit to 8-bit operations. Two functions can be realized.

  In other words, the addition instruction “specific register pair ← specific register pair + specific register” is included in the instruction set, and the lower register of the specific register pair is a register different from the 8-bit arithmetic accumulator.

  Conventionally, since it was not desired to increase the number of instructions in the instruction set, only 16-bit arithmetic and 8-bit arithmetic are mounted. Further, the 16-bit accumulator is only a specific register pair among a plurality of register pairs, and the 8-bit accumulator is Although only a specific register among a plurality of registers is used, a plurality of functions can be realized with a small increase in the number of instructions.

Also, in order to check whether the HL register is 0, conventionally, after the value of the H register is transferred to the A register with the “LD A, H” instruction, the “OR A, L” instruction is executed and then the 0 flag is set. Whether or not the HL register is 0 is confirmed. That is, since an 8-bit operation is executed to check whether it is 0, an 8-bit operation accumulator (in this case, the A register) has been used. However, it is not necessary to use the A register by checking whether or not the 0 flag is set after the “ADDTWOONE HL, n (00H)” instruction. That is, the “ADDTWONE HL, n” instruction has a function of adding an 8-bit direct value to a 16-bit register pair, a function of checking whether the 16-bit register pair is 0, and a function of preserving the A register. I have. Further, since direct values are used for the instructions, the readability of the program source can be improved.
<Special instruction / INCENSOU instruction>

  The INCTENSOU instruction (INCTENSOU OP1, OP2), which is one of the special instructions, adds 1 to the 2-byte length value stored in the two registers indicated by the second operand OP2, and the value of the two registers after the addition The 1-byte length value stored at the address indicated by is stored in the lower register of the two registers indicated by the first operand OP1, and then stored in the two registers indicated by the second operand OP2. 1 is further added to the 2-byte length value, and the 1-byte length value stored in the address indicated by the two register values after the addition is added to the higher order of the two registers indicated by the first operand OP1. This is an instruction for storing in a register. The upper 1 byte of the instruction code of the INCENSOU instruction is a fixed value (EDH in this example), and the lower byte is a combination of the upper bit 1H (0001B) and the lower bits 8H (1000B) to 9H (10001B) of the instruction data table, The higher order bit DH (1101B) and the lower order bits 4H (0100B) to 6H (0110B) are assigned to the instruction data table. In this example, the code of the machine instruction including the accumulator in the first operand OP1 is a serial number (for example, the code of the “INCTENSOU AC, (HL)” instruction is EDD4H, the code of the “INCTENSOU AE, (HL)” is EDD5H). ing. Also, a machine instruction code of a specific INCENSOU instruction (for example, the code of “INCENSOU AE, (HL)” instruction is EDD5H) among instructions including an accumulator in the first operand OP1, and an accumulator is included in the first operand OP1. Among the non-instructions, the machine instruction code of a specific INCENSOU instruction (for example, the code of “INCENSOU BD, (HL)” instruction is EDD6H) is serialized. In addition, a machine instruction code of a plurality of INCENSOU instructions (for example, “INCTENSOU BC, (HL)” instruction code is ED18H, “INTCENSOU DE, ( HL) "instruction code is ED19H) and the machine instruction code of a specific INCENSOU instruction among the instructions that do not include an accumulator in the first operand OP1 (for example, the code of the" INCTENSOU BD, (HL) "instruction is EDD6H) And the numbers apart. In this way, by using an instruction area that has been considered as a free area in the past, it is possible to effectively use limited hardware resources and to embed an illegal instruction (hidden instruction) in the free area. In some cases, it is possible to prevent illegal acts and to ensure the fairness of the game.

  For example, in the case of the “INCENSOU BC, (HL)” instruction, 1 is added to the 2-byte length value stored in the pair register HL indicated by the second operand, and the value is indicated by the value of the pair register HL after the addition. After the 1-byte length value stored in the address (HL) is stored in the lower register C of the pair register BC indicated by the first operand, 2 stored in the pair register HL indicated by the second operand Further, 1 is added to the byte length value, and the 1-byte length value stored in the address (HL) indicated by the value of the pair register HL after the addition is the higher order of the pair register BC indicated by the first operand. This is an instruction for storing in the register B. The INCENSOU instruction is suitable for transferring a value stored in an address subsequent to the address indicated by the value of the HL register to the register. In addition, the INCENSOU instruction determines whether to repeat the instruction based on the value stored in the address indicated by the value stored in the HL register after execution of the instruction. It is suitable to use the instruction because the address indicated by the value stored in the HL register can be set to the next address by adding 1 to the HL register by the instruction.

  For example, in step S1109 of the special symbol variation time lottery process described above, 1 is added to the 2-byte length value (174FH) stored in the HL register by executing “INCENSOUBC, (HL)”. The 1-byte length value (AEH) stored at the address indicated by the value (1750H) of the later HL register is stored in the lower C register of the BC register, and then the 2-byte length stored in the HL register. 1 is added to the value of 1 and the 1-byte length value (20) stored at the address indicated by the value of the HL register (1751H) after addition is stored in the upper B register of the BC registers. Yes.

  In the “INCENSOUBC BC, (HL)” instruction, the required number of states is 14 and the required number of bytes is 2 bytes. On the other hand, when the same processing as the INCENSOU instruction is performed by the conventional instruction, as shown in FIG. 36, the required number of states is 26 states (= 6 + 7 + 6 + 7), and the required number of bytes is 4 bytes (= 1 + 1 + 1 + 1). . Therefore, when the value stored in the next two consecutive addresses after the address indicated by the value of the HL register is transferred to the BC register, the processing time of the control program can be obtained by using the “INCTENSOU BC, (HL)” instruction. In addition, it is possible to reduce the control burden and reduce the amount of program code, and in some cases, it is possible to effectively use the storage area of the ROM with a limited memory capacity.

Further, even if the program code is increased in order to improve game play, an increase in program capacity and a decrease in processing speed may be suppressed. In particular, in the present embodiment, the INCENSOOU instruction is repeatedly executed in the loop processing of steps S1109 to S1111 or the loop processing of steps S1114 to S1116, so that the effect of reducing the processing speed is high. Also, by reducing the program capacity, it is possible to reduce developer coding errors and check mistakes, facilitate debugging, increase development efficiency, and whether or not it has an appropriate function as a game machine. Even when an external organization confirms, there may be a case where it is possible to provide a gaming table that can prevent mistakes in confirmation work and allow a player to play a game with peace of mind.
<Special instruction / TENSOUINC instruction>

  The TENSOUINC instruction (TENSOUINC OP1, OP2), which is one of the special instructions, indicates the 1-byte length value stored in the address indicated by the two register values indicated by the second operand OP2 by the first operand OP1. Two registers indicated by the second operand OP2 after adding 1 to the 2-byte length value stored in the two registers indicated by the second operand OP2 The 1-byte length value stored at the address indicated by the value is stored in the upper register of the two registers indicated by the first operand OP1, and is stored in the two registers indicated by the second operand OP2. This is an instruction for adding 1 to a 2-byte length value. The upper 1 byte of the instruction code of the TENSOUINC instruction is a fixed value (EDH in this example), and the lower byte is a combination of the upper bit 1H (0001B) and the lower bits 6H (0110B) to 7H (0111B) of the instruction data table. The higher order bit DH (1101B) and the lower order bits 0H (0000B) to 2H (0010B) of the instruction data table are assigned. In this example, the code of the machine instruction including the accumulator in the first operand OP1 is a serial number (for example, the code of “TENSOUINC AC, (HL)” is EDD0H, and the code of “TENSOUINC AE, (HL)” is EDD1H). ing. Also, a machine instruction code of a specific TENSOUINC instruction (for example, “TENSOUINC AE, (HL)” instruction code is EDD1H) among instructions including an accumulator in the first operand OP1, and an accumulator is included in the first operand OP1. Among the non-instructions, a machine instruction code of a specific TENSOUINC instruction (for example, a code of “TENSOUINC BD, (HL)” instruction is EDD2H) is serialized. Also, the machine instruction code of a plurality of TENSOUINC instructions (for example, “TENSOUINC BC, (HL)” instruction code is ED16H, “TENSOUINC DE, ( HL) "instruction code is ED17H), and a specific TENSOUINC instruction machine instruction code (eg," TENSOUINC BD, (HL) "instruction code is EDD2H) among instructions that do not include an accumulator in the first operand OP1. And the numbers apart. In addition, the TENSOUINC instruction and the INCENSOU instruction have the same number of instructions in the first operand OP1 in the TENSOUINC instruction than the INCENSOU instruction (for example, the code of “TENSOUINC BC, (HL)” instruction is ED16H, “INCTENSOU BC, (HL) "instruction code is ED18H). Also, the machine instruction code of the TENSOUINC instruction including the accumulator in the first operand OP1 (for example, the code of “TENSOUIC AC, (HL)” instruction is EDD0H) and the machine instruction of the INCTENSOU instruction including the accumulator in the first operand OP1 Codes (for example, the code of the “INCTENSOU AC, (HL)” instruction is EDD4H) and / or before and after the machine instruction code of the instruction other than the TENSOUINC instruction and the INCENSOU instruction (for example, the code EDD3H) Yes.

  Taking the “TENSOUINC BC, (HL)” instruction as an example, the 1-byte length value stored in the address (HL) indicated by the value of the pair register HL indicated by the second operand is indicated by the first operand. The value of the pair register HL indicated by the second operand is stored in the lower register C of the pair register BC and 1 is added to the 2-byte length value stored in the pair register HL indicated by the second operand. 1 byte length value stored in the address (HL) indicated by is stored in the upper register B of the pair register BC indicated by the first operand, and is stored in the pair register HL indicated by the second operand. This is an instruction for adding 1 to a 2-byte length value. The TENSOUINC instruction is suitable for transferring a value stored in an address after the address indicated by the value of the HL register to the register. In addition, when the TENSOUINC instruction determines whether to repeat the instruction depending on whether or not the value of the B register is 0 after the execution of the instruction, if it is determined to repeat, the HL register is incremented by 1 before the determination. Is suitable for using the instruction. Even when the repeated processing is not performed, after the TENSOUINC instruction, the next process can be performed in the state in which the value of the HL register is incremented by 1, so that the instruction is suitable.

In the “TENSOUINC BC, (HL)” instruction, the required number of states is 14 and the required number of bytes is 2 bytes. On the other hand, when the same processing as the TENSOUINC instruction is performed by the conventional instruction, as shown in FIG. 36, the required number of states is 26 states (= 7 + 6 + 7 + 6), and the required number of bytes is 4 bytes (= 1 + 1 + 1 + 1). . Therefore, when transferring the address indicated by the value of the HL register and the value stored at the next address to the BC register, the processing time of the control program can be shortened by using the “TENSOUINC BC, (HL)” instruction. In addition to reducing the control burden, the amount of program code can be reduced, and the ROM storage area with limited memory capacity can be used effectively. Further, even if the program code is increased in order to improve game play, an increase in program capacity and a decrease in processing speed may be suppressed. Also, by reducing the program capacity, it is possible to reduce developer coding errors and check mistakes, facilitate debugging, increase development efficiency, and whether or not it has an appropriate function as a game machine. Even when an external organization confirms, there may be a case where it is possible to provide a gaming table that can prevent mistakes in confirmation work and allow a player to play a game with peace of mind. Note that both the INCENSOU instruction and the TENSOUINC instruction may be provided to be executable in the CPU, or only one of them may be provided to be executable.
<Special instruction / CPT instruction>

The “CPT A, (n: immediate value)” instruction, which is one of the special instructions, is an instruction for comparing the contents of the A register with the data at the address indicating the T register as the upper level and the immediate value as the lower level. When “CPT A, (40H)” is executed while F0H is stored in the T register, the contents of the A register are compared with the data at the address (F040H) indicating the T register as the upper level and the immediate value as the lower level. .
<Special Instruction / ADDONETWO Instruction>

The ADDONETWO instruction (ADDONETWO OP1, OP2), which is one of the special instructions, is stored in the two registers indicated by the second operand OP2 in the 1-byte length value stored in the register indicated by the first operand OP1. This is an instruction for adding a 2-byte length value (or an immediate value of 2-byte length indicated by the second operand OP2). The upper 1 byte of the instruction code of the ADDONETWO instruction is a fixed value (EDH in this example), and the lower byte is assigned to a combination of the upper bit 4H (0100B) and the lower bit AH (1010B) of the instruction data table. In this way, by using an instruction area that has been considered as a free area in the past, it is possible to effectively use limited hardware resources and to embed an illegal instruction (hidden instruction) in the free area. In some cases, it is possible to prevent illegal acts and to ensure the fairness of the game. Note that the ADDONETWO instruction (ADDONETWO OP1, OP2) is easy to carry, and a 1-byte length value (eg, 00H) stored in the A register is a 2-byte length value (eg, 0100H) stored in the HL register. ) Adds a carry. That is, when the H register is other than 00H, a carry can be generated by executing an ADDONETWO instruction (ADDONETWO OP1, OP2). Note that both the ADDTWOONE instruction and the ADDONETWO instruction may be provided in the CPU, or only one of them may be provided.
<Special instruction / SUBTWOONE instruction>

The SUBTWOONE instruction (SUBTWOONE OP1, OP2), which is one of the special instructions, is stored in the register indicated by the second operand OP2 from the 2-byte length value stored in the two registers indicated by the first operand OP1. This is an instruction for subtracting a 1-byte value (or a 1-byte immediate value indicated by the second operand OP2). The upper byte of the instruction code of the SUBTWOONE instruction is a fixed value (EDH in this example), and the lower byte is assigned to a combination of the upper bit 4H (0100B) and the lower bit 8H (1000B) of the instruction data table. In this way, by using an instruction area that has been considered as a free area in the past, it is possible to effectively use limited hardware resources and to embed an illegal instruction (hidden instruction) in the free area. In some cases, it is possible to prevent illegal acts and to ensure the fairness of the game. The SUBTWOONE instruction (SUBTWOONE OP1, OP2) is difficult to carry, but a 2-byte length value (for example, 0001H) stored in the HL register to a 1-byte length value (for example, 0001H) When subtracting (FFH), a carry occurs. That is, if a carry occurs after executing the SUBTWOONE instruction (SUBTWOONE OP1, OP2), it can be determined that the H register is 00H.
<Modification of data table>

  Next, a modified example of the above data table will be described with reference to FIG. This figure shows a modification of the table selection table, the first fluctuation pattern selection table, and the second fluctuation pattern selection table, and corresponds to FIG. 32 described above.

In the first variation pattern selection table shown in FIG. 32B, the item of the number of random numbers is changed to the item of the upper limit of the random numbers with respect to the first variation pattern selection table shown in FIG. Further, in the second variation pattern selection table shown in FIG. 11C, the value of the number of random numbers is changed with respect to the second variation pattern selection table shown in FIG.
<Modified example of special symbol variation time lottery processing>

  Next, a modified example of the special symbol variation time lottery process shown in FIG. 34 will be described with reference to FIG. In addition, the figure is a flowchart which shows the flow of the special symbol fluctuation | variation time lottery process which concerns on a modification.

  In the special symbol variation time lottery process according to this modified example, the process of step S1109 and the process of step S1114 using the “INCTENSOU BC, (HL)” command of the special symbol variation time lottery process shown in FIG. The processing is changed to the processing in step S1150 using the “AC, (HL)” instruction or the processing in step S1152, and the above-described CPT instruction is used in steps S1151 and S1153.

  Specifically, in step S1150, the values stored in the two consecutive addresses next to the address indicated by the value of the HL register are transferred to the AC register (INCTENSOU AC, (HL)). For example, when the value of the HL register is 174FH, the value stored in the two consecutive addresses (1750H, 1751H) next to the address indicated by the value of the HL register is transferred to the AC register, so that the A register 19 and AEH are stored in the C register.

  In the next step S1151, by executing “CPT A, (41H)”, the contents of the A register, the data of the address (F041H) indicating the T register (F0H) as the upper level, and the immediate value (41H) as the lower level, That is, the random number 1 stored in the random number 1 storage area is compared (the random number 1 is subtracted from the value of the A register). In the next step S1154, it is determined whether or not a carry occurs as a result of the comparison (subtraction) in step S1151, that is, whether or not the result of the subtraction has become a positive value. If applicable, the process proceeds to step S1112. If not applicable, the processing of steps S1150 to S1151 is repeatedly executed until it is applicable.

  In step S1152, the values stored at the two consecutive addresses next to the address indicated by the value of the HL register are transferred to the AC register (INCENSOU AC, (HL)). For example, when the value of the HL register is 17FFH, the value stored in the two consecutive addresses (1800H and 1801H) next to the address indicated by the value of the HL register is transferred to the AC register, so that the A register 255 and 01H are stored in the C register.

In the next step S1153, by executing “CPT A, (42H)”, the contents of the A register, the data of the address (F042H) indicating the T register (F0H) as the higher order, and the immediate value (42H) as the lower order, That is, the random number 2 stored in the random number 2 storage area is compared (subtracts the random number 2 from the value of the A register). In the next step S1155, as a result of the comparison (subtraction) in step S1153, it is determined whether or not a carry occurs, that is, whether or not the result of the subtraction has a positive value. If applicable, the process proceeds to step S1117. If not applicable, the processing of steps S1152 to S1153 is repeatedly executed until it is applicable.
<Initial setting process>

  Next, the initial setting process executed in the initial setting 2 (step S107) of the main control unit main process described above will be described using FIG. 40 and FIG. 40A shows an example of the initial setting data table stored in the ROM 306, and FIG. 40B shows a part of the storage area of the RAM 308 after the initial setting process. FIG. 6C is a flowchart showing the flow of the initial setting process. FIG. 41 is an example of a program list for initial setting processing.

  In step S1201, the 1-byte length value stored in the address (HL) indicated by the value of the HL register by the above-described TENSOUINC instruction (“TENSOUINC BD, (HL)”) is converted into the lower D register of the BD register. After adding 1 to the 2-byte length value stored in the HL register, the 1-byte length value stored in the address (HL) indicated by the HL register value is 1 is added to the 2-byte length value stored in the HL register, for example, the initial address of the initial setting data table shown in FIG. In this case, F0H is stored in the D register and 3 is stored in the B register.

  In the next step S1202, the 1-byte length value stored in the address (HL) indicated by the value of the HL register by the above-mentioned TENSOUINC instruction (“TENSOUINC AE, (HL)”) After storing 1 in the 2-byte length value stored in the E register and the 2-byte length value stored in the HL register, the 1-byte length value stored in the address (HL) indicated by the HL register value is stored in the AE register. 1 is added to the 2-byte length value stored in the HL register, for example, in the above example, the E register has a value 17H stored in 100FH. The A register stores 01H, which is the value stored in 1010, and the value in the HL register is updated to 1011H.

  In the next step S1203, the value of the A register is stored in the address (DE) indicated by the value of the DE register. In the previous example, 01H, which is the value of the A register, is stored in 7E17H of the RAM 308, which is the address indicated by the value of the DE register (see FIG. 5B).

  In the next step S1204, 1 is subtracted from the value of the B register, and the processing of steps S1202 to S1203 is repeatedly executed until the subtraction result becomes 0 (relative jump to the processing address of step S1202 is executed). If the subtraction result is 0, the process proceeds to step S1205.

  In the above example, when the B register is 2, 20H which is the value stored in 1011H is stored in the E register and the value stored in 1012H is stored in the A register by the processing in step S1202. 16H is stored, the value of the HL register is updated to 1013H, and the value of 16H, which is the value of the A register, is stored in F020H of the RAM 308, which is the address indicated by the value of the DE register, by the processing of step S1203 (same figure). (See (b)).

  If the B register is 1, 3AH which is the value stored in 1013H is stored in the E register and 06H which is the value stored in 1014H is stored in the A register by the processing in step S1202. The value of the HL register is updated to 1015H, and the value of 06H, which is the value of the A register, is stored in F03AH of the RAM 308, which is the address indicated by the value of the DE register, by the processing of step S1203 ((b) in the figure). reference). The game settings (various information used for game control) stored in F017H, F020H, and F03AH include, for example, power status, payout control command processing type, display display status, etc., and the number of game settings is There may be more than one or only one. In addition, the initial setting process (moDataSet) is performed by setting the value of the HL register at the start of processing (the address set in the HL register is set to the head address of another table different from the initial setting data table). Therefore, it may be handled as a general-purpose data setting processing module that can be called from a plurality of processes (for example, can be called using an HL register as an argument). In this case, the program capacity can be reduced and the processing speed can be improved.

  In this initial setting process, since the TENSOUINC instruction is used in steps S1201 and S1202, the number of states can be reduced from the conventional 26 states to 14 states, the processing time can be shortened, and the number of bytes can be reduced. Can be reduced from the conventional 4 bytes to 2 bytes, and the program capacity can be reduced. In particular, in this example, since the TENSOUINC instruction is repeatedly executed in the loop processing of steps S1202 to S204, the effect of reducing the processing speed is high.

  Also, among the TENSOUINC instructions, the instruction (in this embodiment, TENSOUINC AC, (HL), TENSOUINC AE, (HL)) having a pair of the A register (accumulator) and another register as an operand is the value of the A register. At the same time, the upper byte register (B register and D register in this embodiment) of the pair register (BC register and DE register in this embodiment) is fixed, while the lower byte register (this embodiment) of the pair register is fixed. In the embodiment, only the values of the C register and the E register can be changed, so that more advanced programming than before can be performed, and the program capacity can be reduced and the processing speed can be improved.

  Among the TENSOUINC instructions, the upper byte register (B register in the present embodiment) of the first pair register (BC register in the present embodiment) and the second pair register (DE register in the present embodiment) ) Instruction (TENSOUINC BD, (HL) in this embodiment) having a pair of registers (D register in this embodiment) as operands is higher in the first pair register and the second pair register. Since only the byte register value can be changed, more advanced programming than before is possible, and the program capacity can be reduced and the processing speed can be improved.

  Also, among the TENSOUINC instructions, instructions including the B register in the operand (TENSOUINC BC, (HL), TENSOUINC BD, (HL) in the present embodiment) are used, and steps S1202 to S1204 of the above-described initial setting process are used. If the B register is used to determine the number of times loop processing is performed as in the case of loop processing, the program capacity of the loop processing can be reduced and the processing speed can be improved.

  Note that the CPU 304 can execute both a TENSOUINC instruction and an INCENSOU instruction, and the game control program executes both a table search by the first instruction (TENSOOUINC) and a table search by the second instruction (INCTENSOU). Also good.

  The “table search” may have a meaning according to a general term, for example, a table composed of one or more rows and one or more columns (for example, the first variation pattern selection table of FIG. 32 and FIG. 38). The second variation pattern selection table (initial setting data table of FIG. 40) may be used to search for a corresponding row, and the process of extracting the value of one or more columns of the row may be indicated. It is good also as processing which derives the position (for example, line number). Similarly, a process for finding a corresponding column and extracting a value of one or a plurality of rows of the column may be indicated, or a process for deriving a column position (for example, a column number) in the table of the searched column. Good.

The process of finding the corresponding row here corresponds to the specific row when the value or values you are looking for match or relate to the value of one or more specific columns in the specific row in the table. It is also possible to perform processing such as making a line to be The process for finding the corresponding column may be the same.
<Second special instruction of main control unit>

Next, the second special instruction provided in the main control unit 300 will be described. FIG. 42A is a diagram illustrating a part of the second special instruction included in the main control unit 300. FIG.
<Second special instruction / CPRT instruction (operation + return instruction)>

  The “CPRTZ r” instruction (or “CPRTZ (rr)” instruction), which is one of the second special instructions, is a register indicated by the operand r (or an address stored in the pair register rr indicated by the operand (rr)). 0 is subtracted from the value stored in (1) and the Z flag is set to 1 (when the subtraction result is 0. The same applies hereinafter), the data stored in the stack area SP indicated by the stack pointer PC is After loading (returning) the data stored in the lower address of the program counter PC and the data stored in the stack area SP + 1 indicated by the stack pointer PC to the upper address of the program counter PC, two stack pointers PC are added and then the Z flag is added. Is set to 1 and the Z flag is cleared to 0 (when the subtraction result is other than 0. The same applies hereinafter) ), The address of the subsequent processing is set in the program counter PC, and then the Z flag is cleared to 0. It should be noted that the timing for setting the program counter PC and the timing for clearing the Z flag to 0 may be reversed or simultaneous.

Also, the “CPRTNZ r” instruction (or “CPRTNZ (rr)” instruction) is 0 from the value stored in the register indicated by the operand r (or the address stored in the pair register rr indicated by the operand (rr)). When the Z flag is cleared to 0, the data stored in the stack area SP indicated by the stack pointer PC is stored in the lower address of the program counter PC and in the stack area SP + 1 indicated by the stack pointer PC. When the stored data is loaded (returned) to the upper address of the program counter PC, the stack pointer PC is added by two, the Z flag is cleared to 0, and the Z flag is set to 1. Set the Z flag to 1 after setting the address of subsequent processing in the program counter PC That is an instruction. The register indicated by the operand r includes B, C, D, E, H, and L registers, and the pair register indicated by the operand rr includes BC, DE, and HL (the next CPJR instruction) The same).
<Second special instruction / CPJR instruction (operation + jump instruction)>

  The “CPJRZ r, e” instruction (or “CPJPZ (rr), e” instruction), which is one of the second special instructions, is stored in the register indicated by the operand r (or the pair register rr indicated by the operand (rr)). 0 is subtracted from the value stored in the stored address), and when the Z flag is set to 1, the Z flag is jumped to the address indicated by the program counter PC + e (e is a value from +127 to -128) Is set to 1 and the Z flag is cleared to 0, the address of the subsequent processing is set in the program counter PC and then the Z flag is cleared to 0. The “CPJRNZ r, e” instruction (or “CPJPNZ (rr), e” instruction) subtracts 0 from the value stored in the register indicated by the operand r (or the pair register indicated by the operand rr), When the Z flag is cleared to 0, after jumping to the address indicated by the program counter PC + e (e is a value from +127 to -128), the Z flag is cleared to 0 and the Z flag is set to 1 In this case, the Z flag is set to 1 after the address of subsequent processing is set in the program counter PC.

  The “CPJRC r, n, e” instruction (or “CPJRC (rr), n, e” instruction) is an address stored in the register indicated by the operand r (or the pair register rr indicated by the operand (rr)). ) Is subtracted from the value stored in (8-bit immediate value), and when the C flag is set to 1 (when the subtraction result is 0, the same applies hereinafter), the program counter PC + e (e Jumps to the address indicated by +127 to -128) and then sets the C flag to 1 and the C flag is cleared to 0 (when the subtraction result is other than 0. The same applies hereinafter) This is an instruction for setting the C flag to 0 after setting the address of the subsequent processing in the program counter PC. Further, the “CPJRNC r, n, e” instruction (or “CPJRNC (rr), n, e” instruction) is an address stored in the register indicated by the operand r (or the pair register rr indicated by the operand (rr)). ) Is subtracted from the value stored in (8-bit immediate value), and when the C flag is cleared to 0, the address indicated by the program counter PC + e (e is a numerical value of +127 to −128) This instruction clears the C flag to 0 after the jump and sets the C flag to 1 after setting the address of the subsequent processing in the program counter PC when the C flag is set to 1.

FIG. 42B is a diagram showing the state of the flag register before and after executing the second special instruction. The main control unit 300 includes an 8-bit flag register having an S flag, a Z flag, an SZ flag, an H flag, a P / V flag, an N flag, and a C flag. The S flag, Z flag, SZ flag, H flag, and C flag included in this flag register are set to 1 or cleared to 0 by execution of the second special instruction or execution of other arithmetic logic operation instructions. .
<Process using CPJR instruction>

  Next, processing using the CPJR instruction will be described. FIG. 43 is a diagram showing an example of processing using the CPJR instruction. In the first module shown in the figure, after executing the process X, the CPJR instruction is executed, and when the predetermined condition is satisfied, the process jumps to the process Z. When the predetermined condition is not satisfied, the subsequent module Processing for executing processing Y is performed.

  Here, “when the predetermined condition is satisfied” means that the Z flag is set to 1 if the above-mentioned “CPJRZ r, e” instruction (or “CPJRZ (rr), e” instruction) is used. If the above-described “CPJPNZ r, e” instruction (or “CPJRNZ (rr), e” instruction), the Z flag is cleared to 0. If the above-mentioned “CPJRC r, n, e” instruction (or “CPJPC (rr), n, e” instruction) is used, the C flag is set to 1, and “CPJRNC” In the case of the “r, n, e” instruction (or “CPJPNC (rr), n, e” instruction), the C flag is cleared to 0.

  When the contents of the flag register in the process X performed before the execution of the CPJR instruction are the first contents α, the contents of the flag register in the subsequent processes Y and Z are changed to the second contents α by executing the CPJR instruction. The content changes to β. However, in this embodiment, in addition to not referring to the contents of the flag register during the execution of the CPJR instruction, the contents of the flag register changed by the CPJR instruction are also referred to in the processes Y and Z after the execution of the CPJR instruction. It is configured to perform the processing without doing.

  In this way, in addition to not referring to the contents of the flag register during the execution of the CPJR instruction, the contents of the flag register are changed by the execution of the CPJR instruction. If the processing is performed without referring to the contents, the relationship between the change in the contents of the flag register and the flow of the program execution can be eliminated, the analysis of the program becomes difficult, and unauthorized program tampering can occur. Can be prevented. In this example, the contents of the flag register are not referred to during the execution of the CPJR instruction. However, the contents of the flag register are referred to during the execution of the CPJR instruction, and in a predetermined process performed after the execution of the CPJR instruction. Even if the processing is performed without referring to the contents of the flag register changed before the execution of the CPJR instruction, the same effect may be obtained (the same applies hereinafter).

  FIG. 44A shows an example of a program using a conventional instruction, and FIG. 44B shows an example of a program using a CPJR instruction. For example, when a program for determining whether the value of the A register is 0 or other than 0 and jumping to a predetermined process when the value of the A register is 0, the conventional program shown in FIG. Then, it is necessary to realize by two instructions of an AND instruction (AND A) shown in (1-1) and a JR instruction (JRZ, ITmrRnwCtl020) shown in (1-2). In the program of this embodiment shown, the same processing is realized by only one CPJR instruction (CPJRZ A, ITmrRnwCtl020) shown in (2-1).

  In this way, if the CPJR instruction is used to determine whether or not a predetermined condition is satisfied and a program that jumps to a predetermined process when the predetermined condition is satisfied, the program code can be reduced as compared with the conventional case. In some cases, limited memory can be used effectively.

  In the program of this embodiment shown in FIG. 5B, in the processing Y and processing Z after execution of the CPJR instruction (CPJRZ A, ITmrRnwCtl020) shown in (2-1), the flag register changed by the CPJR instruction is changed. Processing is performed without referring to the contents at all. In this way, if the contents of the flag register are changed by the execution of the CPJR instruction, the predetermined process performed after the execution of the CPJR instruction is performed without referring to the contents of the flag register. The relationship between the change in the contents of the program and the flow of execution of the program can be eliminated, the analysis of the program is difficult, and the analysis of the illegal program can be prevented in advance.

  In the process V following the process Z of the program of the present embodiment shown in FIG. 6B, the flag register changed by another instruction (in this example, the “OR (HL)” instruction) after the execution of the CPJR instruction. Processing (in this example, a JR instruction) based on the contents (in this example, the contents of the Z flag) is performed. In this way, if the process Z that does not refer to the contents of the flag register and the process V that refers to the contents of the flag register are continued, the relationship between the change in the contents of the flag register and the flow of program execution may be complicated. In some cases, it is difficult to analyze a program, and an unauthorized program can be prevented from being analyzed.

  Furthermore, in this example, the LD instruction (load instruction) is executed in the process Z. However, since the LD instruction is one of the instructions that changes the SZ flag without changing the Z flag after the instruction is executed, “ After execution of the “LD A, (HL)” instruction, the Z flag does not change, but the SZ flag changes. On the other hand, in the subsequent process V, “JR Z, ITmrRnwCtL040” is executed. Here, the branch process is performed by referring to the Z flag that has not been changed by the execution of the “LD A, (HL)” instruction of process Z. It is carried out.

  In this way, a first instruction (for example, CPJR instruction) that changes the values of a plurality of flags including the SZ flag and the Z flag is executed, and a second instruction (for example, a DEC A instruction) that does not refer to the flag is executed. Execute a third instruction (for example, an LD instruction) in which only one of the Z flag and the SZ flag changes, and a fourth instruction (for example, refer to the flag that has not changed (changed)) , JR Z instruction), the relationship between the contents of the flag register and the flow of program execution can be complicated, making it difficult to analyze programs and analyzing illegal programs. There are cases where it can be prevented.

  FIG. 45 is a diagram showing an example of another process using the CPJR instruction. In the first module shown in the figure, after the process X is executed, the CPJR instruction is executed, and when a predetermined condition is satisfied, the process jumps to the second module different from the first module and performs the process Z. When the predetermined condition is not satisfied, the subsequent process Y is executed. As described above, when a program that jumps to a predetermined process when a predetermined condition is satisfied using the CPJR instruction, the program may be jumped to not only the process in the same module but also the process of another module. .

FIG. 46 is a diagram showing an example of another process using the CPJR instruction including the process V described above. In the second module shown in the figure, after executing the process Z, an arithmetic logic operation instruction is executed, and a branch process is performed based on the content γ of the flag register changed by the execution of the instruction. In this way, processing based on the flag register changed by execution of the CPJR instruction is not performed, and processing based on the flag register changed by execution of an instruction other than the CPJR instruction (in this example, an arithmetic logic operation instruction) is performed. With this configuration, the relationship between the change in the contents of the flag register and the flow of program execution can be complicated, making it difficult to analyze the program and preventing unauthorized program analysis in some cases.
<Process using CPRT instruction>

  Next, processing using the CPRT instruction will be described. FIG. 47 is a diagram showing an example of processing using the CPRT instruction. In the first module shown in the figure, the CALL instruction is executed to call the second module, the process X is executed in the second module of the call destination, the CPRT instruction is executed, and a predetermined condition is satisfied. Returning to the first module of the caller, the process Z is performed. If the predetermined condition is not satisfied, the subsequent process Y is executed.

  Here, “when the predetermined condition is satisfied” means that the Z flag is set to 1 if the above-described “CPRTZ r” instruction (or “CPRTZ (rr)” instruction) is used. If it is the above-mentioned “CPRTNZ r” instruction (or “CPRTNZ (rr)” instruction), the Z flag is cleared to 0.

  When the contents of the flag register in the process X performed before the execution of the CPRT instruction is the first contents α, the contents of the flag register in the subsequent process Y and process Z are changed to the second contents α by executing the CPRT instruction. The content changes to β. However, in addition to not referring to the flag register during execution of the CPRT instruction, processing Y and processing Z after execution of the CPRT instruction are performed without referring to the contents of the flag register changed by the CPRT instruction. It is configured.

  In this way, in addition to not referring to the flag register during the execution of the CPRT instruction, the contents of the flag register are changed by the execution of the CPRT instruction, while the contents of the flag register are determined in a predetermined process performed after the execution of the CPRT instruction. If the processing is performed without referring to, the relationship between the change in the contents of the flag register and the flow of the program execution can be eliminated, making the analysis of the program difficult and the analysis of the illegal program in advance. Sometimes it can be prevented.

  FIG. 48A shows an example of a program using a CPRT instruction, and FIG. 48B shows an example of a program using a conventional instruction. For example, when it is determined whether the value of the A register is 0 or other than 0, and a program that returns (returns) to a predetermined process when the value of the A register is 0 is shown in FIG. The conventional program needs to be realized by two instructions, ie, an AND instruction (AND A) shown in (1-1) and a RET instruction (RET Z) shown in (1-2). In the program of the present embodiment shown, the same processing is realized by only one CPRT instruction (CPRTZ A) shown in (2-1).

  In this way, it is determined whether or not a predetermined condition is satisfied, and when a program that returns (returns) to a predetermined process when a predetermined condition is satisfied is used, a CPRT instruction is used, so that the program code is reduced as compared with the conventional case. In some cases, limited memory can be used effectively.

  In the program of this embodiment shown in FIG. 9A, in the processing Y and processing Z after execution of the CPRT instruction (CPRTZ A) shown in (2-1), the contents of the flag register changed by the CPRT instruction are displayed. It is configured to perform processing without referring to it at all. In this way, if the contents of the flag register are changed by execution of the CPRT instruction, while the predetermined process performed after the execution of the CPRT instruction is performed without referring to the contents of the flag register, the flag register The relationship between the change in the contents of the program and the flow of execution of the program can be eliminated, the analysis of the program is difficult, and the analysis of the illegal program can be prevented in advance.

In the process V following the process Z of the program of the present embodiment shown in FIG. 6A, a process based on the contents of the flag register changed by another instruction after the execution of the CPRT instruction is performed. In this way, if the process Z that does not refer to the contents of the flag register and the process V that refers to the contents of the flag register are continued, the relationship between the change in the contents of the flag register and the flow of program execution may be complicated. In some cases, it is difficult to analyze a program, and an unauthorized program can be prevented from being analyzed.
<Third special instruction of main control unit>

Next, the third special instruction provided in the main control unit 300 will be described. FIG. 49 is a diagram illustrating a part of the third special instruction included in the main control unit 300.
<Third special instruction / RES instruction>

  One of the third special instructions, “RESmZ n, r” instruction (m is a numerical value of 0 to 7), of the values stored in the register indicated by the second operand r, of the bit indicated by m. This instruction prohibits access and resets the bit n (n is a numerical value of 0 to 7 excluding m) indicated by the first operand to 0. In addition, the “RESmZ n, (rr)” instruction (m is a numerical value of 0 to 7) is a value stored at the address stored in the address stored in the pair register rr indicated by the second operand (rr). In this instruction, access to the bit indicated by m is prohibited, and n bits (n is a numerical value of 0 to 7 excluding m) indicated by the first operand are reset to 0.

  For example, as shown in FIG. 50 (a), the “RES2Z 2, L” instruction has a bit (in this example, a bit) indicated by m among values stored in the L register indicated by the second operand L. 2) is an instruction for prohibiting access and resetting bit 2 indicated by the first operand to 0. In this instruction, bit 2 of the L register is not reset to 0. On the other hand, as shown in FIG. 5B, the “RES2Z 4, L” instruction is a bit indicated by m (in this example, bit bit) among the values stored in the L register indicated by the second operand L. 2) is an instruction that prohibits access and resets bit 4 indicated by the first operand to 0. In this instruction, access to bit 2 of the L register is prohibited, but bit 4 is reset to 0. .

  Further, as shown in FIG. 51A, the “RES2Z 2, (HL)” instruction is stored in the address (F010H in this example) stored in the pair register HL indicated by the second operand (HL). Among these values, this is an instruction that prohibits access to the bit indicated by m (bit 2 in this example) and resets bit 2 indicated by the first operand to 0. In this instruction, the instruction is stored in F010H. Bit 2 of the value being set is not reset to zero. On the other hand, as shown in FIG. 5B, the “RES2Z 4, (HL)” instruction is stored in the address (F010H in this example) stored in the pair register HL indicated by the second operand (HL). Among these values, this is an instruction that prohibits access to the bit indicated by m (bit 2 in this example) and resets bit 4 indicated by the first operand to 0. In this instruction, the instruction is stored in F010H. Access to bit 2 of the current value is prohibited, but bit 4 is reset to 0.

  According to such a RES instruction, while prohibiting access to a predetermined bit, other bits can be reset to 0 at the same time, so that the numerical value of the predetermined bit can be protected, and the predetermined bit can be expected. In some cases, it is possible to prevent a situation in which a malfunction occurs due to a change to a numerical value that does not occur.

FIG. 52 is a diagram showing an extracted part corresponding to the RES instruction in the instruction map of the main control unit 300. As described above, the “RES2Z 2, L” instruction and the “RES2Z 2, (HL)” instruction are instructions that access to bit 2 is prohibited and bit 2 cannot be reset (because they are substantially meaningless instructions). ), As indicated by the thick-lined square in the figure, the 25H portion corresponding to the “RES2Z 2, L” instruction and the 26H portion corresponding to the “RES2Z 2, (HL)” instruction are free areas. . Thus, by providing an empty area in a part of the instruction map, it may be difficult to analyze a program (machine language) using the instruction map.
<Modification 1 of RES instruction>

  FIG. 53 is a diagram showing a RES instruction according to the first modification. A “RESmZ n, r” instruction (m is a decimal number from 1 to 254), which is a modification of the RES instruction, has a decimal number m of 1 among the values stored in the register indicated by the second operand r. Access to a bit that is set to 1 when converted to a binary number of bytes is prohibited, and bit n (n is not set to 1 when m is converted to a binary number of 1 byte) Bit) is reset to 0. The “RESmZ n, (rr)” instruction (m is a decimal number from 1 to 254) is a decimal number among the values stored in the address stored in the pair register indicated by the second operand rr. Access to bits that are set to 1 when m is converted to a 1-byte binary number and n bits (n is set when m is converted to a binary number) indicated by the first operand This is an instruction to reset the bit number (not yet) to 0.

  For example, as shown in FIG. 54 (a), the “RES2Z 4, L” instruction converts a decimal number 2 from a value stored in the register L indicated by the second operand L to a 1-byte binary number. This instruction prohibits access to a bit that is set to 1 (bit 1 in this example) when converted, and resets bit 4 indicated by the first operand to 0. Also, as shown in FIG. 5B, the “RES3Z 4, L” instruction converts the decimal number 3 from the value stored in the register L indicated by the second operand L to a 1-byte binary number. This is an instruction that prohibits access to bits set to 1 when converted (bit 1 and bit 0 in this example) and resets bit 4 indicated by the first operand to 0.

  FIG. 55 is a diagram showing an example of a program using the RES instruction according to the first modification. As described above, the “RESmZ n, (rr)” instruction (m is a decimal number from 1 to 254) is a value stored at the address stored in the pair register rr indicated by the second operand (rr). Among them, access to a bit set to 1 when a decimal number m is converted to a 1-byte binary number is prohibited, and n bits (n is a value converted to a binary number) indicated by the first operand This is a command for resetting the bit number (sometimes 1 is not set) to 0.

  Accordingly, the “RES251Z 2 (= ebCS20pnSGt), (HL)” instruction shown in (3-1) in the figure is an address stored in the pair register HL indicated by the second operand (HL) (in this example, Of the values stored in F096H (= v0ptCS2)), bits that are set to 1 when the decimal number 251 is converted into a 1-byte binary number (in this example, bits 0 to 1, 3 to 7) This instruction prohibits access and resets the bit (bit 2 in this example) indicated by the first operand to 0.

According to such a RES instruction, while prohibiting access to a predetermined bit, other bits can be reset to 0 at the same time, so that the numerical value of the predetermined bit can be protected. (For example, CLR instruction, SET instruction, RES instruction, BIT instruction, etc.) It is possible to prevent a situation in which a predetermined bit is changed to an unexpected numerical value due to a coding error or the like, and debugging or test work can be prevented. May be shortened, and stable game control may be performed. In addition, since the bit for which access is prohibited can be designated by a decimal number, analysis of the program may be difficult.
<Modification 2 of RES instruction>

  FIG. 56 is a diagram showing a RES instruction according to the second modification. A “RESmZ n, r” instruction (m is a numerical value of 0 to 7), which is a modification of the RES instruction, is a bit indicated by m among the values stored in the pair register including the register indicated by the second operand r. And the bit n (n is a numerical value of 0 to 8 excluding m) indicated by the first operand is reset to 0. In addition, the “RESmZ n, (rr)” instruction (m is a numerical value of 0 to 7) is stored in an address stored in the pair register rr indicated by the second operand (rr) and an address consecutive to this address. An instruction that prohibits access to the bit indicated by m in the 2-byte length value and resets the bit n indicated by the first operand (where n is a numerical value of 0 to 8 excluding m) to 0. is there.

  For example, as shown in FIG. 57, the “RES2Z 8, L” instruction is a bit (bit 2) indicated by 2 among the values stored in the pair register HL including the register L indicated by the second operand L. Is an instruction that resets bit 8 (in this example, bit 0 of the H register, which is the upper byte of the HL register) indicated by the first operand to 0.

  Further, as shown in FIG. 58, the “RES2Z 8, (HL)” instruction includes an address (F010H in this example) stored in the pair register HL indicated by the second operand (HL), and this address. Of the 2-byte length values stored in successive addresses (F011H in this example), access to the bit indicated by 2 (bit 2) is prohibited, and bit 8 indicated by the first operand (in this example) , Bit 0 value of the value stored in F011H consecutive to F010H) is reset to 0.

FIG. 59 is a diagram showing a portion corresponding to the RES instruction according to the second modification extracted from the instruction map of the main control unit 300. As described above, the “RES2Z 2, L” instruction and the “RES2Z 2, (HL)” instruction are instructions in which access to bit 2 is prohibited and bit 2 cannot be reset. Instead of these instructions, a “RES2Z 8, L” instruction and a “RES2Z 8, (HL)” instruction are assigned. Thus, by making the order of arrangement of a part of the instruction map irregular, it may be difficult to analyze the program (machine language).
<Other Modifications of RES Instruction>

  FIG. 60 shows another modification of the RES instruction. For example, in the RES instruction shown in FIG. 5A, in the “RESmZ n, r” instruction or “RESmZ n, (rr)” instruction (m is a decimal number from 1 to 254) in the above-described modification example 1, The numerical value m is changed so that 0 can be designated. When 0 is designated, access to all bits is permitted. In the RES instruction shown in FIG. 5B, in the “RESmZ n, r” instruction or the “RESmZ n, (rr)” instruction (m is a decimal number from 1 to 254) in the above-described modification 1, The numerical value m is changed so that the specification can be omitted. When the specification is omitted, access to all bits is permitted.

  FIG. 61A shows an instruction map when an RES instruction that does not prohibit access of a predetermined bit is provided, and an instruction map when an RES instruction that prohibits access of a predetermined bit is provided. As described above, the program (machine) is changed by changing the order of arrangement of a part of the instruction map between the case where the RES instruction which does not prohibit the access of the predetermined bit is provided and the case where the RES instruction which prohibits the access of the predetermined bit is provided. Word) may be difficult to analyze.

FIG. 5B is a diagram showing an example in which the numerical order of the first operand of the RES instruction is different from the arrangement order of the instruction map of the RES instruction. Thus, by assigning the RES instruction to the instruction map so that the numerical values of the first operand of the RES instruction are irregularly arranged as 8 → 1 → 2 → 3 → 4 → 5 → 6 → 7, the program (machine language) May be difficult to analyze.
<Specific examples of user programs>

  Next, a specific example of the above user program will be described. As described above, when the CPU 304 of the main control unit 300 shifts to the user mode, instructions stored after 0000H, which is the first address of the first area of the ROM area, are sequentially executed to start the user program.

  FIG. 62A is a diagram showing an example of a program start setting process that is a part of the user program, and FIG. 62B shows an example of a power-on setting process that is a part of the user program. It is a figure. In the user program shown in the figure, a program start setting process (instructions stored at addresses 0000H to 0005H) is first executed to set a stack pointer and an interrupt mode, and then a power-on setting process. It is configured to jump to (address 0062H). In the power-on process, instructions stored after the address 0062H are sequentially executed, thereby permitting operation to the WDT, setting an initial value, and monitoring the power supply voltage.

FIG. 63 is a diagram showing a part of a user program corresponding to the above-described main control unit timer interrupt process. When a timer interrupt signal is input from the counter timer 312, the basic circuit 302 of the main control unit 300 refers to the interrupt vector table as shown in the figure and jumps to the address defined in the interrupt vector table. In this example, the program jumps to an address 040AH defined corresponding to the timer interrupt. In the main control unit timer interrupt processing, the instructions stored after the address 040AH are sequentially executed, so that register saving and various processes shown in FIGS. Is called.
<Fourth special instruction of main controller>

Next, the fourth special instruction included in the main control unit 300 will be described. FIG. 64 is a diagram showing the contents of the fourth special instruction provided in the main control unit 300 and the ROM area of the main control unit 300.
<4th special instruction / RST instruction>

  The “RST” instruction, which is one of the fourth special instructions, is an instruction for jumping to a fixed address by setting a fixed address in the program counter PC.

  In this embodiment, eight types of RST instructions having different addresses stored in the program counter PC are provided, and the instruction data of the RST instruction is composed of a 5-bit instruction code (opcode) and a 3-bit operand. Yes. Specifically, the 7 bits of 7 types of RST instructions of instruction data C8H to F8H, 5 bits of 2 to 0 are the 3 bits of the RST instruction's instruction code (opcode) and the other 5 to 3 bits. (A portion surrounded by a bold line) indicates a part of a jump destination address (in this example, bits 5 to 3) that can be branched by executing each RST instruction as an operand. Address bits 2 to 0 are fixed to 0).

  For example, since bits 5 to 3 of the RST instruction of the instruction data C8H are 001B, bits 5 to 3 of the jump destination address are 001B and bits 2 to 0 are 0 (fixed), that is, 0008H. Since the bits 5 to 3 of the RST instruction of the instruction data D0H are 010B, it indicates that bits 5 to 3 of the jump destination address are 010B and bits 2 to 0 are 0 (fixed), that is, 0010H. ing. Further, jump destination addresses of other RST instructions are as shown in the figure.

  On the other hand, bits 7-6 and 2-0 of the RST instruction of the instruction data C0H indicate the instruction code (operand) of the RST instruction, and other 3 bits (enclosed by bold lines) of bits 5-3. Indicates a jump destination address that can be branched by executing this RST instruction (in this example, 0040H that cannot be predicted from the numerical value 000B stored in bits 5 to 3). That is, in the RST instruction of the instruction data C0H, even if the operation code and the operand can be analyzed based on the machine language, it is extremely difficult to analyze the jump destination address that can be branched by executing the RST instruction. It is said that.

  Since the instruction data of these RST instructions is composed of a 5-bit instruction code (opcode) and a 3-bit operand as described above, the user cannot freely set the operand (RST instruction). The jump destination address that can be branched by the RST instruction cannot be freely set), and it is only allowed to select the jump destination address that can be branched by the eight types of RST instructions described above. .

  In this example, by including an operand in the instruction data, the jump destination address that can be branched by the instruction is controlled. However, the instruction data may not include the operand. For example, when an opcode (RST) and an operand (0040H) are configured separately as in “RST 0040H” and an address other than a specifiable address (for example, 0000H) is set as an operand, an assembly error is generated. The operands that can be set may be limited, for example, such that it cannot be converted into machine language. In addition, even when a configuration that includes operands in the instruction data is adopted, configurable operands such as an assembly error that cannot be converted into machine language when an address other than a specifiable address is set as an operand. You may restrict.

  That is, in the RST instruction according to the present embodiment, it is possible to jump to only eight types of addresses (0008H, 0010H, 0018H, 0020H, 0028H, 0030H, 0038H, 0040H). The first area of the first area cannot be jumped to 0000H. For this reason, there is a case where an act of incorporating an illegal program and jumping to the start address (starting the user program from the start address and making it an initial state illegally) can be prevented in advance.

In the RST instruction of the instruction data C0H, the numerical value 0040H that is not included in the instruction data is used as the jump destination address. Therefore, it is extremely difficult to specify the jump destination address and the program flow by disassembly or the like. In some cases, unauthorized program modifications can be prevented. In the RST instruction, as shown in the instruction map of FIG. 65, the instruction code order is set in ascending order (C0H → C8H →...), While the jump destination address order (0040H → 0008H → ...) is not arranged in ascending order, it is extremely difficult to analyze instructions, and unauthorized program modification may be prevented in advance.
<Embodiment 2>

Hereinafter, the gaming machine (slot machine 1100) according to Embodiment 2 of the present invention will be described in detail with reference to the drawings.
<Overall configuration>

  First, the overall configuration of the slot machine 1100 according to the second embodiment of the present invention will be described with reference to FIG. This figure is an external perspective view of the slot machine 1100 as seen from the front side (player side).

  A slot machine 1100 shown in the figure includes a main body 1101 and a front door 1102 that is attached to the front surface of the main body 1101 and can be opened and closed with respect to the main body 1101. Inside the center of the main body 1101 (not shown), three reels (left reel 1110, middle reel 1111 and right reel 1112) having a plurality of types of symbols arranged on the outer peripheral surface are stored and rotated inside the slot machine 1100. It is configured to be able to. These reels 1110 to 1112 are rotationally driven by a driving device such as a stepping motor.

  In the present embodiment, an appropriate number of symbols are printed on the belt-like member at equal intervals, and the reels 1110 to 1112 are configured by attaching the belt-like member to a predetermined circular cylindrical frame member. When viewed from the player, the symbols on the reels 1110 to 1112 are generally displayed in the vertical direction from the symbol display window 1113 so that a total of nine symbols can be seen. Then, by rotating the reels 1110 to 1112, the combination of symbols that can be seen by the player varies. That is, each of the reels 1110 to 1112 functions as a display device that displays a plurality of combinations of symbols in a variable manner. In addition to the reel, an electronic image display device such as a liquid crystal display device can also be used as such a display device. In this embodiment, three reels are provided in the center of the slot machine 1100. However, the number of reels and the installation position of the reels are not limited to this.

  Backlights (not shown) for illuminating individual symbols displayed on the symbol display window 1113 are arranged on the rear surfaces of the reels 1110 to 1112. It is desirable that the backlight is shielded for each symbol so that the individual symbols can be illuminated evenly. In the slot machine 1100, an optical sensor (not shown) including a light projecting unit and a light receiving unit is provided in the vicinity of each reel 1110 to 1112. The light projecting unit and the light receiving unit of this optical sensor are provided. A light shielding piece of a certain length provided on the reel passes between the two. Based on the detection result of this sensor, the position of the symbol on the reel in the rotation direction is determined, and the reels 1110 to 1112 are stopped so that the target symbol is displayed on the winning line.

  The winning line display lamp 1120 is a lamp indicating a winning line 1114 that is valid. The effective pay line is determined in advance by the number of medals bet as a game medium. There are 5 winning lines 1114. For example, when one medal is bet, the middle horizontal winning line is valid, and when two medals are betted, the upper horizontal winning line and the lower horizontal winning line are added. If three are valid and three medals are bet, five lines including a right-down winning line and an upper-right winning line are valid as winning lines. Note that the number of winning lines 1114 is not limited to five. For example, when one medal is bet, the middle horizontal winning line, the upper horizontal winning line, the lower horizontal winning line, the right The down line and the upper right line may be set as valid pay lines, and the same number of pay lines may be set as valid pay lines regardless of the number of bets.

  The notification lamp 1123 is, for example, a lamp that informs the player that a specific winning combination (specifically, a bonus) has been won internally in an internal lottery to be described later, or that a bonus game is in progress. The game medal insertable lamp 1124 is a lamp for notifying that the player can insert a game medal. The replay lamp 1122 informs the player that the current game can be replayed (the medal insertion is unnecessary) when winning a replay that is one of the winning combinations in the previous game. It is a lamp. The reel panel lamp 1128 is an effect lamp.

  The bet buttons 1130 to 1132 are buttons for inserting a predetermined number of medals (referred to as credits) stored electronically in the slot machine 1100. In this embodiment, every time the bet button 1130 is pressed, a maximum of three cards are inserted, two are inserted when the bet button 1131 is pressed, and three are inserted when the bet button 1132 is pressed. It has become so. Hereinafter, the bet button 1132 is also referred to as a MAX bet button. The game medal insertion lamp 1129 lights up a number of lamps corresponding to the number of inserted medals, and when a specified number of medals are inserted, a game start is informed that a game start operation is possible. The lamp 1121 is turned on.

  The medal slot 1141 is an slot for a player to insert a medal when starting a game. In other words, the insertion of medals can be performed electronically by using the bet buttons 1130 to 1132, or an actual medal can be inserted (insertion operation) from the medal insertion slot 1141, and the insertion includes both. is there. The stored number display 1125 is a display for displaying the number of medals stored electronically in the slot machine 1100. The game information display 1126 is a display for displaying various types of internal information (for example, the number of medals paid out during a bonus game) as numerical values. The payout number display 1127 is a display for displaying the number of medals to be paid out to the player as a result of winning a winning combination. The stored number display 1125, the game information display 1126, and the payout number display 1127 are 7-segment (SEG) displays.

  The start lever 1135 is a lever type switch for starting the rotation of the reels 1110 to 1112. That is, when a desired medal number is inserted into the medal insertion slot 1141 or when the bet buttons 1130 to 1132 are operated and the start lever 1135 is operated, the reels 1110 to 1112 start to rotate. The operation on the start lever 1135 is referred to as a game start operation.

  The stop button unit 1136 is provided with stop buttons 1137 to 1139. Stop buttons 1137 to 1139 are button-type switches for individually stopping the reels 1110 to 1112 that have started rotating by operating the start lever 1135, and are associated with the reels 1110 to 1112. Hereinafter, the operation on the stop buttons 1137 to 1139 is referred to as a stop operation, the first stop operation is referred to as a first stop operation, the next stop operation is referred to as a second stop operation, and the last stop operation is referred to as a third stop operation. Note that a light emitter may be provided inside each stop button 1137 to 1139, and when the stop button 1137 to 1139 can be operated, the light emitter may be turned on to notify the player.

  The medal return button 1133 is a button for pressing and removing a medal when the inserted medal is clogged. The payment button 1134 is a button for adjusting the medals stored electronically in the slot machine 1100 and the bet medals and discharging them from the medal payout exit 1155. Door key hole 1140 is a hole into which a key for unlocking front door 1102 of slot machine 1100 is inserted. Below the stop button unit 1136, a title panel 1162 for displaying a model name and pasting various types of certificate stamps is provided. At the bottom of the title panel 1162, a medal payout opening 1155 and a medal tray 1161 are provided.

  The sound hole 1180 is a hole for outputting the sound of a speaker provided inside the slot machine 1100 to the outside. Side lamps 1144 provided at the left and right portions of the front door 1102 are decorative lamps for exciting games. An effect device 1160 is disposed above the front door 1102, and a sound hole 1143 is provided above the effect device 1160. This effect device 1160 includes a shutter (shielding device) 1163 including two right shutters 1163a and 1163b that can be opened and closed in a horizontal direction, and a liquid crystal display device 1157 (effect image) disposed on the back side of the shutter 1163. And a display screen of the liquid crystal display device 1157 appears on the front side (player side) of the slot machine 1100 when the right shutter 1163a and the left shutter 1163b are opened horizontally in front of the liquid crystal display device 1157. It has become. It should be noted that the display device is not limited to a liquid crystal display device, and any display device capable of displaying various effect images and various game information may be used. , A reel (drum), or a display device including a projector and a screen. Further, the display screen has a rectangular shape and is configured so that the player can visually recognize the entire display screen. In the case of this embodiment, the display screen is rectangular, but may be square. In addition, a decorative object (not shown) may be provided on the periphery of the display screen, and a part of the peripheral edge of the display screen may be hidden by the decorative object, so that the display screen looks irregular. In the present embodiment, the display screen is a flat surface, but may be a curved surface.

  FIG. 67 is a front view showing the slot machine 1100 with the front door 102 opened. The main body 1101 is a box that is surrounded by an upper surface plate 1261, a left side plate 1260, a right side plate 1260, a lower surface plate 1264, and a back plate 1242 and opens to the front. Inside the main body 1101, a main control board storage case 1210 in which a main control board is stored is disposed at a position that does not overlap with the ventilation opening 1249 provided in the upper part of the back plate 1242. Below the three reels 1110 to 1112 are arranged. On the side plate 1260 on the left side of the main control board storage case 1210 and the reels 1110 to 1112, a sub control board storage case 1220 storing the sub control board is disposed. The right side plate 1260 is attached with an external concentration terminal plate 1248 that is connected to the main control board and outputs information of the slot machine 1100 to an external device.

  The bottom plate 1264 is provided with a medal payout device 1180 (device for paying out medals accumulated in a bucket), and has a power supply board above the medal payout device 1180, that is, below the reels 1110 to 1112. A power supply device 1252 is provided, and a power switch 1244 is provided on the front surface of the power supply device 1252. The power supply device 1252 converts the AC power supplied from the outside to the slot machine 1100 into a direct current, converts it into a predetermined voltage, and supplies it to each control unit and each device such as a main control unit 1300 and sub-control units 1400 and 1500 described later. To do. Furthermore, a power storage circuit (for example, a capacitor) for supplying power to a predetermined part (for example, the RAM 1308 of the main control unit 1300) for a predetermined period (for example, 10 days) even after the power supply from the outside is cut off is provided. Yes.

  A medal auxiliary storage 1240 is arranged on the right side of the medal payout device 1180, and an overflow terminal is arranged behind this (not shown). The power supply device 1252 is provided with a power cord connecting portion for connecting a power cord 1264, and the power cord 1264 connected thereto extends to the outside through a power cord hole 1262 provided in the back plate 1242 of the main body 1101. Yes.

  The front door 1102 is hinged to the left side plate 1260 of the main body 1101 via a hinge device 1276, and an effect device 1160 and an effect control board (which controls the effect device 1160) are provided above the symbol display window 1113. An upper speaker 1272 is provided. At the bottom of the symbol display window 1113, a medal selector 1170 for selecting inserted medals, a passage 1266 through which medals pass when the medal selector 1170 drops illegal medals etc. on the medal tray 1161, etc. are provided. Yes. Further, a bass speaker 1277 is provided at a position corresponding to the sound hole 1180.

  The circuit configuration of the control unit of the slot machine 1100 will be described in detail with reference to FIG. This figure shows a circuit block diagram of the control unit.

The control unit of the slot machine 1100 can be broadly divided into a main control unit 1300 that mainly controls the progress of a game (for example, detection of an operation by a player, transition of a game state, game medium payout control, determination of success / failure, etc.). In response to a command signal transmitted from the main control unit 1300 (hereinafter simply referred to as “command”), a first sub control unit 1400 that mainly controls production and a command transmitted from the first sub control unit 1400 And a second sub-control unit 1500 that controls various devices based on the above.
<Main control unit>

  First, the main control unit 1300 of the slot machine 1100 will be described. The main control unit 1300 includes a basic circuit 1302 that controls the entire main control unit 1300. The basic circuit 1302 includes a CPU 1304, control program data, lottery data used during an internal lottery for a winning combination, and reel stop. ROM 1306 for storing position, RAM 1308 for temporarily storing data, I / O 1310 for controlling input / output of various devices, counter timer 1312 for measuring time, frequency, etc. WDT (watchdog timer) 1314 is mounted. Note that another storage device may be used for the ROM 1306 and the RAM 1308, and this is the same for the first sub-control unit 1400 and the second sub-control unit 500 described later. The CPU 1304 of the basic circuit 1302 operates by inputting a clock signal of a predetermined period output from the crystal oscillator 1314 as a system clock. Further, when the power is turned on, the CPU 1304 transmits the frequency division data stored in the predetermined area of the ROM 1306 to the counter timer 1312. The counter timer 1312 sets the interrupt time based on the received frequency division data. An interrupt request is transmitted to the CPU 1304 at every interrupt time. In response to this interrupt request, the CPU 1304 executes monitoring of each sensor and transmission of drive pulses. For example, when the clock signal output from the crystal oscillator 1314 is set to 8 MHz, the frequency division value of the counter timer 1312 is set to 1/256, and the data for frequency division in the ROM 1306 is set to 47, the interrupt reference time is 256 × 47 ÷ 8 MHz. = 1.504 ms.

  The main control unit 1300 includes a random number generation circuit 1316 that is used as a hardware random number counter that fluctuates a numerical value in the range of 0 to 65535, and an activation signal output circuit that outputs an activation signal (reset signal) when the power is turned on. The CPU 1304 starts game control when a start signal is input from the start signal output circuit 1338 (starts main processing main processing described later).

  Further, the main control unit 1300 includes a sensor circuit 1320, and the CPU 1304 is inserted from various sensors 1318 (a bet button 1130 sensor, a bet button 1131 sensor, a bet button 1132 sensor, and a medal slot 1141 at every interruption time. Medal reception sensor, start lever 1135 sensor, stop button 1137 sensor, stop button 1138 sensor, stop button 1139 sensor, checkout button 1134 sensor, medal payout sensor for medals paid out from the medal payout device 1180, index sensor for reel 1110 , The index sensor of the reel 1111, the index sensor of the reel 1112, etc.).

  When the sensor circuit 1320 detects the H level of the start lever sensor, a signal indicating this detection is output to the random number generation circuit 1316. The random number generation circuit 1316 that has received this signal latches the value at that timing and stores it in a register that stores the random number value used for the lottery.

  Two medal acceptance sensors are installed in the internal passage of the medal insertion slot 1141 and detect whether or not a medal has passed. Two start lever 1135 sensors are installed inside the start lever 1135 and detect a start operation by the player. The stop button 1137 sensor, the stop button 1138 sensor, and the stop button 1139 are installed in each of the stop buttons 1137 to 1139, and detect the operation of the stop button by the player.

  The bet button 1130 sensor, the bet button 1131 sensor, and the bet button 1132 sensor are installed in each of the medal insertion buttons 1130 to 1132, and the medal electronically stored in the RAM 1308 is inserted as an inserted medal into the game. Detecting the input operation when The settlement button 1134 sensor is provided on the settlement button 1134. When the settlement button 1134 is pressed once, medals stored electronically are settled. The medal payout sensor is a sensor for detecting a medal paid out by the medal payout device 1180. Each of the above sensors may be a non-contact type sensor or a contact type sensor.

  The index sensor of the reel 1110, the index sensor of the reel 1111, and the index sensor of the reel 1112 are installed at predetermined positions on the mounting bases of the reels 1110 to 1112. Becomes L level. When detecting this signal, the CPU 1304 determines that the reel has made one rotation, and resets the reel rotation position information to zero.

  The main control unit 1300 is provided in a drive circuit 1322 for driving a stepping motor provided in the reel devices 1110 to 1112, a drive circuit 1324 for driving a solenoid provided in a medal selector 1170 for selecting inserted medals, and a medal payout device 1180. A drive circuit 1326 for driving the motor, various lamps 1338 (a winning line display lamp 1120, a notification lamp 1123, a game medal insertion enable lamp 1124, a re-game lamp 1122, a game medal insertion lamp 1129, a game start lamp 1121, and a stored number display. A driving circuit 1328 for driving a device 1125, a game information display 1126, and a payout amount display 1127).

  In addition, an information output circuit 1334 (external concentration terminal board 1248) is connected to the basic circuit 1302, and the main controller 1300 is connected to an external hall computer (not shown) or the like via the information output circuit 1334. The gaming information (for example, gaming state) of the slot machine 1100 is output to the information input circuit 1652 provided.

  The main control unit 1300 includes a voltage monitoring circuit 1330 that monitors the voltage value of the power supplied from the power management unit (not shown) to the main control unit 1300, and the voltage monitoring circuit 1330 includes the voltage of the power supply. When the value is less than a predetermined value (9 v in this embodiment), a low voltage signal indicating that the voltage has decreased is output to the basic circuit 1302.

The main control unit 1300 includes an output interface for transmitting a command to the first sub control unit 1400 and enables communication with the first sub control unit 1400. Information communication between the main control unit 1300 and the first sub control unit 1400 is one-way communication, and the main control unit 1300 is configured to transmit a signal such as a command to the first sub control unit 1400. However, the first sub-control unit 1400 is configured not to transmit a signal such as a command to the main control unit 1300.
<Sub control unit>

  Next, the first sub control unit 1400 of the slot machine 1100 will be described. The first sub control unit 1400 includes a basic circuit 1402 that receives a control command transmitted from the main control unit 1300 via an input interface and controls the entire first sub control unit 1400 based on the control command. The basic circuit 1402 includes a CPU 1404, a RAM 1408 for temporarily storing data, an I / O 1410 for controlling input / output of various devices, and a counter timer 1412 for measuring time and frequency. It is installed. The CPU 1404 of the basic circuit 1402 operates by inputting a clock signal of a predetermined period output from the crystal oscillator 1414 as a system clock. The ROM 406 stores a control program and data for controlling the entire first sub-control unit 1400, a backlight lighting pattern, data for controlling various displays, and the like.

  The CPU 1404 transmits the frequency dividing data stored in the predetermined area of the ROM 1406 to the counter timer 1412 via the data bus at a predetermined timing. The counter timer 1412 determines an interrupt time based on the received frequency division data, and transmits an interrupt request to the CPU 1404 at each interrupt time. The CPU 1404 controls each IC and each circuit based on the interrupt request timing.

  The first sub-control unit 1400 is provided with a sound source IC 1418, and the sound source IC 1418 is provided with speakers 1272 and 1277 via an output interface. The sound source IC 1418 controls sound output from the amplifiers and speakers 1272 and 1277 in accordance with a command from the CPU 1404. The sound source IC 1418 is connected to an S-ROM (sound ROM) in which sound data is stored. The sound data acquired from the ROM is amplified by an amplifier and output from the speakers 1272 and 1277.

  The first sub-control unit 1400 is provided with a drive circuit 1422, and various lamps 1420 (upper lamp, lower lamp, side lamp 1144, title panel 1162 lamp, etc.) are connected to the drive circuit 1422 through an input / output interface. It is connected.

  The CPU 1404 transmits and receives signals to the second sub control unit 1500 via the output interface. Second sub-control unit 1500 performs various controls of effect device 1160 including display control of effect image display device 1157. Note that the second sub-control unit 1500 is, for example, a control unit that controls display of the liquid crystal display device 1157 and a control unit that controls various driving devices for effects (for example, a control unit that controls the motor drive of the shutter 1163). For example, it may be configured by a plurality of control units.

  The second sub control unit 1500 includes a basic circuit 1502 that receives the control command transmitted from the first sub control unit 1400 via the input interface and controls the entire second sub control unit 1500 based on the control command. The basic circuit 1502 includes a CPU 1504, a RAM 1508 for temporarily storing data, an I / O 1510 for controlling input / output of various devices, and a counter timer for measuring time and frequency 1512. The CPU 1504 of the basic circuit 1502 operates by inputting a clock signal of a predetermined period output from the crystal oscillator 1514 as a system clock. The ROM 506 stores a control program and data for controlling the entire second sub control unit 1500, data for image display, and the like.

  The CPU 1504 transmits the frequency dividing data stored in the predetermined area of the ROM 1506 to the counter timer 1512 via the data bus at a predetermined timing. The counter timer 1512 determines an interrupt time based on the received frequency division data, and transmits an interrupt request to the CPU 1404 at each interrupt time. The CPU 1504 controls each IC and each circuit based on the interrupt request timing.

  The second sub control unit 1500 is provided with a drive circuit 1530 for driving the motor of the shutter 1163, and the drive circuit 1530 is provided with a shutter 1163 via an output interface. The drive circuit 1530 outputs a drive signal to a stepping motor (not shown) provided in the shutter 1163 in response to a command from the CPU 1504.

The second sub-control unit 1500 is provided with a sensor circuit 1532, and a shutter sensor 1538 is connected to the sensor circuit 1532 via an input interface. The CPU 1504 monitors the state of the shutter sensor 1538 every interruption time.

The second sub control unit 1500 is provided with a VDP 1534 (video display processor), and a ROM 1506 and a VRAM 1536 are connected to the VDP 1534 through a bus. The VDP 1534 reads out image data and the like stored in the ROM 1506 based on a signal from the CPU 1504, generates a display image using the work area of the VRAM 1536, and displays the image on the effect image display device 1157.
<Pattern arrangement>

  Next, the symbol arrangement applied to each of the reels 1110 to 1112 will be described with reference to FIG. This figure is a diagram in which the arrangement of symbols applied to each reel (left reel 1110, middle reel 1111, right reel 1112) is developed in a plane.

In each reel 1110 to 1112, a plurality of types (eight types in the present embodiment) of symbols shown on the right side of the same figure are arranged by a predetermined number of frames (21 frames of numbers 0 to 20 in the present embodiment). Also, numbers 0 to 20 shown at the left end of the figure are numbers indicating the arrangement positions of symbols on the reels 1110 to 1112. For example, in the present embodiment, the “Replay” symbol is assigned to the number 1 frame on the left reel 1110, the “Bell” symbol is assigned to the number 0 frame on the middle reel 1111, and the “No. 2” symbol is assigned to the number 2 frame on the right reel 1112. "Watermelon" design is arranged respectively.
<Type of winning prize>

  Next, the types of winning combinations of the slot machine 1100 will be described with reference to FIG. This figure shows the types of winning combinations (including actuating combinations), symbol combinations corresponding to each winning combination, and the operation or payout of each winning combination.

  Of the winning combinations in the present embodiment, the big bonuses (BB1, BB2) and the regular bonus (RB) are used as a combination for shifting to the bonus game, and the replay (replay) is a replay without newly inserting a medal. Each winning combination is sometimes distinguished from a winning combination and sometimes called an “acting combination”. However, in the “winning combination” in this embodiment, a big bonus, a regular bonus, and a replay that are operating combinations are included. included. In addition, “winning” in the present embodiment includes a case where a symbol combination of an actuator not accompanied by a medal payout (without medal payout) is displayed on an active line, for example, a big bonus, regular Includes bonuses and replay wins.

  The winning combination of the slot machine 1100 includes a big bonus (BB1, BB2), a regular bonus (RB), a small combination (cherry, watermelon, bell), and replay (replay). Needless to say, the type of winning combination is not limited to this and can be arbitrarily adopted.

  “Big Bonus (BB1, BB2)” (hereinafter sometimes simply referred to as “BB”) is a special combination (operating combination) in which a big bonus game (BB game), which is a special game, is started by winning a prize. . Corresponding symbol combinations are “white 7-white 7-white 7” for BB1, and “blue 7-blue 7-blue 7” for BB2. Further, flag carryover is performed for BB1 and BB2. That is, when BB1 and BB2 are internally won, a flag indicating this is set (stored in the determination result storage area of the RAM 1308 of the main control unit 1300), but even if BB1 and BB2 are not won in that game, The flag indicating the internal winning is kept until winning, and the BB1 and BB2 are still in the internal winning even after the next game, and the symbol combination corresponding to BB1 "white 7-white 7-white 7", corresponds to BB2. The symbol combination “Blue 7-Blue 7-Blue 7” is in a state of winning a prize.

  The “regular bonus (RB)” is a special combination (operating combination) in which a regular bonus game (RB game) is started by winning. The corresponding symbol combination is “bonus-bonus-bonus”. Note that the RB carries over the flag as well as the above-mentioned BB. However, in the big bonus game (BB game) (details will be described later), the regular bonus game (RB game) is won internally and the combination of symbols is displayed on the winning line. In addition, the regular bonus game is started after the start of the big bonus game, and when the regular bonus game is finished once, the regular bonus game is automatically started so that the next regular bonus game is immediately started. It is good. “Short (cherry, watermelon, bell)” (hereinafter, simply referred to as “cherry”, “watermelon”, “bell”) is a winning combination in which a predetermined number of medals are paid out by winning. The symbol combinations are “cherry-ANY-ANY” for cherry, “watermelon-watermelon-watermelon” for watermelon, and “bell-bell-bell” for bell. The corresponding payout number is as shown in FIG. In the case of “cherry-ANY-ANY”, the symbol of the left reel 1110 may be “cherry”, and the symbol of the middle reel 1111 and the right reel 1112 may be any symbol.

“Replay” is a winning combination (operating combination) in which a game can be performed without inserting a medal (game medium) in the next game by winning, and no medal is paid out. The corresponding symbol combination is “replay-replay-replay” for replay.
<Type of gaming state>

Next, the types of gaming state of the slot machine 1100 will be described. The gaming state is information for identifying the type of lottery data selected in a lottery or the like. In the present embodiment, the gaming state of the slot machine 1100 is roughly divided into a normal game, a BB game, an RB game, and an internal winning game of a big bonus (BB) and a regular bonus (RB). However, the internal winning game may be a division included in the normal game.
<Normal game>

  The winning combinations that are internally won for normal games include a big bonus (BB), regular bonus (RB), replay (replay), and small roles (cherry, watermelon, bell).

  “Big Bonus (BB)” is a special combination (operating combination) in which a big bonus game (BB game), which is a special game, is started by winning. “Regular Bonus (RB)” is a special combination (operating combination) that starts a regular bonus game (RB game) upon winning. The “replay” (replay) is a winning combination (operating combination) in which a game can be performed without a medal being inserted in the next game by winning, and no medal is paid out. The “small role” is a winning combination in which a predetermined number of medals are paid out by winning. In addition, the internal winning probability of each combination is a range of random values obtained at the time of internal lottery from numerical data corresponding to the range of lottery data associated with each combination from lottery data prepared for normal games. It is calculated by the value divided by the numerical data (for example, 65535). The lottery data prepared for the normal game is divided into several numerical ranges in advance, and each combination and lose is associated with each numerical range. It is determined whether the random number value obtained as a result of executing the internal lottery is a value corresponding to the lottery data corresponding to which combination, and the internal lottery combination is determined. This lottery data is provided with settings 1 to 6 in which the winning probabilities of at least one combination are different, and a game shop clerk can arbitrarily select and set any set value.

In the normal game, the internal lottery result is almost lost (big bonus (BB), regular bonus (RB), replay (replay) and small role won), or any stop display result A setting is made so that the stop display result of the losing that does not correspond to the symbol combination of the combination is generally derived, and the total number of medals to be acquired is less than the total number of inserted medals. Therefore, it is a gaming state that is disadvantageous for the player. However, when a predetermined condition is satisfied (for example, when a specific symbol combination is displayed), it is a gaming state that may be changed to increase the probability of internal winning of replaying. In this case, Consumption of medals used for games is suppressed, and a predetermined number of medals are paid out by winning a small role, resulting in a gaming state where the total number of medals exceeds the total number of medals inserted, which is beneficial to the player. May become a gaming state.
<BB game>

The BB game is set to be in a gaming state that is beneficial to the player. That is, the BB game is in a gaming state in which the total number of medals to be acquired exceeds the total number of medals inserted. In this embodiment, the BB game is started by winning a big bonus (BB), and an RB game (described later) can be continuously executed repeatedly, and a predetermined number (for example, during the game) The process ends when more than 465 medals are obtained. However, the BB game only needs to be able to execute the RB game a plurality of times. For example, when a combination (for example, replay-replay-replay) is set for starting the RB game, and this combination is won internally, or The RB game may be set to start when winning. Furthermore, in the BB game, when the BB general game excluding the RB game during the BB game is executed a predetermined number of times (for example, 30 times), or the number of the RB games executed during the BB game is a predetermined number of times. It may be made to end when it reaches (for example, three times).
<RB game>

The RB game is set so as to be in a gaming state that is beneficial to the player. That is, the RB game is in a gaming state in which the total number of medals to be acquired exceeds the total number of medals inserted. In this embodiment, the RB game is started by winning a regular bonus (RB), and a predetermined role is set to a variation that increases the probability of internal winning (for example, “setting 1” or “normal game”). The internal winning probability 1/15 of “small role 1” is increased to an internal winning probability 1 / 1.2, which is a predetermined value), and a predetermined number (for example, 8 times) It ends when there is a prize. In the RB game, when a predetermined number of times (at least 2 times) is won (for example, 8 times), or when the number of RB games executed during the RB game reaches a predetermined number of times (for example, (8 times). Since the BB game described above can execute the RB game a plurality of times, when a single RB game is performed, the number of medals less than the total number of medals obtained in the BB game is acquired and terminated. Become.
<Big winning (BB) and regular bonus (RB) internal winning games>

  The winning combination that is internally won for the internal winning game of the big bonus (BB) and the regular bonus (RB) includes a replay and a small role. The big bonus (BB) and the regular bonus (RB) are not won internally, and are game states in which a symbol combination corresponding to the big bonus (BB) or the regular bonus (RB) can be won.

However, the probability of the internal winning of the replay may be changed from the next game that has been internally won to the big bonus (BB) and the regular bonus (RB), for example, the probability of increasing the internal winning probability of the replay is changed. Until the symbol combination corresponding to the big bonus (BB) and regular bonus (RB) wins, the total number of medals to be acquired is almost the same as the total number of inserted medals, and is compared with the normal game. The gaming state may be beneficial to the player. It should be noted that BB game and RB game are both game states that are beneficial to the player, and may be generally referred to as bonus games or special games.
<Main control unit main processing>

  Next, main control unit main processing executed by the CPU 1304 of the main control unit 1300 will be described with reference to FIG. This figure is a flowchart showing the flow of main processing of the main control unit.

  As described above, the main control unit 1300 is provided with the start signal output circuit (reset signal output circuit) 1338 that outputs the start signal (reset signal) when the power is turned on. The CPU 1304 of the basic circuit 1302 to which this activation signal has been input executes a main control unit main process in accordance with a control program stored in advance in the ROM 1306 after being reset by a reset interrupt.

  When the power is turned on, first, various initial settings are made in step S2101. In this initial setting, setting of the stack initial value to the stack pointer (SP) of the CPU 1304, setting of interrupt inhibition, initial setting of the I / O 1310, initial setting of various variables stored in the RAM 1308, operation permission to the WDT 1314, and initial setting Set the value. In step S2103, medal insertion / start operation acceptance processing is executed. Here, it is checked whether or not a medal has been inserted, and the winning line display lamp 1120 is turned on in response to the insertion of the medal. Note that when a re-win is won in the previous game, a process of inserting the same number of medals as the number of medals inserted in the previous game is performed, so that it is not necessary for the player to insert medals. Further, it is checked whether or not the start lever 1135 has been operated. If there is an operation of the start lever 1135, the process proceeds to step S2105.

  In step S2105, the number of inserted medals is determined, and an effective winning line is determined. In step S2107, the random number generated by the random number generation circuit 1316 is acquired. In step S2109, the winning combination lottery table stored in the ROM 1306 is read according to the current gaming state, and an internal lottery is performed using this and the random value acquired in step S2107. As a result of the internal lottery, when any winning combination (including an operating combination) is won internally, the flag of the winning combination is turned ON. In step S2111, reel stop data is selected based on the internal lottery result.

In step S2113, rotation of all reels 1110 to 1112 is started. In step S2115, the stop buttons 1137 to 1139 can be received. When any one of the stop buttons is pressed, the reel stop control in which one of the reels 1110 to 1112 corresponding to the pressed stop button is selected in step S2111. Stop based on data. When all the reels 1110 to 1112 are stopped, the process proceeds to step S2117. In step S2117, a winning determination is performed. Here, when a symbol combination corresponding to some winning combination is displayed on the activated winning line 1114, it is determined that the winning combination is won. For example, if “bell-bell-bell” is aligned on the activated winning line, it is determined that the player has won the bell. In step S2119, if any winning combination with payout is won, the number of medals corresponding to the winning combination is paid out according to the number of winning lines. In step S2121, a game state control process is performed. In the game state control process, a process related to transition of each game state of normal game, BB game, RB game, and internal winning game is performed, and the game state is shifted when those start conditions and end conditions are satisfied. Thus, one game is completed. Thereafter, returning to step S2103 and repeating the above-described processing, the game proceeds.
<Main control unit 1300 timer interrupt processing>

  Next, the main control unit timer interrupt process executed by the CPU 1304 of the main control unit 1300 will be described with reference to FIG. This figure is a flowchart showing the flow of the main control unit timer interrupt process.

  The main control unit 1300 includes a counter timer 1312 that generates a timer interrupt signal at a predetermined cycle (in this embodiment, about once every 2 ms), and the main control unit timer interrupt is triggered by this timer interrupt signal. The process is started at a predetermined cycle.

  In step S2201, timer interrupt start processing is performed. In this timer interrupt start process, a process of temporarily saving the value of each register of the CPU 1304 to the stack area is performed. In step S2203, the WDT 1314 is periodically updated (not to detect a processing abnormality) so that the count value of the WDT 1314 exceeds the initial setting value (32.8 ms in the present embodiment) and no WDT interruption occurs. In the embodiment, the restart is performed once every about 2 ms, which is the period of the main control unit timer interrupt.

  In step S2205, input port state update processing is performed. In this input port state update process, the detection signals of the sensor circuits 1320 of the various sensors 1318 are input via the input ports of the I / O 1310 to monitor the presence or absence of the detection signals, and each of the various sensors 1318 is partitioned in the RAM 1308. Store in the provided signal state storage area.

  In step S2207, various game processes are performed. Specifically, an interrupt status is acquired (various interrupt statuses are acquired based on signals from various sensors 1318), and processing according to this status is performed (for example, the interrupt statuses of the acquired stop buttons 1137 to 1139). Based on the stop button reception process). In step S2209, timer update processing is performed. Various timers are updated for each time unit.

  In step S2211, command setting transmission processing is performed, and various commands are transmitted to the first sub-control unit 1400. The output schedule information transmitted to the first sub-control unit 1400 is composed of 16 bits in the present embodiment, bit 15 is strobe information (indicating that data is set when ON), bit 11 -14 are command types (in this embodiment, basic command, start lever reception command, production command accompanying production lottery processing, rotation start command when rotation of reels 1110 to 1112 starts, and operation of stop buttons 1137 to 1139 are accepted. Bits 0 to 10 are command data (stop button reception command accompanying the reels 1110 to 1112, stop position information command accompanying the stop processing of the reels 1110 to 1112, payout number command and payout end command accompanying the medal payout processing, etc.) Predetermined information corresponding to the command type). The first sub-control unit 1400 can determine the effect control according to the change in the game control in the main control unit 1300 by the command type included in the received output schedule information, and is included in the output schedule information. Based on the information of the command data, the contents of effect control can be determined.

  In step S2213, external output signal setting processing is performed. In this external output signal setting process, game information stored in the RAM 1308 is output to an information input circuit 1652 that is separate from the slot machine 1100 via the information output circuit 1334.

  In step S2215, device monitoring processing is performed. In this device monitoring process, first, the signal states of the various sensors 1318 stored in the signal state storage area in step S2205 are read, and the presence or absence of errors relating to medal insertion abnormality and medal payout abnormality is monitored. (Not shown) Error processing is executed. Further, according to the current gaming state, the medal selector 1170 (medal blocker in which a solenoid provided in the medal selector 1170 operates), various lamps 1338, and various 7-segment (SEG) indicators are set.

  In step S2217, it is monitored whether the low voltage signal is on. If the low voltage signal is on (when power supply shutoff is detected), the process proceeds to step S2221. If the low voltage signal is off (power supply shutoff is not detected), the process proceeds to step S2219.

In step S2219, various processes for ending the timer interrupt end process are performed. In this timer interrupt end process, the value of each register temporarily saved in step S2201 is set in each original register. Then, the process returns to the main control unit main process. On the other hand, in step S2221, a specific variable or stack pointer for returning to the power-off state at the time of power recovery is saved as a return data in a predetermined area of the RAM 1308, and power-off processing such as initialization of the input / output port is performed. After that, the process returns to the main process of the main control unit.
<Processing of First Sub-Control Unit 400>

  Next, processing of the first sub control unit 1400 will be described with reference to FIG. 2A is a flowchart of the main process executed by the CPU 1404 of the first sub control unit 1400, and FIG. 2B is a flowchart of the command reception interrupt process of the first sub control unit 1400. . FIG. 10C is a flowchart of the timer interrupt process of the first sub control unit 1400.

  First, in step S2301 in FIG. 11A, various initial settings are performed. When power is turned on, initialization processing is first executed in step S2301. In this initialization process, initial setting of input / output ports, initialization processing of a storage area in the RAM 1408, and the like are performed.

  In step S2303, it is determined whether or not the timer variable is 10 or more. This process is repeated until the timer variable becomes 10, and when the timer variable becomes 10 or more, the process proceeds to step S2305. In step S2305, 0 is assigned to the timer variable. In step S2307, command processing is performed. In the command processing, the CPU 1404 of the first sub control unit 1400 determines whether a command is received from the main control unit 1300.

  In step S2309, an effect control process is performed. In this effect control process, for example, when there is a new command in step S2307, a process corresponding to this command is performed. This process includes, for example, performing a process such as reading effect data from the ROM 1406, and performing an effect data update process when the effect data needs to be updated.

  In step S2311, sound control processing is performed based on the processing result of step 2309. For example, if there is a command to the sound source IC 1418 in the effect data read out in step S2309, this command is output to the sound source IC 1418. In step S2313, lamp control processing is performed based on the processing result of step 2309. For example, if there is a command to the various lamps 1420 in the effect data read in step S2309, this command is output to the drive circuit 1422.

  In step S2315, information output processing is performed to perform setting for transmitting a control command to the second sub-control unit 500 based on the processing result of step 2309. For example, if there is a control command to be transmitted to the second sub control unit 1500 in the effect data read in step S2309, the control command is set to be output, and the process returns to step S2303.

  Next, a command reception interrupt process of the first sub control unit 1400 will be described with reference to FIG. This command reception interrupt process is a process executed when the first sub control unit 1400 detects the strobe signal output from the main control unit 1300. In step S2401 of the command reception interrupt process, the command output from the main control unit 1300 is stored in the command storage area provided in the RAM 1408 as an unprocessed command.

  Next, the first sub control unit timer interrupt process executed by the CPU 1404 of the first sub control unit 1400 will be described with reference to FIG. The first sub-control unit 1400 includes a hardware timer that generates a timer interrupt at a predetermined cycle (in this embodiment, once every 2 ms), and this timer interrupt is used as a trigger to perform timer interrupt processing. Execute in the cycle.

In step S2501, 1 is added to the value of the timer variable storage area of the RAM 1408 described in step S2303 in the first sub control unit main process, and the result is stored in the original timer variable storage area. Therefore, in step S2303, the value of the timer variable is determined to be 10 or more every 20 ms (2 ms × 10). In step S2503, transmission of a control command to the second sub-control unit 1500 set in step S2315, update processing of a random number for production, and the like are performed.
<Processing of Second Sub-Control Unit 500>

  Next, processing of the second sub control unit 1500 will be described with reference to FIG. 2A is a flowchart of the main process executed by the CPU 1504 of the second secondary control unit 1500, and FIG. 2B is a flowchart of the command reception interrupt process of the second secondary control unit 1500. . FIG. 6C is a flowchart of the timer interrupt process of the second sub control unit 1500, and FIG. 4D is a flowchart of the image control process of the second sub control unit 1500.

  First, in step S2601 in FIG. 9A, various initial settings are performed. When power is turned on, initialization processing is first executed in step S2601. In this initialization process, input / output port initialization, storage area initialization in the RAM 1508, and the like are performed.

  In step S2603, it is determined whether or not the timer variable is 10 or more, and this process is repeated until the timer variable becomes 10. When the timer variable becomes 10 or more, the process proceeds to step S2605. In step S2605, 0 is assigned to the timer variable.

In step S2607, command processing is performed. In the command processing, the CPU 1504 of the second sub control unit 1500 determines whether a command is received from the CPU 1404 of the first sub control unit 1400.

In step S2609, an effect control process is performed. In this effect control process, for example, when there is a new command in step S2607, a process corresponding to this command is performed. This process includes, for example, performing a process such as reading effect data from the ROM 1506 and performing an effect data update process when the effect data needs to be updated.

  In step S2611, shutter control processing is performed based on the processing result of step S2609. For example, if there is a shutter control command in the effect data read in step S2609, shutter control corresponding to this command is performed. In step S2613, image control processing is performed based on the processing result of step S2609. For example, if there is an image control command in the effect data read in step S2609, image control corresponding to this command is performed (details will be described later), and the flow returns to step S2603.

  Next, the command reception interrupt process of the second sub control unit 1500 will be described with reference to FIG. This command reception interrupt process is a process executed when the second sub control unit 1500 detects a strobe signal output from the first sub control unit 1400. In step S2701 of the command reception interrupt process, the command output from the first sub control unit 1400 is stored in the command storage area provided in the RAM 1508 as an unprocessed command.

  Next, the second sub control unit timer interrupt process executed by the CPU 1504 of the second sub control unit 1500 will be described with reference to FIG. The second sub-control unit 1500 includes a hardware timer that generates a timer interrupt at a predetermined cycle (in this embodiment, once every 2 ms). Execute in the cycle.

  In step S2801, 1 is added to the value of the timer variable storage area of the RAM 1508 described in step S2603 in the second sub-control unit main process, and the result is stored in the original timer variable storage area. Therefore, in step S2603, the value of the timer variable is determined to be 10 or more every 20 ms (2 ms × 10). In step S2803, an effect random number update process is performed.

  Next, the image control process in step S2613 in the main process of the second sub-control unit 1500 will be described with reference to FIG. FIG. 5 is a flowchart showing the flow of image control processing.

  In step S2901, an image data transfer instruction is issued. Here, the CPU 1504 first swaps the designation of the display areas A and B in the VRAM 1536. As a result, the one-frame image stored in the display area not designated as the drawing area is displayed on the effect image display device 1157. Next, the CPU 1504 sets the ROM coordinates (transfer source address of the ROM 1506), VRAM coordinates (transfer destination address of the VRAM 1536) and the like in the attribute register of the VDP 1534 based on the position information table, and then the image from the ROM 1506 to the VRAM 1536. Set an instruction to start data transfer. The VDP 1534 transfers image data from the ROM 1506 to the VRAM 1536 based on the command set in the attribute register. Thereafter, the VDP 1534 outputs a transfer end interrupt signal to the CPU 1504.

  In step S2903, it is determined whether or not a transfer end interrupt signal from VDP 1534 is input. If a transfer end interrupt signal is input, the process proceeds to step S2905. If not, a transfer end interrupt signal is input. Wait for it. In step S2905, parameters are set based on the production scenario configuration table and attribute data. Here, in order to form a display image in the display area A or B of the VRAM 1536 based on the image data transferred to the VRAM 1536 in step S2901, the CPU 1504 has information on the image data constituting the display image (coordinate axes and image sizes of the VRAM 1536). , VRAM coordinates (arrangement coordinates, etc.) are instructed to the VDP 1534. The VDP 1534 performs parameter setting according to the attribute based on the instruction stored in the attribute register.

  In step S2907, a drawing instruction is performed. In this drawing instruction, the CPU 1504 instructs the VDP 1534 to start drawing an image. The VDP 1534 starts drawing an image in the frame buffer in accordance with an instruction from the CPU 1504. In step S2909, it is determined whether or not a generation end interrupt signal from the VDP 1534 based on the end of image drawing is input. If a generation end interrupt signal is input, the process proceeds to step S2911, and if not, a generation end interrupt signal is determined. Wait for input. In step S2911, a scene display counter that is set in a predetermined area of the RAM 1508 and counts how many scene images have been generated is incremented (+1), and the process ends.

  One, a plurality, or all of the features of the present invention described below can be applied to the main control unit 1300 of the slot machine 1100 as well.

  As described above, the pachinko machine 100 (or slot machine 1100) according to the present embodiment has a main control unit (e.g., CPU 304 (or CPU 1304)) that performs game control centered on the progress of the game (e.g., CPU 304 (or CPU 1304)). Main control unit 300 (or main control unit 1300)) and sub-control units (for example, first sub-control unit 400, second sub-control unit 500 (for example) that control the effect of the game based on the game control of the main control unit. Or a first sub-control unit 1400, a second sub-control unit 1500)), and the CPU uses a first register (eg, “POP TI command”, “PUSH TI command”, etc.) The second register can be used with the instruction but cannot be used with the operation instruction (the T register cannot directly change its value by the operation instruction). (For example, an A register, an F register, a B register, a C register, a D register, an E register, an H register, an L register, and a back register thereof) and data to the first register via the second register Instruction (for example, “LD T, A” instruction such as “LD T, A” instruction) is not provided with a direct value (immediate value or immediate value) in the first register. The game machine is provided with a command (for example, “LD T, F0H” command) for setting data.

  According to the pachinko machine 100 (or slot machine 1100) according to the present embodiment, since data is transferred to the first register as a direct value, it is easy to check the set data. There is. In addition, since data is not transferred to the first register via another register, the value of the first register cannot be changed carelessly, resulting in a coding error. There are cases where it can be reduced. In addition, since the first register is only allowed to transfer data by direct value, it is used relatively more than other registers that allow both data transfer via the register and data transfer by direct value. Less frequent. For this reason, it is possible to increase the efficiency of coding review work and debugging (for example, T register tracing).

  Further, the pachinko machine 100 (or slot machine 1100) according to the present embodiment is a game machine having a CPU and game control means for performing game control, and the game machine is a pachinko machine or a slot machine. Yes, the CPU is built in a microcomputer, the CPU includes at least a specific register (for example, a T register), and the CPU receives a load instruction among the functions for setting a value in the specific register What is performed based on is a game machine having only a function of setting a value by a direct value.

  According to the pachinko machine 100 (or the slot machine 1100) according to the present embodiment, since the load instruction cannot set data other than the direct value to the specific register, the value of the specific register cannot be changed carelessly. As a result, the occurrence of coding mistakes can be reduced, and stable game control can be performed. In addition, since the data set in a specific register can be easily confirmed visually on the source code, coding review work and debugging efficiency can be improved, and the occurrence of mistakes is greatly reduced compared to the past. And stable game control can be performed. In addition, since specific registers are only allowed to set data with direct values, they are used more frequently than other registers that allow both data sets via registers and data sets with direct values. Becomes lower. For this reason, it may be possible to improve the efficiency of coding review work and debugging (for example, T register tracing).

  The present invention is not characterized by “not using a load instruction at the time of programming”, but “based on the fact that the CPU receives a load instruction among the functions for setting a value in a specific register. Since it only has a function to set a value by a direct value as it is performed ", it is characterized by" only a load instruction that sets a value by a direct value can be used for a specific register during programming " .

  In other words, the present invention has a function that the CPU itself executes (understands) such a load instruction even when an attempt is made to use a load instruction for setting a value to a specific register via another register during programming. Therefore, normally, in the process of assembling the assembler language into a machine language, it is excluded as an instruction that cannot be executed (understood) by the CPU and cannot be converted into a machine language. For this reason, a programmer cannot use a load instruction that sets a value in a specific register via another register during programming. In this specification, an example is shown in which programming is performed using assembly language. However, the situation is the same when programming is performed using machine language. Even if it is desired to use a load instruction for setting a value via another register, the instruction cannot be used unless the CPU can execute (understand) it.

  For this reason, in the present invention, the above-described remarkable effect can be obtained. However, in the prior art, the load instruction is not limited as in the present invention. A load instruction that sets a value via another register can be freely used. “Whether or not to use a load instruction during programming (whether or not to use it is a matter that can be appropriately selected by those skilled in the art based on the contents of the program, etc.”) Although it is possible to appropriately select whether or not to use a load instruction for setting a value via another register, the conventional technique has an option that the instruction can be used. An effect equivalent to the effect cannot be obtained with certainty.

  Further, even if a rule that the instruction is not used in programming is formulated, whether or not to follow the rule depends on the programmer (human), and other than the specific register as in the present invention. The use of a load instruction that sets a value via the register of 100% is not completely eliminated.

  Furthermore, in an environment where a load instruction for setting a value to a specific register via another register can be used freely, it is usually an instruction that can be executed (understood) by the CPU in the process of assembling the assembler language into a machine language. The instruction can be converted into machine language. For this reason, in the prior art, even if a programmer is careful not to use a load instruction that sets a value to a specific register via another register during programming, the assembler is optimized. The possibility of being assembled into a machine language corresponding to the instruction cannot be completely excluded.

  The second register includes one specific register (for example, A register) and a plurality of non-specific registers (for example, F register, B register, C register, D register, E register, H register, L register, and the like) And the CPU transfers the data to the non-specific register via the first register (for example, “LD B, T” instruction, T register in the B register) May be provided with an instruction (for example, “LD A, T” instruction) for transferring data to the specific register via the first register.

  With such a configuration, the first register can be made difficult to use compared to other registers, so that the value of the first register cannot be changed carelessly, resulting in a coding error. There are cases where it can be reduced.

  The first register and the second register are 8-bit registers capable of storing 8-bit values, and the non-specific register is a register capable of 16-bit operations in combination with other registers. A register that can form a combination (for example, a BC register, a DE register, and an HL register), but the first register cannot be combined with other registers to form a combination of registers that can perform the 16-bit operation. It may be a simple register.

  With such a configuration, the first register can be made difficult to use compared to other registers, so that the value of the first register cannot be changed carelessly, resulting in a coding error. There are cases where it can be reduced. Note that the T register cannot be combined with any other register to allow a 16-bit operation, but as described above, the “PUSH TI” instruction or the “POP TI” instruction uses I Along with the register, it is possible to save and restore a 16-bit length. In other words, the T register is a register that cannot be used as an operand of an operation instruction but can be used as an operand of a transfer instruction.

  In addition, a storage unit that stores data used for the game control is provided, and the storage unit stores a ROM (for example, ROM 306 (or ROM 1306)) that stores a program executed by the CPU, and the CPU performs the game control. RAM (for example, RAM 308 (or RAM 1308)) that can temporarily store data used at the time, and the CPU before the game control is started (for example, “after power-on, the main control unit 300 of Before the CPU 304 executes the user program (control program) ”,“ After the system reset, before the CPU 304 of the main control unit 300 executes the user program (control program) ”,“ Immediately after shifting to the security mode ”,“ Security check ” Immediately after the result is OK and the mode is changed to the user mode "," During a period of initialization processing due to a stem reset, etc.), a specific value (for example, F0H) indicating the upper address of the top address of the RAM is stored in the first register (regardless of the program). It may be set.

  With such a configuration, when reading / writing RAM data, only the lower address of the RAM needs to be specified by fixing the first register as a value indicating the upper address of the RAM, and the amount of program code As a result, it is possible to reduce the occurrence of coding errors as a result of not being able to change the value of the first register inadvertently.

  A gaming machine comprising a microcomputer having a CPU, a ROM storing a gaming control program, and a RAM capable of temporarily storing data, wherein the gaming machine is a pachinko machine or a slot machine. The CPU has at least a specific register, and the upper byte of the start address of the RAM is larger than the upper byte of the start address of the ROM, and the CPU has a function of setting a value in the specific register. Of these, only the function of setting a value by a direct value is performed based on receiving the load instruction, and the CPU has the load instruction among the functions of setting a value in the specific register. As other than what is performed on the basis of having received, the same value as the upper byte of the top address of the RAM is set as the initial value. Set Te functions may be at least a.

  With such a configuration, by setting a value indicating the upper address of the RAM as the initial value of the specific register, when reading or writing RAM data, only the lower address of the RAM needs to be specified. Reduction of the amount and improvement of the processing speed can be realized. In addition, since only the direct value by the load instruction can be set in the specific register other than the initial value, the value of the specific register cannot be changed carelessly. The occurrence of data read / write errors and the like can be avoided, and stable game control can be performed. In addition, since it is frequently used for computation, it is possible to prevent an incorrect value from being set in a specific register via a register in which an unintended computation result is stored, and an upper byte of the RAM start address as an initial value. Since the same value is set in a specific register, if the RAM is accessed using a specific register after the power is turned on, the specific register is not operated without setting the value in the specific register. Can be used to access the RAM, and with regard to the “accessing the RAM”, it is possible to prevent a problem that the information of an unintended address is accessed because the value of a specific register is incorrect. The effect can be further enhanced.

  In addition, since the game cannot be controlled as desired simply by rewriting the program, there are cases where illegal acts caused by rewriting the program can be effectively prevented. In particular, a user mode in which a user program set by a CPU user can be executed and a non-user mode in which the user program cannot be executed (for example, a security mode) are provided, and the specific value is set in the non-user mode. If the first register is set, it may be possible to prevent an illegal act in which a specific value is altered to another value or a specific value is read out.

  The RAM includes a first area (for example, a work area of 7E00H to 7EFFH (or an area accessible by an I / O mapped I / O method)) and a second area (for example, a stack area of 7FE0H to 7FFFH ( Alternatively, the specific value may be a value indicating a higher address (F0H) of the first area.

  With such a configuration, when reading and writing data in the first area of the RAM, the first register is fixed as a value indicating the upper address of the first area of the RAM, so that the first area of the RAM is It is only necessary to specify the lower address, so that the amount of program code can be reduced and the processing speed can be improved, and the value of the first register cannot be changed carelessly. In some cases, it is possible to reduce the occurrence of. In addition, by fixing the upper address of the first area, there is a case where it is possible to prevent a mistake that an intention to read / write the first area erroneously reads / writes the second area.

  In addition, the pachinko machine 100 (or slot machine 1100) according to the present embodiment stores a CPU (for example, the CPU 304 (or CPU 1304) that performs game control centering on the progress of the game and data used for the game control. And a memory for storing a program executed by the CPU (for example, ROM 306 (or ROM 1306)) and data used when the CPU performs the game control. RAM (for example, RAM 308 (or RAM 1308)) at least, and the CPU before the game control is started (for example, “after power-on, the CPU 304 of the main control unit 300 is a user program). (Before executing (control program) "," After system reset, main controller 30 Before the CPU 304 executes the user program (control program), “immediately after shifting to the security mode”, “immediately after shifting to the user mode with the result of the security check being OK”, “initialization processing by system reset” During a period, etc.), a specific value (for example, F0H) indicating the upper address of the top address of the RAM is set to a specific register (for example, the CPU 304 separate from the ROM 306). This is a gaming machine characterized in that it is set in a T register built in.

  According to the pachinko machine 100 (or the slot machine 1100) according to the present embodiment, when reading / writing data in the RAM, by fixing the specific register as a value indicating the upper address of the RAM, only the lower address of the RAM is obtained. It is only necessary to specify this, and it is possible to reduce the amount of program code and increase the processing speed, as well as reduce the occurrence of coding errors as a result of not being able to change the value of a specific register carelessly. May be possible.

  The pachinko machine 100 (or slot machine 1100) according to the present embodiment is a game machine including a microcomputer that includes a CPU, a ROM that stores a game control program, and a RAM that can temporarily store data. The gaming machine is a pachinko machine or a slot machine, the CPU includes at least a specific register, and the upper byte of the top address of the RAM is larger than the upper byte of the top address of the ROM. The gaming machine is characterized in that the same value as the upper byte of the head address of the RAM is set in the specific register as an initial value regardless of the control program.

  According to the pachinko machine 100 (or slot machine 1100) according to the present embodiment, since it is not necessary to describe the upper byte of the RAM address in the game control program, even if the program is illegally analyzed by an unauthorized person. It is difficult to specify the address of the RAM, and the game cannot be controlled as desired simply by rewriting the game control program, so that illegal acts caused by rewriting the game control program can be effectively prevented. In addition, when reading and writing data in the RAM, it is sufficient to specify only the lower address of the RAM by fixing the specific register as a value indicating the upper address of the RAM, thereby reducing the amount of program code and improving the processing speed. In addition to being able to be realized, the value of the specific register cannot be changed carelessly, and as a result, the occurrence of coding errors can be reduced.

  In addition, since the game cannot be controlled as desired simply by rewriting the program, there are cases where illegal acts caused by rewriting the program can be effectively prevented. In particular, a user mode in which a user program set by a CPU user can be executed and a non-user mode in which the user program cannot be executed (for example, a security mode) are provided, and the specific value is set in the non-user mode. If the first register is set, it may be possible to prevent an illegal act in which a specific value is altered to another value or a specific value is read out.

  The CPU further includes non-specific registers (for example, an A register, an F register, a B register, a C register, a D register, an E register, an H register, an L register, and a back register thereof), and the specific register Are not provided with an instruction for transferring data via the non-specific register (eg, an instruction for transferring data via the A register to the T register, such as an “LD T, A” instruction). May be provided with an instruction (for example, an “LD T, F0H” instruction) for setting data.

  With such a configuration, since data is transferred to a specific register as a direct value, it may be easy to check the set data. In addition, since it is configured so that data cannot be transferred to a specific register via another register, the value of the specific register cannot be inadvertently changed, thereby reducing the occurrence of coding errors. There are cases where it is possible. In addition, because specific registers are only allowed to transfer data by direct data, they are used more frequently than other registers that allow both data transfer through registers and direct data transfer. Becomes lower. For this reason, it is possible to increase the efficiency of coding review work and debugging (for example, T register tracing).

  The CPU may be configured to transfer the specific value to the specific register based on an instruction to transfer data to the specific register as a direct value.

  With such a configuration, when the general-purpose register becomes empty due to loop processing or the like, the specific register is temporarily used and then returned to the initial value, so that convenience can be improved.

  Further, the CPU is configured to be able to transfer the specific value to the specific register (for example, transfer by a “POP TI” instruction) based on an instruction to transfer data from the RAM to the specific register. May be.

  With such a configuration, the specific register can be used for specific processing, and the convenience of the specific register can be improved in some cases.

  The RAM includes a first area (for example, a work area of 7E00H to 7EFFH (or an area accessible by an I / O mapped I / O method)) and a second area (for example, a stack area of 7FE0H to 7FFFH ( Alternatively, the specific value may be a value indicating a higher address (F0H) of the first area.

  With such a configuration, when reading and writing data in the first area of the RAM, the specific register is fixed as a value indicating the upper address of the first area of the RAM, thereby lowering the lower address of the first area of the RAM. It is possible to reduce the amount of program code and increase the processing speed, as well as reduce the occurrence of coding errors as a result of the inadvertent change of specific register values. There is a case that can be made. In addition, by fixing the upper address of the first area, there is a case where it is possible to prevent a mistake that an intention to read / write the first area erroneously reads / writes the second area.

  In addition, the CPU can execute an interrupt process (for example, main control unit main process) that is executed based on a predetermined interrupt condition being satisfied, and executes the first interrupt process after the power is turned on. Prior to this, processing for determining whether the specific value is set in the specific register (for example, T-registration check processing) may be executed. In addition, examples of “before executing the first interrupt process after turning on the power” include other “after power on and before confirming the low voltage state in step S105 of the main control unit main process”, “ For example, after power-on, before confirming whether or not to return to the state before power interruption in step S109 of the main control unit main process, or “before power-on, before confirming the rise of the first sub-control unit”. it can. Further, depending on the result of the “determination process”, a specific value may be set in the specific register as shown in FIG. 11 or error processing may be executed as shown in FIG.

  With such a configuration, it may be possible to determine whether or not the game machine is operating normally by checking the value of the specific register.

  Further, the pachinko machine 100 (or the slot machine 1100) according to the present embodiment has a plurality of types of data (for example, non-use data and data) including control program data in storage areas (for example, ROM areas) indicated by a plurality of addresses. A plurality of ROMs (for example, ROM 306) storing reference data) and interrupt processing (for example, main control unit timer interrupt processing) executed at predetermined intervals based on the control program data stored in the ROM A CPU (for example, a CPU 304) that executes a type of game control process, and the ROM is one or a plurality of the control program data, each of which corresponds to a plurality of types of commands executed by the CPU (Opcode) and one or more of the control program data, the CPU Specific identification information (for example, a subroutine) that stores supplementary data (operands) necessary for executing the instruction, and is capable of identifying a specific address (for example, the head address of the subroutine). First address data (for example, m) indicating the first identification information that is a part of the first address of information in binary format) and other data different from the first address data (for example, the EXESUB instruction) Specific instruction data (for example, EXESUB instruction), for example, which causes the CPU to read the data stored in the storage area indicated by the specific address. , The instruction data of the EXESUB instruction) and the supplementary data, the information obtained by removing the first identification information from the specific identification information Specific supplementary data that is composed of second address data (for example, n) indicating second identification information that is at least a part of the CPU and that is necessary for the CPU to execute the specific instruction. (For example, in the storage area of the ROM 306 corresponding to the timer interrupt processing area in the ROM control area (the storage area indicated by the address corresponding to the timer interrupt processing)) It is a game stand characterized by being.

  According to the pachinko machine 100 (or the slot machine 1100) according to the present embodiment, the first address data m included in the instruction data is defined as upper address data, thereby grouping the instruction data into the address area. In some cases, coding errors can be suppressed. In addition, since the instruction data is configured to include data that forms part of the start address of the subroutine to be called, even if the destination address data is wrong, the wrong data If included in the instruction data, the execution of the control program may be stopped, so that a coding error may be suppressed. In addition, a control instruction (for example, a CALL instruction) for calling a conventional subroutine can be compressed, and conventional control program data stored in the storage area of the ROM 306 corresponding to the ROM control area can be compressed. . In addition, due to the compression of the control program, there are cases where the processing speed of the control program for calling a subroutine can be improved (the number of states can be reduced) as compared with the conventional case (for example, CALL instruction).

  In addition, the pachinko machine 100 (or the slot machine 1100) according to the present embodiment includes a plurality of types of data including control program data and reference data referred to based on the control program data in a storage area indicated by each of a plurality of addresses. And a CPU for executing a plurality of types of game control processes including an interrupt process executed at predetermined intervals based on the control program data and the reference data stored in the ROM, The ROM is one or a plurality of the control program data, the command data corresponding to each of a plurality of types of instructions executed by the CPU, and the one or a plurality of the control program data, the CPU And supplementary data necessary for executing A storage area composed of first address data indicating first identification information that is part of specific identification information enabling identification of an address and different data different from the first address data, and indicated by the specific address Specific instruction data corresponding to a specific instruction for causing the CPU to read the data stored in the CPU and the supplementary data, the second identification information which is information obtained by removing the first identification information from the specific identification information And the specific supplementary data necessary for the CPU to execute the specific instruction is stored so as to correspond to the instruction executed in the interrupt processing, and All the control program data is stored in a specific storage area that can be read by the CPU by execution, and the specific record in which all the control program data is stored is stored. In different storage area from the region, a gaming table, characterized in that stores the reference data.

  According to the pachinko machine 100 (or slot machine 1100) according to the present embodiment, when the CPU executes a specific command, the reference data is erroneously read, and an unintended game control process is performed based on the reference data. Such a situation can be prevented and game control can be stabilized. Further, since the specific instruction is configured to be able to read all the control program data stored in the specific storage area, the arrangement (storage location) of the call source and the call destination in the control program data may be limited. Therefore, the control program can be designed with a degree of freedom. In the field of gaming machines, a plurality of types of gaming machines share control program data (for example, frequently used subroutines), while reference data (for example, lottery values) according to the specifications and performance of each gaming machine. Or production data) is generally different, and is particularly suitable for a game machine.

  A ROM storing a plurality of types of data including control program data and reference data referred to based on the control program data in a storage area indicated by each of a plurality of addresses; and the control program data stored in the ROM And a CPU that executes a plurality of types of game control processes including an interrupt process that is executed at predetermined intervals based on the reference data, and the ROM is one or a plurality of the control program data, Storing instruction data corresponding to each of a plurality of types of instructions executed by the CPU, and one or a plurality of the control program data, which is supplementary data necessary for the CPU to execute the instructions; Indicates first identification information that is part of specific identification information that is instruction data and enables identification of a specific address. Specific instruction data corresponding to a specific instruction that is constituted by first address data and different data different from the first address data, and causes the CPU to read data stored in the storage area indicated by the specific address; The supplementary data is composed of second address data indicating second identification information, which is information obtained by removing the first identification information from the specific identification information, and the CPU executes the specific instruction. Specific supplementary data necessary for the interrupt processing is stored so as to correspond to the instruction executed in the interrupt processing, and all the control program data is stored in a specific storage area readable by the CPU by the execution of the specific instruction. The reference data may be stored in a storage area different from the specific storage area in which all control program data is stored.

  With such a configuration, it is possible to prevent a situation in which, when the CPU executes a specific command, the reference data is erroneously read and an unintended game control process is performed based on the reference data. And stabilization of game control can be achieved. Further, since the specific instruction is configured to be able to read all the control program data stored in the specific storage area, the arrangement (storage location) of the call source and the call destination in the control program data may be limited. Therefore, the control program can be designed with a degree of freedom. In the field of gaming machines, a plurality of types of gaming machines share control program data (for example, frequently used subroutines), while reference data (for example, lottery values) according to the specifications and performance of each gaming machine. Or production data) is generally different, and is particularly suitable for a game machine.

  Further, the ROM includes the first identification information (for example, mn) that makes it possible to identify the specific address by defining at least the order of the first identification information and the second identification information. The first instruction data indicating one identification information and the specific command data composed of the separate data, and the second address data indicating the second identification information among the specific identification information. The specific supplementary data may be stored so as to correspond to an instruction executed in the interrupt process.

  With such a configuration, since the instruction data is configured to include data that forms part of the top address of the subroutine to be called, even if the destination address data is wrong, If erroneous data is included in the instruction data, the execution of the control program is stopped, so that a coding error may be suppressed.

  The ROM includes at least first configuration data (for example, bit 7 of the instruction data of the EXESUB instruction) that is a part of the first address data, and second configuration data that is at least a part of the other data. (For example, bits 6 to 3 of the instruction data of the EXEBUS instruction), third configuration data obtained by removing the first configuration data from the first address data (for example, bits 2 to 0 of the instruction data of the EXESUB instruction) The specific instruction data configured in this order may be stored so as to correspond to the instruction executed in the interrupt processing.

  With such a configuration, it is possible to finely assign the instruction data to a free area of the instruction data table while grouping the instruction data. Therefore, limited hardware resources (for example, patterns that can be defined by 1 byte (256 patterns)) can be used effectively and stored in the ROM storage area corresponding to the ROM control area by compressing instruction data. The conventional control program data can be compressed.

  Further, the third configuration data (for example, bits 2 to 0 of the instruction data of the EXEBUS instruction) has a larger data capacity than the first configuration data (for example, bit 7 of the instruction data of the EXESUB instruction). Alternatively, the specific instruction data configured such that the first configuration data has a data capacity larger than that of the third configuration data (for example, 1 bit compared to 3 bits) is generated by the interrupt processing. You may memorize | store corresponding to the command performed.

  With such a configuration, it is possible to finely assign the instruction data to a free area of the instruction data table while grouping the instruction data. Therefore, limited hardware resources (for example, patterns that can be defined by 1 byte (256 patterns)) can be used effectively and stored in the ROM storage area corresponding to the ROM control area by compressing instruction data. The conventional control program data can be compressed.

  The ROM stores all the control program data in a specific storage area (for example, 0000H to 0FFFH or 0000H to 11FFH) in which data that can be read by the CPU by execution of the specific instruction is stored. A storage area (for example, a storage area of the ROM 306 corresponding to a non-use area) excluding a control storage area (for example, a storage area of the ROM 306 corresponding to the ROM control area) in which the control program data is stored from the specific storage area ) May be stored non-use data (for example, 00H) that is not used for execution of the game control process.

  With such a configuration, the CPU 304 does not directly read data (for example, reference data or management data) excluding non-use data and control program data as instruction data. It may be possible to prevent operation.

  The ROM stores a plurality of types of data represented by a specific data length (for example, 1 byte (8 bits)) in a storage area indicated by each of a plurality of addresses. A plurality of types of game control processes including the interrupt process are executed by reading the data stored in the storage area indicated by one address stored in the ROM for each process, and the ROM further includes: The specific identification information that can identify the specific address represented by a first data length (for example, 2 bytes (16 bits)) that is an integer multiple of 2 or more of the specific data length The specific instruction data composed of the first address data indicating the first identification information and the separate data, and data that is an integer multiple of the specific data length than the first data length The specific supplementary data composed of the second address data expressed by a second data length (for example, 1 byte (8 bits)) that is short only so as to correspond to the instruction executed in the interrupt processing May be stored.

  With such a configuration, it is possible to finely assign the instruction data to a free area of the instruction data table while grouping the instruction data. Therefore, limited hardware resources (for example, patterns that can be defined by 1 byte (256 patterns)) can be used effectively and stored in the ROM storage area corresponding to the ROM control area by compressing instruction data. The conventional control program data can be compressed.

  Further, the pachinko machine 100 (or the slot machine 110) according to the present embodiment has a ROM (eg, ROM 306) storing a control program composed of a plurality of control program data, and game control based on the control program. And the ROM executes first data (for example, bit 6 and bit 7 in the instruction data of the EXESUB instruction (EXESUBmn)) among the plurality of control program data. , Second data (for example, bit 5 (α) in the instruction data of the EXESUB instruction (EXESUBMn)), third data (for example, bits 3 and 4 in the instruction data of the EXESUB instruction (EXESUBmn)), 4 data (for example, the EXESUB instruction (EX Bit 0 (δ), bit 1 (γ), bit 2 (β)) in the instruction data of SUBmn), and fifth data (for example, supplementary data (n) in the instruction data of the EXESUB instruction (EXESUBmn)) The instruction data of specific control program data (EXESUB instruction (EXESUBmn)) configured to include at least the second data, the third data, and the fourth data are arranged in order (for example, the address is young) The CPU stores the first instruction (for example, the first address of the subroutine) specified by using the first and third data when the specific control program data is read. And a second instruction (for example, specified by using the second data, the fourth data, and the fifth data) For example, an instruction for specifying the start address of a subroutine to be called) and a specific instruction (for example, EXESUB instruction) specified in (1) during interrupt processing (for example, timer interrupt processing) executed at a predetermined cycle. It can be said that it is a game stand.

  The ROM includes at least one of the first data and the second data, the second data and the third data, and the third data and the fourth data. The specific control program data configured to include another data between any one of the data may be stored. However, the ROM stores the first data, the second data, and the data. If the specific control program data composed only of the third data and the fourth data is stored, the machine language after assembly can be checked more easily and coding errors can be suppressed. it can.

  The data length of the first data, the second data, the third data, and the fourth data is the same as the data length of the fourth data (for example, 1 byte ( (8 bits) long). Furthermore, the data length of the data read by the CPU at the same time may be the same as the data length of the fourth data.

  In addition, the pachinko machine 100 (or slot machine 1100) according to the present embodiment stores storage means (for example, ROM 306, RAM 308 (or ROM 1306, RAM 1308)) for storing program data and temporary data, and storage in the storage means. A main control unit (for example, main control unit 300 (or main control unit 1300)) that performs game control centered on the progress of the game using the stored data, and a game based on the game control of the main control unit A sub-control unit (for example, the first sub-control unit 400 and the second sub-control unit 500 (or the first sub-control unit 1400 and the second sub-control unit 1500)) that performs the production control. The main control unit has a plurality of registers (for example, an A register, an F register, a B register, Register, D register, E register, H register, L register, T register), and can calculate a second bit length (for example, 16-bit length) that is double the first bit length. Indicated by a value stored in a first register and a second register (for example, an H register and an L register) of the plurality of registers (for example, a BC register, a DE register, and an HL register). And a first value (for example, AEH) stored in a first address (for example, 1750H) in the storage means and a second address (for example, 1751H) continuous with the first address, and a second The value (for example, 19) is assigned to the third register (for example, C register) and the fourth register (for example, A register) of the plurality of registers. A predetermined instruction (for example, an “INCENSOU AC, (HL)” instruction) to be transferred, and the predetermined instruction is executed in the game control (for example, a special symbol variation time lottery process), and the third register And the fourth register is a gaming machine characterized by being different from a combination of registers capable of calculating the second bit length (BC register, DE register, HL register). The “second address continuous with the first address” is not limited to an address larger than the first address, and may be an address smaller than the first address. In the above example, the first address is 1750H. The second address may be 174FH.

  According to the pachinko machine 100 (or the slot machine 1100) according to the present embodiment, two data stored in consecutively arranged addresses are converted into two types of registers that do not constitute a register pair by one instruction. Since the program capacity can be stored, the capacity of the program can be reduced, the capacity can be allocated to the program for improving the game performance, and the fun of the game can be enhanced. Further, there are cases where the processing time can be shortened and stable game control can be performed. In addition, by reducing the program capacity, it becomes easier to see the program, and in some cases, coding errors and bugs can be suppressed. In addition, since the third register and the fourth register are not a register pair, a program can be created with care when performing 16-bit arithmetic processing, and the occurrence of coding errors and bugs may be suppressed. .

  In addition, the pachinko machine 100 (or slot machine 1100) according to the present embodiment includes at least first to fourth registers, and a CPU that can execute processing using a register pair including an upper register and a lower register, A gaming machine equipped with a microcomputer storing a ROM for storing a gaming control program, wherein the gaming machine is a pachinko machine or a slot machine, and the CPU receives a first instruction and a second instruction. A plurality of instructions can be executed, and a combination of at least two of the first register and the second register is a predetermined register pair of the register pair, and the third register and the second register At least one of the fourth registers is the upper register, and is based on execution of the first instruction. A first value stored in an area indicated by a first address indicated by a value stored in the predetermined register pair is set in the fourth register, and the second value is continuous with the first address. The second value stored in the area indicated by the address of the second address is set in the third register, and the value of the predetermined register pair becomes a value indicating an address continuous with the second address, Based on the execution of the instruction, the second value stored in the area indicated by the second address continuous with the first address indicated by the value stored in the predetermined register pair is the fourth value. A third value stored in a region indicated by a third address that is set in the register and indicated by the third address that is continuous with the second address is set in the third register, and a value of the predetermined register pair is set in the third register Indicates address The CPU can set the value stored in the ROM to a combination of two registers of the third register and the fourth register different from the register pair with one instruction. The predetermined function for changing the value of the predetermined register pair is based on receiving the first function and the second instruction for setting a value based on receiving the first instruction. It is a gaming machine having only two of the second functions for setting values.

  According to the pachinko machine 100 (or slot machine 1100) according to the present embodiment, the function of setting values to two combinations of the third register and the fourth register, which are less versatile than the register pair, is limited by one instruction. For this reason, it is possible to make it difficult for an unauthorized person to perform an unauthorized act of illegally altering a value related to a player's profit. In addition, the first command and the second command can be properly used according to the preceding and subsequent processing, and the capacity of the game control program can be reduced. In addition, the capacity of the game control program can be reduced as compared with the case where the first instruction and the second instruction are configured by conventional instructions, and capacity can be allocated to a program for improving game play. Can enhance the interest of Further, since the third register and the fourth register are less versatile than the register pair, the program can be created with care, and coding errors and bugs can be suppressed. In addition, interrupt processing may occur during execution of an instruction, and the value of a register during instruction execution may be rewritten to an unintended value due to interrupt processing, or execution of the instruction may be hindered and processing may be delayed. In some cases, stable game control can be performed.

  In addition, a microcomputer including at least first to fourth registers, a CPU capable of executing processing using a register pair including an upper register and a lower register, and a ROM storing a game control program is provided. The gaming table is a pachinko machine or a slot machine, and the CPU can execute a plurality of instructions including a first instruction and a second instruction, and at least the first register And the combination of the two registers of the second register is a predetermined register pair of the register pair, and at least one of the third register and the fourth register is the upper register, Based on the execution of the first instruction, the first instruction indicated by the value stored in the predetermined register pair. The first value stored in the area indicated by the address is set in the fourth register, and the second value stored in the area indicated by the second address that is continuous with the first address is the third value. Is set in a register, and the value of the predetermined register pair becomes a value indicating an address continuous with the second address, and is stored in the predetermined register pair based on the execution of the second instruction. The second value stored in the area indicated by the second address that is continuous with the first address indicated by the value is set in the fourth register, and the third address that is continuous with the second address is The third value stored in the area indicated is set in the third register, the value of the predetermined register pair becomes the value indicating the third address, and the CPU is different from the register pair. Third register A value stored in the ROM can be set to a combination of two registers of the fourth register with one instruction, and a predetermined function for changing the value of the predetermined register pair includes the first register The CPU has at least two of a first function for setting a value based on receiving one command and a second function for setting a value based on receiving the second command; The CPU has at least a specific register, and among the functions for setting a value in the specific register, the CPU has only a function for setting a value by a direct value as a function that is performed based on receiving a load instruction. It may be.

  With such a configuration, the function for setting a value to one combination of the third register and the fourth register, which is less versatile than the register pair, is limited. It is possible to make it difficult for an unauthorized person to perform an unauthorized act of tampering. In addition, the first command and the second command can be properly used according to the preceding and subsequent processing, and the capacity of the game control program can be reduced. In addition, the capacity of the game control program can be reduced as compared with the case where the first instruction and the second instruction are configured by conventional instructions, and capacity can be allocated to a program for improving game play. Can enhance the interest of Further, since the third register and the fourth register are less versatile than the register pair, the program can be created with care, and coding errors and bugs can be suppressed. In addition, interrupt processing may occur during execution of an instruction, and the value of a register during instruction execution may be rewritten to an unintended value due to interrupt processing, or execution of the instruction may be hindered and processing may be delayed. And stable game control can be performed.

  Further, at least one of the third register and the fourth register may constitute a combination of registers capable of calculating the second bit length (for example, the B register has a 16-bit length). A BC register, which is a register pair that can be operated, is configured).

  With this configuration, the value of one register of a register pair that performs 16-bit arithmetic can be fixed, and the value of one register set before a predetermined instruction can be saved without saving the value of one register. In some cases, the program capacity can be reduced. Also, when performing 16-bit arithmetic processing, a program can be created with care, and in some cases, coding errors and bugs can be suppressed.

  Further, at least one of the third register and the fourth register may be an upper register of a combination of registers capable of calculating the second bit length (for example, the B register is a 16-bit register). (It is a high-order register of the BC register, which is a register pair capable of long operations).

  With such a configuration, the value of the upper 8 bits of the register pair that performs 16-bit arithmetic can be changed, and the upper part of the address indicated by the register pair can be changed and used in processing after a predetermined instruction. May be possible. For example, each of the third register and the fourth register can be used for different processing (for example, one is used by the INCENSOU instruction and the other is used as a counter for counting the number of loop processes). It is possible to effectively use the limited registers. Also, when performing 16-bit arithmetic processing, a program can be created with care, and in some cases, coding errors and bugs can be suppressed.

  The predetermined instruction may include a process of adding a predetermined value to a value of a lower register of the first register and the second register (for example, a process of adding 2 to the HL register). .

  With such a configuration, the following processing can be performed in a state in which the value of an address obtained by adding a predetermined value from a predetermined address is set in a register after the completion of the predetermined instruction. In some cases, the program capacity can be reduced compared to a program that is executed a predetermined number of times.

  The first address is an address next to an address (for example, 174FH) (for example, 174FH) indicated by values stored in the first register and the second register before executing the predetermined instruction (for example, 1750H).

  With such a configuration, the address can be specified first in the repetition process, and when the repetition process is finished, the address value obtained by adding a predetermined value from the address before the predetermined instruction is set in the register. The following processing can be performed in this state. In particular, when using a data table in which two types of data are alternately stored, desired data can be quickly read from the data table.

  In addition, the pachinko machine 100 (or slot machine 1100) according to the present embodiment stores storage means (for example, ROM 306, RAM 308 (or ROM 1306, RAM 1308)) for storing program data and temporary data, and storage in the storage means. A main control unit (for example, main control unit 300 (or main control unit 1300)) that performs game control centered on the progress of the game using the stored data, and a game based on the game control of the main control unit A sub-control unit (for example, the first sub-control unit 400 and the second sub-control unit 500 (or the first sub-control unit 1400 and the second sub-control unit 1500)) that performs the production control. The main control unit includes a first register (for example, C register) capable of storing a value of a first bit length (for example, 8-bit length) and the first A plurality of registers (for example, BC register, DE register, HL) including a second register (for example, HL register) capable of storing a value of a second bit length (for example, 16-bit length) that is an integral multiple of the bit length A predetermined instruction (for example, “ADDTWOONE HL, C” instruction) that adds the value of the first register to the value of the second register and stores the value in the second register, The gaming machine is characterized in that the predetermined command is executed in the game control (for example, special symbol variation time lottery processing). The second register only needs to be able to store a value of the second bit length that is an integral multiple of the first bit length. For example, when the bit length of the first register is 4 bits, the second register is 4 bits. May be a register whose bit length is a multiple of (4, 8, 12,...), And when the bit length of the first register is 16 bits, a multiple of 16 (16, 32, 64,...) Is a bit length. A register may be used.

  According to the pachinko machine 100 (or the slot machine 1100) according to the present embodiment, it is not necessary to carry out a carry process separately, so that the program capacity can be reduced and a capacity is allocated to a program for improving game playability. It is possible to enhance the interest of the game. Further, there are cases where the processing time can be shortened and stable game control can be performed. In addition, by reducing the program capacity, it becomes easier to see the program, and in some cases, coding errors and bugs can be suppressed. Furthermore, since addition operations between registers having different bit lengths can be performed, for example, an addition operation that has conventionally been performed using two 16-bit register pairs can be performed with a 16-bit register pair and an 8-bit register. In some cases, a long register can be used, and a limited number of registers can be used effectively.

  Further, the pachinko machine 100 (or slot machine 1100) according to the present embodiment includes a CPU including at least first to third registers capable of storing an 8-bit value, and the CPU has a 16-bit value. At least a fourth register, and the CPU is capable of executing a process using a register pair including the first register and the second register, and includes a microcomputer incorporating the CPU. The gaming machine is a pachinko machine or a slot machine, and the CPU adds the value of the third register to the value of the fourth register and adds the value to the fourth register. A first instruction capable of setting a result is executable, wherein the first instruction adds the value of the third register to the value of the register pair; The CPU can set the addition result to the register pair, and the CPU can subtract the value of the third register from the value of the register pair and set the subtraction result to the register pair. The function of adding / subtracting the 8-bit value to / from the 16-bit register pair in the CPU is realized by both the first instruction and the second instruction. The function of adding / subtracting the value of the 8-bit length to / from the fourth register of the 16-bit length in the CPU is realized only by the first instruction.

  According to the pachinko machine 100 (or the slot machine 1100) according to the present embodiment, values of registers having different bit lengths can be added and subtracted. For example, conventionally, two 16-bit register pairs are used. In some cases, the addition and subtraction performed can be performed with a 16-bit register pair and an 8-bit register, and a limited number of registers can be used effectively. In addition, since addition / subtraction is performed between register values, the processing time for addition / subtraction can be shortened compared to the case of using RAM or the like, and stable game control can be performed. In addition, by configuring such that addition / subtraction using the fourth register can be executed only by the first instruction, a fraudulent act of illegally tampering with the value related to the player's profit (for example, a numerical value advantageous to a register pair) It is possible to make it difficult for an unauthorized person to perform an act of improperly embedding an instruction to add the. In addition, since the capacity of the game control program can be reduced compared to the case where the first instruction and the second instruction are configured with conventional instructions, capacity can be allocated to a program for improving game play, There are cases where the interest of the game can be enhanced.

  In addition, a microcomputer including at least first to fourth registers, a CPU capable of executing processing using a register pair including an upper register and a lower register, and a ROM storing a game control program is provided. The gaming table is a pachinko machine or a slot machine, and the CPU can execute a plurality of instructions including a first instruction and a second instruction, and at least the first register And the combination of the two registers of the second register is a predetermined register pair of the register pair, and at least one of the third register and the fourth register is the upper register, Based on the execution of the first instruction, the first instruction indicated by the value stored in the predetermined register pair. The first value stored in the area indicated by the address is set in the fourth register, and the second value stored in the area indicated by the second address that is continuous with the first address is the third value. Is set in a register, and the value of the predetermined register pair becomes a value indicating an address continuous with the second address, and is stored in the predetermined register pair based on the execution of the second instruction. The second value stored in the area indicated by the second address that is continuous with the first address indicated by the value is set in the fourth register, and the third address that is continuous with the second address is The third value stored in the area indicated is set in the third register, the value of the predetermined register pair becomes the value indicating the third address, and the CPU is different from the register pair. Third register A value stored in the ROM can be set to a combination of two registers of the fourth register with one instruction, and a predetermined function for changing the value of the predetermined register pair includes the first register The CPU has at least two of a first function for setting a value based on receiving one command and a second function for setting a value based on receiving the second command; The CPU has at least a specific register, and among the functions for setting a value in the specific register, the CPU has only a function for setting a value by a direct value as a function that is performed based on receiving a load instruction. It may be.

  With such a configuration, the function for setting a value to one combination of the third register and the fourth register, which is less versatile than the register pair, is limited. It is possible to make it difficult for an unauthorized person to perform an unauthorized act of tampering. In addition, the first command and the second command can be properly used according to the preceding and subsequent processing, and the capacity of the game control program can be reduced. In addition, the capacity of the game control program can be reduced as compared with the case where the first instruction and the second instruction are configured by conventional instructions, and capacity can be allocated to a program for improving game play. Can enhance the interest of Further, since the third register and the fourth register are less versatile than the register pair, the program can be created with care, and coding errors and bugs can be suppressed. In addition, interrupt processing may occur during execution of an instruction, and the value of a register during instruction execution may be rewritten to an unintended value due to interrupt processing, or execution of the instruction may be hindered and processing may be delayed. And stable game control can be performed.

  Further, the first register (for example, C register) may be a lower register of a combination of registers (for example, BC register) capable of calculating the second bit length.

  With such a configuration, the value of the upper 8 bits of the register pair can be fixed, and a program can be created with care when performing 16-bit arithmetic processing, which can lead to coding errors and bugs. In some cases, it can be suppressed. In addition, each of the upper register and the lower register of the register pair can be used for different processing (for example, one is used by the ADDTWOONE instruction and the other is used as a counter for counting the number of loop processes). Limited registers can be used effectively.

  In addition, the main control unit includes a first value and a second value stored at two consecutive addresses based on a predetermined address indicated by a value stored in the second register (for example, an HL register). Are transferred to the first register (for example, C register) and the third register (for example, B register) of the plurality of registers, respectively, for example, a predetermined second instruction (for example, “INCTENSOU BC, (HL ) "Instruction), and after executing the predetermined second instruction, the predetermined instruction may be executed.

  With such a configuration, one of the values stored in two consecutive addresses is added to the first register, and a value indicating an address related to a predetermined address is set in the first register. The following processing can be performed, and the program capacity may be reduced.

  Further, the main control unit executes a predetermined determination process (for example, as shown in steps S <b> 1110 to S <b> 1111) from a B register (third register) after executing the predetermined second instruction. The value stored in the predetermined storage area) is subtracted to determine whether or not carry occurs, and the result of the predetermined determination process is a predetermined value (for example, carry occurs) The predetermined command may be performed.

  With such a configuration, when the result of the predetermined determination process is a predetermined value, the next process can be performed in a state where a value indicating an address related to the predetermined address is set in the first register, The program capacity may be reduced.

  Further, the main control unit may execute the predetermined second instruction and the predetermined determination process again after executing the predetermined instruction (for example, executing the INCENSOOU instruction in step S1109, After the ADDTWOONE instruction is executed in step S1112, the INCENSOU instruction is executed again in step S1114, and a specific value is subtracted from the B register in step S1116 to determine whether or not a carry occurs.

  With such a configuration, for example, the second table address of the two-stage lottery can be set, the program of the two-stage lottery can be made easy to see, and the occurrence of coding errors and bugs can be suppressed in some cases. .

  Further, the pachinko machine 100 (or slot machine 1100) according to the present embodiment includes a main control unit (for example, the main control unit 300 (or the main control unit 1300)) having a CPU for performing game control, and the main control unit. A sub-control unit (for example, the first sub-control unit 400, the second sub-control unit 500 (or the first sub-control unit 1400, the second sub-control unit 1500)) that controls the production of the game based on the game control The CPU includes a predetermined flag (for example, Z flag, SZ flag), and the main control unit is executed between the first process and the second process. A third process for changing the content of the flag, which was the first content in the first process, to the second content before the start of the second process, The second process is the result of the execution of the third process. A process performed when the result of the second does not refer to the flag changes to the content process (e.g., CPRT instruction, CPJR instruction) is a gaming table which is a.

  According to the pachinko machine 100 (or the slot machine 1100) according to the present embodiment, it is possible to eliminate the relationship between the change in the flag contents and the flow of program execution, making it difficult to analyze the program and altering the illegal program. Can be prevented in advance. For this reason, stable game control can be performed and the fairness of the game can be ensured.

  The third process may be a process that does not refer to the flag that is the first content.

  With such a configuration, it is possible to eliminate the relationship between the change in the flag contents and the flow of program execution, making it difficult to analyze the program and preventing unauthorized alteration of the program in some cases. For this reason, stable game control can be performed and the fairness of the game can be ensured.

  Further, the pachinko machine 100 (or slot machine 1100) according to the present embodiment includes a main control unit (for example, the main control unit 300 (or the main control unit 1300)) having a CPU for performing game control, and the main control unit. A sub-control unit (for example, the first sub-control unit 400, the second sub-control unit 500 (or the first sub-control unit 1400, the second sub-control unit 1500)) that controls the production of the game based on the game control The CPU includes instructions (for example, RES instruction, RST instruction) in which access to a predetermined area of storage means (for example, ROM 306, RAM 308, register, program counter) is restricted. The gaming machine is characterized in that the command is executed in the game control.

  According to the pachinko machine 100 (or the slot machine 1100) according to the present embodiment, since access to a predetermined area can be prohibited, the predetermined area can be protected, and the content of the predetermined area changes to an unexpected value. In some cases, it may be possible to prevent such a situation from occurring.

  The instruction may be an instruction that can access a predetermined specific area among the areas excluding the predetermined area.

  With such a configuration, it is possible to read and write the contents of the specific area at the same time while prohibiting access to the predetermined area, so that the contents of the predetermined area can be protected and the degree of freedom in program design is reduced. There is nothing.

  The CPU may further include an instruction capable of accessing the predetermined area. With such a configuration, it is possible to read and write the contents of the specific area at the same time while prohibiting access to the predetermined area, so that the contents of the predetermined area can be protected and the degree of freedom in program design is reduced. There is nothing.

  Further, if the instruction is configured not to be able to jump to a predetermined area of the storage means, a malicious program is incorporated and jumped to the top address of the user program (the user program is started from the top address and illegally initialized). In some cases, it is possible to prevent such actions.

  The game machine according to the present invention is not limited to the pachinko machine 100 and the slot machine 1100 described above. Therefore, for example, in the above-described embodiment, an example of a little endian CPU is shown, but the present invention can also be applied to a big endian CPU. Further, the present invention is not limited to an 8-bit CPU, and can be applied to a 16-bit CPU, a 32-bit CPU, and the like. Further, the name of the instruction is not limited to the name shown in the above embodiment.

  Moreover, although the example applied to CPU304 of the main control part 300 (or CPU1304 of the main control part 1300) was shown, you may apply to CPU of another control part. Further, the storage means is not limited to ROM and RAM, and other storage means may be applied.

  Also, as shown in FIG. 74 (a), “a bill is inserted into the bill insertion slot 2002, a lottery is executed based on the bet 2004 and start 2006 operation, and the lottery result is displayed on the lottery result display device 2008. When the number of coins is added to the number of remaining credits and cashout 2009 is selected, the present invention is applied to a casino machine 2000 that issues a receipt in which a code corresponding to the number of remaining credits is issued from the receipt issuing machine 2010. May be. Further, it may be suitable for an arrange ball game machine, a ball ball game machine, a smart ball, or the like.

  Further, as shown in FIG. 4B, the mobile phone 3000 having a control unit including the configuration of the present invention is provided, and as shown in FIG. 5C, the control unit including the configuration of the present invention is provided. The present invention may be applied to a portable game machine 4000 and a home video game machine 5000 including a control unit including the configuration of the present invention.

  More specifically, the cellular phone 3000 in FIG. 5B stores an operation unit operated by a player, a data acquisition unit that acquires data related to the game through a mobile phone line, and the acquired data related to the game. A storage unit, and a control unit including the configuration of the present invention, which controls the game based on the data stored in the storage unit and the operation of the operation unit.

  Further, the portable game machine 4000 in FIG. 10C includes an operation unit operated by the player, a data acquisition unit that acquires data related to the game from a predetermined storage medium (DVD or the like), and acquired data related to the game. And a control unit including the configuration of the present invention, which controls the game based on the data stored in the storage unit and the operation of the operation unit.

  In addition, the home video game machine 5000 in FIG. 5C includes an operation unit operated by a player, a data acquisition unit that acquires data related to the game from a predetermined storage medium (DVD or the like), and an acquired game. A storage unit that stores data, and a control unit including the configuration of the present invention that controls the game based on the data stored in the storage unit and the operation of the operation unit are provided.

  Furthermore, as shown in FIG. 6D, the present invention may be applied to a data server 6000 including a control unit including the configuration of the present invention. In some cases, the program code including the configuration of the present invention is downloaded from the data server 6000 to the home video game machine 5000 shown in FIG. The present invention can also be applied to a game program in which the operation of a real machine such as a pachinko machine is simulated for a home game machine.

In addition, the gaming machine according to the present invention can be applied to an enclosed gaming machine. In addition, the main control unit, the first sub control unit, and the second sub control unit may be configured as a single chip, or the main control unit and the first sub control unit may be configured to allow bidirectional communication. Good. Moreover, while enabling bidirectional communication between the main control unit and the first sub control unit, communication from the first sub control unit to the second sub control unit may be one-way communication.
<Embodiment 3>

Next, a pachinko machine according to Embodiment 3 of the present invention will be described in detail with reference to the drawings.
<Example of basic circuit configuration of main controller>

  Next, a configuration example of the basic circuit 302 of the main control unit 300 will be described with reference to FIG. This figure is a diagram showing an example of the configuration of the basic circuit 302 when the microprocessor 3000 is used.

  The microprocessor 3000 shown in FIG. 75 corresponds to an example of the electric control unit according to the present invention, and has the function of the basic circuit 302 shown in FIG. 4 and the function of the random number generation circuit 318 shown in FIG. . 75, parts corresponding to the configuration shown in FIG. 4 are described with the same reference numerals used in FIG.

  75 includes a CPU 304, a ROM (built-in ROM) 306, a RAM (built-in RAM) 308, an external bus control circuit 3101, a parallel input port 3102, an address decoding circuit 3103, a timer circuit 311, a counter circuit 312, In addition to the reset control circuit 314, an interrupt control circuit 3100, a clock circuit 3200, and a random number generation circuit 318 are provided, all of which are connected to each other via an internal bus 3300. The built-in ROM 306 corresponds to an example of a storage unit. Note that the external bus control circuit 3101, parallel input port 3102, and address decode circuit 3103 correspond to the I / O 310 in FIG. 4.

  Hereinafter, details of each of the above-described units will be described. First, the CPU 304, the ROM 306, and the RAM 308 are as described with reference to FIG. The external bus control circuit 3101 includes an IO request terminal (XIORQ terminal), a memory request terminal (XMREQ terminal), a read signal terminal (XRD terminal), a write signal terminal (XWR terminal), a 16-bit width address output terminal (A0 terminal to A15 terminal) and data input / output terminals (D0 terminal to D7 terminal) which are input / output terminals having an 8-bit width. In this embodiment, the data input / output terminals (D0 terminal to D7 terminal) are used for data output to the drive circuits 324, 326, 330, and 334 shown in FIG. 4 and data input from the peripheral control circuits. It has been. The data input / output destinations of the data input / output terminals (D0 terminal to D7 terminal) are the address signal output from the address output terminals (A0 terminal to A15 terminal) and the chip select signal output from the address decode circuit 3103. Use to switch.

  The parallel input port 3102 has four input terminals (P0 terminal to P3 terminal). These input terminals (P0 terminal to P3 terminal) are connected to the sensor circuit 322 shown in FIG. 4 and are used to input signals from the sensor circuit 322. In this embodiment, a signal from a sphere detection sensor that detects a ball entering the first special figure start port 230 is input to the P0 terminal, and a ball detection sensor that detects a ball entering the second special figure start port 232 is used. Is input to the P1 terminal, and a signal from a ball detection sensor that detects a ball entering the normal start port 228 is input to the P2 terminal. The signal from the sensor circuit 322 is output to the random number generation circuit 318 as a latch signal for causing the CPU 304 to acquire a random number generated by the random number generation circuit 318. This operation will be described later.

  The address decoding circuit 3103 has 14 output terminals (XCS0 terminal to XCS13 terminal). The output terminals (XCS0 terminal to XCS13 terminal) are connected to a peripheral control circuit outside the microprocessor 3000, and data output from the data input / output terminals (D0 terminal to D7 terminal) of the external bus control circuit 3101. Is used to output a chip select signal or the like for switching the transmission destination.

  The timer circuit 311 is used for time measurement. The timer circuit 311 outputs a timeout signal to the counter circuit 312 when the set measurement time has passed. On the other hand, the counter circuit 312 is used for measuring the number of rises (or falls) of various signals. In addition to the system clock of the microprocessor 3000, the counter circuit measures the timeout signal from the timer circuit, the memory read / write signal, the memory request signal, the external input / output signal, the interrupt response signal, and the like. can do.

  The reset control circuit 314 has two terminals, a system reset input terminal (XSRST terminal) and a reset output terminal (XRSTO terminal). This system reset input terminal (XSRST terminal) is connected to the voltage monitoring circuit 338. When a system reset signal (for example, a signal at L level for a predetermined time) is input from the system reset input terminal (XSRST terminal), the reset control circuit 314 outputs the system reset signal to the internal circuit of the microprocessor 3000. At the same time, a reset signal (for example, a rising signal from L level to H level) is output from the reset output terminal (XRSTO terminal) to the peripheral control circuit outside the microprocessor 3000. In this case, the microprocessor 3000 executes a process called system reset and initializes each circuit. An example in which this system reset is executed is when the power is turned on. This system reset will be described later.

  Further, the reset control circuit 314 includes a watch dog timer (WDT) 3141 (corresponding to an example of a return instruction unit), and a travel prohibition circuit 3142 outside the designated area. When the WDT 3141 times out or when the CPU 304 refers to an address outside the predetermined range (running outside the designated area), the reset control circuit 314 sends a system reset signal to the internal circuit of the microprocessor 3000 and One of the user reset signals is output. Whether to output the system reset signal or the user reset signal depends on the setting of the program management area (details will be described later) in the ROM 306. A reset signal is output from a reset output terminal (XRSTO terminal) to the peripheral control circuit outside the microprocessor 3000.

  The microprocessor 3000 can execute either the system reset or the process called user reset according to the setting. In the user reset, each circuit is initialized as necessary. This user reset will be described later.

  The traveling outside the designated area means that the program is operating unexpectedly. In this case, the CPU 304 operates with a code that should not be handled as a program. Such a situation may be caused by some sort of fraud other than a so-called runaway state due to a program mistake. In this case, normal operation can be restored by the system reset process described above. In addition, when the WDT 3141 times out, there are a runaway state due to a program error, a case where the CPU 304 cannot perform the originally designed operation due to a voltage drop, and the like. Also in this case, it is possible to return to normal operation by the above-described system reset processing.

  The interrupt control circuit 3100 generates an interrupt in order to appropriately execute a process according to a change in external input or internal state. This interrupt process includes, for example, a process executed when an external input (signal from a sensor) is received. In this embodiment, even when the random number generation circuit 318 receives a latch signal for acquiring a random number, it can execute interrupt processing (generate an interrupt). The interrupt control circuit 3100 includes an internal information register 3101. The internal information register 3101 includes an abnormality in the cycle of the external clock (count clock) that determines the random number update cycle by the random number generation circuit 318, and update of the random number. In addition, information on the reset factor that occurred immediately before is stored. The internal information register 3101 corresponds to an example of an abnormality detection information holding unit.

  The clock circuit 3200 has an external clock (24 MHz in this example) input from an external clock input terminal (EX terminal) from the crystal oscillator 316b shown in FIG. Clock) is divided by a predetermined frequency division ratio (1/2 in this example), and the divided system clock (12 MHz clock in this example) is supplied to each circuit in the microprocessor 3000. The system clock is output to a peripheral control circuit outside the microprocessor 3000 via a system clock output terminal (CLKO terminal).

  The random number generation circuit 318 uses the clock signal (count clock) for updating the random number and holds the updated random number in the random number register when the random number latch signal is received. In the present embodiment, the external clock signal input from the crystal oscillator 316a via the external clock input terminal (RCK terminal) is divided by a predetermined frequency division ratio (1/2 in this example) and is used as this count clock. Although it is used, a clock signal in the microprocessor 3000 can also be used. In this case, the crystal oscillator 316a is not necessary. The value held in the random number register can be read and used as a random number. Note that when a random number is read from the random number register, an allowable state in which the random number register is allowed to latch the next random number can be set. Details of the random number generation circuit 318 will be described later.

  Next, a processing flow when reset is executed will be described with reference to FIG. This figure is a flowchart showing the flow of reset. This flowchart is a process executed by each circuit of the microprocessor 3000 when a system reset signal is input to the reset control circuit 314, when the WDT 3141 times out, or when traveling outside the designated area is detected. .

  In the first step SH01, it is determined whether or not the reset operation to be executed is a system reset operation. There are two reset operations executed by the microprocessor 3000: a system reset operation and a user reset operation. Here, when the system reset operation is executed, the process proceeds to step SH03. This system reset operation corresponds to an example of a return process according to the present invention. When executing a reset operation that is not a system reset operation, that is, a user reset operation, the process proceeds to step SH11.

  In step SH03, a first internal circuit initialization process is executed. This first internal circuit initialization process is performed by the CPU 304 core and built-in registers (timer circuit 311, counter circuit 312, parallel input port 3102, RAM 308 access protect register, interrupt control circuit 3100, and random number generation circuit 318). Initialize the value. When the first internal circuit initialization process is completed, the process proceeds to step SH05.

  In step SH05, a security check process is executed. In this security check process, it is determined whether or not the value calculated based on the user program matches the value representing the authentication code stored in the program management area of the ROM 306. That is, recalculation of whether or not the authentication code is correct is performed. The user program here corresponds to an example of the contents stored in the storage unit (internal ROM 306) according to the present invention, and the authentication code stored in the program management area of the internal ROM 306 is the predetermined authentication according to the present invention. This corresponds to an example of information. If the authentication code is correct, the process proceeds to step SH07. If not, the operation of the CPU 304 is stopped. In the gaming machine of the present embodiment, the security check is performed in this way, so that stable control can be performed by the gaming machine.

  In step SH07, a fixed extension process is executed. In this fixed extension process, the security mode is extended for a preset fixed time (for example, set using 0 to 2 bits of the security time setting in the program management area of the ROM 306). For example, when n is the time set in the program management area and the system clock is SCLK, the time is extended by 3n × 2 ^ 24 / SCLK seconds. A reset signal is output from the XRSTO terminal when this extended time has elapsed. Thereafter, the process proceeds to step SH09.

  In step SH09, a random extension process is executed. In this random extension process, the security mode is extended by a random time selected in advance (for example, setting using 3 to 4 bits of security time setting in the management area). For example, when the short mode is set, the time is extended from 0 to Sμ seconds, when the middle mode is set, 0 to Mμ seconds, and when the long mode is set, the time is extended from 0 to Lμ seconds ( S <M <L). When this process ends, the process shifts to the user mode, and the CPU 304 starts the process from address 0000H in the memory map. In the present embodiment, the main process of the main control unit 300 is started.

On the other hand, in step SH11 which proceeds when executing the user reset operation in step SH01, the second internal circuit initialization process is executed. This second internal circuit initialization processing is performed by using internal registers (timer circuit 311, counter circuit 312, parallel input port 3102, RAM 308 access protect register, interrupt control circuit 3100) excluding the registers for controlling the core of CPU 304 and random number generation circuit 318. ) Value is initialized. That is, in the second internal circuit initialization process, the value of the register that controls the random number generation circuit 318 is maintained in the state before the reset. When the second internal circuit initialization process is completed, the process shifts to the user mode, and the CPU 304 starts the process from address 0000H in the memory map. In the present embodiment, the main process of the main control unit 300 is started.
<Random number generation circuit>

  Next, details of the random number generation circuit 318 of the microprocessor 3000 shown in FIG. 75 will be described with reference to FIG. This figure is an internal block diagram of the random number generation circuit 318 shown in FIG.

  The random number generation circuit 318 includes four random number generation channels CH1 to CH4 that generate different random numbers. Since the internal configuration of each channel circuit is the same, FIG. 77 shows one random number generation channel CH1, and the remaining random number generation channels CH2 to CH4 are simplified in illustration. In the following description, the random number generation circuit 318 will be described focusing on the random number generation channel CH1.

  The random number generation circuit 318 includes an initial setting register 3181, a frequency monitoring circuit 3182, a random number updating circuit 3183, a random number monitoring circuit 3184, a noise filter 3185, a soft latch register 3186, a latch selection register 3187, and a random number register 3188. And a random number latch flag register 3189 and a random number interrupt control register 3180. The frequency monitoring circuit 3182 and the random number monitoring circuit 3184 correspond to an example of update abnormality detection means.

  The initial setting register 3181 stores clock selection information for determining which of the external clock signal from the RCK terminal and the system clock (internal clock signal) to use in the random number update circuit 3183 in the program management area. Set based on information. The external clock signal and the system clock (internal clock signal) from the RCK terminal are input to a multiplexer provided in front of the random number update circuit 3183. The initial setting register 3181 inputs the update clock selection signal to the multiplexer according to the clock selection information, so that the clock signal selected by the update clock selection signal is input to the random number update circuit 3183. When an external clock signal is selected, a clock signal divided by a predetermined frequency division ratio (in this example, 1/2) is input to the random number update circuit 3183. Note that the frequency-divided clock signal cannot be used when the frequency is not lower than that of the internal clock. In the present embodiment, the description will be continued assuming that the external clock signal is selected.

  The frequency monitoring circuit 3182 monitors the period of the internal clock signal and the external clock signal, and outputs information indicating that the clock signal is abnormal to the internal information register 3101 when the period is not constant.

  The random number update circuit 3183 receives the clock signal selected by the initial setting register 3181 and updates the random number according to the cycle of the clock signal. The updated random number value is output to the random number monitoring circuit 3184 and the random number register 3188, respectively. Details of the random number update circuit 3183 will be described later with reference to FIGS. 79 to 82.

  The update of the random number value may be started (automatic start) when the mode is changed to the above-described user mode, or started when the maximum random number value is set in the random number register 3188 by the user program (manual start). ), Or may be configured so that it cannot be manually started when the automatic start is performed (a maximum value cannot be set). Further, the maximum value of the random number may be set individually in the random number generation channels CH1 to CH4. Further, it may be configured such that the update of the random number value cannot be stopped in the case of automatic start, and the update of the random number value can be manually stopped in the case of manual start. In the case of manual start, a register for instructing start, a register for instructing stop of update, and a register for instructing restart of update may be provided separately.

  In addition, one of the 16-bit random value and the 8-bit random value may be configured so that an initial value can be set, and the other may be configured so that an initial value cannot be set, and whether or not the random number is normally updated. One may be monitored and the other may not be monitored. In addition, the initial value of the random number value may be different between an internal reset and an external reset described later (for example, the initial value at the time of internal reset is 33H, and the initial value at the time of external reset is CCH). In the initial setting of the user program or the like, the type of reset may be determined based on the initial value of the random number value, and processing according to the type of reset may be executed.

  Based on the input from the random number update circuit 3183, the random number monitoring circuit 3184 monitors whether or not the random number has been updated normally. If there is an abnormality in updating the random number, information indicating that there is an abnormality in updating the random number is output to the internal information register 3101.

  In the above description, the frequency monitoring circuit 3182 and the random number monitoring circuit 3184 are provided inside the random number generation circuit 318, but may be provided outside the random number generation circuit 318. In the above description, the frequency monitoring circuit 3182 and the random number monitoring circuit 3184 are provided separately from the random number update circuit 3183. However, these circuits may be provided inside the random number update circuit 3183.

  Input from the P0 terminal to P3 terminal is input to the noise filter 3185 as a latch signal via the parallel input port 3102. In FIG. 77, the P3 terminal and the circuit connected to the P3 terminal are not shown. As described above, a signal from a ball detection sensor that detects a ball entering the first special figure start port 230 is input to the P0 terminal, and a ball entering the second special figure start port 232 is input to the P1 terminal. A signal from a sphere detection sensor to be detected is input, and a signal from a sphere detection sensor that detects a ball entering the normal start port 228 is input to the P2 terminal. Further, the clock signal selected by the initial setting register 3181 is input to the noise filter 3185. Using this clock signal, the noise generated at the inputs from the P0 to P3 terminals is removed, and then the latch signal is detected. When this latch signal is detected, a hard latch signal is output to a multiplexer provided in front of the random number register 3188. Details of the noise removal will be described later with reference to FIG.

  Information indicating that a random number is latched from the random number register 3188 is appropriately set in the soft latch register 3186 according to an instruction from the CPU 304. This information is output as a soft latch signal to a multiplexer provided in front of the random number register 3188.

  The latch selection register 3187 has information indicating which of the hard latch signal and the soft latch signal is output from the multiplexer provided in front of the random number register 3188, that is, which latch signal is input to the random number register 3188. These are set as appropriate according to instructions from the CPU 304. By setting this information, a random number can be obtained by appropriately using a hard latch signal and a soft latch signal.

  Three signals are input to the random number register 3188. The first signal is a signal representing a random number output from the random number update circuit 3183. The second signal is a random number latch signal (a signal set by the latch selection register 3187 out of the hard latch signal and the soft latch signal) output from the multiplexer provided in front. The third signal is a read signal indicating random number reading.

  A signal indicating the random number updated by the random number update circuit 3183 is always input to the random number register 3188. Here, when a random number latch signal is input, a random number at this input timing is latched (held) in the random number register 3188. At this time, a set signal indicating that the random number is latched is output from the random number register 3188 to the random number latch flag register 3189. At this time, the CPU 304 can acquire the latched random number. Note that when a random number is acquired by the CPU 304, a read signal is input to the random number register 3188. When a new random number latch signal is input by this signal, an allowable state is entered in which the random number is allowed to be latched. In other words, once the random number is latched, it becomes an unacceptable state in which the random number cannot be newly latched until the read signal is inputted. Note that since the latched random number is held even when a read signal is input, the CPU 304 can acquire the latched random number any number of times at the same latched timing. With this configuration, the influence of chattering in the sensor circuit that outputs the random number latch signal can be suppressed. A clear signal indicating that the read signal has been input is output to the random number latch flag register 3189. As shown in FIG. 77, since there are a plurality of random number registers 3188, random numbers generated from the same random number update circuit can be acquired at various timings.

  The random number latch flag register 3189 stores information indicating whether or not a random number is latched in the random number register 3188. The random number latch flag register 3189 is automatically cleared when the random number latched in the random number register 3188 (all or part of a 16-bit random number or all or part of an 8-bit random number) is read. You may comprise so that it may clear by CPU.

  In the random number random number interrupt control register 3180, information indicating whether or not the interrupt control circuit generates an interrupt when a random number is held in the random number register 3188 is set. This information can be set for each random number register 3188. For example, when the random number of the random number generation channel CH1 is latched by entering the first special figure starting port 230, an interrupt is generated, and by entering the second special figure starting port 232, the random number generating channel CH2 is set. If a random number is latched, it can be set such that no interrupt is generated.

  In the present embodiment, using the random number generation circuit 318 described above, random numbers are acquired at the timing when the ball enters each of the general map start port 282, the first special figure start port 230, and the second special diagram start port 232. Note that the program can be executed so that the CPU 304 can acquire a random number at an arbitrary timing. Further, independent random numbers can be acquired using different random number generation channels, and the maximum value of the random number generation range can be set for each channel.

  In the present embodiment, the example in which the random number generation range can be changed for each individual channel and a predetermined maximum value (for example, 65535) is applied when the range is not set has been described. For example, when changing the random number generation range, the configuration may be required to set the random number generation range for all channels.

  In addition, the random number acquired at the timing of entering the general figure starting port 282 is used as a general figure winning random number described later. In addition, the random number acquired at the timing of entering the first special figure starting port 230 is counted up (down) by processing (for example, a circuit different from the random number generation circuit (for example, the basic circuit 302 or the counter circuit 312)). The value is added (subtracted) to the random number, etc.) and used as a special figure 1 winning random number described later. Furthermore, the random number acquired at the timing of entering the second special figure starting port 232 is processed and used as a special figure 2 winning random number described later.

  The random number processing is not limited to the random number acquired at the timing of entering the first special figure starting port 230 and the second special figure starting port 232, but other triggers (for example, entering the normal figure starting port 282). You may perform with respect to the random number acquired by the timing of balling etc.). Furthermore, when the maximum value of the random number generation range described above is set, processing corresponding to the set maximum value (for example, a process of adding a value not exceeding the maximum value to the random number) may be performed.

  In addition, although it is not always necessary to perform random number processing, it is effective to prevent random numbers from being processed. For example, when the CPU 304 monitors whether or not the random number after processing has been updated, it cannot be accurately determined whether or not the random number is updated normally in the random number generation circuit 318. Thus, when processing random numbers, monitoring of update of random numbers by the random number monitoring circuit 3184 described above works more effectively.

  Next, the operation of the noise filter 3185 will be described with reference to FIG. This figure is a diagram showing an example of processing by the noise filter 3185 shown in FIG.

  As described above, the noise filter 3185 receives input from the P0 terminal to P3 terminal as a latch signal via the parallel input port 3102 and receives the clock signal selected by the initial setting register 3181. For example, as shown in FIG. 78, the noise filter 3185 receives the input signal from the P0 terminal to the P3 terminal until the down edge of the clock signal (the falling signal from the H level to the L level) is continuously input four times. If H is at the H level, a hardware latch signal is output. If a hardware latch signal is simply output based on only the rising and falling edges of the signal, the hardware latch signal is output even when noise occurs. For this reason, the hardware latch signal is not output due to noise by detecting the sensor signal for a certain period using the clock signal as described above.

  In the above description, the example in which the hard latch signal is output by the input from the P0 terminal to the P3 terminal has been described. . In this case, the random number is latched not by the hard latch signal but by the soft latch signal output from the soft latch register 3186. In this case, the CPU 304 executes processing similar to the processing by the noise filter. That is, it is determined whether or not the input from the P0 terminal to the P3 terminal has continued for a predetermined period. Thereafter, the soft latch register 3186 is set so as to output a soft latch signal.

  Next, details of the random number update circuit 3183 shown in FIG. 77 will be described with reference to FIG. This figure shows the details of the random number update circuit 3183 shown in FIG.

  The random number update circuit 3183 shown in FIG. 79A includes a counter circuit 3183a, a start value selection circuit 3183b, and a maximum value setting register 3183c. 77 shows that either the external clock signal or the internal clock signal is input to the random number update circuit 3183 as an update clock signal for updating the random number, the random number shown in FIG. Maximum value data is further input to the update circuit 3183 from the CPU 304.

  A random number (random number data) is output from the counter circuit 3183a. The initial value of this random number is set in the start value selection circuit 3183b. The initial value is set to one of a fixed value (for example, 0), a value based on the ID number of the microprocessor 3000 stored in the program management area, and a value lottery within the random number generation range. Is done.

  The counter circuit 3183a is provided with a counter in which 1 is added for each clock of the update clock signal, and a value obtained by adding the initial value of the random number input from the start value selection circuit 3183b to the value of this counter is provided. Output as a random number.

  The maximum value of the random number output from the counter circuit 3183a is set in the maximum value setting register 3183c. Note that the maximum value of the random number is set in the maximum value setting register 3183c in accordance with an instruction from the CPU 304. FIG. 79 (b) shows a 16-bit register in which this maximum value is set. The initial value when there is no instruction for setting the maximum value from the CPU 304 is FFFFH (65535). Instead of the maximum value setting register 3183c, for example, an area for setting a maximum value may be provided in the program management area of the ROM 306, and the set maximum value may be referred to.

  When the output random number exceeds the maximum value, the counter circuit 3183a subtracts a value obtained by adding 1 to the maximum value, and then outputs this value as a random number. For example, in the case where the maximum value is 65535, if the value obtained by adding the initial value and the counter value is updated in the order of 65534, 65535, 65536, and 65537, the output random number is 65534, 65535, 0 (655536). (65535 + 1)), 1 (65537- (65535 + 1)). That is, when the maximum value is exceeded, the output random number returns to zero.

  When the value of the counter provided in the counter circuit 3183a reaches the maximum value set in the maximum value register 3183c, the counter value is cleared to 0, and the counter circuit 3183a to the start value selection circuit 3183b. A signal (circular signal) indicating that the output of the random number has been completed is output. In the start value selection circuit 3183b that has received this round signal, the initial value of the random number is updated. When the initial value updated at this time exceeds the maximum value of the random number set in the maximum value setting register 3183c, for example, a fixed value can be used, or it can be set after multiplying the current maximum value of the random number once. By using a value divided by the maximum value (65535) of the random number generation range, a value that does not exceed the maximum random number value (a value within the random number generation range) is reset as an initial value. Of course, a value within the random number generation range may be set as an initial value by using this resetting method from the beginning.

  In the present embodiment, the maximum value set in the maximum value setting register 3183c is automatically updated when the output from the counter circuit 3183a completes a cycle, but for example, when an update command from the CPU 304 is received. It may be updated.

  Here, the range of the above random number generation will be described with reference to FIGS. FIG. 80 is a diagram illustrating a range of random numbers output when the maximum value of the random number generation range is not set (default state). FIG. 81 is a diagram showing a range of random numbers output when a maximum value different from that in FIG. 80 is set.

  First, FIG. 80 (a) will explain the situation in the nth cycle (immediately after the (n-1) th round signal is output). FIG. 80A shows a random number generation range of 0 to 65535. Further, the initial value of the output random number is shown as the start value (X).

  A random number is updated and output from the random number update circuit 3183 for each clock of the update clock. More specifically, the start value (X) is output first, and then the random numbers updated in the order of X + 1 and X + 2 are output every clock thereafter. When the value of the random number reaches 65535, which is the maximum value of the random number generation range, the random number output next is returned to 0 by the above-described processing. Thereafter, the random numbers updated in the order of 1, 2 are output, and when the X-1 is output, this random number generation range is completed. At this time, the counter value of the counter circuit 3183a in the random number update circuit 3183 is the same as the maximum value. The start value selection circuit 3183b outputs a signal (round signal) indicating that the random number output has rounded.

  Subsequently, when 1 clock is input, the output of the random number update circuit 3183 enters the (n + 1) period (immediately after the n-th round signal is output). The situation in the (n + 1) th cycle will be described with reference to FIG. First, the counter value of the counter circuit 3183a in the random number update circuit 3183 is cleared to zero. In the start value selection circuit 3183b, a new initial value is set. FIG. 80B shows this new initial value as the start value (X ′). A random number is output in the same flow as the flow described above based on the new initial value and the counter value of the counter circuit 3183a.

  Next, in FIG. 81 (a), the situation in the nth cycle (immediately after the (n-1) th round signal is output) when the maximum value smaller than the maximum value of the random number generation range shown in FIG. 80 is set. Will be described. FIG. 81 (a) shows a random number generation range that is narrower than the random number generation range shown in FIG. 80 (a) by a set maximum value from 0 to 65535. Note that the range of random numbers that are not output is indicated by a left-down hatching. Further, the initial value of the output random number is shown as the start value (Y).

  Similar to the situation described with reference to FIG. 80, the random number update circuit 3183 first outputs a start value (Y), and then outputs random numbers updated in order of Y + 1 and Y + 2 every clock. . When the value of the random number reaches the set maximum value, the random number output next is returned to 0 by the above-described processing. That is, random numbers in the range indicated by the left-down hatching are not output. Thereafter, the random numbers updated in the order of 1, 2 are output, and when the Y-1 is output, this random number generation range is completed. At this time, the counter value of the counter circuit 3183a in the random number update circuit 3183 is the same as the set maximum value. The start value selection circuit 3183b outputs a signal (round signal) indicating that the random number output has rounded.

  Subsequently, when 1 clock is input, the output of the random number update circuit 3183 enters the (n + 1) period (immediately after the n-th round signal is output). The situation in the (n + 1) th cycle will be described with reference to FIG. As in the case described with reference to FIG. 80B, the counter value of the counter circuit 3183a in the random number update circuit 3183 is cleared to zero. In the start value selection circuit 3183b, a new initial value is set. FIG. 81 (b) shows this new initial value as the start value (Y ′). A random number is output in the same flow as the flow described above based on the new initial value and the counter value of the counter circuit 3183a.

  In addition to appropriately setting the maximum value of the random number generation channel as described above, for example, the maximum random number value is 65535 in one random number generation channel, but the maximum random number value is 255 in another random number generation channel. For example, the random number generation range may be different for each channel. In this case, the channel may be selected according to the required random number generation range. In this case, the capacity of the maximum value setting register can be reduced and the processing load for setting the maximum value can be reduced. Furthermore, even if a plurality of maximum values that can be set in advance are set and an appropriate maximum value is selected and set from these, it is possible to reduce the capacity of the maximum value setting register and to reduce the processing load for maximum value setting Can be reduced.

  The random number output from the random number update circuit 3183 has been described above. Hereinafter, a modification of the random number update circuit 3183 will be described with reference to FIG. This figure is a diagram showing a range in which random numbers can be acquired in a random number generation range in which a maximum value and a minimum value are set.

  In the example of FIGS. 79 to 81, the example in which the maximum value of the random number generation range is changed has been described. However, for example, the minimum value may be set. Further, a register for setting not only the maximum value but also the minimum value may be prepared, and as shown in FIG. 82A, the minimum value and the maximum value may be set to set the random number generation range. In addition, as shown in FIG. 82 (b), a plurality of random number generation ranges may be set. That is, any configuration can be used as long as the range of the output random number can be set. Further, in the above description, the example in which the output random number increases by 1 has been described for easy understanding, but other random number update methods may be used.

  Hereinafter, random numbers used in the game machine of this embodiment and main derivation sources will be described with reference to FIG. FIG. 2 is a table showing random number derivation sources used in the game machine of this embodiment. Each random number shown in this figure is used in a flowchart described later.

  First, the special figure 1 winning random numbers, the special figure 2 winning random numbers, and the universal winning random numbers are based on random numbers generated by the random number generation channels CH1 to CH4 of the random number generation circuit 318. This value is appropriately processed as necessary and used as these random numbers.

  The big hit special figure random number, the small hit special figure random number, and the lost special figure random number are generated in a main control unit timer interrupt process to be described later. That is, these random numbers are so-called software random numbers. Note that the initial value generating random numbers used when generating these random numbers are generated by the main control unit main process and the main control unit timer interrupt process.

  For the special figure fluctuation time determination random number and the normal figure fluctuation time determination random number, the value of the counter circuit 312 is used as a random number. In the count circuit 312 of this embodiment, in addition to the system clock of the microprocessor 3000, a timeout signal from the timer circuit, a memory read / write signal, a memory request signal, an external input / output signal, and the like can be used as counter targets. . Therefore, by combining these, a value having no regularity is derived and used for the above random number. The production random number is generated by the main control unit main process and the main control unit timer interrupt process.

  Next, details of the internal information register 3101 provided in the interrupt control circuit 3100 shown in FIG. 75 will be described with reference to FIG. As described above, the internal information register 3101 has an external clock (count clock) cycle abnormality that determines the random number update cycle by the random number generation circuit 318, an abnormality of the generated random number value, and a user reset that occurred immediately before. The reset factor information and the like are stored. The internal register 3101 includes a first internal information register, a second internal information register, and a third internal information register.

  FIG. 84 is a diagram for explaining the first internal information register prepared in the internal register 3101 of the interrupt control circuit 3100. FIG. 84A shows a range in which information indicating abnormality of the random number generation circuit 318 is stored in the first internal information register. This range is composed of 8 bits, and FIG. 84 (b) shows a table showing what information each bit represents.

  The CPU 304 checks the contents of the first internal information register every time a timer interrupt described later is executed (step S235a in FIG. 95). This content is used to determine whether or not to perform processing such as stopping the progress of a game when an abnormality occurs. For example, the present embodiment is configured such that the winning acceptance process is not executed when an abnormality is detected by the random number generation circuit 318 (see step S235c in FIG. 95 and FIG. 96). In addition, the ball may not be launched, the payout may not be performed, or the variation timer may not be subtracted. In particular, when there is an abnormality in random number update, there is a possibility that a large current is flowing through the random number update circuit 3183 (latch-up state). Good.

  Bit number 0 is a bit indicating an abnormality of the external clock (update clock) of the random number generation circuit 318. 0 indicates no abnormality and 1 indicates an abnormality. Bit numbers 1 to 4 are bits indicating an abnormality of the random number generated by the random number generation circuit 318 for each channel, where 0 indicates no abnormality and 1 indicates an abnormality. Bit numbers 5 to 7 are not used (fixed to 0).

  When the value of the first internal information register is 1, when read from the CPU 304, it is set (cleared) to 0. Since the internal information register is read by the CPU 304 at a time, if the value held in the first internal information register is set to 0 (cleared), the value is read after reading the value of the first internal information register to the CPU 304. You can discard the value. Further, as described above, when either system reset or user reset processing is executed, the internal information register is set (cleared) to 0 as in the case of reading from the CPU 304. It will be.

  As described above, how the abnormality of the random number generation circuit 318 is stored has been described, but information indicating the reset factor is also stored in the first internal information register as in this example. In the above description, the abnormality of the random number generation channel is represented for each channel by the bit numbers 1 to 4, but it may be represented by one bit whether an abnormality has occurred in any channel. (It may be common to all channels). In this embodiment, the internal information register 3101 is provided in the interrupt control circuit 3100, but may be provided in another circuit. The second internal information register and the third internal information register prepared in the internal register 3101 of the interrupt control circuit 3100 will be described later.

  Next, an example of abnormality detection in the frequency monitoring circuit 3182 shown in FIG. 77 will be described with reference to FIG. The figure shows an example of abnormality detection in the frequency monitoring circuit 3182. FIG. 85 shows, from the top, normal operation, abnormal operation example 1 (abnormal time 1), and abnormal operation example 2 (abnormal time 2), respectively. In these examples, in addition to the internal clock of the microprocessor 3000 and the external clock (RCK) input to the random number generation circuit 318, the ratio of the cycle of the internal clock to one cycle of the external clock is shown. In this detection operation, the ratio of the period between the external clock and the internal clock is monitored, and a case where this ratio changes is detected as an abnormality.

  In the normal example shown in FIG. 85 (a), a state in which the internal clock has 2.5 cycles continues during one cycle of the external clock. That is, since the ratio of the period between the external clock and the internal clock does not change, information indicating abnormality is not output.

  Next, in the operation example 1 (abnormal time 1) at the time of abnormality shown in FIG. When the state shown in FIG. 85 (a) is changed to the state shown in FIG. 85 (b), information indicating abnormality is output at this point.

  Next, at the beginning of operation example 2 (abnormal time 2) at the time of abnormality shown in FIG. 85 (c), there is shown a state in which the internal clock has 0.5 cycles in one cycle of the external clock. If the state shown in FIG. 85 (a) is changed to the first state shown in FIG. 85 (c), information indicating an abnormality is output at this point. Further, in FIG. 85 (c), the state in which the internal clock is 0.5 cycles in one cycle of the external clock continues, and the state in which the internal clock is 2.5 cycles in one cycle of the external clock continues. ing. Information indicating abnormality is output even when the ratio of the period changes.

  In the above example, when one of the external clock and the internal clock becomes abnormal, information indicating abnormality is output. That is, even when the internal clock is used as a random number update clock, an abnormality can be detected. If the ratio between the external clock and the internal clock is the same, no information indicating abnormality is output even if both frequencies are changed. In this case, for example, information indicating the frequency of the external clock or the internal clock can be stored in the program management area, and the abnormality of the external clock or the internal clock can be detected using this information. The method for detecting an abnormality of the update clock is not limited to the above-described method, and other methods may be adopted as long as the abnormality of the update clock cycle can be detected.

  Next, an example of abnormality detection in the random number monitoring circuit 3184 shown in FIG. 77 will be described with reference to FIG. This figure is a diagram showing an example of detecting an abnormality in the random number monitoring circuit 3184. In this detection example, the random numbers before and after the update are compared every time the random number is updated, and it is checked whether or not the same random number is generated. If the same random number is generated, information indicating abnormality is output. In the example of FIG. 86A, since the same random number is not generated before and after the update, information indicating abnormality is not output. On the other hand, in the example of FIG. 86 (b), the same random number is generated in the middle of the update (random number 4 is generated twice), and at this time (second time 4 is output) Will output information indicating anomalies. In the above example, the check is performed every time the random number is updated. However, the check may be performed every predetermined cycle longer than the random number update cycle.

  As described above, in the random number generation circuit 318, information indicating abnormality is output from the frequency monitoring circuit 3182 and the random number monitoring circuit 3184 to the internal information register 3101. Further, the value of the internal information register 3101 is read by the CPU 304 at every timer interruption.

  By monitoring the abnormality of the random number generation circuit 318 using both the frequency monitoring circuit 3182 and the random number monitoring circuit 3184 as described above, there is an abnormality in the update clock frequency, but there is no abnormality in updating the random number ( An abnormal state that cannot be detected only by the random number monitoring circuit 3184) and an abnormal state in which the frequency of the update clock is normal but there is an abnormality in updating the random number can be accurately grasped. Control can be stabilized.

  In conventional game machines, fraud may be made by targeting the random numbers used in the lottery so that it is easy to derive the lottery results advantageous to the player, making it difficult to ensure the fairness of the game. ing. However, according to the gaming table of the present embodiment, since the random number generation 318 described above can grasp the abnormality of the random number used in the lottery, it can be dealt with. Can be secured. Note that the frequency monitoring circuit 3182 and the random number monitoring circuit 3184 continuously monitor regardless of the information stored in the internal information register 3101.

  Here, the value of the internal information register 3101 is a cycle in which the random number generated by the random number generation circuit 318 makes a round (a period required to output all the values in the random number generation range once, hereinafter, a random cycle) 87), the problem that occurs in the configuration that is held and then cleared will be described with reference to FIG. This figure is a comparison of the cycle of the random number and the timer interrupt cycle. At the top of FIG. 87, a random number round cycle t1 longer than the timer interrupt cycle t4 shown at the bottom is shown. Also, in the second and third from the top in FIG. 87, random number round cycles t2 and t3 shorter than the timer interrupt cycle t4 are shown, respectively.

  As described above, the contents of the internal information register 3101 are confirmed for each timer interrupt. For example, when the random number round cycle is longer than the timer interrupt cycle t4 as in the random round cycle t1 shown in FIG. 87, this value can be read before the value held in the internal register 3101 is cleared. However, in this embodiment, since the maximum value of the random number generation range can be set, there may occur a situation where the random number cycle period is shortened accordingly. For example, when the round cycle of the random number is shorter than the timer interrupt cycle t4 as shown in the round trip cycles t2 and t3 of FIG. 87, this value may be cleared before reading the value held in the internal register 3101. That is, the CPU 304 may not be able to acquire information indicating abnormality.

In this embodiment, once the value of the internal information register 3101 is set, the value is held until this value is read. That is, this value is maintained regardless of whether it has returned to normal. Further, when the CPU 304 reads this value, the value of the read portion is cleared. For this reason, even if the round cycle of the random number has changed as described above, information indicating abnormality can be acquired from the internal information register 3101. If the abnormality continues after the value indicating abnormality is read, the value indicating abnormality is set again.
<Main control unit main processing>

  Next, main control unit main processing executed by the CPU 304 of the main control unit 300 shown in FIG. 4 will be described with reference to FIG. This figure is a flowchart showing the flow of main processing of the main control unit.

  This main control unit main process corresponds to the above-described process in the user mode, and is a process executed regardless of whether a system reset is applied or a user reset is applied. The RAM 308 of the main control unit 300 shown in FIG. 4 has a special jackpot special random number counter, a small bonus special figure 1 random counter, a lost special figure 1 random number counter, and a counter for these counters for the special figure 2. Is provided. In addition, the RAM 308 stores the number of holds shown in FIG. 1, the special figure 1 winning random number, the special jackpot special figure 1 random number, the small bonus special figure 1 random number, the lost special figure 1 random number, the special figure 1 hit determination result, The determination result of FIG. 1, the special figure 1 variation time, and the reservation number, random number, and result for the special figure 2 are stored. In addition, the RAM 308 has separate storage units that are divided into the maximum number of areas (four in this example) that can hold the start of the determination (lottery), separately for Special Figure 1 and Special Figure 2. Yes. As shown below, the reserved storage unit of Special Figure 1 determines Special Figure 1 winning random numbers, Special Bonus Figure 1 random numbers, Special Bonus Figure 1 random numbers, Loss Special Figure 1 random numbers, and Special Figure 1 variation time determination. The five random numbers for use are set as one set, and these five random numbers are stored for each area one by one in the winning order (holding order).

  As described above, the main control unit 300 shown in FIG. 4 includes the start signal output circuit (reset signal output circuit) 340 that outputs the start signal (reset signal) when the power is turned on. The CPU 304 of the basic circuit 302 to which this activation signal has been input performs reset start by a reset interrupt and executes main control unit main processing shown in FIG. 88 according to a control program stored in advance in the ROM 306.

  In step S101, initial setting 1 is performed. In this initial setting 1, the stack initial value is set to the stack pointer (SP) of the CPU 304 (temporary setting), the interrupt mask is set, the I / O 310 is initialized, various variables stored in the RAM 308 are initialized, and the like. .

  In step S103, whether or not the low voltage signal is ON, that is, the voltage value of the power supply that the voltage monitoring circuit 338 supplies to the main control unit 300 via the second sub control unit 500 by the power supply control unit 660. Is less than a predetermined value (9v in this embodiment), it is monitored whether or not a low voltage signal indicating that the voltage has dropped is output. When the low voltage signal is on (when the CPU 304 detects that the power is cut off), this step S103 is repeatedly executed, and when the low voltage signal is off (when the CPU 304 has not detected the power supply is cut off). Then, the process proceeds to step S105. Even if the predetermined value (9 V) is not yet reached immediately after the power is turned on, step S103 is repeatedly executed until the supply voltage becomes equal to or higher than the predetermined value. In step S105, initial setting 2 is performed.

  FIG. 89 is a flowchart showing a flow of initial setting 2 in the main process of the main control unit. First, in step S1051, setting processing relating to the counter circuit 312 such as processing for setting a maximum value and a numerical value for determining an update source in the counter circuit 312 is performed. Note that setting processing related to the timer circuit 311 is also performed, such as processing for setting a numerical value for determining a cycle for executing a main control unit timer interrupt processing, which will be described later, to the timer circuit 311 at regular intervals. In step S1052, a process of outputting a clear signal from the output port to the first sub control unit 400 is performed, and the process proceeds to step S1053. In step S1053, a random number generation circuit initial setting process is performed, and in step S1054, a setting for permitting writing to the RAM 308 is performed, and the initial setting 2 is completed.

  FIG. 90 is a flowchart showing the flow of the random number generation circuit initial setting process in step S1053. This random number generation circuit initial setting process is an initial setting process of the random number generation circuit 318 shown in FIG. 77 performed in the above-described user mode. First, a range of random numbers (random number generation range) is set (step S1053a), and the process proceeds to step S1053b. As described above, in the random number generation circuit 318 shown in FIG. 77, the maximum width of the generated random number is 0 to 65535, and this maximum width is the default of the random number generation range. Here, FIGS. 79 to 82 are used. As described in detail, the random number generation range can be set to a range different from the default. Since the main process of the main control unit shown in FIG. 88 is a process that is executed every time reset (system reset or user reset) is performed, the setting of the random number generation range is also performed every time reset is performed. By doing in this way, the problem by abnormality of the random number generation range mentioned later using FIG. 97, FIG. 98 can be prevented.

  In step S1053b, the random number register 3188 shown in FIG. 77 is read, and the read random number is discarded, and the process proceeds to step S1053c. By this processing, every time the random number generation range is reset, the random number register 3188 enters an allowable state that allows the random number to be latched. In this permissible state, even if a random number that may be abnormal remains in the random number register, it is possible to immediately update the random number, thereby preventing the use of a random number that may be abnormal.

  In the present embodiment, the random number generation circuit 318 generates a random number that is the basis of the special figure winning random number and the universal winning random number, but the output channel differs depending on the control state. That is, the random number that is the basis of the special figure winning random number is output from the channel CH1 during non-probability fluctuation (special figure low probability state), and is output from the channel CH2 during probability fluctuation (special figure high probability state). . Further, the normal winning random number is output from the channel CH3 in the normal low probability state (during non-electric support) and is output from the channel CH4 in the normal high probability state (during electric support). Note that the random number generation circuit 318 may generate the special figure winning random number itself, or may generate a random number that is the basis of the special figure winning random number. Further, the normal winning random number itself may be generated, or the random number that is the basis of the normal winning random number may be generated. In step S1053c, it is determined whether or not step S1053a and step S1053b have been executed for all four channels. If all channels have not been completed, the process returns to step S1053a for each channel that has not been completed. Process. Note that the setting of the random number generation range may be executed only for the channel used according to the state, or may be executed only for the channel for which the random number generation range is set. On the other hand, if all the channels have been completed, this random number generation circuit initial setting process is completed.

  In the present embodiment, when the random number generation circuit initial setting process described above is performed, the random number generation circuit 318 starts updating the random number. When a user reset is applied, the random number is updated, and the random number is generated in the new random number generation range without delay based on the update of the random number generation range in that state. In addition, when a user reset is applied, a process for stopping the update of the random number may be performed once, and a process for restarting the update of the random number may be performed after setting the random number generation range. In addition, the timer interrupt of the main control unit is prohibited at this point, and the random number generation circuit initial setting processing is performed before the timer interrupt is permitted, so even if a new random number is latched, it is used for various lotteries. The lottery process can be stabilized.

  The random number generation circuit 318 may not perform the random number generation circuit initial setting process when receiving an instruction from the CPU 304 to execute the random number generation circuit initial setting process. That is, regardless of whether or not the random number generation circuit 318 performs the random number update, the CPU 304 may be instructed to execute the random number generation circuit initial setting process. With this configuration, the analysis result of the user program and the operation of the random number generation circuit 318 do not match, so that it becomes difficult to analyze the operation of the basic circuit 302 and fraud can be prevented. Therefore, the operation of the basic circuit 302 is not unstable due to fraud, and the game control can be stabilized. If the operation of the basic circuit 302 is analyzed by fraud, there is a possibility that an operation advantageous to the player may be performed. However, with the above configuration, such fraud can be prevented, so that game control is stable. Can be achieved.

  Furthermore, regardless of whether or not the random number generation circuit 318 performs the random number update, if the CPU 304 is instructed to execute the random number generation circuit initial setting process, the process when the user reset is performed may be unified. it can. That is, even if the state becomes unstable after the user reset, it is not necessary to perform the branch process, so that the game control can be stabilized. In addition, although the above-mentioned content described the case where a user reset was applied, the same effect can be acquired also when a system reset is applied.

  In step S107 in the main process of the main control unit shown in FIG. 88, it is determined whether or not to return to the state before the power interruption (before the power interruption), and the state before the power interruption is not restored (main control part 300). When the basic circuit 302 is initialized, the process proceeds to the RWM clear process (step S115).

  Specifically, first, a RAM clear signal transmitted when a store clerk or the like of a game store operates the RAM clear switch 180 provided on the power supply board 182 shown in FIG. If the RAM clear signal is ON (RAM clear is necessary), the process goes to step S113 to set the basic circuit 302 to the initial state. move on. On the other hand, when the RAM clear signal is OFF (when the RAM clear is not necessary), the power status information stored in the power status storage area provided in the RAM 308 is read, and the power status information is information indicating suspend. It is determined whether or not. If the power status information is not information indicating suspend, the process proceeds to step S113 to set the basic circuit 302 to an initial state. If the power status information is information indicating suspend, a predetermined area of the RAM 308 is set. A checksum is calculated by adding all 1-byte data stored in (for example, all areas) to a 1-byte register whose initial value is 0. The result of the calculated checksum is It is determined whether or not the value matches the value set in the RAM 308 (whether or not the checksum result is normal). If the checksum result is a specific value (if the checksum result is normal), the process proceeds to step S109 to return to the state before the power interruption, and the checksum result is other than the specific value. In the case (when the result of the checksum is abnormal), the process proceeds to step S113 in order to set the pachinko machine 100 to the initial state. Similarly, when the power status information indicates information other than “suspend”, the process proceeds to step S113.

  In step S109, data write-back processing is performed. In this data write-back process, the value of the stack pointer stored in the stack pointer save area provided in the RAM 308 at the time of power interruption is read and reset to the stack pointer (this setting). In addition, the value of each register stored in the register save area provided in the RAM 308 at the time of power interruption is read out and reset in each register, and then the interrupt permission is set. Thereafter, as a result of the CPU 304 executing the control program based on the reset stack pointer and registers, the pachinko machine 100 returns to the state when the power is turned off. That is, the processing is resumed from the instruction next to the instruction executed immediately before branching to the timer interrupt process (described later) immediately before the power interruption. A RAM 308 mounted on the basic circuit 302 in the main control unit 300 shown in FIG. 4 is provided with a transmission information storage area. In step S109, a power recovery command is set in the transmission information storage area. This power recovery command is a command indicating that the power has been restored to the state at the time of power-off, and is transmitted to the first sub-control unit 400 in step S231 in the timer interrupt process of the main control unit 300, which will be described later.

  In step S111, processing for starting WDT 3141 is performed. Here, activation permission of WDT 3141, setting of an initial value, and the like are performed. In the present embodiment, a numerical value corresponding to 32.8 ms is set as an initial value in WDT 3141.

  In step S113, RWM clear processing is performed. In this RWM clear process, all storage areas in the RAM 308 are initialized. In addition, setting of timer interrupt permission of the main control unit, setting of the stack initial value to the stack pointer (this setting), etc. are also performed. Further, here, a normal return command is set in the transmission information storage area provided in the RAM 308 of the main control unit 300. This normal return command is a command indicating that the RWM clear process (step S113) of the main control unit 300 has been performed. Like the power recovery command, in step S231 in the timer interrupt process of the main control unit 300, 1 is transmitted to the sub-control unit 400. In step S115, similarly to step S111, processing for starting WDT 3141 is performed.

  In step S117, basic random number initial value update processing is performed. Here, the basic random number corresponds to a big hit special figure random number, a small hit special figure random number, and a lost special figure random number, which are software random numbers. Note that each random number includes a random number for special figure 1 and a random number for special figure 2, but in the following description, unless otherwise noted, both will be described as a special figure without distinction. In this basic random number initial value updating process, an initial value generating random number counter for generating initial values of the big hit special figure random number counter, the small hit special figure random number counter, and the lost special figure random number counter is updated. Each counter is provided in the RAM 308. The initial value generation random number counter is also updated in step S204 described later.

  In step S119, effect random number update processing is performed. The effect random number here is also a software random number, and this effect random number is a random number from which the effect is determined. In the present embodiment, when the lottery is executed to determine whether or not to perform a prefetch notice described later. It corresponds to the random number used. In this effect random number update process, the effect random number counter provided in the RAM 308 is updated. The effect random number counter is also updated in step S211 described later.

The main control unit 300 repeatedly executes the processes of step S117 and step S119 except during a timer interrupt process that starts every predetermined period. These steps S117 and S119 correspond to an example of main processing.
<Main control unit timer interrupt processing>

  Next, the main control unit timer interrupt process executed by the CPU 304 of the main control unit 300 will be described with reference to FIG. This figure is a flowchart showing the flow of the main control unit timer interrupt process.

  The main control unit 300 shown in FIG. 4 includes a timer circuit 311 that generates a timer interrupt signal at a predetermined cycle (in this embodiment, about once every 4 ms), and the main control is triggered by this timer interrupt signal. The part timer interrupt process is started at a predetermined cycle.

  In step S201, a timer interrupt start process is performed. In this timer interrupt start process, a process of temporarily saving each register value of the CPU 304 to the stack area is performed. In step S203, the WDT 3141 is periodically changed to prevent the WDT 3141 interrupt from occurring when the count value of the WDT 3141 exceeds the initial setting value (32.8 ms in the present embodiment) (so as not to detect a processing abnormality). In the embodiment, the restart is performed once every about 4 ms, which is the period of the main control unit timer interrupt.

  In step S205, input port state update processing is performed. In this input port state update process, the detection signals of the various sensors 320 shown in FIG. The data is stored in a signal state storage area provided for each sensor 320. If the detection signal of the sphere detection sensor is described as an example, information on the presence / absence of the detection signal of each sphere detection sensor detected in the timer interruption process (about 4 ms before) is stored in the RAM 308 for each sphere detection sensor. This information is read out from the previous detection signal storage area partitioned and stored in the RAM 308 in the previous detection signal storage area partitioned for each sphere detection sensor, and the previous timer interrupt processing (about 2 ms before) ) Is read from the current detection signal storage area provided for each sphere detection sensor in the RAM 308, and this information is read out from the previous detection signal storage area described above. To remember. Further, the detection signal of each sphere detection sensor detected this time is stored in the above-described current detection signal storage area.

  Further, in step S205, the information on the presence or absence of the detection signal of each sphere detection sensor stored in each storage area of the above-mentioned detection signal storage area, the previous detection signal storage area, and the current detection signal storage area is compared. It is determined whether or not the information on the presence or absence of detection signals for the past three times in the ball detection sensor matches the winning determination pattern information. This main control unit timer interruption process that is repeatedly started at a very short interval of about 2 ms is started several times while one game ball passes through one ball detection sensor. For this reason, every time the main control unit timer interrupt process is activated, in step S205 described above, a detection signal indicating that the same game ball has passed the same ball detection sensor is confirmed. As a result, a detection signal indicating that the same game ball has passed the same ball detection sensor is stored in each of the detection signal storage area, the previous detection signal storage area, and the current detection signal storage area. That is, when the game ball starts to pass through the ball detection sensor, there is no detection signal before, a previous detection signal, and a current detection signal. In the present embodiment, in consideration of erroneous detection of the sphere detection sensor and noise, it is determined that there is a prize when the detection signal is stored twice continuously after no detection signal. The ROM 306 of the main control unit 300 shown in FIG. 4 stores winning determination pattern information (in this embodiment, information indicating that there is no previous detection signal, that there is a previous detection signal, and that there is a current detection signal). In this step S205, information on the presence or absence of detection signals for the past three times in each sphere detection sensor is predetermined winning determination pattern information (in this embodiment, no previous detection signal, previous detection signal, current detection signal present). In the case of the general winning port 226, the variable winning port 234, the first special figure starting port 230, and the second special figure starting port 232, or the ordinary drawing starting port 228. Is determined to have passed. In other words, it is determined that there has been a winning at these winning ports 234, 230 and the starting ports 230, 232, 228. For example, when the information on the presence / absence of the detection signals for the past three matches with the above-described winning determination pattern information in the general winning opening sensor for detecting the winning at the general winning opening 226, there is a winning at the general winning opening 226. If the information on the presence / absence of detection signals for the past three times does not match the above-described winning determination pattern information, the subsequent general winnings are performed. The process branches to the subsequent process without performing the process associated with winning the prize to the mouth 226. Note that the ROM 306 of the main control unit 300 stores winning determination clear pattern information (in this embodiment, information indicating that there is a detection signal before the previous time, no previous detection signal, and no current detection signal). After it is determined that there has been a single win, it is not determined that there has been a win until the information on the presence or absence of detection signals for the past three times matches the winning determination clear pattern information in each ball detection sensor, and the winning determination is cleared. If it matches the pattern information, it is next determined whether or not it matches the winning determination pattern information.

  In step S207 and step S209, basic random number initial value update processing and basic random number update processing are performed. In these basic random number initial value update processing and basic random number update processing, the value of the initial value generation random number counter performed in step S117 is updated, and then the jackpot special figure random number used in the main control unit 300, The random number counter for generating the special figure random number for small hits and the special figure random number for lose is updated. For example, if the possible numerical range for the big hit special figure random number is 0 to 100, the value is acquired from the random number counter storage area for generating the big hit special figure random number provided in the RAM 308, and 1 is added to the acquired value. Then, it is stored in the original random number counter storage area. At this time, if the result of adding 1 to the acquired value is 101, 0 is stored in the original random number counter storage area. If it is determined that the random number counter has made one round as a result of adding 1 to the acquired value, the value of the initial value generating random number counter corresponding to each random number counter is acquired and stored in the storage area of the random number counter. set. For example, a value is acquired from a random counter for generating a special jackpot random number for big hit that fluctuates in a numerical range of 0 to 100, and a result obtained by adding 1 to the acquired value is stored in a predetermined initial value storage area provided in the RAM 308. If the value is equal to the previously set initial value (for example, 7), the value is acquired as the initial value from the initial value generating random number counter corresponding to the random number counter for generating special jackpot random numbers, The initial value set this time is stored in the above-described initial value storage area in order to determine that the special counter random number counter for generating a big hit special round has been made next round. Keep it. In the present embodiment, the counter for acquiring the random number related to the special figure 1 and the counter for acquiring the random number related to the special figure 2 are separately provided, but the same counter may be used.

  In step S211, effect random number update processing is performed. In this effect random number update process, a random number counter for generating an effect random number used by the main control unit 300 is updated, as in step S119. In step S213, timer update processing is performed. In this timer update processing, the normal symbol display symbol update timer for timing the time for the symbol to be changed / stopped on the normal symbol display device 210, and the time for the symbol to be changed / stopped to be displayed on the first special symbol display device 212 are timed. Special symbol 1 display symbol update timer for performing, special symbol 2 display symbol update timer for measuring the time for the symbol to be changed and stopped on the second special symbol display device 214, a predetermined winning effect time, a predetermined opening time Various timers including a timer for measuring a predetermined closing time, a predetermined end effect period, and the like are updated.

  In step S215, winning prize counter update processing is performed. In this winning opening counter update process, when winning holes 234, 230 and starting holes 230, 232, 228 are won, the RAM 308 stores the winning ball number storage area provided for each winning hole or for each starting hole. The value is read, and 1 is added to set the original prize ball number storage area.

  In step S217, a winning acceptance process is performed. In this winning acceptance process, if there is a winning at the first special figure starting port 230 and the number of special figure 1 variable games on hold is less than a predetermined number (4 in this embodiment), a predetermined Get startup information. That is, if the number of holdings is less than the predetermined number, a hardware random number that is the basis of the special figure 1 winning random number is obtained from the random number generation circuit 318 shown in FIG. . This point will be described in more detail later. Also, the big hit special figure 1 random number, the small hit special figure 1 random number, and the lost special figure 1 random number are acquired from a random number counter storage area provided in the RAM 308. Special jackpot special figure 1 random numbers, small hit special figure 1 random numbers, and lost special figure 1 random numbers are values obtained by processing software random numbers derived from software random number counters provided in the RAM 308 (software random number value + R register value). Value + 1). Further, the special figure 1 variation time determination random number is acquired from the counter circuit 312 shown in FIG. The combination of the random number generation circuit 318, the counter circuit 312 and the software random number counter provided in the RAM 308 and the main control unit 300 that performs random number processing shown in FIG. This corresponds to an example of information deriving means (first starting information deriving means, second starting information deriving means). If attention is paid to the generation of hardware random numbers, the random number generation circuit 318 or the counter circuit 312 shown in FIG. 4 generates start information, and start information generation means (first start information generation means, second start information generation means, Corresponds to an example of the starting information generating means). The various random numbers (starting information) acquired here are stored as a set of starting information in a vacant area corresponding to the winning order (holding order) of the holding storage unit of FIG. . The special storage unit of FIG. 1 stores the start information acquired when a game ball enters the first special figure start port 230 (first start area) up to a predetermined first upper limit number (here, four). This corresponds to the first start information storage means that can be stored. At this time, various random numbers (starting information) may be temporarily stored in a temporary area provided in the RAM 308, and the value stored in the temporary area may be stored in the holding storage unit of FIG. 1 may be used as the first start-up information storage unit, or the reserved storage unit and the temporary area in FIG. 1 may be used as the first start-up information storage unit. Further, the CPU 304 of the main control unit 300 adds 1 to the value of the number of holdings in FIG. 1 stored in the RAM 308, and the number of holdings in FIG. Therefore, the CPU 304 of the main control unit 300 corresponds to an example of a holding unit. As for special figure 2, each random number which is start information is acquired as in special figure 1, and the obtained random number is similarly stored as a set of start information in the holding storage unit of special figure 2 provided in RAM 308. Further, 1 is added to the value of the number of holdings in FIG. 2 stored in the RAM 308. The reserved storage unit of the special figure 2 stores the start information acquired when the game ball enters the second special figure start port 232 (second start area) up to a predetermined second upper limit number (here, four). This corresponds to a possible second starting information storage means. At this time, various random numbers (starting information) may be temporarily stored in a temporary area provided in the RAM 308, and the value stored in the temporary area may be stored in the holding storage unit of FIG. The starting information storage means may be used, or the holding storage unit and the temporary area of FIG. 2 may be used as the second starting information storage means.

  In addition, when it is detected that a ball has passed through the general figure starting port 228 and the number of pending custom figure variable games is less than a predetermined number (4 in this embodiment), the timing is as follows. 4 is obtained from the random number generation circuit 318 shown in FIG. 4, and is stored in a random number storage area different from that for the special figure provided in the RAM 308. The point that the normal winning random number is acquired from the random number generation circuit 318 will also be described later.

  In this winning acceptance process, a predetermined ball detection sensor detects a winning (winning) at the first special figure starting port 230, the second special figure starting port 232, the ordinary drawing starting port 228, or the variable winning port 234. In such a case, the transmission information to be transmitted to the first sub-control unit 400 includes the winnings of the first special figure starting port 230, the second special figure starting port 232, the general drawing starting port 228, and the variable winning port 234. ) Is set to receive winning information. Whether the start information of the special figure or the start information of the usual figure, if the number of holdings is equal to or greater than the predetermined number, the start information is not acquired and the process proceeds to step S219.

  In step S219, a payout request number transmission process is performed. The output schedule information and the payout request information output to the payout control unit 600 shown in FIG. 4 are composed of 1 byte, strobe information (indicating that data is set when ON), bit 6 Power-on information (if turned on, indicates that this is the first command transmission after power-on), bits 4-5 indicate the current processing type for encryption (0-3), and bits 0-3 indicate encryption The number of payout requests after processing is shown.

  In step S221, a normal state update process is performed. This normal state update process performs one of a plurality of processes corresponding to the normal state. For example, in the normal state update process in the middle of the normal symbol display (the above-described general symbol display symbol update timer value is 1 or more), the 7-segment LED constituting the normal symbol display device 210 is repeatedly turned on and off. Turns off drive control. By performing this control, the normal symbol display device 210 performs a usual fluctuation display (ordinary figure fluctuation game).

  Also, in the normal state update process at the timing when the normal symbol change display time has elapsed (the timing at which the value of the general symbol display symbol update timer has changed from 1 to 0), if the hit flag is on, the hit symbol is displayed. The normal symbol display device 210 is controlled so that the 7-segment LED constituting the normal symbol display device 210 is turned on / off, and when the hit flag is off, the normal symbol display device 210 is configured to display the lost symbol display mode. 7 segment LED on / off drive control is performed. Further, the RAM 308 of the main control unit 300 is provided with a setting area for performing various settings in various processes, not limited to the normal state update process. Here, the above-described lighting / extinguishing drive control is performed, and the setting area is set to indicate that the normal stop display is being performed. By performing this control, the normal symbol display device 210 determines the symbol of either one of the winning symbols (the common symbol A shown in FIG. 5C) or the lost symbol (the universal symbol B shown in FIG. 5C). Display. Thereafter, information indicating the stop period is set in a storage area of a normal stop time management timer provided in the RAM 308 in order to maintain the display for a predetermined stop display period (for example, 500 msec). With this setting, the symbol that has been confirmed and displayed is stopped and displayed for a predetermined period, and the player is notified of the result of the normal game.

  Further, if the result of the usual figure variable game is a hit, the usual figure hit flag is turned on as will be described later. When the usual figure hit flag is on, in the usual figure state update process at the timing when the predetermined stop display period ends (when the usual figure stop time management timer value changes from 1 to 0), The normal operation is set in the setting region, and the blade member 2321 is opened to the solenoid (332) for opening and closing the blade member 2321 of the second special figure starting port 232 for a predetermined opening period (for example, 2 seconds). And a signal indicating the open period is set in the storage area of the blade open time management timer provided in the RAM 308. The CPU 304 of the main control unit 300 that performs the opening control of the pair of blade members 2321 in this way corresponds to an example of a variable start region control unit that performs variable start region control. On the other hand, if it is in the non-electric support state, in the setting area of the RAM 308, the normal operation is not set, and no signal is sent to the solenoid (332) for opening and closing the blade member 2321 of the second special figure starting port 232. Is not output. By doing so, the blade member 2321 remains closed. Note that a signal for maintaining the blade member 2321 in the closed state may be output without fail.

In the case of the electric support state, in the process starting at the timing when the predetermined opening period ends (the timing when the value of the blade opening time management timer is changed from 1 to 0), the predetermined closing period (for example, 0.1 second), a signal for holding the blade member 2321 in a closed state is output to the solenoid (332) for opening / closing driving of the blade member 2321, and it is closed in the storage area of the blade closing time management timer provided in the RAM 308. Set information indicating the period.

  In the case of the electric support state, in the normal state update process that starts at the timing when the predetermined closing period ends (the timing when the value of the blade closing time management timer changes from 1 to 0), In the setting area, set “Normal” inactive. Further, if the result of the usual figure variable game is lost, the usual figure lose flag is turned on as will be described later. When the usual figure loss flag is on, even in the usual figure state update process at the timing when the above-described predetermined stop display period ends (when the value of the usual figure stop time management timer is changed from 1 to 0), In the setting area of the RAM 308, normal operation inactive is set. In the general state update process in the case where the general map is not operating, nothing is done and the process proceeds to the next step S223. Subsequently, in step S223, a general drawing related lottery process is executed.

  FIG. 92 (a) is a flowchart showing the flow of a general drawing related lottery process. In the general drawing related lottery process shown in FIG. 92A, first, it is determined whether or not there is general drawing hold information (step S2231). Here, the general map hold information refers to the number of hold of the general map. In other words, here, it is determined whether or not the number of pending variable games is one or more. In addition, even if it does not have the usual number of reservations as data, for example, a random number corresponding to the reservation (a normal winning random number) may be recognized as the general reservation information. If there is no general map hold information, this general drawing related lottery process is terminated, and if there is general map hold information, the process proceeds to step S2232. In step S2232, it is determined whether or not the usual figure variable game is being performed. If it has been performed, the usual figure related lottery process is terminated, and if not, the process proceeds to step S2233. In step S2233, it is determined whether or not the opening / closing control of the second special figure starting port 232 is being performed (whether or not the normal map is operating). If it is not normally operated, the process proceeds to step S2234. In step S2234, a random number lottery based on the regular winning random number stored in the random number storage area is performed.

  FIG. 92 (b) is a diagram showing a general drawing lottery table. This table is stored in the ROM 306 of the main control unit 300. The CPU 304 of the main control unit 300 takes out the normal winning random number from the random number storage area of the RAM 308, refers to the short time flag, and if the short time flag is on, it is in a high probability state (during electric support) Subtracting the high-probability common-plan winning data from the common-lot winning random number, if a carry occurs (if the value of the general-plan winning data is larger than the normal winning random number), it is determined to be a general winning and a carry occurs. If you don't, you will lose your usual figure. That is, the normal winning random number range is 0-9. In the normal high probability state, the normal winning random number is output from the channel CH4 of the random number generation circuit 318 shown in FIG. In this channel CH4, a random number generation range of 0 to 9 is set in the setting of the random number generation range (step S1053a) in the random number generation circuit initial setting process shown in FIG. 90. The range that can be taken is 0-9. Therefore, the probability of winning the normal drawing in the normal high probability state is 1/1. On the other hand, if the time flag is off, it is in the low probability state (non-powered support), so the winning symbol in the low probability state is the same as the data in the high probability state from the acquired random number. If the data is pulled and a carry occurs (when the value of the win-winning data is larger than the normal-winning random number), the win-winning is determined. If no carry occurs, the win-win is lost. That is, even in the normal figure low probability state, the normal figure winning random number range is 0-9. In the normal low probability state, the normal winning random number is output from the channel CH3 of the random number generation circuit 318 shown in FIG. For this channel CH3, a random number generation range of 0 to 999 is set in the setting of the random number generation range (step S1053a), and the range that can be taken by the normal winning random number in the normal low probability state is 0 to 999. Therefore, the probability of winning the normal figure in the normal figure low probability state becomes 1/100.

  In this embodiment, by limiting the range (random number generation range) that the normal winning random numbers can take from the default 0 to 65535 to 0 to 999, the big hit probability can be reduced to 1/100. In addition, the common figure winning data can be set to the same value in the common figure high probability state and the common figure low probability state. Determining the probability without limiting the random number generation range may lead to an increase in development man-hours and may cause erroneous probability design. In particular, the complexity becomes more noticeable when lottery is performed a plurality of times based on one opportunity. Therefore, limiting the random number generation range can reduce the development man-hours and stabilize the lottery process. In addition, it can be said that sharing the common figure winning data in the common figure high probability state and the common figure low probability state can reduce the development man-hours and stabilize the lottery process.

  When the regular drawing lottery is won, the hit flag provided in the RAM 308 is set to ON. In case of losing (unfair), the winning flag is set to OFF. Regardless of the result of the general drawing lottery, a random number for determining the normal variation time is acquired from the counter circuit 312 shown in FIG. One time for variably displaying the normal map on the figure display device 210 is selected, and this variable display time is stored as a normal map variable display time in the normal time variable time storage area provided in the RAM 308. The CPU 304 of the main control unit 300 that selects one common map change time from a plurality of change times by lottery using the random number for determining the normal map change time corresponds to an example of a lottery means. Here, the lottery process for the usual time fluctuation time is different from the determination of whether or not the lottery is successful. Note that the number of pending general figure variable games is stored in the usual figure pending number storage area provided in the RAM 308. Each time step S2234 is executed, the number of pending custom figure variable games is stored. The value obtained by subtracting 1 from is re-stored in the usual figure number-of-holds storage area. In addition, acquisition of the random number for determining the normal figure change time from the counter circuit 312 may be performed at the time of winning a prize in the general figure start port 228.

  In step S2235, the normal winning lottery used in the previous general drawing lottery is deleted from the random number storage area described above, and this general drawing related lottery process ends. Subsequently, special figure prefetching processing (step S225) is executed. In this prefetching process, first, the special figure 1 winning random number in the special memory 1 of FIG. 1 provided in the RAM 308 is prefetched, or the special figure 2 winning random number in the special memory 2 of FIG. 2 is prefetched. Note that the prefetching here means that the start information is read first before the success / failure determination (final lottery), but in the subsequent prefetching processing, the word “prefetching” is used as the result of the predecessor (prevention / correction (final lottery)). ) May be used to mean read. In this step S225, a pre-judgment table having the same contents as the contents of the special figure lottery table shown in FIG. 94 (a) used in the special figure related process (step S229) described later is used, and the validity based on the pre-read special figure winning random number. Pre-determination is performed. In the special figure related process, the special figure lottery table is used again to determine whether or not the special figure variable game is successful, and the determination result here is only the result of the preliminary determination. In the pre-judgment determination, a result of “big hit” or a result other than “big hit” is derived. The special figure 1 random number is prefetched, or the big hit special figure 2 random number in the reserved storage unit of the special figure 2 is prefetched. Subsequently, using the pre-determination table having the same content as the content of the stop symbol lottery table shown in FIG. 94 (b) used in the special symbol related process in step S229, the special symbol stop symbol based on the pre-determined special bonus random number for jackpot Make a prior judgment.

  In the special symbol related process, the special symbol stop symbol lottery table is used again, and the special symbol stop symbol lottery is performed again, and the determination result here is a preliminary determination result. In this way, when the stop symbol of the special figure is determined in advance, a lottery for whether or not to perform the pre-reading notice is performed. This pre-reading notice indicates that the result of the success / failure determination performed in the special drawing-related lottery process before the special figure-related lottery process (step S229) is executed, that is, before the determination of success / failure is performed. 15R big hit (15R special big hit or 15R big hit). The pre-reading notice here is a fake pre-reading notice that gives a false notice as if it was a big hit of 15R even if the pre-determined result of the stop symbol is not a big hit of 15R (Special Figure A or Special Figure B) Is also included. In other words, the pre-reading notice indicates that there is a possibility that the result of the success / failure determination will be a 15R jackpot, an advance notification that suggests to the player, or an advance notice that the player expects that the result of the success / failure determination will be a 15R jackpot. It can be said that it is information. An effect random number (for example, a possible range is 0 to 99) is acquired from an effect random number counter provided in the RAM 308 at the timing of performing the pre-reading notice execution availability lottery, and the execution availability lottery is performed based on the acquired effect random number. In addition, the prior determination result of the stop symbol may be transmitted to the first sub-control unit 400, and the first sub-control unit 400 may perform this execution availability lottery.

  Next, the special figure state update process (step S227) for each of the special figure 1 and the special figure 2 is performed. First, the special figure state update process for the special figure 2 is performed, and then the special figure state for the special figure 1 is performed. Perform figure state update processing. In the special figure 2 state update process, one of the following eight processes is performed according to the state of the special figure 2. For example, in the special figure 2 state update process in the middle of the special figure 2 fluctuation display (the value of the above-mentioned special figure 2 display symbol update timer is 1 or more), Performs lighting / extinguishing drive control that repeatedly turns off. By performing this control, the second special symbol display device 214 performs the variable display of the special figure 2 (special figure 2 variable game). In addition, predetermined transmission information indicating that the general command rotation start setting transmission process is executed in the command setting transmission process (step S231) is additionally stored in the transmission information storage area, and the process ends.

  In addition, the RAM 308 of the main control unit 300 includes 15R big hit flag, 2R big hit flag, first small hit flag, second small hit flag, first lose flag, second lose flag, probability change flag, and hourly flag. Is prepared. In the special figure 2 state update process starting at the timing when the special figure 2 variable display time has passed (the timing when the value of the special figure 2 display symbol update timer is changed from 1 to 0), the special figure in the special figure related lottery process to be described later Based on the determination result (stop pattern mode of the special figure), the 7 segment LED constituting the second special figure display device 214 is controlled to be turned on / off, and the special figure 2 stop display is being displayed in the setting area of the RAM 308. Set to represent. By performing this control, the second special symbol display device 214 has a 15R special jackpot symbol (special symbol A), a 15R jackpot symbol (special symbol B), a 2R special jackpot symbol (special symbol C), and a sudden time shortening symbol (special symbol). Figure D), hidden probability variation (special E), suddenly normal (special F), first small hit (special G), second small (special H), first loss (special) One of the symbols (Fig. I) and the second lost symbol (special symbol J) is confirmed and displayed. After that, information indicating the stop period is set in the storage area of the special figure 2 stop time management timer provided in the RAM 308 in order to maintain the display for a predetermined stop display period (for example, 500 milliseconds). With this setting, the specially displayed special figure 2 is stopped and displayed for a predetermined period, and the result of the special figure 2 variable game is notified to the player. Further, when a value is set in the electric support number storage unit provided in the RAM 308, if the value is 1 or more, 1 is subtracted from the shortest number of times, and the subtraction result becomes 1 to 0. In this case, if the special figure probability is not changing, the time reduction flag is turned off. Further, the hourly flag is turned off during the big hit game or the small hit game. That is, the CPU 304 of the main control unit 300 shifts to the non-electric support state (first entry rate control state) when the big hit gaming state and the small hit gaming state (second control state).

  In addition, a predetermined transmission information indicating that a general command rotation stop setting transmission process is executed in a command setting transmission process (step S231), which will be described later, is additionally stored in the above-described transmission information storage area, and a pattern for stopping the variable display is displayed. Special figure 2 identification information indicating that it is special figure 2 is additionally stored in the RAM 308 as information to be included in command data, which will be described later, and the processing is terminated.

  If the result of the special figure 2 variable game is a big hit, the big hit flag is turned on. When the jackpot flag is on, in the special figure 2 state update process at the timing when the predetermined stop display period ends (the timing when the special figure 2 stop time management timer value changes from 1 to 0), the RAM 308 In the setting area, the special figure 2 is in operation and waits for a predetermined winning effect period (for example, 3 seconds), that is, a period during which an image for notifying the player that the big win by the decorative symbol display device 208 is started is displayed. Therefore, information indicating the winning effect period is set in the storage area of the special figure 2 standby time management timer provided in the RAM 308. Further, 5H is additionally stored as transmission information (command type) in the transmission information storage area described above in order to execute the general command winning effect setting transmission process in the command setting transmission process (step S231).

  Further, in the special figure 2 state update process that starts at the timing when the predetermined winning effect period ends (the timing when the value of the special figure 2 standby time management timer changes from 1 to 0), a predetermined release period (for example, 29 seconds) Alternatively, the door member 2341 is opened to the solenoid (332) for opening and closing the door member 2341 of the variable prize opening 234 until a winning of a predetermined number of balls (for example, 10 balls) is detected at the variable prize opening 234. In addition to outputting a signal to be held at the same time, information indicating the opening period is set in the storage area of the door opening time management timer provided in the RAM 308. Further, 7H is additionally stored as transmission information (command type) in the above-described transmission information storage area in order to execute the general command big prize opening release setting transmission process in the command setting transmission process (step S231).

  In the special figure 2 state update process that starts at the timing when the predetermined opening period ends (the timing when the door opening time management timer value changes from 1 to 0), the predetermined closing period (for example, 1.5 seconds) A signal for holding the door member 2341 in a closed state is output to a solenoid (332) for opening and closing the door member 2341 of the variable prize opening 234, and a closing period is stored in a storage area of a door closing time management timer provided in the RAM 308. Set the information indicating. In addition, predetermined transmission information indicating that the special winning opening closing setting transmission process is executed in the command setting transmission process (step S231) is additionally stored in the transmission information storage area.

  In addition, in the special figure 2 state update process that starts at the timing when the door member opening / closing control is repeated a predetermined number of times (15 rounds or 2 rounds in this embodiment) and finished, a predetermined end effect period (for example, 3 seconds) In other words, the effect standby period is stored in the storage area of the effect standby time management timer provided in the RAM 308 in order to set to wait for a period during which an image for informing the player that the big hit by the decorative symbol display device 208 is to be ended is displayed. Set the information indicating.

  As described above, the CPU 304 of the main control unit 300 corresponds to an example of variable winning control means for performing change control of the open / closed state of the door member 2341 of the variable winning opening 234 during the big hit gaming state. The ROM 306 of the main control unit 300 stores the opening / closing pattern of the door member 2341 of the variable prize opening 234, and the CPU 304 of the main control unit 300 responds to the determination of whether or not the special figure variable game is successful from the ROM 306. Get the open / close pattern.

  Further, the CPU 304 of the main control unit 300 sets the probability variation flag and the time reduction flag provided in the RAM 308 to be on simultaneously with the end of the big hit game, based on the stop symbol form represented by the special figure determination result. That is, the CPU 304 of the main control unit 300 sets both the probability variation flag and the time reduction flag to ON when the special figure determination result is “special figure A” or “special figure C” in the special figure lottery process described later. . When the special figure determination result is “special figure E”, only the probability variation flag is set to ON among the probability variation flag and the time reduction flag. Furthermore, when the special figure determination result is “special figure B” or “special figure D”, only the short time flag is set to ON among the probability variation flag and the short time flag, and the electric support number storage unit provided in the RAM 308 is set. Set power support 100 times. When the probability variation flag is set to ON, it is in a special figure high probability state (during probability fluctuation), and is a state in which the probability of winning a big hit after the big hit game is high (a special figure high probability state). On the other hand, if the probability variation flag is not set to ON (set to OFF), it is a special figure low probability state. Therefore, the setting state of the probability variation flag affects the result of the determination of success / failure (special drawing lottery). In addition, when the time reduction flag is set to ON, it is in an electric support state, the electric chew is easy to open (for example, easy to hit), the opening time based on one hit is long, and the number of times of opening based on one hit is large. The variable starting area control is performed so as to be advantageous to the player. On the contrary, if the time reduction flag is set to OFF, it is in a non-electric support state, and the variable start area control is performed so as to be disadvantageous to the player. Therefore, the setting state of the time reduction flag also affects the variable start area control. Therefore, information indicating the setting state of the probability variation flag and / or the time reduction flag corresponds to an example of game control information, and the CPU 304 of the main control unit 300 corresponds to an example of game control information determination means.

  Furthermore, 6H is additionally stored as transmission information (command type) in the above-described transmission information storage area in order to execute the general command end effect setting transmission process in the command setting transmission process (step S231).

  Also, in the special figure 2 state update process that starts at the timing when the predetermined end production period ends (when the production standby time management timer value changes from 1 to 0), the special figure 2 is not activated in the setting area of the RAM 308. Set medium. Furthermore, if the result of the special figure 2 variable game is a loss, the loss flag is turned on. When the lost flag is on, even in the special figure 2 state update process at the timing when the predetermined stop display period described above ends (the timing when the special figure 2 stop time management timer value changes from 1 to 0), In the setting area of the RAM 308, special figure 2 inactive is set. In the special figure 2 state update process when the special figure 2 is not in operation, nothing is done and the process proceeds to the next process.

  When the special figure 2 state update process is completed, the special figure 1 state update process is performed. In the special figure 1 state update process, each process described in the special figure 2 state update process is performed according to the state of the special figure 1. Each process performed in the special figure 1 state update process is the same as the process in which “special figure 2” in the contents described in the special figure 2 state update process is replaced with “special figure 1”. Omitted. The order of the special figure 2 state update process and the special figure 1 state update process may be reversed.

  When the special figure state update process in step S227 is completed, a special figure related lottery process for each of special figure 1 and special figure 2 is performed. The CPU 304 of the main control unit 300 that executes this special drawing related lottery process corresponds to an example of the determination unit. The main control unit 300 first performs the process for the special figure 2 (the special drawing 2 related lottery process), and then performs the process for the special figure 1 (the special figure 1 related lottery process). As described above, the main control unit 300 performs the special figure 2 related lottery process before the special figure 1 related lottery process, so that the game ball enters the first special figure start port 230 at the same timing. The start information is acquired and the start information is acquired based on the fact that the game ball has entered the second special figure start port 232, the special condition 2 variable game start conditions, and the special figure 1 variable game start. Even if the conditions are satisfied at the same time, or if both the special figure 2 variable game start condition and the special figure 1 variable game start condition are satisfied, the special figure 2 variable game is changing first. Figure 1 Floating game does not start to fluctuate. That is, the pachinko machine 100 according to the present embodiment performs special figure 2 priority fluctuation, and the lottery based on the winning at the second special figure start port 232 (determination of special figure 2) is determined as the first special figure start. This is prioritized over a lottery based on winning a prize in the mouth 230 (a determination of success / failure in FIG. 1). In other words, in the pachinko machine 100 of the present embodiment, when a game ball enters the first special start area, the random numbers are stored in the first random number storage area up to the maximum number of reservations, and the game is stored in the second special start area. When a ball wins, a random number is stored in both the first random number storage area and the first random number storage area, and the winning random number storage area that stores random numbers up to the maximum number of reservations in the second random number storage area In this case, the random number is stored in the second random number storage area regardless of the time when the random number is stored in the first random number storage area and the time when the random number is stored in the second random number storage area. If the random number is determined based on the random number, and the random number is not stored in the first random number storage area and the random number is stored in the second random number storage area, the second random number Based on random numbers stored in the storage area If the random number is not stored in the second random number storage area and the random number is stored in the first random number storage area, it is stored in the first random number storage area. In this case, a determination unit is provided for determining whether or not the image is correct based on the random number. In addition, the main control unit 300 notifies the result of the jackpot determination of the special figure variable game by the first special figure display device 212 or the second special figure display device 214, and wins a prize to the second special figure start port 232. Based on the determination result, the start information of FIG. 1 is used as the start information in which the determination result is not performed. In the state where only the start information of the special figure 1 of the start information of the special figure 2 remains, and the start information of the special figure 2 is newly stored, the newly stored start of the special figure 2 The notification of the result of the determination based on the information is performed prior to the notification of the result of the determination based on the already stored start information of FIG. Further, the start information acquisition means for acquiring start information, when start information is stored in both of the first start information storage means and the second start information storage means, the second start information When starting information is acquired from the storage means and the starting information is stored in one of the first starting information storing means and the second starting information storing means, the starting information is stored. The starting information is obtained from the information storage means. Note that the special figure 2 related lottery process may be performed first after the special figure 2 state update process, then the special figure 1 state update process may be performed, and then the special figure 1 related lottery process may be performed.

  FIG. 93 is a flowchart showing the flow of the special drawing related lottery process. In the special drawing related lottery process shown in FIG. 93, special drawing 1 and special drawing 2 are shown without being distinguished from each other, but first, the processing from step S2291 to step S2296 is performed on special drawing 2, and thereafter, special drawing 1 is processed. The process from step S2291 to step S2296 is performed. Here, it demonstrates without distinguishing special figure 2 and special figure 1. FIG.

  In the special figure-related lottery process shown in FIG. 93, first, it is determined whether or not there is special figure holding information (step S2291). Here, special figure hold information refers to the number of special figure hold. That is, here, it is determined whether or not the number of special figure variable games that are on hold is one or more. For example, a random number corresponding to a hold (a special figure winning random number) may be recognized as the special figure hold information without having the number of special figure hold as data. If there is no special figure hold information, the special figure related lottery process is terminated, and if there is special figure hold information, the process proceeds to step S2292. In step S 2292, it is determined whether or not the special figure display device (212, 214) is in the special figure variation display or in the stop display. The related lottery process ends, and if none of the displays is in progress, the process proceeds to step S2293. In step S2293, it is determined whether or not the special figure is in operation. If the special figure is in operation, the special figure-related lottery process ends. If the special figure is inactive, the process proceeds to step S2294.

  In step S2294, special drawing lottery processing is performed. Here, first, a special set of random numbers (special figure winning random number, big hit special figure random number, small hit special figure random number, Take out the special figure random number for losing and the random number for determining the special figure fluctuation time), and transfer the starting information (set of random numbers) still stored in the reserved storage part from the currently stored area to the next area . That is, if the starting information stored in the past is taken out from the reserved storage unit of the special figure and the starting information is stored in the reserved storage unit of the special figure, the Nth oldest starting information is stored in the reserved storage unit of the special figure 2 Is set as the (N-1) oldest starting information. Also, 1 is subtracted from the pending number stored in the RAM 308. One set of random numbers (special figure winning random number, big hit special figure random number, small hit special figure random number, lose special figure random number, and special figure variable time determination random number) are extracted from the special figure holding storage unit of the RAM 308. The CPU 304 of the main control unit 300 that performs processing corresponds to an example of the start information acquisition unit.

  FIG. 94A shows a special drawing lottery table. This table is stored in the ROM 306 of the main control unit 300.

  When the CPU 304 of the main control unit 300 retrieves the start information from the holding storage unit of the RAM 308, the CPU 304 refers to the probability variation flag. If the probability variation flag is ON, the probability variation is in progress (the special figure high probability state). If the special figure jackpot winning data with probability fluctuation is subtracted from the figure winning random number and carry occurs (if the value of the special figure winning data is larger than the special figure winning random number), the special figure jackpot is won and the carry occurs If not, the special figure jackpot will not be selected. That is, the special figure big hit winning random number range is 0 to 124. During the probability variation, the random number that is the basis of the special figure winning random number is output from the channel CH2 of the random number generation circuit 318 shown in FIG. In this channel CH2, a random number generation range of 0 to 4999 is set in the setting of the random number generation range in the random number generation circuit initial setting process shown in FIG. 90 (step S1053a). The range obtained is 0-4999. Therefore, the winning probability of the special figure jackpot during the probability change is 1/40.

  On the other hand, if the probability variation flag is off, it means that non-probability fluctuation is in progress (special figure low probability state). On the other hand, if a carry occurs (when the value of the special figure winning data is larger than the special figure winning random number), the special figure big hit is won, and if no carry occurs, the special figure big hit is not selected. That is, the special figure big hit winning random number range is 0 to 124 even during non-probability fluctuation. During non-probability fluctuation, the random number that is the basis of the special figure winning random number is output from the channel CH1 of the random number generation circuit 318 shown in FIG. In this channel CH1, a random number generation range of 0 to 49999 is set in the setting of the random number generation range (step S1053a), and the range that can be taken by the special figure winning random number during non-probability variation is 0 to 49999. Therefore, the winning probability of the special figure jackpot during non-probability fluctuation is 1/400.

  In the present embodiment, by limiting the range (random number generation range) that the special figure winning random number can take from 0 to 65,999 from the default, 0 to 49999, the jackpot probability can be reduced to 1/400. Further, the special figure big hit winning data can be set to the same value during the probability fluctuation and the non-probability fluctuation. Determining the probability without limiting the random number generation range may lead to an increase in development man-hours and may cause erroneous probability design. In particular, the complexity becomes more noticeable when lottery is performed a plurality of times based on one opportunity. Therefore, limiting the random number generation range can reduce the development man-hours and stabilize the lottery process. In addition, it can be said that sharing the special figure big hit winning data during probability fluctuation and non-probability fluctuation can reduce the development man-hours and stabilize the lottery process.

  In FIG. 94 (a), only the special drawing big hit lottery table is shown, but a predetermined value is prepared as the special drawing small hit winning data. The CPU 304 of the main control unit 300 subtracts the special figure big hit winning data from the acquired special figure winning random number, and when no carry occurs (when the value of the special figure winning data is smaller than the special figure winning random number), This time, if the special figure small win winning data is subtracted from the value obtained by subtracting the special figure big hit winning data, and a carry occurs here (if the special figure small winning data is larger than the special figure winning random number) If you win a small figure and no carry occurs, you will lose. It is also possible to separately provide lost winning data. In this way, the special chart “big hit”, “small hit”, and “losing” are determined, and the determination result is obtained as the special figure determination result. The number of special figure variable games that are held is stored in the special figure variable number storage area provided in the RAM 308, and the number of special figure variable games that are held each time step S2294 is executed. The value obtained by subtracting 1 from is re-stored in this special figure holding number storage area.

  Next, in the special figure related lottery process shown in FIG. 93, a special figure stop symbol is drawn using software random numbers based on the special figure success / failure determination result (step S2295). FIG. 94B shows a stop symbol lottery table. This table is also stored in the ROM 306 of the main control unit 300. In the stop symbol lottery table, symbol winning data corresponding to the stop symbol mode of the special symbol (see FIG. 5A) is defined for each success / failure determination result. In FIG. 5B, the winning probability is also shown.

  When the determination result is a big hit, the CPU 304 of the main control unit 300 determines a special jackpot random number for a big hit out of one set of random numbers previously acquired from the reserved storage unit of the RAM 308 (a possible numerical range is 0 to 0). 99) from special figure A, special figure B, ... special figure F, the symbol winning data corresponding to each stop symbol is gradually subtracted, and the stop symbol when a carry occurs is used as the special symbol determination result. . If the result of the determination is a small hit, a special hit random number for a small hit (a numerical range that can be taken is 0 to 99) out of one set of random numbers previously acquired from the reserved storage unit of the RAM 308. If the symbol winning data of Fig. G is drawn and a carry occurs, "Special Illustration G" is won, and if no carry occurs, the special drawing H is further subtracted from the value obtained by subtracting the symbol winning data of Special Illustration G. The symbol winning data is drawn, and since a carry occurs here, “Special Figure H” is won. Note that before drawing the symbol winning data of the special figure H, it may be determined that the “special figure H” has been won. In this way, when the determination result is a small hit, “special figure G” or “special figure H” is determined as the special figure determination result. Further, if the determination result is a loss, a special figure random number for loss (a possible numerical range is 0 to 99) out of one set of random numbers previously acquired from the storage unit of the RAM 308 will be special figure I. If a carry occurs, the special symbol I will be selected, and if no carry occurs, the special symbol J will be further subtracted from the value obtained by subtracting the special symbol I symbol winning data. The winning data is drawn, and here a carry occurs, so “Special Figure J” is won. Here, it may be determined that “Special Figure J” has been won before drawing the symbol winning data of Special Figure J. In this way, when the determination result is lost, “Special Figure I” or “Special Figure J” is determined as the special figure determination result. Note that the first sub-control unit 400 determines a stop symbol pattern that is a combination of decorative symbols according to the special symbol determination result determined here.

  Further, a special figure variation time determination random number (possible numerical range is 0 to 255) of the random numbers for one set previously acquired from the reserved storage unit of the RAM 308 is acquired, and the acquired special figure variation time determination random number is acquired. In the lottery using, based on the result of the special figure determination, one time (special figure fluctuation time) for displaying the special figure on the special figure display device (212, 214) is selected from a plurality of fluctuation times. . In addition, in the 1st sub control part 400, the production | presentation aspect of the decoration symbol display apparatus 208 according to the special figure change time determined here is determined. The CPU 304 of the main control unit 300 that selects one special figure fluctuation time from a plurality of fluctuation times by lottery using the special figure fluctuation time determination random number value also corresponds to an example of a lottery means. Here, the lottery process for the special figure variation time corresponds to the lottery process related to the production, which is different from the determination of whether or not the special figure is a big hit, and different from the lottery for determining the symbol of the special figure. That is, the lottery process is irrelevant to the change of the control state and is not related to the payout of the prize ball.

  In step S2296, the one set of random numbers previously acquired from the reserved storage unit of the RAM 308 is erased, and this special drawing related lottery process ends. In step S231 performed following the special figure related lottery process in step S229, a command setting transmission process is performed, and various commands are transmitted to the first sub-control unit 400. Note that the output schedule information transmitted to the first sub-control unit 400 is composed of 16 bits in the present embodiment, bit 15 is strobe information (indicating that data is set when ON), bit 11 -14 are command types (in this embodiment, basic command, symbol variation start command, symbol variation stop command, winning effect start command, end effect start command, per round number designation command, power recovery command, RAM clear command, special figure. Bits 0 to 10 are constituted by command data (predetermined information corresponding to the command type).

  Specifically, the strobe information is turned on and off in the command transmission process described above. If the command type is a symbol variation start command, the command data includes information indicating the special symbol stop symbol, information indicating the control state (information indicating the setting state of the time reduction flag and the probability variation flag), and the special symbol variation time. In the case of a symbol variation stop command, information indicating a special symbol stop symbol (result of determining a special symbol), information indicating a control state, and the like, a winning effect start command and an end effect start are included. In the case of a command, information indicating a control state is included, and in the case of a per-round number designation command, information indicating a control state, a per-round number, and the like are included. When the command type indicates a basic command, device information in the command data, presence / absence of winning at the first special figure starting port 230, presence / absence of winning at the second special figure starting port 232, winning of the variable winning port 234 Includes presence or absence.

  In the general command rotation start setting transmission process described above, information representing the special figure stop symbol (special figure determination result), information representing the control state, and information representing the special figure variation time stored in the RAM 308 as command data. The information indicating the number of the first special figure variable game or the second special figure variable game that is on hold is set.

  In the general command rotation stop setting transmission process described above, information indicating the special figure stop symbol (special figure determination result), information indicating the control state, and the like stored in the RAM 308 is set in the command data. In the above-described general command winning effect start setting transmission process, the command data includes the effect control information and the control state that are stored in the RAM 308 and are output to the decorative symbol display device 208, various lamps 418, and the speaker 120 during the winning effect period. Information indicating the number of the first special figure variable game or the second special figure variable game that is held is set. The first sub control unit 400 that has received the winning effect start command transmits a winning effect control command to the second sub control unit 500 based on the winning effect start command. The second sub-control unit 500 that has received the winning effect control command causes the decorative symbol display device 208 to display an image for notifying the player that the big hit game is started for a predetermined opening effect period (for example, 3 seconds), The jackpot game starts.

  In the above-described general command end effect start setting transmission process, the command data includes the effect control information and the control state stored in the RAM 308 and output to the decorative symbol display device 208, various lamps 418, and the speaker 120 during the effect standby period. Information indicating the number of the first special figure variable game or the second special figure variable game that is held is set. The first sub control unit 400 that has received the end effect start command transmits an end effect control command to the second sub control unit 500 based on the end effect start command. Receiving the end effect control command, the second sub-control unit 500 causes the decorative symbol display device 208 to display an image for informing the player that the big hit is to be ended for a predetermined end effect period (for example, 3 seconds). finish.

  In the general command big prize opening release transmission process described above, information indicating the number of winning rounds stored in the RAM 308, the current number of rounds, information indicating the control state, etc. is set in the command data. In the above-described general command big prize opening closing setting transmission process, the command data, the current round number stored in the RAM 308, information indicating the control state, the first special figure variation game or the second special figure variation held. Information indicating the number of games is set.

  In step S231, a general command special figure hold increase process is also performed. In this general command special figure hold increase processing, special figure identification information (information showing special figure 1 or special figure 2) stored in the transmission information storage area of the RAM 308 in the command data of the special figure hold increase command, the control state And information on the special figure 1 or the special figure 2 determined in advance.

  Furthermore, in this step S231, general command usual figure hold increase processing is also performed. In this general command usual figure hold increase process, information indicating a control state is set in the command data of the general figure hold increase command. In addition, the main control unit 300 also transmits to the first sub-control unit 400 a general map change start command indicating that the normal map display has started (or is) as a general command-related command. Note that the main control unit 300 to the first sub-control unit 400 start (do) the usual figure change stop command indicating that the usual change display has stopped (do), or the pair of blade members 2321. An electric chew opening start command indicating that, or an electric chew closing command indicating that the pair of blade members 2321 are closed (to do) may be transmitted.

  In the first sub-control unit 400, it is possible to determine the production control according to the change of the game control in the main control unit 300 by the command type included in the received output schedule information, and it is included in the output schedule information. Based on the information of the command data, the contents of effect control can be determined. In addition, the first sub-control unit 400 acquires the number of remaining rounds until all the rounds are completed based on the number of rounds included in the command and the current number of rounds.

  In this command setting transmission process, a command is also transmitted to the payout control unit 600 shown in FIG. The output schedule information and the payout request information output to the payout control unit 600 are composed of 1 byte, strobe information (indicating that data is set when turned on) in bit 7, and power-on information in bit 6. (In the case of ON, it indicates that this is the first command transmission after power-on), the current processing type (0-3) for encryption in bits 4-5, and the encrypted processing in bits 0-3 The number of payout requests is indicated.

  Next, in the main controller timer interrupt process shown in FIG. 91, an external output signal setting process (step S233) is performed. In this external output signal setting process, the game information stored in the RAM 308 is output to the information input circuit 350 separate from the pachinko machine 100 via the information output circuit 336. In step S235, device monitoring processing is performed.

  FIG. 95 is a flowchart showing the flow of device monitoring processing. First, in step S235a, information in the internal information register 3101 is acquired. Since step S235a is executed for each timer interrupt, the information in the internal information register 3101 is acquired for each timer interrupt.

  In step S235b, it is determined whether there is an abnormality in the random number generation circuit 318 based on the information acquired in step S235a. Here, the abnormality of the random number generation circuit refers to both abnormality of the frequency monitoring circuit 3182 and abnormality of the random number monitoring circuit 3184. If it is determined that there is an abnormality, the process proceeds to step S235c. If it is not determined that there is an abnormality, the process proceeds to step S235e.

  In step S235c, the random number generation circuit abnormality flag is set to ON. This flag is stored in the RAM 308. More specifically, there are a flag indicating abnormality of the frequency monitoring circuit 3182 and a flag indicating abnormality of the random number monitoring circuit 3184. Hereinafter, these flags may be collectively referred to as a random number generation circuit abnormality flag.

In subsequent step S235d, preparation for transmission of a random number generation circuit abnormality flag setting command is executed, and the process proceeds to step S235e. The random number generation circuit abnormality flag setting command is a command including information that can identify whether the frequency monitoring circuit 3182 is abnormal or the random number monitoring circuit 3184 is abnormal.

  In step S235e, other device monitoring processing is executed. For example, by reading the signal states of various sensors stored in the signal state storage area in step 205 described above, the presence or absence of a glass frame opening error or the bottom pan full error is monitored, and the glass frame open error or bottom pan full error is monitored. Device information indicating whether or not there is a glass frame open error or a lower pan full error is set in the transmission information to be transmitted to the first sub-control unit 400. Also, the various solenoids 332 shown in FIG. 4 are driven to control the opening / closing of the second special figure starting port 232 and the variable winning port 234, and the normal symbol display device 210, the first symbol is displayed via the driving circuits 324, 326, 330. Display data to be output to the first special figure display device 212, the second special figure display device 214, the various status display units 328, and the like is set in the output port of the I / O 310. Further, the output schedule information set in the payout request number transmission process (step S219) is output to the first sub-control unit 400 via the output port of the I / O 310. When these processes are finished, the device monitoring process in step S235 is finished.

  In the subsequent step S237, it is determined whether or not the low voltage signal is on in order to determine whether or not a power interruption (power interruption) has been detected. Then, when the low voltage signal is off (when the power supply cutoff is not detected), the process proceeds to step S239, and when the low voltage signal is on (when the power supply cutoff is detected), the process proceeds to step S241.

  In step S239, a timer interrupt end process is performed. In this timer interrupt end process, the value of each register temporarily saved in step S201 is set in each original register, interrupt permission is set, etc., and then the main control unit main process shown in FIG. 88 is executed. Return. On the other hand, in step S241, a power interruption process for returning to the power interruption state upon power recovery is performed.

  FIG. 96 is a flowchart showing a flow of power interruption processing in the main control unit. In this power interruption process, first, the stack pointer is saved as a return data in a predetermined area of the RAM 308 (step S2431), and then the power status stored in the power status storage area provided in the RAM 308 is updated to information indicating suspend. (Step S2432). Subsequently, a checksum is calculated by adding all the 1-byte data stored in a predetermined area (for example, all areas) of the RAM 308 to a 1-byte register whose initial value is 0, and the calculated checksum Is set in the RAM 308 (step S2433). Finally, access to the RAM 308 is set to be prohibited (step S2433), the power interruption process is terminated, and the pachinko machine 100 is eventually disconnected. When the voltage is restored before the voltage completely decreases, the reset operation is performed by the reset control circuit 314 when the WDT 3141 provided in the reset control circuit 314 shown in FIG. System reset). The main control unit timer interrupt process described above also corresponds to an example of the main process.

  Next, a process of acquiring the special winning random number and the normal winning random number in the winning acceptance process (step S217) shown in FIG. 91 will be described. FIG. 96 is a diagram showing a flow of processing for acquiring the special winning random number and the normal winning random number in the winning acceptance process in step S217.

  In step S217a, it is determined whether or not the random number generation circuit abnormality flag is set to ON. This flag is set in step S235c of FIG. 95, and when the frequency of the random number update clock is abnormal, or the random number updated by the random number update circuit 3183 shown in FIG. 77 is updated normally. If not, the corresponding flag is set to ON. If this flag is set to ON, the winning acceptance process is terminated. If there is no abnormality, the process proceeds to step S217b.

  In step S217b, there is a special signal of FIG. 1 indicating that the first special figure starting port 230 has won, and the number of special figure variable games held is less than a predetermined number (4 in this embodiment). If the result is negative, the process proceeds to step S217f. If the result is positive, the process proceeds to step S217c. In step S217c, the probability variation flag prepared in the RAM 308 is referred to and it is determined whether or not the probability is changing (special figure high probability state). If the probability variation flag is set to OFF, it means that non-probability variation is in progress (special figure low probability state), and step S217d is executed. In step S217d, a random number is acquired from the random number register of channel CH1 of the random number generation circuit 318. In the present embodiment, a similar signal is sent to the CPU separately from the incoming signal that triggers random number latching, and the CPU responds to a signal in a predetermined channel (here, CH1) based on the reception of the signal. Get the latched random number from the random number register. The CPU 304 adds the value of the R register to the obtained random number, and further obtains a value obtained by adding 1 as the special figure 1 winning random number, and proceeds to step S217f. The CPU 304 recognizes the random number generation range set in step S1053a shown in FIG. 23, and performs addition processing based on the random number generation range. That is, when the added value exceeds the maximum value of the random number generation range, the remaining value is added to the minimum value of the random number generation range.

  On the other hand, if the probability variation flag is set to ON, the probability is changing, and step S217e is executed. In this step S217e, a random number is acquired from the random number register of the channel CH2 of the random number generation circuit 318, and as in step S217d, the CPU 304 adds the value of the R register to the acquired random number, and further adds a value obtained by adding 1. 1 is obtained as a winning random number, and the process proceeds to step S217f.

  In step S217f, there is a special signal of FIG. 2 indicating that the second special figure starting port 232 has been won, and the number of special figure variable games held is less than a predetermined number (4 in this embodiment). If the result is negative, the process proceeds to step S217j. If the result is positive, the process proceeds to step S217g. Also in step S217g, as in step S217c, the probability variation flag prepared in the RAM 308 is referred to, and if the probability variation flag is set to OFF (if non-probability variation is in progress), the random number of channel CH1 of the random number generation circuit 318 The random number is acquired from the register, and similarly to step S217d, the CPU 304 adds the value of the R register to the acquired random number, and further obtains a value obtained by adding 1 as a special figure 2 winning random number (step S217h), The process proceeds to step S217j. On the other hand, if the probability variation flag is set to ON (if the probability is changing), the random number is acquired from the random number register of the channel CH2 of the random number generation circuit 318, and similarly to step S217d, the CPU 304 The value of the R register is added to the value, and a value obtained by adding 1 is obtained as the special figure 2 winning random number (step S217i), and the process proceeds to step S217j.

  In step S217j, whether there is a general-purpose entrance signal indicating that a win has been made at the general-purpose start opening 228, and whether the number of general-purpose variable games that are on hold is less than a predetermined number (2 in this embodiment). If the answer is negative, the winning acceptance process ends. If the answer is affirmative, the process proceeds to step S217k. In step S217k, the time reduction flag prepared in the RAM 308 is referred to. If the time reduction flag is set to OFF, it is a normal low probability state (non-electric support), and step S217l is executed. In step S217l, a random number is acquired as a normal winning random number from the random number register of channel CH3 of the random number generation circuit 318, and this winning acceptance process ends. On the other hand, if the time reduction flag is set to ON, it is a normal high probability state (during electric support), and step S217m is executed. In step S217m, a random number is acquired as a regular winning random number from the random number register of channel CH4 of the random number generation circuit 318, and the winning acceptance process is completed.

  Here, based on the content described above, the operation when the voltage supply to the game machine is reduced will be described. For example, when the power is turned off due to a power failure or the like in a big hit state, when the game table is returned to the initial state by turning on the power again, the player becomes extremely disadvantageous. In order to prevent such a situation from occurring, a power interruption process (step S241 in FIG. 91) for holding the state of the game machine with the electric power stored in the capacitor is executed. This power interruption process is executed not only when the power is turned off, but also when the supply voltage temporarily decreases due to factors such as static electricity. Hereinafter, an operation when the power is turned off (hereinafter referred to as “power off”) and an operation when the supply voltage is temporarily reduced (hereinafter referred to as “momentary interruption”) will be described with reference to FIG. FIG. 4A is a diagram showing an operation when the power is off, and FIG. 4B is a diagram showing an operation when there is an instantaneous interruption.

  When the power is turned off, the voltage is not supplied (power interruption occurs), but the voltage does not immediately become 0, but the supply voltage gradually drops due to the electric power stored in the capacitor. When the supply voltage is effective up to a predetermined voltage (9 V in this embodiment), a low voltage signal is transmitted from the voltage monitoring circuit 338 to the CPU 304. By receiving this signal, it is determined that a power interruption has occurred in step S237 of the main control unit timer interrupt process, and the power interruption process in step S241 is executed. FIG. 97 (a) shows that the normal processing is executed until the supply voltage drops to 9V after the power failure occurs, and the power interruption processing is started when the supply voltage becomes 9V. Has been. By this power interruption process, data indicating the state of the game machine is stored in the RAM 308. In the present embodiment, a capacitor is provided that can sufficiently secure the time required for the execution of the power interruption process (main control section power interruption time delay). After that, when the process at the time of power interruption is completed, the apparatus is in a standby state as it is. Thereafter, when the supply of power is not resumed, the voltage drops to 0 and the operation of the game machine stops.

  On the other hand, even in the case of a momentary interruption, a low voltage signal is transmitted from the voltage monitoring circuit 338 to the CPU 304, so that the power interruption process is executed, and then the apparatus enters a standby state. FIG. 97 (b) shows that the power interruption process is started due to a temporary voltage drop. Here, even if the voltage recovers to the operating voltage, the standby state continues. If this standby state continues, WDT 3141 of reset control circuit 314 of main control unit 300 is not restarted (step S203 in FIG. 91 is not executed), and WDT 3141 times out. As a result, the reset control circuit 314 outputs a system reset signal. Thereafter, when the main process of the main control unit shown in FIG. 88 is resumed, the return process (steps S109 to S111) including the data write-back process in step S109 is executed based on the data stored in the power interruption process. . FIG. 97 (b) shows that a reset signal due to timeout of WDT 3141 is transmitted, so that the process shifts from a standby state to a return process (reset process). By this return processing, the state of the gaming table is restored to the state before the processing at the time of power interruption. Here, if there is a problem with the data stored in the power interruption process, it is determined that the state before the power interruption process cannot be restored, and the contents of the RAM 308 are cleared (step S113 in FIG. 88). ).

  Next, the effect of setting a random number generation range by the random number generation circuit 318 of the present embodiment will be described, and then problems will be described. As described above, the random number generation circuit 318 included in the gaming machine of the present embodiment can set a random number generation range that is the basis of the lottery result. Using this function, the game state can be easily set.

  First, the case where the random number generation range is 0 to 65535 will be described. For example, when these random numbers correspond to either winning or losing, an attempt is made to design the winning probability to be 1/400 (0.25%). There are 65536 random numbers to be generated, but when 1/400 of 65536 is calculated, it is 163.84, which is not an integer. If 164 random numbers close to this number are made to correspond, the winning probability is not exactly 1/400.

  Here, it is assumed that the random number generation range is set to 0-49999. Similarly to the above case, in order to make the winning probability 1/400 (0.25%), it is only necessary to match 1/400 of the generated random numbers 50000, that is, 125 values. . For example, the winning probability can be reduced to 1/400 by associating a value of 0 to 124 among 50000 random numbers and associating other values of 125 to 49999 with a loss. That is, the random number generation range (for example, 0 to 49999) and the random number range (for example, 0 to 124) corresponding to the winning can be set so that the winning probability is as designed (for example, 1/400).

  As described above, a desired winning probability can be set by appropriately setting the random number generation range. For example, it is possible to exclude the random number generation range corresponding to the jackpot and leave the random number generation range corresponding to the jackpot, or to prevent generation of random numbers corresponding to half of the random number generation range corresponding to the jackpot. It is. In particular, if a random number generation range as described with reference to FIG. 82 can be set, it becomes easier to design a gaming machine than when only the maximum value is set. For this reason, it can be said that setting the random number generation range is useful in the design of a game machine.

  Next, a method for changing the winning probability by changing the random number generation range will be described. For example, it is assumed that the maximum value of the random number generation range is changed from 49999 to 249 from the state in which the values from 0 to 124 are associated with each other in the random number generation range of 0 to 49999. In this case, the value from 0 to 124 corresponds to the win, the value from 125 to 249 corresponds to the loss, and the winning probability is ½. That is, the winning probability can be easily changed by changing only the random number generation range while fixing the value corresponding to the winning or losing. In the above description, in order to make it easier to understand, the example in which the hit range is biased has been described, but the hit range may not be biased.

  As a method for determining whether it is a hit or a loss based on the generated random number, a method that prepares a table that defines these correspondences and uses this table can be considered. However, if the winning probability is to be changed by this method, it is necessary to prepare a table corresponding to the winning probability and execute a process for selectively using these according to the state of the game. In the above-described method, only one table in which values corresponding to winning or losing are determined is required, so that the memory capacity burden can be reduced. As a matter of course, the process of switching the table is unnecessary.

  In this embodiment, a plurality of random number generation channels having different random number generation ranges are prepared, and the winning probability during the game is changed by using these channels properly. However, the random number generation range is appropriately changed for one channel. The winning probability may be changed by using a configuration to do so. In this embodiment, random numbers may be processed and used for lottery. In this case, a corresponding table may be prepared in consideration of processing.

  Here, a problem when the random number generation range is unintentionally changed will be described with reference to FIG. The figure shows the problem of the random number generation range. For example, it is assumed that the above-described instantaneous interruption occurs due to factors such as static electricity, and then a return process (user reset) is performed. In this case, the internal register of the random number generation circuit 318 is maintained as it is before the return process. However, information in the internal register may be rewritten due to a change in voltage. If the random number generation range is changed unintentionally, the winning probability will change.

  For example, in the non-stochastic fluctuation state, as shown in the upper part of FIG. 98 (a), a random number generation range of 0 to 49999 is set, and further, 0 to 124 (range indicated by left-down hatching) is hit. Is a random number corresponding to. It is assumed that a factor such as static electricity is generated in this state, and the random number generation range becomes 0 to 250. In this case, since the winning probability is reduced from 1/400 to 1/2, the store side is seriously damaged.

  Also, in the probability variation state, as shown in the upper part of FIG. 98 (b), a random number generation range of 0 to 4999 is set, and among these, 0 to 124 (range indicated by left-downward hatching) is the hit. Assume that the corresponding random number. It is assumed that a factor such as static electricity is generated in this state and the random number generation range becomes 0 to 59999. In this case, the winning probability is reduced from 1/40 to 1/480, which is extremely disadvantageous for the player.

  As explained in the above example, if lottery processing is performed using a method that limits the numerical range in which random numbers are generated to an arbitrary numerical range, the lottery processing will not be performed if the numerical range restricted due to some abnormality changes. There arises a problem that it leads to stabilization.

  In order to prevent such a situation, in the gaming machine of this embodiment, in step S1053a in FIG. 90, a process for resetting the random number generation range to a state immediately before the cause of the return process is executed. By re-setting the random number generation range in this way, the above problem can be prevented from occurring. That is, it is possible to prevent the lottery process from becoming unstable while performing the lottery process using a method of limiting the numerical value range in which the random number is generated to an arbitrary numerical value range.

  In this embodiment, since the random number generation range is set when the game machine is started, the state immediately before the cause of the return process is the same as the initial state. For example, the random number generation range is set during the game. In the case of a changeable configuration, a process for returning to the previous state may be executed.

  In addition, as in this embodiment, the random number generation range is reset for a channel for which the random number generation range is set, and the random number generation range is set for a channel for which the random number generation range is not set. In the case of a configuration that is not corrected, there are channels that are initialized and channels that are not initialized. In this case, since it is not known whether the channel is initialized from the outside of the basic circuit 302, there is an effect of preventing fraud.

  Furthermore, in the gaming machine of this embodiment, the random number register 3188 is allowed to be latched in step S1053b of FIG. In this way, when there is an abnormality in the random number latched in the random number register 3188, the frequency with which this random number is used can be lowered. At this time, the content of the random number latch flag register 3189 is rewritten with information indicating that the random number register 3188 is in a state in which the random number can be latched. In this embodiment, the random number register 3188 and the random number generation range are set simultaneously by the user program (see FIG. 89). It may be. In the gaming machine of this embodiment, even if the random number register 3188 enters the permissible state, the random number remains until a new random number is latched, but if possible, the value of the random number register 3188 is set to a predetermined value. You may make it set (for example, set to 0). In this case, it is possible not to use random numbers that may be abnormal.

  When the user reset by the WDT 3141 is executed, the above-described resetting is executed through the determination of the drive voltage (step S103 in FIG. 87) after the user reset is executed (step S1053 in FIG. 87). The time required for this determination process is not constant because it depends on the voltage supply. For this reason, it is possible to give randomness to the timing at which random numbers reflecting the resetting start to be output, which is effective in preventing fraud. Note that the same effect can be obtained in the above-described configuration in which the maximum random number is updated when an update command is received from the CPU 304.

  In the above description, an example of a problem caused by a change in voltage and a countermeasure for the problem has been described. However, for example, a value in the start value selection circuit 3183b of the random number generation circuit 318 may be rewritten. is there. In this case, a value that should not be generated may be output from the random number update circuit 3183. Also for such a problem, as in the example of the random number generation range described above, by executing a process of resetting the value in the start value selection circuit 3183b to the state immediately before the cause of the return process occurs, It is possible to prevent the above problems from occurring. In addition, the value in the start value selection circuit 3183b may be reset separately according to the random number generation range. That is, it is possible to prevent an abnormal operation from occurring due to a voltage change by executing a process of appropriately resetting a value that can be set by the random number generation circuit 318 as necessary.

  In addition to the change in voltage, for example, when an unexpected operation occurs due to traveling outside the specified area, the above-described problem may occur. In particular, when traveling outside the designated area, there is a high possibility that the same situation will be reproduced due to a program mistake or the like, and there is a risk that fraud will be easier than when the voltage changes. Therefore, in the present embodiment, even when traveling outside the designated area occurs, resetting is performed by step S1053a and step S1053b in FIG.

  Here, based on the above description, a supplementary description will be given of the start timing (steps S111 and S115) of WDT 3141 in the main process of the main control unit in FIG. In normal WDT, counting up is performed independently of program execution. With this configuration, even if there is some problem in the execution of the program, the reset operation (user reset) can be executed without being affected by this. For this reason, WDT needs to be activated (reactivated) at the time of initial setting. However, there may be a problem depending on the start timing. This problem will be described with reference to an example in which WDT is activated immediately after initial setting 1 in step S101 in FIG.

  It is assumed that the main process of the main control unit is started in a state where data for restoration is stored in the RAM 308 by the user reset. First, initial setting 1 is executed in step S101, and then WDT is activated. Next, standby processing in step S103 is executed until a sufficient drive voltage is secured.

  For example, when the above-described user reset is executed due to instability of the supply voltage, the execution time of this standby process may become long. If the standby process takes time here,

 In some cases, the WDT times out during execution of step S107 or step S109, and the user reset is executed again. In this case, since the main control unit main process is executed again from the beginning, the processing time until the return data stored in the RAM 308 is returned to the register becomes long.

  Further, for example, in step S109, when the process of returning the data of the RAM 308 to the register and erasing the data of the RAM 308 is executed, the user reset is executed in a state where a part of the data of the RAM 308 is erased. There is also a possibility. In this case, even if the main control unit main process is executed again from the beginning, the restoration data in the RAM 308 is incomplete, and it is not determined that restoration is possible in step S107. Even if it is determined in step S107 that recovery is possible, the data write-back processing in step S109 cannot completely return to the state before the user reset.

  In order to avoid such a problem, in this embodiment, a system reset is executed by a timeout by WDT 3141. However, in this embodiment, a user reset may be further executed by a timeout by WDT 3141. The WDT 3141 is configured to be activated after the drive voltage is determined until the main control unit timer interrupt process is permitted (steps S111 and S115). The above configuration is an example, and WDT 3141 is activated so that WDT 3141 does not time out after main control unit main processing is started after user reset and before main control unit timer interrupt processing is permitted. It is preferable to do. In addition, after the user reset is performed, the main control unit starts the progress of the game (in this embodiment, steps S117 to S119 of the main control unit main process are started, and the main control unit timer interrupt process is started). WDT 3141 is preferably activated so that WDT 3141 does not time out before In particular, the process for returning the game after the user reset (the process for enabling the progress of the game) includes a standby process for executing the initial setting process of the liquid crystal image display device (decorated symbol display device). In such a case, the above problem is more likely to occur, so that the WDT 3141 is activated more effectively at the timing described above. Furthermore, even if the WDT 3141 is activated in the first process of the main control unit timer interrupt process, the above problem can be avoided. In the above description, the case where the user reset is executed is described as an example, but the same applies to the case where the system reset is executed.

  Here, a modification of the random number update circuit 3183 described with reference to FIG. 79 will be described with reference to FIG. This figure shows a modification of the random number update circuit 3183 described in FIG. The random number update circuit 3183n shown in FIG. 99 (a) is obtained by adding a random number sequence change circuit 3183d to the random number update circuit 3183 described in FIG.

  The random number sequence change circuit 3183d is provided with a plurality of random number tables in advance. FIG. 99B shows a plurality of random number sequences in which an array of 65536 random numbers is predetermined. When using these plurality of random number sequences, it is possible to set whether to use the same random number sequence continuously or to change to another random number sequence when one random number sequence is made a round. Furthermore, when changing to another random number sequence, it is possible to set whether to change automatically even if there is no instruction, or whether to instruct a change each time. Note that when a round signal is received from the counter circuit 3183a, it is determined that one round of the random number sequence has been made.

  When the random number sequence to be used in the random number sequence changing circuit 3183d is determined, a value is extracted from this random number sequence according to the count value output from the counter circuit 3183a. This extracted value is output as a random number. For example, in FIG. 99 (b), when it is decided to use the random number sequence B, when a count value “5” is input, “9806” is output as a random number (the thick frame in FIG. 99 (b)). (See the part indicated by).

  Here, an example of processing when the maximum value is set in the maximum value setting register 3183c will be described. In FIG. 81, the example in which the range of values output from the count circuit 3183a is changed according to the maximum value set in the maximum value setting register 3183c has been described. In FIG. 81, the value output from the count circuit 3183a is used as a random number as it is. Here, the value output from the count circuit 3183a is used as a count value instead of a random number, and is input to the random number sequence change circuit 3183d.

  For example, when the maximum value is set to 9999, a count value of 0 to 9999 is output from the count circuit 3183a. Here, the random number sequence change circuit 3183d acquires the maximum value data from the maximum value setting register 3183c, and executes a process of deleting a value exceeding the maximum value from the values of the random number sequence and filling the empty portion. By this process, a random number sequence in which values 0 to 9999 are randomly arranged is prepared. When a value corresponding to the count value is output as a random number using this random number sequence, a random number having a random number generation range of 0 to 9999 can be output. Note that the above method is an example. For example, when a value corresponding to a count value is referred to from a random number sequence and the maximum value is exceeded, subsequent values are sequentially referred to, and the referenced value indicates the maximum value. Other methods may be used, such as outputting a value that does not exceed the value.

  Here, an example of detecting an abnormality in the random number monitoring circuit 3184 when the random number update circuit 3183n is used will be described. In this case, the count value output from the counter circuit 3183a is compared before and after one random number update, and it is checked whether or not the same count value is output. If the same count value is output, information indicating abnormality is output. The check timing may be every predetermined cycle longer than the random number update cycle. The random number monitoring circuit 3184 may monitor the random number output from the random number sequence changing circuit 3183d. However, as described above, the monitoring accuracy is improved by monitoring the count value output from the counter circuit 3138a. At the same time, the monitoring burden can be reduced.

  In addition, as described in the random number generation circuit 318 shown in FIG. 77, a random number monitoring circuit 3183n may be provided outside the random number generation circuit 318, and a random number monitoring circuit 3184 is provided inside the random number update circuit 3183n. May be.

  Next, with reference to FIG. 100, a payout control unit main process executed by the payout control unit 600 shown in FIG. 4 will be described. This figure is a flowchart showing the flow of the main process of the payout control unit.

  The payout control unit 600 shown in FIG. 4 includes a CPU, a RAM, a ROM, an I / O port, and a voltage monitoring circuit. Similarly to the voltage monitoring circuit provided in the main control unit 300, the voltage monitoring circuit provided in the payout control unit 600 has a predetermined voltage value (in this embodiment, the voltage value of the power supplied from the power management unit 650 to the payout control unit 600). If it is less than 9v), a low voltage signal indicating that the voltage has dropped is output to the CPU of the payout control unit 600. Even if a low voltage signal is output from the voltage monitoring circuit 338 of the main control unit 300, the low voltage signal may not be output from the voltage monitoring circuit of the payout control unit 600.

  A command including power-on information is transmitted from the CPU 304 of the main control unit 300 to the payout control unit 600. Based on the reception of this command, the CPU of the payout control unit 600 starts the payout control unit main process.

  First, in step S501, initial setting 1 is performed. In the initial setting 1, the stack initial value is set in the stack pointer (SP) of the CPU of the payout control unit 600. In step S502, it is determined whether or not a low voltage signal is output from the voltage monitoring circuit of the dispensing control unit 600, that is, whether or not the low voltage signal is on. If the low-voltage signal is on (when power-off is detected), the process of step S502 is repeatedly executed. If the low-voltage signal is off (when power-off is not detected), the process proceeds to step S503. move on.

  In step S503, initial setting 2 is performed. In this initial setting 2, a process for setting a numerical value for determining a cycle for executing a payout control unit timer interrupt process, which will be described later, to the counter / timer, a setting for allowing the payout control unit 600 to write to the RAM, I Performs initial setting of / O port.

  In step S504, it is determined whether or not the state before the power interruption (before power interruption) is restored. If the state before the power interruption is not restored (when the pachinko machine 100 is set to the initial state), step S506 is performed. If the process returns to the state before the power interruption, the process proceeds to step S505. Specifically, also in this step S504, processing similar to that in step S111 of the main process of the main control unit 300 is performed, and if RAM clear is necessary, the process proceeds to step S506 in order to set the pachinko machine 100 to the initial state. On the other hand, when the RAM clear is not necessary, the power status information is read from the RAM of the payout control unit 600, and when the power status information is not the information indicating the suspend, the pachinko machine 100 is set to the initial state in step S506. If it is information indicating suspend, the checksum is executed on the RAM of the payout control unit 600. If the checksum result is normal, the process proceeds to step S505 to return to the state before power interruption. If the result of the checksum is abnormal, the process proceeds to step S506 to set the pachinko machine 100 to the initial state. Similarly, if the power status information indicates information other than “suspend”, the process proceeds to step S506.

  In step S505, power recovery processing is performed. In this power recovery process, of the storage area of the payout controller 600 RAM, a storage area to be cleared upon power recovery (a command buffer for storing commands, a memory other than an error status for storing error status, etc.) Area) is initialized.

  In step S506, initialization processing is performed. In this initialization process, interrupt prohibition setting, stack initial value setting to the stack pointer, predetermined areas (for example, all storage areas) of the RAM of the payout control unit 600, and the like are performed.

  In step S507, initial setting 3 is performed. In the initial setting 3, information other than the illegal payout error and the payout excess error among the error statuses stored in the error status storage area provided in the RAM of the payout control unit 600 is cleared, interrupt permission is set, and the like.

  In step S508, it is determined whether there is unanalyzed data in the data input from the main control unit 300. If there is unanalyzed data, command analysis processing is performed in step S509, and there is no unanalyzed data. Then, the process proceeds to step S510.

  In step S510, similarly to step S502, it is monitored whether or not the low voltage signal is off. If the low voltage signal is off (when the power supply shutoff is not detected), the process returns to step S508. If the signal is on (when power-off is detected), the process proceeds to step S511.

In step S511, a power interruption process is performed. In this power interruption process, the current stack pointer value is stored in the stack pointer save area provided in the RAM of the payout control unit 600, and information indicating suspend is set in the power status storage area. Also, all the 1-byte data stored in a predetermined area (for example, all areas) of the RAM of the payout control unit 600 is added to a 1-byte register whose initial value is 0, and a numerical storage area for checksum calculation The value obtained by subtracting the result of addition from the value stored in is calculated as a checksum (checksum at power interruption), and the calculated checksum at power interruption is stored in the above-described numerical storage area for checksum calculation, A setting for prohibiting writing to the RAM of the payout control unit 600 is performed.
<Discharge control unit timer interrupt processing>

  Next, a payout control unit timer interrupt process executed by the CPU of the payout control unit 600 will be described with reference to FIG. This figure is a flowchart showing the flow of the payout control unit timer interrupt process.

  The payout control unit 600 also includes a counter circuit that generates a timer interrupt at a predetermined cycle (in this embodiment, once every 1 ms), and starts the payout control unit timer interrupt processing at a predetermined cycle triggered by this timer interrupt. To do.

  In step S601, timer interrupt start processing is performed. In the timer interrupt start process, a process of temporarily saving the value of each register of the CPU of the payout control unit 600 to the stack area is performed. The payout control unit 600 is also provided with a watch dog timer (WDT). In step S602, the WDT is restarted.

  In step S603, input port state update processing is performed. In this input port state update process, the value of the I / O port of the payout control unit 600 is acquired to detect the state of the payout sensor 604 and the like shown in FIG. In step S604, timer update processing is performed. In this timer update process, various timers are updated, including timers for timing the turn-on / off time of the payout notification LED, the drive / non-drive time of the payout motor 602 shown in FIG.

  In step S605, an error monitoring process is performed. Various error signals such as a lower pan full error signal and a glass frame opening error signal are sent from the main control unit 300 to the I / O port of the payout control unit 600. The RAM of the payout control unit 600 is provided with an error status storage area, a game medium lending information storage area, a payout completion number check storage area, and a motor drive amount storage area. Information corresponding to each error signal is stored in the error status storage area. In this error monitoring process, it is determined whether or not various error signals are ON. If ON, information indicating an error corresponding to the error status storage area is stored. If OFF, the error status storage area is stored. The information indicating the cancellation of the error corresponding to is stored. Further, whether or not communication between the main control unit 300 and the payout control unit 600 is possible is determined based on whether or not a command from the main control unit can be received continuously for a predetermined time (for example, 1000 ms), and an error status is stored. If the communication is possible, information indicating that communication is possible is stored in the area, and if the communication is impossible, information indicating that communication is not possible (main control communication error) is stored. In addition, as to whether or not communication between the card unit (CR unit) 608 and the payout control unit 600 shown in FIG. 4 is possible, is it impossible to continuously receive a signal from the card unit 608 for a predetermined time (for example, 1000 ms)? If the communication is possible in the error status storage area, information indicating that communication is possible is conversely impossible if communication is impossible (CR unit unconnected error) Is stored. In addition, an error release signal is also sent to the I / O port of the payout control unit 600. In this error monitoring process, it is also determined whether or not the error cancellation signal is on. If the error cancellation signal is on, the information stored in the error status storage area is initialized to cancel the error.

  In step S606, CR unit communication processing is performed. In this CR unit communication process, a game medium lending signal is received from the interface unit 606 shown in FIG. 4 to determine whether or not the game medium lending signal sensor signal is on. When the game medium lending signal is on (interface) When a ball lending request is input from the unit 606), information indicating that there is a game medium lending request is stored in the game medium lending information storage area provided in the RAM.

  In step S607, a payout operation management process is performed. In the error status storage area described above, information on illegal payout errors and information on payout excess errors are also stored. In this payout operation management process, the information on the illegal payout error and the payout excess error information are read from the error status storage area, and if neither error has occurred, the signal from the payout sensor 604 shown in FIG. Hereinafter, the number of payouts is monitored based on the payout sensor signal. That is, when a predetermined error has occurred, the driving of the payout motor 602 is stopped, that is, the payout of a prize medium (for example, a game ball) from the payout device is stopped. Specifically, the signal of the payout sensor 604 is detected to determine whether or not the payout sensor signal is on. When the payout sensor signal is on (when the ball passes through the payout sensor), the number of payouts completed. 1 is added to the check and stored in the payout completion number check storage area. Further, when the payout sensor signal is turned on when there is no request for a winning ball or a lending ball, information indicating an illegal payout error is stored in the error status storage area, and the number of winning balls or the number of lending balls is When each request number is exceeded and the number exceeds the predetermined number, information indicating a payout excess error is stored in the error status storage area.

  In addition, the information indicating the bottom full tank error, the information on the illegal payout error, and the information on the payout excess error are read from the error status storage area described above, and when any error has not occurred, the payout start monitoring process, the initial Any one of position search operation processing, normal payout operation processing, retry operation processing, and reverse rotation operation processing is performed.

  As described above, the payout device 152 includes a sprocket that is configured to be rotatable by the payout motor 602. This sprocket temporarily retains the game ball that has passed through the tank rail 154 and flowed down into the payout device 152, and also drives the payout motor 602 to rotate by a predetermined angle, thereby temporarily retaining the game ball. Are delivered one by one downward to the dispensing device 152. In the payout start monitoring process, when the number of lending requests and the number of requested prize balls are 0, and the number of requested next prize balls is other than 0, the number of requested next prize balls is set as the number of requested prize balls, and the next prize ball request Clear the number. When the position of the payout motor 602 is indefinite (when the operation mode is the initial position search operation mode), 1 is subtracted from the payout completion number check and stored in the payout completion number check storage area. When the position is fixed (when the operation mode is the normal payout operation mode), 0 is set in the payout completion number check storage area as a payout completion number check. Also, the requested number of winning balls is converted into an amount for driving the payout motor 602 (motor drive amount), and this is stored in the motor drive amount storage area provided in the RAM, and the motor control data table provided in the RAM is referred to. Then, motor drive control data corresponding to the motor drive amount is selected, and motor drive control data indicating normal rotation is output to the motor control circuit that controls the payout motor 602 via the I / O port. As a result, the motor control circuit changes the excitation position of the motor of the payout motor 602 a predetermined number of times to rotate the sprocket in the forward direction.

  In the initial position search operation process and the normal payout operation process, after the driving of the payout motor 602 is completed, the payout completion check is read from the payout completion number check storage area, and the payout completion check is 0.

 If the payout completion check is other than 0, information indicating the payout device error is set in the error status storage area and the retry operation process is prepared. I do.

  In the retry operation process, wait for a predetermined time to elapse (wait for the retry operation start wait timer to become 0), and when the retry operation start wait timer becomes 0, execute the reverse rotation operation process. Make preparations. In the reverse rotation operation process, motor drive control data corresponding to the motor drive amount is selected with reference to the motor control data table described above, and motor drive control data indicating reverse rotation is output to the motor control circuit via the I / O port. To do. Thus, the motor control circuit changes the excitation position of the payout motor 602 a predetermined number of times to drive the sprocket in the reverse rotation. Further, in the reverse rotation operation process, preparation for executing the payout start monitoring process is performed after the driving of the payout motor 602 is completed.

  In step S608, a payout motor drive monitoring process is performed. In the payout motor drive monitoring process, any one of a drive start monitoring process, an acceleration drive process, a constant speed drive process, a brake drive process, and a drive end process is performed.

  In the drive start monitoring process, the information on the lower pan full tank error, the information on the illegal payout error, and the information on the payout excess error are read from the error status storage area described above. Motor control data corresponding to the motor drive amount is selected with reference to the control data table, and motor drive control data indicating normal rotation is output to the motor control circuit via the I / O port. As a result, the motor control circuit changes the excitation position of the dispensing motor 602 a predetermined number of times to rotate the sprocket in the forward direction.

  In the acceleration drive process and constant speed drive process, 1 is subtracted from the payout completion number check every time the excitation position of the payout motor 602 is changed 16 times, except during the initial position search operation of the sprocket or the reverse rotation operation. And stored in the payout completion number check storage area. When the updated payout completion number check is less than −4, preparation for executing the brake drive process is made. Further, the game medium lending information is read from the above-mentioned game medium lending information storage area, the presence / absence of information indicating that there is a request for lending a game medium is determined, and information indicating that there is a request for lending a game medium is present. In some cases (when a ball lending request is input from the interface unit 606 while paying out a prize ball), preparations for executing the brake driving process are made. In the brake drive process, it waits for a predetermined time to elapse (waits for the motor drive management timer to become 0), and when the motor drive management timer becomes 0, prepares to execute the drive end process In the drive end process, a post-process for driving the motor is performed.

  In step S609, an external output signal setting process is performed. In this external output signal setting process, game information stored in the RAM of the payout control unit 600 (for example, a prize ball signal output every time a payout sensor signal is input) is sent via an information output circuit (not shown). The information is output to an information input circuit 350 that is separate from the pachinko machine 100.

  In step S610, port output processing is performed. In this port output process, a launch permission signal for permitting launch is output from the I / O port of the payout controller 600 to the launch controller 630 shown in FIG. However, when the above-mentioned main control communication error or CR unit non-connection error has occurred, a state is set in which the firing permission signal is not output. Therefore, when the main control unit 300 is cut off and power is supplied to the payout control unit 600, a main control communication error is recognized in the above-described step S605, and a launch permission signal is output in this port output processing. It is set to the state that does not.

In step S611, timer interrupt end processing is performed. In this timer interrupt end process, the value of each register temporarily saved in step S601 is set in each original register, interrupt permission is set, etc., and the payout control unit timer interrupt process ends.
<Second internal information register>

  Next, the second internal information register of the interrupt control circuit 3100 whose first internal information register is shown in FIG. 84 will be described. FIG. 102 is a diagram for explaining the second internal information register prepared in the internal register 3101 of the interrupt control circuit 3100.

  As shown in FIG. 102, the second internal information register is an 8-bit register, but the seventh to third bits remain set to “0” and are not used. The initial values of the 2nd to 0th bits are “0”.

  In this embodiment, a system reset signal is input from the voltage monitoring circuit 338 to the reset control circuit 314 when the power is turned on. Then, the system reset signal 1 is output from the reset control circuit 314 to the internal circuit of the microprocessor 3000 via the internal bus 3300. In this embodiment, when the WDT 3141 times out, the reset control circuit 314 indicates that a WDT timeout signal has been output to the internal circuit of the microprocessor 3000 via the internal bus 3300. A system reset signal 2 is output. Further, when the CPU 304 refers to an address outside the predetermined range (running outside the designated area), the reset control circuit 314 runs outside the designated area via the internal bus 3300 to the circuit inside the microprocessor 3000. A system reset signal 3 indicating that the prohibit signal has been output is output.

  When the interrupt control circuit 3100 acquires the system reset signal 1 via the internal bus 3300, it sets “1” to the second bit. That is, the second bit of the first internal information register corresponds to a bit indicating that the reset factor generated immediately before is a reset due to power-on.

  Further, when the interrupt control circuit 3100 acquires the system reset signal 2 via the internal bus 3300, it sets “1” to the first bit. That is, the first bit of the first internal information register corresponds to a bit indicating that the reset factor generated immediately before is a timeout of WDT 3141.

Furthermore, when the interrupt control circuit 3100 acquires the system reset signal 3 via the internal bus 3300, it sets “1” to the 0th bit. That is, the 0th bit of the first internal information register corresponds to a bit indicating that the reset factor generated immediately before is traveling outside the designated area of the CPU 304. The value of each bit is cleared when the CPU 304 reads the value (becomes the initial value “0”). Note that the second internal information register may be configured by the first internal information register shown in FIG.
<Third internal information register>

  FIG. 103 is a diagram for explaining a third internal information register prepared in the internal register 3101 of the interrupt control circuit 3100. As shown in FIG. 103, the third internal information register is also an 8-bit register, but the seventh and second bits remain set to “0” and are not used.

  The first bit of the third internal information register shown in FIG. 103 is a bit for setting whether to perform a user reset operation or a system reset operation when WDT 3141 times out. “0” is set when the user reset operation is performed, and “1” is set when the system reset operation is performed.

  The 0th bit is a bit for setting whether the user reset operation or the system reset operation is performed when the CPU 304 travels outside the designated area. In this bit, “0” is set when the user reset operation is performed, and “1” is set when the system reset operation is performed.

  The values set for the first bit and the 0th bit described here are stored in the program management area of the built-in ROM 306. These values stored in the program management area are called from the program management area in the initial setting 2 (step S107) in the main process of the main control unit shown in FIG. 88, and are set in the first bit and the 0th bit, respectively. The In this embodiment, “1” is set to cause the system reset operation to be performed on any bit. Note that “0” for performing the user reset operation may be set in the first bit, and “1” for performing the system reset operation may be set in the 0th bit. Further, “1” for performing the system reset operation may be set in the first bit, and “0” for performing the user reset operation may be set in the 0th bit.

This third internal information register may also be composed of the empty bits (unused bits) of the first internal information register shown in FIG. 84, or the empty bits of the second internal information register shown in FIG. (Unused bits) may be used. When a reset occurs, the value of the reset operation setting data stored in the program management area of the ROM 306 may be directly referred to. In this case, the process of setting a value in the third internal information register may not be performed.
<Fourth internal information register>

  FIG. 104 is a diagram for explaining a fourth internal information register prepared in the internal register 3101 of the interrupt control circuit 3100. As shown in FIG. 104, the fourth internal information register is an 8-bit register, but the seventh and second bits remain set to “0” and are not used.

  The first bit of the fourth internal information register is a bit indicating an abnormality in the external clock (update clock) RCK of the random number generation circuit 318. If there is an abnormality in the update clock, the information “1 (abnormal)” is read from the first bit of the fourth internal information register. If there is no abnormality in the update clock, the fourth internal information register Information of “0 (no abnormality)” is read from the first bit.

The 0th bit is a bit for indicating whether or not the immediately preceding reset factor is a system reset (reset upon power-on) when a reset occurs. When the interrupt control circuit 3100 acquires the system reset signal 1 via the internal bus 3300, the interrupt control circuit 3100 sets “1” to the 0th bit. If the immediately preceding reset factor is a system reset, information “1 (system reset has occurred)” is read from the 0th bit of the fourth internal information register, and if the immediately preceding reset factor is not a system reset (reset factor Is the time-out of WDT 3141, or when the reset factor is running outside the designated area of CPU 304), the information of “0 (system reset has not occurred)” is read from the 0th bit of the fourth internal information register Is done.
<Other internal information registers>

  Although not shown, the microprocessor 3000 includes a start register and a clear register as registers for controlling the WDT 3141. The start register is an 8-bit register for controlling start / stop of the WDT 3141. When starting the WDT 3141, a value (for example, CCh) instructing start is set (written) and stopped when the WDT 3141 is stopped. Is set so as to set a value (for example, 33h).

  This start register is valid when “start by software” is set (selected) in the program management area at the time of reset. In this case, a stop instruction value (for example, 33h) is set as an initial value. Is set. Therefore, in order to activate WDT 3141 when “activation by software” is set (selected), it is necessary to set a value (for example, CCh) instructing activation by the game control program (manually). On the other hand, when “activation by software” is not set (selected) at the time of resetting, a value instructing activation (for example, CCh) is an initial value (automatically) regardless of the game control program. The WDT 3141 is activated (automatically) without depending on the game control program.

  The clear register is an 8-bit register for controlling clearing and restarting of the WDT 3141. After setting a predetermined first value (for example, 55h), a predetermined second value (for example, AAh) Is set, WDT 3141 is cleared and restarted immediately after. When the value of the clear register is read, a predetermined fixed value (for example, FFh) is read.

  Here, the flow of system reset will be described again, including the relationship with random number update. FIG. 105 is a diagram showing the flow of system reset including the relationship with random number update. Up to now, it has been described that when a momentary interruption occurs due to factors such as static electricity, the reset control circuit 314 outputs a system reset signal (here, the system reset signal 2) due to the timeout of the WDT 3141, and the reset operation is performed. Further, not only the timeout of WDT 3141 but also, for example, when the CPU 304 runs out of the designated area, the system reset signal (here, system reset signal 3) is output from the reset control circuit 314, and the reset operation is performed. . In this reset operation, the gaming machine shifts to the security mode, and a security check process (step SH05 shown in FIG. 76) is executed.

  The time-out of WDT 3141 and the running out of the designated area of CPU 304 correspond to an example of an abnormality that hinders normal progress of the game process. The system reset signal 2 and the system reset signal 3 correspond to an example of a return instruction. Further, the reset control circuit 314 illustrated in FIG. 76 corresponds to an example of an abnormality detection unit that detects the abnormality.

  Although not shown in FIG. 105, in the security mode, first, the first internal circuit initialization process in step SH03 shown in FIG. 76 is executed, and the core of the CPU 304, the timer circuit 311, the counter circuit 312, and the parallel input port 3102 are executed. The values of built-in registers such as the RAM 308 access protect register, the interrupt control circuit 3100, and the register that controls the random number generation circuit 318 are initialized. Since the register that controls the random number generation circuit 318 is initialized, the random number update range is reset, and the initial value of the random number is also reset. In particular, when traveling outside the designated area of the CPU 304 occurs, it is preferable that the random number update range is reset because there is a possibility that the random number update range has some influence.

  Subsequently, a fixed extension process (step SH07) is performed. When this fixed extension process is completed, the reset control circuit 314 sends a reset output terminal (XRSTO terminal) to the peripheral control circuit outside the microprocessor 3000. Output a reset signal. That is, the reset signal (reset output) from the XRSTO terminal is output after the end of the fixed extension process (during the security mode), and is output at a timing different from the start of the user mode.

  Next, a random extension process (step SH09) is performed, and the delay process time becomes indefinite. When the random extension process is completed, the gaming machine shifts to the user mode, and a game control program (in this case, the main control unit main process) is started.

  In this game control program, first, various initial settings (steps S101 to S115 shown in FIG. 88) are performed. In this initial setting, as shown in FIG. 106 (a), after reading the value of “bit indicating update clock abnormality” from the first bit of the fourth internal information register, the read value is set in the general-purpose register. On the other hand, while the process of reading (writing) is executed, the process of reading “the bit indicating whether or not the reset factor is a system reset” is executed from the 0th bit of the fourth internal information register. It is configured not to execute the process of setting (writing).

  In other words, as shown in FIG. 7B, the microprocessor 3000 uses the bits (for example, the fourth information register) that change based on the first factor (for example, the state of the update clock of the random number generation circuit 318). While reading the value of bit 1) of the internal information register and setting (writing) the read value in the general-purpose register, it changes based on a second factor (for example, a reset factor) different from the first factor A value of the bit of the internal information register (for example, bit 0 of the fourth internal information register) is read, but the read value is not set (not written) in the general-purpose register.

  When the initial setting is completed, the software random number update process (step S117 and step S119) is performed, and then the first big hit random number acquisition timing is reached. Here, if a random number is illegally acquired at the first big hit random number acquisition timing, the big hit may be forced. However, since the time of delay processing is indefinite due to the random extension processing, the above-mentioned predetermined time is also indefinite even if the above-mentioned reset output is caught illegally and the timing for acquiring the first big hit random number is attempted. Therefore, cheating can be prevented.

  FIG. 107 is a diagram showing a modification of the reset control circuit 314 of the microprocessor 3000 shown in FIG. The reset circuit 1314 according to this modification includes a signal output timing control circuit 1314a instead of the out-of-designated area travel prohibition circuit 3142 and the watchdog timer (WDT) 3141 included in the reset control circuit 314 shown in FIG. The signal output timing control circuit 1314a is a circuit for determining the output timing of the reset output signal output from the reset output terminal XRSTO based on the reset input signals input from the two reset input terminals XSRST1 and XSRST2. is there.

  FIG. 108 is a timing chart showing an example in the case where a timeout of WDT 3141 occurs only in main control unit 300 out of main control unit 300 and first sub control unit 400. In the timing chart shown in FIG. 108, time (T) elapses from the left to the right in the figure. In the state at the left end of the figure, a voltage of 12 V is supplied to both the main control unit 300 and the first sub control unit 400, and both the main control unit 300 and the first sub control unit 400 perform normal processing. In this example, the main control unit 300 starts the special figure variation display, and the first sub control unit 400 performs the second sub control (not shown here) in accordance with the start of the special figure fluctuation display by the main control unit 300. Via the unit 500, the decorative symbol display device 208 starts the variable display of decorative symbols. The symbols (a) to (g) in the timing chart shown in FIG. 108 indicate the timing of the position where the symbol is written, and the state of the decorative symbol display device 208 at that timing is shown below FIG. It is shown.

  Shortly after the main control unit 300 starts displaying the special figure fluctuation, an instantaneous interruption occurs in the main control unit 300, and a process at the time of power interruption is performed due to a temporary voltage drop, and a transition is made to a standby state. As described with reference to FIG. 97 (b), in the standby state, the WDT 3141 of the main control unit 300 is not restarted, and the WDT 3141 times out. A system reset signal 2 is output from the reset control circuit 314 based on the timeout of the WDT 3141.

  When the system reset signal 2 is output, the main control unit 300 starts the reset process shown in FIG. In the main control unit 300, after the first internal circuit initialization process (step SH03) is executed in this reset process, the security check process (step SH05) is executed. Then, even if the security check process is completed, the user mode (main control unit main process shown in FIG. 88) is not immediately shifted, the delay process is performed, and the reset process is continued. In this delay process, the fixed extension process (step SH07) shown in FIG. 76 is executed. As described above, when the fixed extension process is completed, the reset control circuit 314 outputs a reset signal from the reset output terminal (XRSTO terminal) to the peripheral control circuit outside the microprocessor 3000. The signal is not transmitted to the first sub control unit 400. Further, in the delay process, a random extension process (step SH09) is executed, and the transition to the user mode is further delayed by a random time of a maximum of 30 seconds. These steps SH07 and SH09 correspond to an example of the delay processing referred to in the present invention.

  Further, as described above, when the dispensing control unit 600 shown in FIG. 4 cannot receive a command from the main control unit 300 until a predetermined time (for example, 1000 ms) elapses after the power interruption process is started. Then, the output of the firing permission signal to the firing control unit 630 is stopped.

  On the other hand, in this example, although the main control unit 300 has an instantaneous interruption, the first sub-control unit 400 is continuously supplied with a voltage of 12 V, and the main control unit 300 performs the power interruption process and the reset process. The first sub-control unit 400 continues normal processing even during the process. As a result, the effect executing means continues the effect, and the decorative symbol display device 208 continues to display the decorative symbol fluctuating, and it is shortly after the main control unit 300 starts the power interruption process (b). At this timing, the decorative symbol is stopped and displayed in the left symbol display area 208a (so-called left symbol stop). At the timing (c), the decorative symbol is stopped and displayed in the right symbol display area 208c (so-called right symbol stop), and the reach state is reached. Subsequently, at the timing of (d), it develops into a special reach (here, so-called triple reach), at the timing of (e), a reach-off effect is once performed, and at the timing of (f), a combination of decorative symbols ( Here, “decoration 5—decoration 4—decoration 5”) fluctuates and fluctuates. Based on the fact that the symbol variation stop command is sent from the main control unit 300, the first sub-control unit 400 completely stops the combination of the decorative symbols and performs the fixed stop. However, no command is transmitted from the main control unit 300 to the first sub-control unit 400 while the main control unit 300 is performing a power interruption process or a reset process.

  As a result, the fluctuation of the shaking continues even if the fluctuation time of the special figure elapses. Players who have seen fluctuations that continue to forever are worried that the pachinko machine 100 may have broken, and can expect to call a store clerk at the amusement store, informing the game store clerk that a momentary break or reset has occurred. May be possible. In other words, in the conventional game machine, a technique has been devised to perform a reset process when a reset occurs due to an instantaneous voltage drop due to static electricity or the like during the game, but the reset process takes only a short time. Although the store side could not grasp the occurrence of the reset and could not allow the game machine to perform stable control, according to the game machine of this embodiment, by delaying the start of game control, The game store clerk can grasp the occurrence of the reset. Further, since the game store clerk can grasp the occurrence of the reset, it is possible to cause the game machine to perform stable control by eliminating the cause of the occurrence of the reset (for example, by separating the wiring on the back of the game machine). Furthermore, in this example, the out-of-reach performance is performed, but if the fluctuation of fluctuation continues more than usual after the per-reach performance, the pachinko machine is expected for the player who expected the big hit. It is possible to further raise the player's anxiety that the 100 may have broken and changed so that it does not become an advantageous state, letting the player call the store clerk, that the game store clerk had a momentary break You may be able to inform.

  Further, during the period when the reset process is being performed, the output of the launch permission signal is stopped, and the game ball cannot be launched from the launch device 110. For this reason, although the display by the decorative symbol display device 208 is continued, the game ball is not fired no matter how many times the ball launch handle 134 shown in FIG. 1 is operated, and the player may have broken the pachinko machine 100. I am worried that there may be a chance, I can expect to call a store clerk at the amusement store, and I may be able to inform the amusement store clerk that an interruption or reset has occurred. In other words, the game store clerk may be able to grasp the occurrence of the reset via the player by stopping the launch during the delay process.

  Further, a clear signal is output to each circuit (for example, the drive circuits 324 to 334) of the main control unit 300 at a timing when the XRSTO signal falls, and the main control unit 300 is driven, the special figure display device 210, the first special figure display device 212, the second special figure display device 214, the universal figure hold lamp 216, the first special figure hold lamp 218, and the second special figure. The game display means such as the hold lamp 220 and the high-probability lamp 222 are not displayed, and the player who notices these non-displays is anxious that the pachinko machine 100 is broken, and is a store clerk of the game store. Can be expected to inform the game store clerk that a momentary interruption or reset has occurred. In particular, the display device for displaying the status based on the rights acquired by the player, such as the general figure hold lamp 216, the first special figure hold lamp 218, the second special figure hold lamp 220, and the high accuracy medium lamp 222, is not provided. When it is displayed, the pachinko machine 100 is broken and the player's anxiety that the acquired rights have been lost can be further exaggerated. It may be possible to notify that a disconnection or reset has occurred. Also, from a different perspective, the store clerk can be given an opportunity to apologize to the player, communicate with the player, and help to realize a cozy game store.

  In the main control unit 300, when the random extension process (step SH09) ends, the main control unit 300 first shifts to the user mode and starts the normal process (main control unit main process shown in FIG. 88). In the main process of the main control unit shown in FIG. 88, since the supply voltage to the main control unit 300 has returned to 12 V, the initial setting 2 shown in FIG. 89 is performed, and the first sub-control unit 400 includes A clear signal is output for the first time (step S1052). The first sub-control unit 400 performs various initial settings when receiving the clear signal. With this initial setting, the initial design screen (default screen) is displayed on the decorative symbol display device 208. Note that the default screen is displayed on the decorative symbol display device 208 even when a timeout occurs in the WDT 3141 of the first sub-control unit 400. At the timing (g) shown in FIG. 108, a character display “Please wait” is displayed on the decorative symbol display device 208. That is, the screen of the decorative symbol display device 208 is switched to a character display screen of “Please wait” from the shaking fluctuation that has not ended indefinitely, and the player who was watching this series of displays broke the pachinko machine 100. I am worried that it may have been, I can expect to call a store clerk at the amusement store, and may be able to inform the amusement store clerk that a momentary break has occurred.

  When the main control unit main process is started, a command is transmitted from the main control unit 300 to the payout control unit 600, and a launch permission signal is output to the launch control unit 630, and the game ball is fired. Will be able to.

  In this example, the timing at which the main control unit 300 shifts from the reset process to the normal process is during the fluctuation fluctuation of the decorative symbol combination (after the timing (f)), but before the fluctuation fluctuation (timing (f). Even before, a default screen is displayed on the decorative symbol display device 208.

  FIG. 108 described above is an example in the case where a timeout of WDT 3141 occurs. Similarly, when a run out of the designated area of CPU 304 occurs, the game store clerk can grasp the occurrence of reset via the player. Thus, it is possible to cause the game machine to perform stable control. In addition, even if other abnormalities such as resetting occur, if the system reset operation is performed, a delay process is executed during the system reset, and the game store clerk detects the occurrence of the reset via the player. In some cases, the game table can be grasped and stable control can be performed.

  In the above description, “a game control unit (for example, a game process related to a game including a main process (for example, steps S117 and S119, and a main control unit timer interrupt process) that is repeatedly executed until power-off is detected) (for example, , The main control unit 300), and the game control unit detecting an abnormality (for example, time-out of the WDT 3141 or running out of the designated area of the CPU 304) that prevents normal progress of the game process while the game process is being executed. Provided with an electrical control means (for example, a microprocessor 3000) provided with an abnormality detection unit (for example, a reset control circuit 314) for performing a return instruction (for example, system reset signals 2 and 3), and the game control unit (for example, The main control unit 300) stops the execution of the game process based on the return instruction, and The air control means (for example, the microprocessor 3000) performs a return process (for example, a system reset operation) for the game control unit to start execution of the game process based on the return instruction, and performs the return process. A game machine characterized by executing a delay process (for example, steps SH07 and SH09) for delaying the start of the game process during the execution. Is explained.

  Here, a storage unit (for example, a built-in ROM 306) that stores a game process program for the game process is provided, and the electrical control means performs an initialization process (for example, in step SH03) for resuming the execution of the game process. The first internal circuit initialization process) is performed based on the return instruction, and the game control unit suspends execution of the game process based on the return instruction, and the initialization process is performed. Thereafter, the game process program is sequentially read out from the storage unit and the game process is resumed, and the electrical control means is a period between the completion of the initialization process and the start of the game process. In addition, a delay process for delaying the start timing of the game process may be executed. That is, the return process here is a process that combines the initialization process and the delay process.

  Also, a game control means for executing a game process relating to a game including a main process that is repeatedly executed until power-off is detected, and an abnormality that prevents the progress of the game process while the game control means is executing the game process An abnormality detecting means for giving a return instruction based on the detection of the game, and the game control means stops the execution of the game process based on the return instruction and resumes the execution of the game process. A gaming machine that performs processing, and executes delay processing that delays resumption of the game processing during execution of the return processing. The aspect of this may be sufficient. According to this aspect, instead of the means that can perform both hardware processing and software processing such as the electrical control means, the return processing is performed by means that performs only software processing such as game control means, The delay process is executed while the return process is being executed. The game processing program includes a first storage unit storing a game processing program for the game process and a second storage unit storing a return program for the return process, and the game control unit is configured to receive the game processing program from the first storage unit. Are sequentially read out to execute the game process, and the electrical control means may execute the return process according to the return program.

  In this case, stable game control may be performed. In other words, by delaying the start of game control, the game store clerk may be able to grasp the occurrence of reset via the player. In addition, since the game store clerk can grasp the occurrence of the reset, it is possible to identify and deal with the cause of the reset (for example, an electrical component that generates static electricity) (for example, review the layout of the wiring behind the game table) In some cases, the game machine can be controlled stably. In addition, since the game process is not performed during the return process, the process based on the entry is performed even if the game ball rolling in the game area when the reset occurs enters the first special figure starting port 230 during the return process. In some cases, it is possible to make the game store clerk easy to call with anxiety. In addition, the game store clerk may be able to confirm the state of the game table by manually inserting the game ball into the first special figure starting port 230 or the like. In addition, since the game process is not performed during the return process, even if the main body 104 or the front frame door 106 is opened, the process based on the opening is not performed, and the game store clerk opens the main body 104 or the front frame door 106, You may be able to check the status of the game console.

  Further, in the above description, “the electrical control means (for example, the microprocessor 3000) performs a security check process for determining whether or not an abnormality has occurred during the return process (for example, the security in step SH05). A game machine characterized by a check process). Is also explained.

  In this case, since the security check process is also performed during the return process, the time during which the return process is being performed can be used effectively, and security can be improved.

  The abnormality detection unit detects a first return instruction (for example, a system reset) among the return instructions based on a first abnormality (for example, traveling outside the designated area of the CPU 304) among the abnormalities. Signal) and a second return instruction (for example, a user reset signal) of the return instructions based on the presence of a second abnormality (for example, timeout of WDT 3141) among the abnormalities. The electrical control means executes the delay process while executing the return process based on the first return instruction, and executes the return process based on the second return instruction. The delay process may not be executed during the operation.

  In this case, since the time until the game process is started differs depending on the type of abnormality, the game store clerk may be able to determine the type of abnormality.

  The first abnormality may have a higher degree of abnormality than the second abnormality.

  In this case, since the delay process is performed in the return process when the first abnormality having a high degree of abnormality occurs, the game clerk may be able to confirm that a reset based on the abnormality having a high degree of abnormality has occurred. .

  Further, the electrical control means executes the security check process while executing the return process based on the first return instruction, and performs the return process based on the second return instruction. The security check process may not be executed during the execution.

  In addition, a launching unit (e.g., launching device 110) that launches a game ball toward the game area is provided, and the launching unit stops launching the game ball while the delay process is being executed. Also good.

  In this case, the player is worried that the pachinko machine 100 may have broken, and can expect to call a store clerk at the amusement store, and may be able to notify the game store clerk that an instantaneous interruption or reset has occurred. is there. In other words, the game store clerk may be able to grasp the occurrence of the reset via the player by stopping the launch during the delay process.

  In addition, a storage unit (for example, a built-in ROM 306) that stores a game processing program for the game processing is provided, and the game control unit (for example, the main control unit 300) reads the game processing program from the storage unit and stores the game The storage unit (for example, the built-in ROM 306) receives predetermined authentication information (for example, an authentication code) obtained based on the contents (for example, a user program) stored in the storage unit. The electrical control means (for example, the microprocessor 3000) acquires the authentication information during the return process based on the content stored in the storage unit, and the acquired authentication information is stored in the storage unit. Case in memory

 It may be determined during the restoration process (for example, the security check process in step SH05 is performed) whether or not it matches the predetermined authentication information stored.

  In this case, since it is determined whether or not it matches the predetermined authentication information during the return process, the time during which the return process is performed can be used effectively, and security can be improved. There is a case.

  The electrical control unit may execute the delay process based on the fact that the acquired authentication information matches the predetermined authentication information stored in the storage unit.

  The game control unit may stop the operation based on the fact that the acquired authentication information does not match the predetermined authentication information stored in the storage unit.

  Further, the electrical control means is configured to delay the start of the gaming process by a predetermined time (for example, a fixed extension process at step SH07) and a second delay process (for example, a variable time delay). , Random extension process in step SH09) may be performed.

  The electrical control means performs a first delay process for delaying the start of the game process for a predetermined time, and then performs a reset instruction (for example, a reset signal from a reset output terminal (XRSTO terminal)) to the outside. ), And then a second delay process that delays the start of the game process by a variable time may be performed. The changeable time here may be a time selected from a plurality of prepared times at the time of manufacture or setting of the electrical control means, or may be a time that can be arbitrarily changed. Good.

  In this case, since the start timing of the game process and the output timing of the reset instruction to the outside are different, it is possible for an unauthorized person to make it difficult to analyze the initial timing at which an advantageous random number can be obtained. It may be possible to prevent the act.

  In addition, the game control unit may perform a predetermined lottery process (for example, determination of whether or not a special figure is appropriate) using a numerical value that is repeatedly updated and updated in a predetermined numerical range (for example, a random number generation range) in the gaming process. The electrical control means initializes the numerical value in the return process (for example, executes the first internal circuit initialization process in step SH03). Also good.

  In addition, game display means controlled by the game control unit (for example, the common figure display device 210, the first special figure display device 212, the second special figure display device 214, the common figure holding lamp 216, the first A special figure holding lamp 218, a second special figure holding lamp 220, and a high-probability medium lamp 222), and the game display means is not displayed while the delay process is being executed. Good.

  In this case, since the game display means should not be displayed, there is a case where it is possible to make the game store clerk easy to call with anxiety. In addition, the game store clerk may be able to check the state of the game table by putting the game ball into the first starting port 230 or the like by hand.

  In addition, variable winning means (for example, the second special figure starting port 232, variable) that can be changed between a first state in which a game ball can enter and a second state in which a game ball is difficult to enter than the first state. The variable winning means may change to the second state based on the return instruction in the first state.

  In this case, since the variable winning means should be in the first state but in the second state, the game store clerk may be able to be called easily by making the player uneasy. In addition, the game store clerk may be able to check the state of the game table by putting the game ball into the first starting port 230 or the like by hand. The variable winning means may maintain the first state based on the return instruction in the first state. In this case, since the first state is maintained for a predetermined time (for example, opening time) for a predetermined time, it may be possible to make the game store clerk easy to call with anxiety.

  In addition, an effect execution means (for example, a decorative symbol display device 208) that executes an effect based on an instruction from the game control unit is provided, and the effect execution means continues the effect while the delay process is being executed. You may do. Here, the effect executing means may have a larger display area than the game display means.

  In this case, it may be possible to prevent the player from being bored during the delay process.

   The electrical control means selectively executes a first return process and a second return process based on the return instruction, and stores a return operation of the first return process. A storage unit, and a second return operation storage unit that stores a return operation of the second return process, and the electrical control means stores the first return operation memory when the first return process is selected. The first return process is executed according to the return operation stored in the unit, and when the second return process is selected, the second return process is executed according to the return operation stored in the second return operation storage unit. It may be executed.

  Further, the game control unit performs a predetermined lottery process using a numerical value that is repeatedly updated and updated within a predetermined numerical value range in the gaming process, and the electrical control means includes: Based on the return instruction, a first return process for initializing the numerical value (for example, a first internal circuit initialization process in step SH03) and a second value for holding the numerical value at a value before the return instruction is given. The return process (for example, the second internal circuit initialization process in step SH11) may be selectively executed.

  Further, the present invention may be applied to an enclosed game machine that circulates and uses a predetermined number of game balls. In addition, the main control unit 300 and the sub control unit 400 may be bi-directional communication, or a single control unit having the functions of the main control unit 300 and the sub control unit 400 may be provided instead.

  Conventionally, as a game stand, there are obstacles that change the direction of the fall of the game ball in the game area of the game board, a winning opening, a starting opening, a variable winning opening, etc. that can be used for winning the game ball. There is known a ball game machine (pachinko machine) that gives a player a privilege such as paying out a prize ball when winning a prize. This ball game machine is advantageous to the player by performing a lottery process for determining whether or not the game ball has entered the starting port and opening the variable prize opening for a predetermined time according to the result of the determination. A game state is generated.

  In addition, when the reel is rotated by inserting a medal (game medium) and operating the start lever, the winning combination is determined internally by internal lottery, and the reel is stopped by operating the stop button. If a combination of symbols that is predetermined according to the internal decision is displayed on the window, a winning combination is established. If a winning combination that involves paying out medals is achieved, a special number of medals are paid out. Also known is a slot machine.

  By the way, during the operation of the game store, an abnormality may occur in the electrical system of the game machine, and the power supply of the game machine may be cut off (power interruption). After the power is turned off, the game table is automatically restored immediately (power is turned on) so that the game is not hindered. For this reason, the game store may not be aware of the fact that the game stand has been disconnected. In addition, if any abnormality occurs, such as when the game machine program operates unexpectedly, a reset is temporarily applied. However, even if an abnormality that requires a reset occurs, the game automatically returns immediately so that there is no problem with the game.

  There are a variety of causes for abnormalities in the electrical system of the game console and the causes of abnormalities that may cause a reset. The game store may experience a power outage or be reset. There is a case where it is desired to grasp on the spot that an abnormal abnormality has occurred.

On the other hand, according to the above-mentioned game machine, it is easy to give the game store an opportunity to grasp on the spot that an abnormality of the electric system has occurred or that an abnormality that requires resetting has occurred. In addition, by delaying the start of the game control, the game store clerk can grasp the occurrence of the reset through the player, and the game store clerk identifies and deals with the cause of the reset (for example, the layout of the wiring behind the game table) Etc.), and may allow the game stand to perform stable control.
In the following, we will add that we have explained so far.

(Appendix 1)
Game control means for performing game control including a plurality of types of processing relating to games;
An abnormality detecting means for detecting an abnormality related to the progress of the process of the game control means and instructing a return to the game control means when the abnormality is detected;
A voltage supply means for supplying a predetermined voltage to the game control means and the abnormality detection means,
The game control means includes
Performing a return process performed based on receiving the return instruction from the abnormality detection means, and a main process that is started after the return process and repeatedly executed until a predetermined end condition is satisfied,
The game table characterized in that the return process includes a delay process for delaying the start of the game control.

(Appendix 2)
Random number generation means for generating a random number and capable of setting a random number generation range that is a numerical range in which the random number is generated (random number generation circuit 318 in the first embodiment, random number generation circuit 316 ′ in the second embodiment) )When,
Game control means (CPU 304 in the first embodiment, CPU 304 ′ in the second embodiment) for performing a plurality of types of processing relating to the game, including lottery processing using random numbers generated by the random number generation means;
A process for detecting whether or not there is an abnormality related to the progress of the process of the game control means is executed, and when the abnormality is detected, the process of the game control means is restarted from a specific process and the game control means An abnormality detection means (a reset control circuit 314 in the first embodiment, a reset control circuit 314 in the second embodiment) that performs a return instruction (system reset or user reset) for returning the processing to normal to the game control means. ')
The random number generation means includes
A generation range update process (step S1053 in FIG. 89) for updating the random number generation range based on receiving a random number range setting instruction for setting the random number generation range from the game control means;
The game control means includes
When receiving the return instruction from the abnormality detection means, the random number range setting instruction for setting the same numerical range as the random number generation range set before the return instruction is performed as the random number generation range. A game machine (game machine 100 according to the first embodiment, slot machine 100 ′ according to the second embodiment), which is performed on the random number generation means (step S1053 in FIG. 89).

(Appendix 3)
A game machine according to appendix 2,
The abnormality detection means includes
Based on the fact that the elapsed time starts to be measured based on the establishment of a predetermined start condition, whether or not the elapsed time has exceeded a specific time, and determined that the elapsed time has exceeded the specific time A game table characterized by giving a return instruction to the game control means (see the description of WDT 3141 in FIG. 6).

(Appendix 4)
Random number generation means (random number generation circuit 318 in the first embodiment, random number generation circuit 316 ′ in the second embodiment) that generates a random number that is updated every predetermined period within a predetermined numerical range and is used for lottery related to games,
Update abnormality detection means (frequency monitoring circuit 3182 and random number monitoring circuit 3184) for detecting an abnormality related to the update of the random number;
An abnormality detection information holding unit (internal information) that holds abnormality detection information indicating that the abnormality is detected by the abnormality detection unit until a predetermined condition is satisfied based on detection of the abnormality by the abnormality detection unit. Register 3101),
An abnormality handling processing unit (first operation) that performs a predetermined abnormality handling process by referring to the abnormality detection information holding unit at a predetermined timing and based on the fact that the abnormality detection information is held by the abnormality detection information holding unit. 95. A game table comprising a CPU 304 and a device monitoring process and winning acceptance process of FIG. 95 in the embodiment, and a CPU 304 ′ and a device monitoring process in the second embodiment.

(Appendix 5)
A gaming machine according to appendix 4,
The abnormality detection information holding means is
A game characterized in that the abnormality detection information is erased on the basis of being referenced by the abnormality handling processing means in a state where the abnormality detection information is held (refer to the explanation of the internal information register). Stand.
<First Modification of Main Control Unit>

  FIG. 109A is a diagram showing a first modification of the configuration of the main control unit. In this example, the CPU 304 includes a reset signal input terminal XSRST, and a random delay circuit 317 is connected to the reset signal input terminal XSRST. Note that the letter “X” attached to the head of the terminal name indicates that the signal input to and output from the terminal is low active, but it goes without saying that the signal may be high active (the same applies hereinafter).

  The random delay circuit 317 has two input terminals, a low voltage signal output from the voltage monitoring circuit 338 and a WDT activation signal output from the WDT 314. The voltage monitoring circuit 338 is a low voltage signal indicating that the voltage has dropped when the voltage value of the power source supplied from the power source control unit 660 to the main control unit 300 is less than a predetermined value (9v in this embodiment). (For example, an L level signal) is output. Further, the WDT 314 outputs a WDT activation signal (for example, an L level signal) due to a timeout of the WDT.

The random delay circuit 317 inputs the low voltage signal output from the voltage monitoring circuit 338 or the WDT activation signal output from the WDT 314 from the input terminal, waits for the delay time selected at random, and receives the input signal. It outputs toward the reset signal input terminal XSRST of the CPU 304. As described with reference to FIG. 9, the CPU 304 inputs an H level signal after an L level signal is input to the reset signal input terminal XSRST for a predetermined period (for example, a period corresponding to four cycles of the system clock). System reset (initialization). Therefore, in this example, the CPU 304 is reset (initialized) based on a signal obtained by adding a delay time to either the low voltage signal output from the voltage monitoring circuit 338 or the WDT activation signal output from the WDT 314. The
<Second Modification of Main Control Unit>

  FIG. 109B is a diagram showing a second modification of the configuration of the main control unit. In this example, the WDT activation signal output from the WDT 314 is directly output to the reset signal input terminal XSRST of the CPU 304 without going through the random delay circuit 317. Therefore, in this example, the CPU 304 performs a system operation based on a signal obtained by delaying the output timing of the low voltage signal output from the voltage monitoring circuit 338 by a delay time or a WDT activation signal (no delay time) output from the WDT 314. It is reset (initialized).

FIG. 6C is a diagram showing a configuration example of a reset circuit configured to include the random delay circuit 317, the voltage monitoring circuit 338, and the WDT 314 described above. In this example, the CPU 304 outputs (1) a system reset based on the WDT activation signal (no delay time) output from the WDT 314, and (2) outputs the WDT activation signal output from the WDT 314 for the delay time selected by the random delay circuit 317. One of three states: system reset based on a signal with delayed timing, and (3) system reset based on only a low voltage signal without inputting the WDT activation signal output from the WDT 314 to the reset signal input terminal XSRST. Can be selected by the CPU 304. Further, the delay time added by the random delay circuit 317 can be set, and the delay time added to the WDT activation signal and the delay time added to the low voltage signal can be individually set. These selections and settings, WDT 314 start and reset, for example, write a set value to a register built in the reset circuit via the data input / output terminals D0 to D7 of the CPU 304, or set a predetermined value to a predetermined input terminal of the reset circuit. This is performed by inputting a level signal (a signal corresponding to a set value).
<First Modification of Reset Circuit>

FIG. 110A shows a first modification of the reset circuit shown in FIG. 109C. In this example, apart from the first WDT 314a built in the reset circuit, the CPU 304 also incorporates a second WDT 314b. The CPU 304 can select whether a system reset (external reset) is performed by a reset signal input to the reset signal input terminal XSRST or a system reset (internal reset) is performed by a timeout of the built-in second WDT 314b. It has.
<Second Modification of Reset Circuit>

FIG. 10B is a diagram showing a second modification of the reset circuit shown in FIG. In this example, the CPU 304 has a random delay circuit 317 built in the reset circuit and a reset signal output terminal XRSTO. The CPU 304 includes a register that can select whether to output a reset signal from the reset signal output terminal XRSTO based on an external reset or to output a reset signal from the reset signal output terminal XRSTO based on an internal reset. Yes. The CPU 304 also includes a register capable of selecting whether or not to add the delay time selected by the random delay circuit 317 to the reset signal output from the reset signal output terminal XRSTO, and reset based on an external reset. The delay time for delaying the output timing of the signal and the delay time for delaying the output timing of the reset signal based on the internal reset can be individually set.
<Third Modification of Reset Circuit>

FIG. 111 (a) is a diagram showing a third modification of the reset circuit shown in FIG. 109 (c). In this example, the first random delay circuit 317a for setting the delay time for delaying the output timing of the low voltage signal output from the voltage monitoring circuit 338, and the delay for delaying the output timing of the WDT activation signal output by the WDT. A second random delay circuit 317b for setting the time is provided separately. That is, in this example, the CPU 304 performs (1) system reset based on a signal obtained by delaying the output timing by the delay time selected by the first random delay circuit 317a to the low voltage signal output from the voltage monitoring circuit 338. 2) System reset based on a signal obtained by delaying the output timing by the delay time selected by the second random delay circuit 317b to the WDT activation signal output by the WDT 314. (3) WDT activation signal output by the WDT 314 (no delay time) ) Based on the system reset so that the CPU 304 can select one of the three states. Each delay time for delaying the output timing of the low voltage signal and the WDT activation signal can be individually set by the first random delay circuit 317a and the second random delay circuit 317b. These selections and settings, WDT 314 start and reset, for example, write a set value to a register built in the reset circuit via the data input / output terminals D0 to D7 of the CPU 304, or set a predetermined value to a predetermined input terminal of the reset circuit. This is performed by inputting a level signal (a signal corresponding to a set value).
<Example of reset signal output terminal connection>

  FIG. 111 (b) is a diagram showing a part of various ICs connected to the CPU 304. In this example, the CPU 304 has a reset signal input terminal XSRST1 to which a reset signal generated based on a low voltage signal output from the voltage monitoring circuit 338 shown in FIG. The three terminals of the reset signal input terminal XSRST2 to which a reset signal generated based on the WDT activation signal output from the WDT 314 shown in FIG. 5A is input and the reset signal output terminal XRSTO for outputting the reset signal are provided. Prepare.

  As described with reference to FIG. 9, the CPU 304 receives an L level signal that is equal to or longer than a predetermined period (for example, a period corresponding to four cycles of the system clock) at the reset signal input terminal XSRST1 (or the reset signal input terminal XSRST2). After that, when an H level signal is input to the input terminal, the system is reset (initialized).

The reset signal output terminal XRSTO is connected to input terminals of a plurality (four in this example) of IC11 to IC14 and input terminals of other circuits. Here, as the IC 11 to IC 14 and other circuits, for example, a logic IC such as an address decoder or a flip-flop, various circuits / ICs / devices shown in FIG. 4 (for example, a random value generation circuit, a start signal output circuit, a drive) Circuit, sound source IC, sensor circuit, shielding device, decorative design display device) can be applied. In addition, as input terminals of IC11 to IC14 and other circuits, a reset terminal for inputting a reset signal for initializing the entire circuit, or a CLR terminal for inputting a signal for initializing a part of the circuit Etc. can be applied.
<First Modification of Connection of Reset Signal Output Terminal>

FIG. 112 is a diagram showing a first modification of the connection of the reset signal output terminal XRSTO shown in FIG. 111 (b). In this example, in addition to connecting the reset signal output terminal XRSTO to the input terminal 9 of the IC 11, the CPU 304 includes eight data signal terminals D 0 to D 7, and the data signal input terminal 1 to the input terminal 8 of the IC 11. Connected to each of. The IC 11 includes output terminals 1 to 8 corresponding to the data signal input terminals 1 to 8, and these output terminals 1 to 8 are connected to the CPU 404 of the first sub-control unit 400 (not shown). It is connected to the data signal input terminal. That is, the data signal line of the CPU 304 is input to the CPU 404 of the first sub control unit 400 via the IC 11, and the CPU 304 and the CPU 404 of the first sub control unit 400 are configured to be able to communicate via the IC 11. . Note that the CPU 304 and the CPU 404 may be configured to be communicable via a part or all of the above-described IC12 to IC14 in addition to (or instead of) the IC11. Further, the CPU 304 and the CPU 404 may be configured to be communicable via a relay board in addition to (or instead of) these ICs 11 to 14.
<Second Modification of Connection of Reset Signal Output Terminal>

  FIG. 113 is a diagram illustrating the basic circuit 302 described with reference to FIG. 4 and a part of various ICs connected to the basic circuit 302. Although the basic circuit 302 of the main control unit 300 will be described here, the basic circuit 402 and the second sub control of the first sub control unit 400 are replaced with (or in addition to) the basic circuit 302 of the main control unit 300. The present invention can also be applied to the basic circuit 502 of the unit 500 and a circuit corresponding to the basic circuit of another control unit (for example, the payout control unit 600).

  The basic circuit 302 includes two terminals, the reset signal input terminal XSRST and the reset signal output terminal XRSTO described above, as terminals related to reset. The reset signal input terminal XSRST is connected to the output terminal of IC01 (for example, the above-described reset circuit or power supply monitoring circuit). As described with reference to FIG. 9, the CPU 304 of the basic circuit 302 receives the reset signal input. The system is reset (initialized) when an H-level signal is input after an L-level signal having been input for a predetermined period (for example, a period of four cycles of the system clock) is input to the terminal XSRST.

The reset signal output terminal XRSTO is connected to input terminals of a plurality (four in this example) of IC11 to IC14 and input terminals of other circuits. Here, as the IC 11 to IC 14 and other circuits, for example, a logic IC such as an address decoder or a flip-flop, various circuits / ICs / devices shown in FIG. 4 (for example, a random value generation circuit, a start signal output circuit, a drive) Circuit, sound source IC, sensor circuit, shielding device, decorative design display device) can be applied. In addition, as input terminals of IC11 to IC14 and other circuits, a reset terminal for inputting a reset signal for initializing the entire circuit, or a CLR terminal for inputting a signal for initializing a part of the circuit Etc. can be applied.
<Fixed extension time and random extension time>

  Next, the time setting for the fixed extension process and the random extension process executed by the basic circuit 302 after the system reset will be described with reference to FIG. As described with reference to FIG. 9, the CPU 304 executes each process in the order of security check process → fixed extension process → random extension process in the security mode, then shifts to the user mode and executes the game control program. Is configured to do. In this embodiment, the security mode (= security check process + fixed extension process) is set in advance in the CPU 304 for each of the fixed extension process time (fixed extension time) and the random extension process time (random extension time). + Random extension process) can be extended by the set time.

  FIG. 114A shows an example of setting the fixed extension time. In this example, the fixed extension time can be extended by the time shown in the figure by presetting any one of the 3-bit set value data 000B to 111B in a predetermined storage area of the CPU 304. In this example, except for the case where the set value data is 111B, the fixed extension time is calculated by a calculation formula of “2 to the 22nd power × (1 / SCLK) × set value data”.

  For example, when the set value data is set to 000B, the fixed extension time is set to 0 (not extended) regardless of the frequency of the system clock SCLK, and when the set value data is set to 001B, the system clock SCLK When the frequency is 8 MHz, the fixed extension time is set to about 525 ms (= 2 to the power of 22 × (1/8 MHz) × 1), and when the frequency of the system clock SCLK is 10 MHz, the fixed extension time is about 420 ms (= 2). 22 × (1/10 MHz) × 1), and when the frequency of the system clock SCLK is 12 MHz, the fixed extension time is set to about 350 ms (= 2 to the 22nd power × (1/12 MHz) × 1). The

  In this example, the fixed extension time is calculated based on the system clock SCLK. However, for example, the fixed extension time may be calculated based on another set value (for example, a random extension time described later). The calculation may be based on both the system clock SCLK and other set values. Further, although an example in which the system clock SCLK and the fixed extension time are in an inversely proportional relationship has been shown, both may be in a proportional relationship. Further, in the case where the set value data is 111B, an example in which the fixed extension time is set to about 30000 ms in common regardless of the frequency of the system clock SCLK is shown. However, the above calculation formula is also used when the set value data is 111B. Or a maximum value may be set. Further, the data length of the set value data is not limited to 3 bits, and the type of extension time may be increased. Further, the fixed extension time may be limited to a time longer than 0 without including 0 (the CPU 304 may always execute the fixed extension process). Further, different fixed extension times may be set for the internal reset and the external reset.

  FIG. 114 (b) shows an example of setting the random extension time. In this example, the random extension time can be extended by the time shown in the figure by presetting any of the 2-bit length set value data 00B to 11B in a predetermined storage area of the CPU 304. ing. For example, when the set value data is set to 00B, the random extension time is set to 0 (not extended) regardless of the frequency of the system clock SCLK, and when the set value data is set to 01B, the frequency of the system clock SCLK is When the frequency is 8 MHz, the random extension time is set to a random time of 0 to 0.5 ms (a time randomly selected by the core of the CPU 304). When the frequency of the system clock SCLK is 10 MHz, the random extension time is 0 to 0. When the frequency of the system clock SCLK is 12 MHz, the random extension time is set to a random time of 0 to 0.3 ms.

In this example, an example in which the random extension time is changed by the system clock SCLK is shown, but the same may be set between different system clocks SCLK. Further, it may be calculated based on other set values (for example, the above-described fixed extension time) or may be calculated based on both the system clock SCLK and other set values. Further, the data length of the set value data is not limited to 2 bits, and the type of extension time may be increased. Further, the random extension time may be limited to a time longer than 0 without including 0 (the CPU 304 may always execute the random extension process). Further, different random extension times may be set for the internal reset and the external reset. Further, the reference clock may be variable for one of the fixed extension time and the random extension time, and the reference clock may be fixed for the other.
<WDT timeout period>

  Next, the timeout time setting of the WDT 314 will be described with reference to FIG. This figure shows an example of setting the timeout time of WDT 314. In this example, the time-out time can be set for the time shown in the figure by presetting any one of 4-bit set value data 0000B to 1000B in a predetermined storage area of the CPU 304. For example, when the set value data is set to 0000B, the timeout time is set to be prohibited (WDT is not used) regardless of the frequency of the system clock SCLK, and when the set value data is set to 0001B, the system clock SCLK is set. When the frequency of the clock is 8 MHz, the timeout time is set to about 65 ms, when the frequency of the system clock SCLK is 10 MHz, the timeout time is set to about 52 ms, and when the frequency of the system clock SCLK is 12 MHz, the timeout time is about 44 ms. Set to

In this example, the timeout time is changed according to the system clock SCLK. However, the same time may be set between different system clocks SCLK. Further, it may be calculated based on other set values (for example, the above-described fixed extension time or random extension time), or may be calculated based on both the system clock SCLK and other set values. Further, the data length of the set value data is not limited to 4 bits, and the types of timeout time may be increased. Further, although the timeout time is set to be smaller than the above-described fixed extension time, the timeout time may be set to be longer than the above-described fixed extension time.
<Reset output signal and security mode>

  Next, the relationship between the change in the output signal of the reset output terminal XSRSTO and the change in the security mode state will be described. The example shown in FIG. 116 (a) shows the same state as FIG. 9 described above, and when an H level signal is input to the reset input terminal XSRST after an L level signal of a predetermined period or longer is input. Transition to security mode. Then, in this security mode, the security check process is first executed, then the fixed extension process waiting for the elapse of a period according to the above-described setting of the fixed extension time is executed, and when the fixed extension process is completed A game control program that shifts to a user mode when a random extension process that outputs an H level signal from the reset output terminal XRSTO and then waits for the passage of a random period according to the setting of the above-described random extension time is completed. Execution has started. That is, in this example, the end timing of the fixed extension processing (= start timing of the random extension processing) is matched with the timing of outputting an H level signal from the reset output terminal XRSTO.

In the example shown in FIG. 116B, when a predetermined time has elapsed after the fixed extension process is completed, an H level signal is output from the reset output terminal XRSTO, and then the random extension process is completed. Transition to the user mode, the execution of the game control program is started. That is, in this example, after the fixed extension process is finished, before the random extension process is finished and before the transition to the user mode (before the execution of the game control program is started), an H level signal is output from the reset output terminal XRSTO. Is output. The predetermined time (the time from the end of the fixed extension process to the output of the H level signal from the reset output terminal XRSTO) may be a fixed time or a variable time. Further, when the fixed time is adopted, for example, the rising edge (or falling edge) of the system clock SCLK after a predetermined clock (for example, 4 clocks) has elapsed since the end of the fixed extension process. The time until may be set to a predetermined time. When variable time is adopted, the predetermined time may be changed to a random time each time the system is reset.
<When changing the random extension time>

  117 (a) and 117 (b) show that the end timing of the fixed extension processing (= start timing of the random extension processing) coincides with the timing of outputting the H level signal from the reset output terminal XRSTO. It is the figure which showed the different example. That is, in FIGS. 9A and 9B, the set value of the fixed extension time is the same (for example, set value = 001B, SCLK = about 8 MHz), and the set value of the random extension time is also the same (for example, the set value). (Value = 01B, SCLK = 8 MHz) In FIG. 9A, the time A1 (for example, 0.2 ms) is selected from the numerical range of the random extension time (for example, 0 to 0.5 ms). In FIG. 5B, a time A2 (for example, 0.3 ms) longer than the time A1 is selected from the numerical range (for example, 0 to 0.5 ms) of the random extension time. In this example, since 0 to 0.5 ms is selected as the numerical range of the random extension time, the case where the random extension time becomes 0 (no random extension time) is also included.

As described above, the user mode is started from the H level signal output of the reset output terminal XRSTO by changing the random extension time (A1, A2) even if the setting of the fixed extension time and the random extension time is the same. The time until (A1, A2) can be changed at every system reset. For this reason, after outputting an H level signal to IC11 to IC14 or other circuits connected to the reset signal output terminal XRSTO (after starting or initializing IC11 to IC14 or other circuits), for game control The time until the program is executed can be changed, and the execution timing of the game control program (for example, lottery timing for determination of success / failure) based on the output signals from the respective terminals of the CPU 304 and the operation of peripheral ICs of the CPU 304 ) Can be prevented in advance. In this example, the setting value of the random extension time is the same, but the setting value of the random extension time may be different.
<When changing the fixed extension time>

  117 (c) and 117 (d), the end timing of the fixed extension process (= start timing of the random extension process) and the timing of outputting the H level signal from the reset output terminal XRSTO coincide, but the fixed extension time It is the figure which showed the different example. That is, the setting value data of the random extension time is the same (for example, setting value = 01B, SCLK = 8 MHz) in FIGS. 10C and 10D, and the random extension time is shown in FIGS. While the same time A1 (for example, 0.2 ms) is set from a numerical range of (for example, 0 to 0.5 ms), in FIG. 5C, the fixed extension time is set to the time B1 (for example, set value = (001B, SCLK = 8 MHz, about 525 ms), in FIG. 4D, the fixed extension time is set to a time B2 longer than the time B1 (for example, set value = 010B, SCLK = 8 MHz, about 1050 ms) (B1). <B2).

Thus, by changing the fixed extension time (B1, B2) even if the random extension time (A1) is the same, the time from the start of the fixed extension process to the start of the user mode (C1, C2) can be varied. For this reason, the time from the system reset of the CPU 304 to the execution of the game control program can be changed every time the system reset is performed, and for the game control using the reset signal input to the reset input terminal XSRST of the CPU 304 as a clue. In some cases, it is possible to prevent fraudulent acts such as grasping the execution timing of the program (for example, the lottery timing for determination of success / failure). Note that FIG. 109 shows an example in which one of the fixed extension time and the random extension time is made different. However, if both are made different, an illegal act of grasping the execution timing of the game control program is more reliably performed. Can be prevented.
<When changing the reset output signal triggered by fixed extension processing>

  FIG. 118 is a diagram illustrating an example in which the reset output signal is changed in response to the fixed extension process. In this example, the start timing of the fixed extension process (= end timing of the security check process) and the timing of outputting an H level signal from the reset output terminal XRSTO are matched. Since the reset output signal may be changed in response to the fixed extension process, for example, the reset output signal may be output before the start of the fixed extension process (for example, 200 ms before the start timing of the fixed extension process). The delay time may be determined according to the set value of the fixed extension time, and the reset output signal may be output after the delay time has elapsed. Also, it determines whether it is an internal reset (reset based on a built-in WDT timeout) or an external reset (reset based on a signal input to the XSRST terminal), and determines the output timing of the reset output signal according to the type of the reset. May be.

Further, a storage unit that stores past reset types may be provided, and the output timing of the reset output signal may be changed based on the history of reset types stored in the storage unit. If it is continuous, the output timing of the reset output signal may be delayed or advanced from the previous time.
<Other output signals and security mode>

  FIG. 119 is a diagram illustrating changes in the address signal, data signal, control signal, and reset output signal output from the CPU 304, and changes in the security mode state. In this example, the CPU 304 outputs an H level signal from the reset output terminal XRSTO when the fixed extension process is completed (when the random extension process is started) and at the same timing, an external IC (for example, ROM 306, RAM 308). Data read (or write) has started. Therefore, in this example, at the same time that the H level signal is output from the reset output terminal XRSTO, output of 16-bit address information (0000h in this example) is started from the address signals A0 to A15, and the control signal XM1 terminal A control signal indicating the latch timing of the address information (timing at which the external IC captures the address information) is output, and subsequently, 8-bit data information (opcode in this example) is output from the data signals D0 to D7 terminals. The control signal indicating the latch timing of the data information (the timing at which the external IC captures the data information) is output from the control signal XM1 terminal.

  In this example, the output of the address signal and the control signal is started simultaneously with the output of the H level signal from the reset output terminal XRSTO. For example, the output of the address signal and the control signal is started before the reset output. Alternatively, the output of the address signal and the control signal may be started after the reset output (for example, immediately after shifting from the security mode to the user mode). The control signal output from the XM1 terminal may be, for example, an output signal indicating a machine cycle of the CPU 304, a request output signal to a memory space or an I / O space, or an output signal indicating a read cycle or a write cycle. But you can.

  FIG. 120A is a diagram showing a change in the state of another output signal after the external reset, and FIG. 120B is a diagram showing a change in the state of another output signal after the internal reset. In this example, in the case of an external reset, the output of 16-bit address information (0000h in this example) is started from the address signals A0 to A15 by a predetermined time A1 before the random extension process, and the control signal A control signal indicating the latch timing of the address information is output from the XM1 terminal. On the other hand, in the case of an internal reset, output of 16-bit address information (0000h in this example) is started from the address signals A0 to A15 for a predetermined time A2 (A2> A1) before the random extension process. The control signal indicating the latch timing of the address information is output from the control signal XM1 terminal. That is, in this example, the signal output timing of the address signals A0 to A15 and the signal output of the control signal XM1 terminal are different between the external reset and the internal reset.

  In the case of an internal reset, 16-bit address information (E000h in this example) is output from the address signals A0 to A15 immediately after timeout of the WDT 314, and the address information immediately after the external reset ( For example, it is different from 0000h). Note that the address information output immediately after the internal reset and the address information output immediately after the external reset may be set to be the same.

FIG. 121 (a) is a diagram showing another example of the state change of another output signal after the external reset, and FIG. 121 (b) is another example of the state change of another output signal after the internal reset. FIG. In this example, in the case of an internal reset, the internal reset is canceled after the elapse of a time B2 longer than the reset cancellation time B1 of the external reset. Note that this configuration and each configuration described with reference to FIG.
<Start timing of security mode>

  FIG. 122 (a) is a diagram showing an example of the security mode start timing after the external system reset, and FIG. 122 (b) is a diagram showing an example of the security mode start timing after the internal system reset. In this example, in the case of an external system reset, after the cause of the external system reset occurs (for example, after the falling edge of the reset input signal XSRST is detected), the time C1 (for example, the system clock SCLK) The security mode is started after the elapse of 4 clocks). On the other hand, in the case of an internal system reset, after the cause of the internal reset occurs (for example, after the WDT timer times out), the time C2 (for example, the time corresponding to one clock of the system clock SCLK) elapses. Security mode is configured to start.

  In this example, the time C1 from the occurrence of the external reset factor to the start of the security mode is set longer than the time C2 from the occurrence of the internal reset factor to the start of the security mode. However, (C1> C2), the time C1 from the occurrence of the external reset factor to the start of the security mode is determined from the time C2 from the occurrence of the internal reset factor to the start of the security mode. May be shortened (C1 <C2).

  In the above example, the execution time of random extension processing (random extension time) and fixed extension processing (fixed extension time) included in the security mode can be freely set regardless of the reset factor. Configured to have only one random extension time setting register and one fixed extension time setting register for external reset and internal reset, and set random extension time and fixed extension time individually for external reset and internal reset. Setting may be prohibited (only common setting may be permitted).

  FIG. 123 is a diagram showing the basic concept of the present invention. In the present invention, when starting the second event based on the first event, the case where the first event is caused by the first factor and the case where the first event is caused by the second factor The timing for starting the second event can be varied.

  For example, considering the start timing of the security mode described with reference to FIG. 122 above, when the second event (security mode) is started based on the first event (reset), the first event is the first event. The timing for starting the second event (security mode) differs depending on whether the first event is caused by an external system reset or if the first event is caused by a second factor (internal system reset). Can do. Therefore, the time C1 from the occurrence of the first factor (external system reset) to the start of the second event (security mode) is the same as the time C1 after the second factor (internal system reset) occurs. The second event (security mode) starts after the first event (external system reset) occurs or the time C2 is longer than the time C2 until the second event (security mode) starts (C1> C2) The time C1 until the second event (internal system reset) occurs can be made shorter than the time C2 until the second event (security mode) is started.

  Moreover, since the timing at which the security mode is started can be made different, the timing at which the user mode to be executed thereafter is also made different. For example, the security mode is started even when the execution time of the security mode is the same between the case where the first event is caused by the first factor and the case where the first event is caused by the second factor. If the timing is different, the timing at which the user mode is started can be made different between the case where the first event is caused by the first factor and the case where the first event is caused by the second factor.

Also, the security mode can be executed without changing the timing of starting the security mode between the case where the first event is caused by the first factor and the case where the first event is caused by the second factor. If the times are different, the timing at which the user mode is started can be made different between the case where the first event is caused by the first factor and the case where the first event is caused by the second factor.
<Other embodiments>

  Next, a pachinko machine according to another embodiment will be described. In some cases, the contents described in one configuration among a plurality of configurations described in the present embodiment may be applied to other configurations to further widen the game.

  For example, FIG. 124A is a diagram illustrating an example of connection of the power supply board 182, the payout board 170, and the main board 156 described with reference to FIG. The power supply board 182 includes a RAM clear switch 180 and a detection signal output terminal for outputting a detection signal when an operation of the RAM clear switch 180 is detected. The CPU of the power supply board 182 periodically detects whether or not the RAM clear switch 180 is operated, and outputs a detection result (for example, an H level signal when there is an operation, an L level signal when there is no operation). Output from the detection signal output terminal toward the dispensing substrate 170.

  The payout board 170 is a RAM clear for temporarily storing the detection signal input terminal connected to the detection signal output terminal of the power supply board 182 and the operation information of the RAM clear switch 180 acquired through the detection signal input terminal. Switch operation information temporary storage means 171 (for example, RAM, CPU register, flip-flop) and an operation information output terminal for outputting the operation information stored in the RAM clear switch operation information temporary storage means 171. . The CPU of the payout board 170 detects the signal input to the detection signal input terminal in the initial processing after power-on or system reset, and indicates operation information (for example, whether or not the RAM clear switch 180 is operated). When the H level signal is detected, the RAM clear switch operation information temporary storage 171 stores 1 information indicating that there is an operation and 0 information indicating that there is no operation when an L level signal is detected. The operation information is stored in a predetermined storage area and information corresponding to the operation information (for example, an H level signal in the case of operation information with an operation and an L level signal in the case of operation information without an operation) is output. Output from the terminal toward the main board 156.

  The main board 156 includes an operation information input terminal (the above-mentioned I / O 410) connected to the operation information output terminal of the payout board 170, and a RAM clear timing notification LED 155. The CPU 304 mounted on the main board 156 inputs the operation information input terminal (I / O 310) after turning on the RAM clear timing notification LED 155 in the initial setting (after notifying that the RAM can be cleared). When the signal is confirmed and an H level signal is detected, a predetermined area of the RAM 308 is initialized (RAM clear).

  FIG. 125 is a flowchart showing the flow of the main process of the main control unit according to the modification, and is a flowchart corresponding to FIG. In addition, the same code | symbol is attached | subjected about the part same as the flowchart shown in FIG. 10, and the description is abbreviate | omitted. FIG. 126 is a flowchart showing a flow of initial setting 2 in the main process of the main control unit.

  In step S128 of the initial setting 2, the CPU 304 turns on the RAM clear timing notification LED 155 (after notifying that the RAM can be cleared), and then checks the input signal of the operation information input terminal (I / O 310). Operation information indicating whether or not the RAM clear switch 180 is operated (for example, 1 information indicating that there is an operation when an H level signal is detected, and no operation when an L level signal is detected) Is stored in a predetermined storage area of the RAM 308.

  In the determination process in step S109 after the initial setting 2 is executed, first, it is determined whether or not 1 information indicating that there is an operation is stored in the RAM 308, and if applicable (when the RAM needs to be cleared). In step S113, the basic circuit 302 is initialized. On the other hand, when 0 information indicating no operation is stored (when RAM clear is not necessary), the power status information stored in the power status storage area provided in the RAM 308 is read, and the power status information is It is determined whether the information indicates suspend. If the power status information is not information indicating suspend, the process proceeds to step S113 to set the basic circuit 302 to an initial state. If the power status information is information indicating suspend, a predetermined area of the RAM 308 is set. A checksum is calculated by adding all the 1-byte data stored in (for example, all areas) to a 1-byte register whose initial value is 0, and the calculated checksum results in a specific value (for example, 0) (whether or not the checksum result is normal). When the checksum result is a specific value (eg, 0) (when the checksum result is normal), the process proceeds to step S111 to return to the state before the power interruption, and the checksum result is a specific value. If the value is other than 0 (for example, 0) (if the checksum result is abnormal), the process proceeds to step S113 to set the pachinko machine to an initial state. Similarly, when the power status information indicates information other than “suspend”, the process proceeds to step S113.

  Returning to FIG. 125, FIG. 125 (b) is a diagram showing a conventional connection mode corresponding to FIG. 124 (a). In the conventional connection mode, when the setting data 111B (about 30 seconds) is set as the above-described fixed extension time on the main board 156, the security mode ends, the user mode is entered, and the game control program is started. Will be at least about 30 seconds later. For this reason, when the configuration for detecting the signal input to the operation information input terminal (I / O 410) is adopted in the game control program of the main board 156, the RAM clear switch 180 must be operated for at least about 30 seconds. For example, whether or not the RAM clear switch 180 is operated cannot be detected, and the timing at which the main board 156 detects the operation of the RAM clear switch 180 cannot be known from the outside.

  On the other hand, in the connection mode according to the present embodiment shown in FIG. 6A, whether the store clerk or the like of the game shop can clear the RAM by confirming that the RAM clear timing notification LED 155 is turned on / off. It is possible to immediately determine whether or not. For this reason, the RAM clear switch 180 can be operated by waiting for the RAM clear timing notification LED 155 to be lit, and the RAM clear switch 180 can be operated for a long time. In some cases, it is freed from bothersomeness and convenience. Even if the RAM clear switch 180 is operated before the RAM clear timing notification LED 155 is turned on (before the game control program of the CPU 304 is started), the CPU of the payout board 170 is activated. The dispensing board 170 can store the operation information. Therefore, when the main board 156 can reliably execute the RAM clear after the start of the game control program based on the operation information stored in the RAM clear switch operation information temporary storage means 171 of the payout board 170. There is.

In the present embodiment, an example in which input / output of signals between the power supply board 182, the payout board 170, and the main board 156 is performed via the input / output terminals is shown. It may be by transmission and reception. Further, the RAM clear switch 180 is not limited to the example arranged on the power supply board 182, and may be arranged on the payout board 170, for example.
<Other commands of main control unit>

  Next, other commands included in the main control unit 300 will be described. In the following description, “r”, “s”, “ss”, or “qq” is an abbreviation representing an arbitrary register,

“k” is an abbreviation representing a lower address paired with the T register, “n” is an abbreviation representing an 8-bit number (hexadecimal number), and “mn” is a 16-bit number (hexadecimal number). “()” Is an abbreviation that represents data at an address indicated by a value in parentheses.
<Other instructions / 8-bit load instructions>

  The 8-bit load instruction is an instruction for loading 8-bit data into a predetermined storage area, and corresponds to, for example, an LD instruction, an LDT instruction, or a CLRT instruction.

  For example, the (LD A, T) instruction is an instruction for loading data stored in the T register into the A register, and the (LD T, n) instruction is for loading a numerical value n having an 8-bit length into the T register. It is an instruction to do.

  The (LDT A, (r)) instruction stores the data stored in the T register as the upper byte and the data stored in the register (A, B, C, D, E, H, L) indicated by r as the lower byte. (LDT A, (k)) instruction is an instruction for loading data stored in the T register into the upper byte, the register indicated by k. This is an instruction to load the data stored in the address having the data as the lower byte into the A register. The (LDT r, (k)) instruction is the register indicated by the upper byte, k, of the data stored in the T register. This is an instruction to load the data stored in the address having the data stored in the lower byte into the register (B, C, D, E, H, L) indicated by r.

  The (LDT (r), A) instruction is the data stored in the A register, the data stored in the T register is the upper byte, and the registers (A, B, C, D, E, H, L indicated by r) (LDT (k), A) is an instruction to load data stored in the A register, data stored in the T register as upper bytes, This is an instruction to load the data stored in the register indicated by k into an address having a lower byte, and the (LDT (k), r) instruction is a register (B, C, D, E, H, This is an instruction to load data stored in L) into an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte.

  The (LDT (k), (ss)) instruction is obtained by changing the data stored in the address indicated by the data stored in the pair register (BC, DE, HL) indicated by ss and the data stored in the T register. This is an instruction to load the data stored in the register indicated by byte k to the address having the lower byte, and the (LDT (k), (HL + v)) instruction is indicated by v in the data stored in the HL register. Data stored at the address indicated by the addition result of data (v = 1 to 7), the data stored in the T register as the upper byte, and the data stored in the register indicated by k as the lower byte The (LDT (k), (HL + d)) instruction is data indicated by d in the data stored in the HL register (d = 8 to 127, −1 to 128) is an instruction to load the data stored at the address indicated by the addition result of 128) into the address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. , (LDT (ss), (k)) instruction, the data stored in the address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte This is an instruction to load to the address indicated by the data stored in the indicated pair register (BC, DE, HL).

  The (LDT (HL + v), (k)) instruction stores data stored in an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. This is an instruction to load the address indicated by the addition result obtained by adding the data indicated by v (v = 1 to 7) to the stored data, and the (LDT (HL + d), (k)) instruction is stored in the T register. The data stored in the address having the data stored in the register indicated by k as the upper byte, the data stored in the register indicated by k as the lower byte, and the data indicated by d in the data stored in the HL register (d = 8 to 127, − 1 to -128) is added to the address indicated by the addition result, and the (LDT (k), n) instruction uses the value indicated by n as the data stored in the T register. High byte data is an instruction to load the address of the lower byte data stored in the register indicated by k.

The (CLRT (k)) instruction is an instruction to load a numerical value 0 to an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte.
<Other instructions / 16-bit load instructions>

  The 16-bit load instruction is an instruction for loading 16-bit data into a predetermined storage area, and corresponds to, for example, an LDT instruction, an LDWT instruction, a CLR instruction, a CLRWT instruction, and the like. Specifically, the (LDT BC, n) instruction is an instruction for loading data stored in the T register into the B register and loading a numerical value indicated by n into the C register, and (LDT DE, n ) Instruction is an instruction to load data stored in the T register into the D register and load a numerical value indicated by n into the E register, and the (LDT HL, n) instruction is stored in the T register. This is an instruction to load data into the H register and load a numerical value indicated by n into the L register.

  The (LDT IX, n) instruction loads the data stored in the T register into the upper 8 bits of the 16-bit IX register, and sets the numerical value indicated by n to the lower 8 bits of the 16-bit IX register. The (LDT IY, n) instruction loads data stored in the T register into the upper byte of the 16-bit IY register, and the numerical value indicated by n is a 16-bit IY register. This is an instruction to load the lower byte of.

  The (LDT ss, (k)) instruction is a pair indicated by ss with data stored at an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. Load the upper byte of the register (BC, DE) and store the data stored in the T register as the upper byte and the address stored in the register indicated by k as the lower byte plus 1 This is an instruction to load the read data into the lower byte of the pair register (BC, DE) indicated by ss.

  The (LDT qq, (k)) instruction is a pair indicated by qq with data stored at an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. Load the upper byte of the register (IX, IY), store the data stored in the T register as the upper byte, and store the data stored in the register indicated by k as the lower byte. This is an instruction to load the read data into the lower byte of the pair register (IX, IY) indicated by qq.

  The (LDT HL, (k)) instruction uses the data stored in the address stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. And the data stored in the address obtained by adding 1 to the address having the data stored in the T register as the upper byte, the data stored in the register indicated by k as the lower byte, and the H register of the HL register. Is an instruction to load.

  The (LDT (k), ss) instruction is data stored in the lower byte of the pair register (BC, DE, HL) indicated by ss, data stored in the T register is higher byte, and register indicated by k The data stored in the upper byte of the pair register (BC, DE, HL) indicated by ss, the data stored in the T register as the upper byte, This is an instruction to load an address obtained by adding 1 to an address having the data stored in the register indicated by k as a lower byte.

  The (LDT (k), qq) instruction stores the data stored in the lower byte of the pair register (IX, IY) indicated by qq, the data stored in the T register as the upper byte, and the register indicated by k. The data stored in the upper byte of the pair register (IX, IY) indicated by qq, the data stored in the T register as the upper byte, and k This is an instruction to load an address obtained by adding 1 to an address having the data stored in the register as the lower byte.

  The (LDT (k), HL) instruction loads data stored in the L register into an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. And an instruction to load data stored in the H register into an address obtained by adding 1 to an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. .

  The (LDWT (r), mn) instruction uses the data stored in the T register as the upper byte and the data stored in the register (A, B, C, D, E, H, L) indicated by r as the lower byte. The data stored in the address indicated by mn + 1, which is a 16-bit numerical value, the data stored in the T register as the upper byte, and the register indicated by r (A, B, C, D) , E, H, L) is an instruction to load an address obtained by adding 1 to an address having the data stored in the lower byte.

  The (CLR (ss)) instruction is an instruction for storing a numerical value 0 in a pair register (BC, DE) indicated by ss, and the (CLRW (ss)) instruction is a pair register (BC, DE) indicated by ss. , HL) is an instruction that stores a numerical value 0 at the address indicated by the data stored in the data, and stores a numerical value 0 at an address obtained by adding 1 to the address. The (CLRW (qq)) instruction is qq This is an instruction for storing a numerical value 0 at an address indicated by data stored in the indicated register (IX, IY) and storing a numerical value 0 at an address obtained by adding 1 to the address, (CLRW (qq + d)) The instruction is an address indicated by an addition result obtained by adding data (d = 8 to 127, −1 to −128) indicated by d to data stored in the register (IX, IY) indicated by qq. In vinegar, it is an instruction to store the numeric 0.

  The (CLRT (k)) instruction is an instruction for storing a numerical value 0 at an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte, and (CLRWT (K)) The instruction loads the data stored in the T register to the upper byte, the data stored in the register indicated by k as the lower byte, and stores the numerical value 0 in the T register. This is an instruction for storing a numerical value of 0 at an address obtained by adding 1 to an address having the data stored as the upper byte and the data stored in the register indicated by k as the lower byte.

As described above, the registers (BC, DE) indicated by ss and the registers (IX, IY) indicated by qq are (CLR (ss)) instruction, (CLRW (ss)) instruction, (CLRW (qq + d)). It can be specified as an instruction operand. On the other hand, the T register (special register) can be specified only as an operand of the CLRT instruction or the CLRWT instruction, and in addition, a part of the operand (the lower 1 byte of the address indicated by k in this embodiment) is It can only be specified as a direct value. For this reason, a situation in which the value of the T register is unexpectedly cleared to 0 or an unexpected value is stored in the T register may be prevented.
<Other instructions / stack manipulation instructions>

  The stack operation instruction is an instruction for saving data in the stack area or restoring data from the stack area, and corresponds to, for example, a PUSH instruction, a POP instruction, and the like.

  For example, the (PUSH ss) instruction saves the data stored in the upper byte of the pair register (AF, BC, DE, HL) indicated by ss to the address indicated by (SP (stack pointer) -1). An instruction that subtracts 2 from SP after saving the data stored in the lower byte of the pair register (AF, BC, DE, HL) indicated by ss to the address indicated by (SP-2). is there. The (PUSH TI) instruction saves the data stored in the T register to the address indicated by (SP-1), and the data stored in the I register is indicated by (SP-2). This instruction subtracts 2 from SP after saving to an address. The (PUSH qq) instruction saves the data stored in the upper byte of the pair register (IX, IY) indicated by qq to the address indicated by (SP-1), and the pair indicated by qq. This instruction subtracts 2 from SP after saving the data stored in the lower byte of the register (IX, IY) to the address indicated by (SP-2).

  (PUSH ALL) instruction is for all registers (T, I, A, F, B, C, D, E, H, L, IX high byte, IX low byte, IY high byte, IY low byte This is an instruction for subtracting 14 (total number of registers) from SP after the data stored in () is saved to the stack area byte by byte in this order. In addition, the (PUSH GPR) instruction saves data stored in some registers (A, F, B, C, D, E, H, L) one byte at a time in this order, This is an instruction to subtract 8 from SP.

  The (POP ss) instruction restores the data stored at the address indicated by SP to the upper byte of the pair register (AF, BC, DE, HL) indicated by ss and the address indicated by (SP + 1) This is an instruction to add 2 to SP after the data stored in is restored to the lower byte of the pair register (AF, BC, DE, HL) indicated by ss. The (POP TI) instruction returns the data stored at the address indicated by SP to the I register and returns the data stored at the address indicated by (SP + 1) to the T register. This is an instruction to add 2 to SP. The (POP qq) instruction restores the data stored at the address indicated by SP to the lower byte of the pair register (IX, IY) indicated by qq and stores it at the address indicated by (SP + 1). This is an instruction to add 2 to SP after the restored data is restored to the upper byte of the pair register (IX, IY) indicated by qq.

The (POP ALL) instruction reads the data stored in SP, (SP + 1),..., (SP + 12), (SP + 13) in this order in all registers (lower byte of IY, upper byte of IY, lower byte of IX). , IX, upper byte, L, H, E, D, C, B, F, A, I, T) one byte at a time (lower byte of IY ← (SP), upper byte of IY ← (SP + 1), ..., I ← (SP + 12), T ← (SP + 13)), and then an instruction to add 14 to SP. In addition, the (POP GPR) instruction is used to store data stored in SP, (SP + 1),..., (SP + 6), (SP + 7) in this order in some registers (L, H, E, D, C, B). , F, A) is an instruction for adding 8 to SP after returning one byte at a time (L ← (SP), H ← (SP + 1),..., F ← (SP + 6), A ← (SP + 7)).
<Other instructions / arithmetic logic operation instructions>

  The arithmetic logic operation instruction is an instruction for performing various logic operations. For example, an ADD instruction, a SUB instruction, an ANDT instruction, an ORT instruction, an XORT instruction, a CPT instruction, an INC instruction, an INCT instruction, an INCWT instruction, a DEC instruction, A DECT instruction, a DECWT instruction, and the like are applicable.

  For example, the (ADD A, r) instruction adds the data stored in the A register and the data stored in the register (A, B, C, D, E, H, L) indicated by r, and adds This is an instruction for storing the result in the A register. The (ADDT r, (k)) instruction stores the data stored in the register (B, C, D, E, H, L) indicated by r and the T register. The stored data is added to the upper byte, the data stored in the address having the data stored in the register indicated by k as the lower byte, and the addition result is added to the register (B, C, D, E, H, L).

  For example, the (SUB r) instruction subtracts the data stored in the register (A, B, C, D, E, H, L) indicated by r from the data stored in the A register. This is an instruction to be stored in the A register. The (SUBT r, (k)) instruction is stored in the T register from the data stored in the register (B, C, D, E, H, L) indicated by r. The data stored in the address having the data stored in the register indicated by k as the upper byte and the data stored in the register indicated by k as the lower byte are subtracted, and the subtraction result is indicated by the register (B, C, D, E, H, L) is an instruction to be stored.

  For example, the (ANDT (k)) instruction is stored in an address having the data stored in the A register, the data stored in the T register as the upper byte, and the data stored in the register indicated by k as the lower byte. Is an instruction that calculates a logical product (AND) of the data and stores the operation result in the A register. The (ANDT r, (k)) instruction is a register (B, C, D, E) indicated by r. , H, L) and the data stored in the address stored in the address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte ( AND), and the operation result is stored in a register (B, C, D, E, H, L) indicated by r.

  The (ORT (k)) instruction is data stored in an address having the data stored in the A register, the data stored in the T register as the upper byte, and the data stored in the register indicated by k as the lower byte. And (ORT r, (k)) instructions are registers (B, C, D, E, H) indicated by r. , L) and the data stored at the address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte (OR) And the operation result is stored in a register (B, C, D, E, H, L) indicated by r.

  The (XORT (k)) instruction is data stored in an address having the data stored in the A register, the data stored in the T register as the upper byte, and the data stored in the register indicated by k as the lower byte. And an XORT r, (k) instruction is a register (B, C, D, E) indicated by r. , H, L) and the data stored in the address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. This is an instruction for calculating the sum (XOR) and storing the operation result in a register (B, C, D, E, H, L) indicated by r.

  The (CPT (k)) instruction is the data stored in the address stored in the A register with the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. When the calculation result overflows, the predetermined flag is set to 1, while when the calculation result does not overflow, the predetermined flag is cleared to 0, and the S flag, Z flag, TZ flag, H flag, Alternatively, it is an instruction for changing the value stored in the carry flag (C flag) from 0 to 1 (or from 1 to 0). The (CPT r, (k)) instruction indicates the data stored in the T register from the data stored in the register (B, C, D, E, H, L) indicated by r by the upper byte, k. The data stored in the address stored in the register is subtracted from the data stored in the lower byte. When the operation result overflows, the predetermined flag is set to 1. On the other hand, when the overflow does not occur, the predetermined flag is set. This instruction clears the value to 0 and changes the value stored in the S flag, Z flag, TZ flag, H flag, or carry flag (C flag) from 0 to 1 (or from 1 to 0).

  The (INC T) instruction is an instruction for adding 1 to the data stored in the T register, and the (INCT (r)) instruction is used to store the data stored in the T register as an upper byte and a register (A , B, C, D, E, H, L) is an instruction for adding 1 to the data stored in the address having the lower byte as the data stored therein, and the (INCT (k)) instruction is stored in the T register. This is an instruction to add 1 to the data stored at the address having the stored data as the upper byte and the data stored in the register indicated by k as the lower byte. In addition, the (INCWT (k)) instruction stores the data stored in the T register as the upper byte, the address stored in the register indicated by k as the lower byte, and the address obtained by adding 1 to the address. This is an instruction for adding 1 to the 2-byte data.

The (DEC T) instruction is an instruction for subtracting 1 from the data stored in the T register, and the (DECT (r)) instruction is used to store the data stored in the T register in the upper byte, the register (A , B, C, D, E, H, L) is an instruction for subtracting 1 from the data stored in the address having the lower byte as the data stored therein, and the (DECT (k)) instruction is stored in the T register. This is an instruction for subtracting 1 from data stored at an address having stored data as an upper byte and data stored in a register indicated by k as a lower byte. In addition, the (INCWT (k)) instruction stores the data stored in the T register as the upper byte, the address stored in the register indicated by k as the lower byte, and the address obtained by adding 1 to the address. This is an instruction to subtract 1 from the 2-byte data.
<Other instructions / Rotate shift instructions>

  Arithmetic logical operation instructions are instructions for performing various logical operations. For example, RLC instruction, RLCT instruction, RRC instruction, RRCT instruction, RL instruction, RLT instruction, RR instruction, RRT instruction, SLA instruction, SLAT instruction, An SRA instruction, SRAT instruction, SRL instruction, SRLT instruction, and the like are applicable.

  For example, the (RLC r) instruction rotates the data stored in the register (A, B, C, D, E, H, L) indicated by r by 1 bit to the left (from the LSB to the MSB side) This instruction stores the bits shifted out from the MSB in the LSB and the carry flag. The (RLC (HL)) instruction rotates the data stored in the HL register to the left by 1 bit and is shifted out from the MSB. The bit is stored in the LSB and the carry flag. The (RLC (qq + d)) instruction is data stored in the register (IX, IY) indicated by qq (d = 8 to 127, −1 to −128) is added, the data stored at the address indicated by the addition result is rotated left by 1 bit, and the bit shifted out from the MSB is LSB (RLCT (k)) instruction is data stored in an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. Is rotated to the left by 1 bit, and the bit shifted out from the MSB is stored in the LSB and carry flag.

  The (RRC r) instruction rotates the data stored in the register (A, B, C, D, E, H, L) indicated by r to the right (from the MSB to the LSB side) by 1 bit, and from the LSB This instruction stores the shifted out bits in the MSB and carry flag. The (RRC (HL)) instruction rotates the data stored in the HL register to the right by 1 bit, and shifts the bits shifted out from the LSB. This is an instruction stored in the MSB and carry flag, and the (RRC (qq + d)) instruction is data indicated by d (d = 8 to 127, −1) in data stored in the register (IX, IY) indicated by qq. The data stored at the address indicated by the addition result is rotated by 1 bit to the right, and the bit shifted out from the LSB is carried with the MSB. (RRCT (k)) instruction stores data stored in an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. This instruction rotates to the right by one bit and stores the bits shifted out from the LSB in the MSB and carry flag.

  The (RL r) instruction rotates the data stored in the register (A, B, C, D, E, H, L) indicated by r to the left (from the LSB to the MSB side) by 1 bit, and carries the carry flag. The bit stored in the LSB is stored in the LSB, and the bit shifted out from the MSB is stored in the carry flag. The (RL (HL)) instruction stores the data stored in the HL register 1 bit to the left. The bit stored in the carry flag is stored in the LSB, and the bit shifted out from the MSB is stored in the carry flag. The (RL (qq + d)) instruction is a register ( IX, IY) is stored in the address indicated by the addition result obtained by adding the data indicated by d (d = 8 to 127, −1 to −128). Is rotated to the left by 1 bit, the bit stored in the carry flag is stored in the LSB, and the bit shifted out from the MSB is stored in the carry flag. The (RLT (k)) instruction is Rotate the data stored in the address with the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte by one bit to the left, and change the bit stored in the carry flag. This is an instruction for storing the bit shifted out from the MSB and stored in the LSB in the carry flag.

  The (RR r) instruction rotates the data stored in the register (A, B, C, D, E, H, L) indicated by r by 1 bit to the right (from the MSB to the LSB side), and carries the carry flag. The bit stored in the MSB is stored in the MSB, and the bit shifted out from the LSB is stored in the carry flag. The (RR (HL)) instruction stores the data stored in the HL register 1 bit to the right. Only the bit stored in the carry flag is stored in the MSB, and the bit shifted out from the LSB is stored in the carry flag. The (RR (qq + d)) instruction is a register ( IX, IY) is stored in the address indicated by the addition result obtained by adding the data indicated by d (d = 8 to 127, −1 to −128). Is rotated to the right by 1 bit, the bit stored in the carry flag is stored in the MSB, and the bit shifted out from the LSB is stored in the carry flag. The (RRT (k)) instruction is Rotate the data stored in the address with the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte by one bit to the right, and change the bit stored in the carry flag. This is an instruction to store in MSB the bit shifted out from LSB in the carry flag.

  The (SLA r) instruction shifts the data stored in the register (A, B, C, D, E, H, L) indicated by r by 1 bit to the left (from the LSB to the MSB side), and from the MSB. This instruction stores the shifted out bit in the carry flag and stores 0 in the LSB. The (SLA (HL)) instruction shifts the data stored in the HL register by 1 bit to the left and shifts from the MSB. This is an instruction for storing the out bit in the carry flag and storing 0 in the LSB. The (SLA (qq + d)) instruction is indicated by d in the data stored in the register (IX, IY) indicated by qq. Data stored at the address indicated by the addition result of data (d = 8 to 127, −1 to −128) is shifted left by 1 bit, and the bits shifted out from the MSB are keyed. The instruction is stored in the Lee flag and 0 is stored in the LSB. The (SLAT (k)) instruction uses the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. This is an instruction to shift the data stored in the address by 1 bit to the left, store the bit shifted out from the MSB in the carry flag, and store 0 in the LSB.

  The (SRAR) instruction shifts the data stored in the register (A, B, C, D, E, H, L) indicated by r to the right (from the MSB to the LSB side) by 1 bit, and from the LSB This is an instruction to store the shifted out bit in the carry flag and store the previous MSB value in the MSB. The (SLA (HL)) instruction shifts the data stored in the HL register by 1 bit to the right. The bit shifted out from the LSB is stored in the carry flag, and the MSB value is stored in the MSB. The (SLA (qq + d)) instruction is stored in the register (IX, IY) indicated by qq. The data stored at the address indicated by the addition result obtained by adding the data indicated by d (d = 8 to 127, −1 to −128) to the generated data is shifted to the right by 1 bit, and from the LSB The bit stored in the carry flag is stored in the carry flag, and the value of the previous MSB is stored in the MSB. The (SLAT (k)) instruction stores the data stored in the T register in the upper byte, a register indicated by k. An instruction that shifts data stored in the address having the data stored in the lower byte by 1 bit to the right, stores the bit shifted out from the LSB in the carry flag, and stores the previous MSB value in the MSB It is.

The (SRL r) instruction shifts the data stored in the register (A, B, C, D, E, H, L) indicated by r by 1 bit to the right (from the MSB to the LSB side), and from the LSB This instruction stores the shifted-out bit in the carry flag and stores 0 in the MSB. The (SRL (HL)) instruction shifts the data stored in the HL register to the right by 1 bit and shifts from the LSB. This is an instruction to store the out bit in the carry flag and store 0 in the MSB. The (SRL (qq + d)) instruction is indicated by d in the data stored in the register (IX, IY) indicated by qq. The data stored at the address indicated by the addition result of data (d = 8 to 127, −1 to −128) is shifted to the right by 1 bit, and the bit shifted out from the LSB is captured. -An instruction to store in the flag and 0 in the MSB. The (SRLT (k)) instruction uses the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. This is an instruction to shift data stored in the address by 1 bit to the right, store the bit shifted out from the LSB in the carry flag, and store 0 in the MSB.
<Other instructions / bit manipulation instructions>

  The bit operation instruction is an instruction for performing various operations in bit units, and corresponds to, for example, a BITT instruction, a SETT instruction, a REST instruction, and the like.

For example, the (BITT b, (k)) instruction inverts data stored at an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. The (SETT b, (k)) instruction is an instruction that sets the data stored in the T register to the upper byte and 1 stored in the data stored in the register indicated by k. The (REST b, (k)) instruction is an instruction to set 0 to data stored in an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. is there.
<Other instructions / arithmetic & jump instructions>

  The calculation & jump instruction is an instruction for performing a branch process based on the calculation and the calculation result of the calculation. For example, a JCPT instruction, a JTT instruction, a JBITT instruction, or the like is applicable.

  For example, the instruction (JCPT Z, A, (k), e), from the data stored in the A register, the data stored in the T register is the upper byte, and the data stored in the register indicated by k is the lower byte. When the Z flag is 1, when the Z flag is 1, the address indicated by e is loaded into the PC (program counter) (branch to the address indicated by e), and the Z flag is 0 In this case, it is an instruction to execute a subsequent instruction. The instruction (JCPT NZ, A, (k), e) is obtained by changing the data stored in the T register from the data stored in the A register with the upper byte, k. The data stored in the address stored in the indicated register is subtracted from the address stored in the lower byte. If the Z flag is 0, the address indicated by e is set in the PC (program counter). It is an instruction to load (branch to an address indicated by e) and execute the subsequent instruction when the Z flag is 1.

  In the (JCPT C, A, (k), e) instruction, from the data stored in the A register, the data stored in the T register is the upper byte, and the data stored in the register indicated by k is the lower byte. The data stored in the address having the data stored in the address as the lower byte is subtracted, and when the carry flag is 1, the address indicated by e is loaded into the PC (program counter) (to the address indicated by e) Branch), and when the carry flag is 0, it is an instruction for executing the subsequent instruction. The instruction (JCPT NC, A, (k), e) is stored in the T register from the data stored in the A register. When the carry flag is 0, the stored data is subtracted from the address where the stored data is the upper byte and the data stored in the register indicated by k is the lower byte. Is an instruction for loading the address indicated by e into the PC (program counter) (branching to the address indicated by e) and executing the subsequent instruction when the carry flag is 1.

  The instruction (JCPT Z, (k), ss, e) adds an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte, and 1 is added to the address. The 2-byte data stored in the pair register (BC, DE) indicated by ss is subtracted from the 2-byte data stored at the specified address, and when the Z flag is 1, the address indicated by e is set to PC. (Program counter) is an instruction to load (branch to an address indicated by e) and execute the subsequent instruction when the Z flag is 0. (JCPT NZ, (k), ss, e) The data stored in the T register is the upper byte, the data stored in the register indicated by k is the lower byte, and the address obtained by adding 1 to the address. The 2-byte data stored in the pair register (BC, DE) indicated by ss is subtracted from the 2-byte data, and when the Z flag is 0, the address indicated by e is loaded into the PC (program counter). (Branch to an address indicated by e), and when the Z flag is 1, this is an instruction for executing the subsequent instruction.

  The (JCPTC C, (k), ss, e) instruction adds an address having the data stored in the T register as the upper byte, the data stored in the register indicated by k as the lower byte, and 1 to the address. The 2-byte data stored in the pair register (BC, DE) indicated by ss is subtracted from the 2-byte data stored at the specified address, and when the carry flag is 1, the address indicated by e is set to PC. It is an instruction to load (program counter) (branch to the address indicated by e) and execute the subsequent instruction when the carry flag is 0. The (JCPT NC, (k), ss, e) instruction is , An address having the data stored in the T register as the upper byte, the data stored in the register indicated by k as the lower byte, and an address obtained by adding 1 to the address The 2-byte data stored in the pair register (BC, DE) indicated by ss is subtracted from the 2-byte data stored in, and when the carry flag is 0, the address indicated by e is set to PC (program This is an instruction to load the counter) (branch to an address indicated by e) and execute the subsequent instruction when the carry flag is 1.

  The (JTT Z, (k) e) instruction calculates the numerical value 0 from the data stored in the address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. When the Z flag is 1, the address indicated by e is loaded into the PC (program counter) (branch to the address indicated by e), and when the Z flag is 0, the subsequent instruction is executed. The (JTT NZ, (k) e) instruction is an instruction from data stored at an address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. The numerical value 0 is subtracted, and if the Z flag is 0, the address indicated by e is loaded into the PC (program counter) (branch to the address indicated by e), and if the Z flag is 1, This is an instruction for executing a subsequent instruction.

The (JBITT Z, b, (k), e) instruction includes the data stored in the address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. The inverted data of the bit indicated by b is stored in the Z flag, and when the Z flag is 1, the address indicated by e is loaded into the PC (program counter) (branch to the address indicated by e), and the Z flag Is an instruction to execute the following instruction when 0 is 0, the (JBITT NZ, b, (k), e) instruction stores the data stored in the T register in the upper byte, the register indicated by k. Of the data stored in the address having the lower data as the lower byte, the inverted data of the bit indicated by b is stored in the Z flag, and when the Z flag is 0, the address indicated by e is set to PC Program counter) in the load branches to (address indicated by e), if Z flag is 1 is an instruction to execute the subsequent instruction.
<Other instructions / arithmetic & return instructions>

  The operation & return instruction is an instruction for performing a return process based on the operation and the operation result of the operation, and corresponds to, for example, an RTT instruction.

For example, the (RTT Z, (k)) instruction is a numerical value 0 from the data stored in the address having the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. When the Z flag is 1, the address stored in SP and (SP + 1) is loaded into the PC (program counter) (returned to the address indicated by SP and (SP + 1)), and the Z flag is 0. In the case of (1), an instruction to execute a subsequent instruction is executed. The (RTT NZ, (k)) instruction has the data stored in the T register as the upper byte and the data stored in the register indicated by k as the lower byte. The value 0 is subtracted from the data stored at the address to be loaded, and when the Z flag is 0, the address stored in SP and (SP + 1) is loaded into the PC (program counter). It returned to the address indicated by SP and (SP + 1)), if Z flag is 1 is an instruction to execute the subsequent instruction.
<Other instructions / Compound instructions>

  The compound instruction is an instruction in which a plurality of processes are combined, for example, an INCPLD instruction, an INCWLD instruction, a DECPLD instruction, a DECPWLD instruction, or the like.

  The (INCPLD A, r) instruction subtracts the data stored in the register (B, C, D, E, H, L) indicated by r from the data stored in the A register, and the carry flag is 1. In this case, 1 is added to the data stored in the A register, and 0 is stored in the A register when the carry flag is 0. The (INCPLD (HL), r) instruction is stored in the HL register. The data stored in the register (B, C, D, E, H, L) indicated by r is subtracted from the data stored at the address indicated by the data, and stored in the HL register when the carry flag is 1. This instruction adds 1 to the data stored at the address indicated by the read data and stores 0 in the data stored at the address indicated by the data stored in the HL register when the carry flag is 0. .

  The (INCPLD A, n) instruction subtracts the numerical value n from the data stored in the A register, adds 1 to the data stored in the A register when the carry flag is 1, and the carry flag is 0 The (INCPLD (HL), n) instruction subtracts the numerical value n from the data stored at the address indicated by the data stored in the HL register, and the carry flag is 1. In this case, 1 is added to the data stored at the address indicated by the data stored in the HL register, and when the carry flag is 0, 0 is added to the data stored at the address indicated by the data stored in the HL register. Is an instruction to memorize.

  The (INCPLD HL, mn) instruction subtracts the numerical value mn from the data stored in the HL register, adds 1 to the data stored in the HL register when the carry flag is 1, and the carry flag is 0 The instruction (INCPWLD (HL), mn) is stored at the address indicated by the data stored in the HL register and at the address indicated by the data +1 stored in the HL register. The numerical value mn is subtracted from the data, and when the carry flag is 1, 1 is added to the data stored at the address indicated by the data stored in the HL register and the data indicated by the data +1 stored in the HL register. When the carry flag is 0, the address indicated by the data stored in the HL register and the data stored in the HL register + This is an instruction for storing 0 in the data stored at the address indicated by 1.

  The (DECPLD A, r) instruction subtracts 1 from the data stored in the A register, and when the carry flag is 1, stores it in the register (B, C, D, E, H, L) indicated by r. The stored data is stored in the A register, and when the carry flag is 0, 1 is subtracted from the A register. When the data stored in the register (B, C, D, E, H, L) indicated by r is subtracted from the data stored in, and the carry flag is 1, the register (B, C, D, E, H, L) is stored in the data stored at the address indicated by the data stored in the HL register, and stored in the HL register when the carry flag is 0. Data indicated by the data This instruction subtracts 1 from the data stored in the dress.

  The (DECPLD A, n) instruction subtracts the numerical value n from the data stored in the A register, stores the numerical value n in the A register when the carry flag is 1, and stores the numerical value n when the carry flag is 0. This is an instruction to subtract 1 from the data stored in the register. The (DECPLD (HL), n) instruction subtracts the numerical value n from the data stored at the address indicated by the data stored in the HL register, When the flag is 1, the numerical value n is stored in the data stored at the address indicated by the data stored in the HL register. When the carry flag is 0, the numerical value n is stored at the address indicated by the data stored in the HL register. This instruction subtracts 1 from the data.

  The (DECPLD HL, mn) instruction subtracts the numerical value mn from the data stored in the HL register, stores the numerical value mn in the HL register when the carry flag is 1, and outputs the HL when the carry flag is 0. This is an instruction to subtract 1 from the data stored in the register. The (DECPWLD (HL), mn) instruction is an address indicated by the data stored in the HL register and an address indicated by the data +1 stored in the HL register. When the numerical value mn is subtracted from the stored data and the carry flag is 1, the numerical value is stored in the data stored in the address indicated by the data stored in the HL register and the data stored in the address indicated by the data stored in the HL register + 1. When mn is stored and the carry flag is 0, the address indicated by the data stored in the HL register and the HL register This is an instruction to subtract 1 from the data stored at the address indicated by the stored data + 1.

  For example, in the basic random number initial value update process (step S115) of the main control unit main process described above, the normal timer random number value is stored in the A register, and the maximum value (for example, 100) of the normal timer random value is stored in the numerical value n. If the (INCPLD A, n) instruction is executed after (loading), if the carry flag is 1, that is, if the usual timer random number is not the maximum value, 1 is added to the ordinary timer random value. When the carry flag is 0, that is, when the usual timer random number value reaches the maximum value, 0 can be stored in the ordinary timer random value. For this reason, the usual timer random number value can be easily updated by only the (INCPLD A, n) instruction, and the program capacity may be reduced and the processing speed may be improved.

  Further, in the basic random number initial value updating process (step S115) of the main control unit main process described above, the normal timer random number value is stored in the A register, and the maximum value (for example, 100) of the normal timer random value is stored in the numerical value n. If the (DECPLD A, n) instruction is executed after (loading), if the carry flag is 1, that is, if the usual timer random number value becomes negative, the ordinary timer random number value is When the maximum value of the figure timer random value is stored and the carry flag is 0, that is, when the common timer random number is not a negative value, 1 can be subtracted from the common timer random value. For this reason, it is possible to easily update the regular timer random number value only with the (DECPLD A, n) instruction, and it may be possible to reduce the program capacity and improve the processing speed. In this example, the random number value is updated only by the A register. However, another register (for example, R register) may be used together, or a hardware random value may be used together.

  As described above, the pachinko machine 100 according to the present embodiment is a gaming machine including at least a CPU (for example, the CPU 304) and a ROM (for example, the ROM 306) in which at least a game control program is stored. The gaming table is a pachinko machine or a slot machine, and the CPU includes at least a specific register (for example, a T register), and the gaming control program performs a predetermined process (for example, FIG. 1 shown in FIG. 31). Related lottery process) and a predetermined sub-process called from the predetermined process (for example, the number of reservations stored in the “retention number storage area (RWM area address F040H)” in step S1103 in FIG. 34 is transferred to the A register. The predetermined process includes a first process and a second process (for example, as shown in FIG. 31). The first process which is two processes of the separate symbol random number transfer process, the special symbol lottery process, the display symbol lottery process, the special symbol variable time lottery process, the special symbol variable time setting process, and the special symbol on-hold information transfer process The predetermined sub-process is called from both the first process and the second process, and the process using the specific register is the predetermined sub-process. It is a gaming machine characterized by being at least executable.

  The first process according to the present invention is a process called from the main control section main process (main loop process) (for example, each process shown in the main control section main process of FIG. 10), and the second process according to the present invention. The process may be a process called from the main control unit timer interrupt process (timer interrupt process) (for example, each process shown in the main control unit timer interrupt process of FIG. 14), and the predetermined sub-process according to the present invention is These may be called from both the process called from the main control part main process and the process called from the main control part timer interrupt process.

  According to the pachinko machine 100 according to the present embodiment, in the sub-process called from two different processes (the first process and the second process), the process using the common specific register is executed. The program can be simplified, the code amount of the program can be reduced as compared with the conventional case, the occurrence of coding errors can be reduced, and stable game control can be performed in some cases.

  Further, the CPU can execute at least a predetermined instruction (for example, the RST instruction shown in FIG. 64), and the predetermined instruction has a predetermined address (for example, 0008H) from a process in which the instruction is executed. , 0010H, 0018H, 0020H, 0028H, 0030H, 0038H, and 0040H), and the predetermined sub-process includes the first process and the second process. It may be one of the processes that can be called from both of the processes using the predetermined instruction.

  Such a configuration makes it difficult to analyze and falsify the game control program. Therefore, it is possible to obtain an illegal profit by incorporating a program for reading out the sub-processing illegally, or an internal operation stored in the RAM illegally. There are cases where an act of acquiring information can be prevented in advance.

  Further, the CPU sets a predetermined value as an initial value as a function other than a function that is performed based on receiving a load command among functions that set a value in the specific register (for example, 8 A bit load (transfer) instruction, a 16-bit load (transfer) instruction, a stack operation instruction, a composite instruction, and the like.

  With such a configuration, the degree of freedom in designing the game control program can be increased, and stable game control can be performed in some cases.

  Further, it includes an effect control means (for example, the first sub-control unit 400 or the second sub-control part 500) for effect control, and the CPU is not mounted on the effect control means, and a game control means (game control means for performing game control). For example, it may be mounted only on the main control unit 300). Further, the CPU includes an effect control means (for example, the first sub-control unit 400 or the second sub-control part 500) for performing effect control, and a pay-out control means (for example, the pay-out control unit 600) for performing pay-out control. May be mounted on at least one of the game control means (for example, the main control unit 300) for performing game control and the payout control means, without being mounted on the effect control means.

  With such a configuration, it may be possible to make analysis and alteration of the game control program more difficult.

  The microprocessor further includes a microprocessor (for example, a basic circuit 302) including at least the CPU and the ROM, and the microprocessor has at least a predetermined output terminal (for example, a reset output terminal XRSTO), and the predetermined output terminal Can be started up at least at a predetermined timing (for example, before the execution of the random extension function), and when the predetermined condition is satisfied (for example, the time-out time shown in FIG. 115 has elapsed) A watchdog timer (for example, WDT 314, first WDT 314a, second WDT 314b) capable of generating at least a predetermined signal (for example, a WDT activation signal (WDT timeout signal) or a signal inside the CPU) , Storage area code other than the legitimate designated area A non-designated area travel prohibition circuit (for example, a non-designated area travel prohibition circuit 3142) capable of generating at least a non-designated area travel prohibition signal based on the execution of The security check started during the predetermined timing after the outside travel prohibition signal is generated may include at least a period during which the watchdog timer counter is stopped.

  With such a configuration, when performing reset processing based on the travel prohibition signal outside the designated area, the watchdog timer time-out can be stopped (automatically) without depending on the control program. In some cases, the reset process based on the prohibition signal can be performed quickly.

  In addition, the gaming machine according to the above embodiment includes a microprocessor (for example, basic circuit 302) including at least a CPU (for example, CPU 304) and a ROM (for example, ROM 306) in which at least a game control program is stored. The gaming machine is a pachinko machine or a slot machine, the microprocessor has at least a predetermined output terminal (for example, a reset output terminal XRSTO), and the microprocessor is at least randomly It has an extension function (for example, a random extension process), the random extension function is capable of randomly changing the execution start timing of the game control program, the output from the predetermined output terminal, The first level from the first level at least at a predetermined timing It changes to a second level (for example, a high level signal) higher than a bell (for example, a low level signal), and the predetermined timing is before execution of the random extension function. It is a game stand.

  In addition, the gaming machine according to the above embodiment is a game including a microprocessor (for example, basic circuit 302) including at least a CPU (for example, CPU 304) and a ROM (for example, ROM 306) for storing a game control program. The microprocessor has at least a predetermined output terminal (for example, reset output terminal XRSTO), and the microprocessor has a predetermined signal from the predetermined output terminal (for example, reset output terminal XRSTO). Start of random delay processing that is performed before the start of execution of the game control program with respect to rising timing or falling timing of output (for example, reset output signal output) (for example, rising timing for changing from a low level signal to a high level signal) It is feasible before It is a skill base.

  127 and 128 are diagrams for explaining an example of a signal output from a predetermined output terminal according to the present invention. In the figure, the voltage change of the output signal of the reset output terminal XRSTO which is an example of the predetermined output terminal and the low level which is a reference voltage for judging whether or not the first level according to the present invention is set. A threshold voltage VL and a high level threshold voltage VH, which is a reference voltage for determining whether or not the second level according to the present invention is present, are shown.

  In this example, when the voltage of the output signal of the reset output terminal XRSTO is lower than the low level threshold voltage VL, it is defined as the first level (low level), and the voltage output from the reset output terminal XRSTO is high level. When it is higher than the threshold voltage VH, it is defined as the second level (high level). In this example, hysteresis is given to the low-level threshold voltage VL and the high-level threshold voltage VH, but the present invention is not limited to this. For example, the low-level threshold voltage VL and the high-level threshold voltage VH The level threshold voltage VH may be set to the same voltage (for example, when the high voltage is 5V and the low voltage is 0V, the average of both is 2.5V).

  In FIG. 127A, the voltage of the output signal of the reset output terminal XRSTO is changed from the first level (low level) voltage to the voltage exceeding the low level threshold voltage VL after the execution of the random extension process is started. After that, during the execution of the random extension process, the voltage is further changed to a voltage exceeding the high level threshold voltage VH to be changed to the second level (high level). In FIG. 6B, the voltage of the output signal of the reset output terminal XRSTO is changed from the first level (low level) voltage to the voltage exceeding the low level threshold voltage VL almost simultaneously with the start of the random extension processing. After the change, during execution of the random extension process, the voltage is further changed to a voltage exceeding the high level threshold voltage VH to be changed to the second level (high level).

  In FIG. 8C, the voltage of the output signal of the reset output terminal XRSTO is changed from the first level (low level) voltage to the low level threshold voltage VL before the execution of the random extension process. Then, during the execution of the random extension process, after the start of the random extension process, the voltage is further changed to a voltage exceeding the high level threshold voltage VH and changed to the second level (high level). . In FIG. 4D, the voltage of the output signal of the reset output terminal XRSTO is changed from the first level (low level) voltage to the voltage exceeding the low level threshold voltage VL before the execution of the random extension process is started. Then, almost simultaneously with the start of execution of the random extension process, the voltage is further changed to a voltage exceeding the high level threshold voltage VH to be changed to the second level (high level).

  On the other hand, in FIG. 5E, the voltage of the output signal of the reset output terminal XRSTO is changed from the first level (low level) voltage to the low level threshold voltage VL before the execution of the random extension process is started. Then, before the execution of the random extension process is started, the voltage is further changed to a voltage exceeding the high level threshold voltage VH to be changed to the second level (high level). In FIG. 128 (a), the voltage of the output signal of the reset output terminal XRSTO is lowered from the first level (low level) voltage before the start of the random extension process and after the end of the fixed extension process. After changing to a voltage exceeding the threshold voltage VL, before starting the execution of the random extension process and after completing the fixed extension process, the voltage is further changed to a voltage exceeding the high level threshold voltage VH to the second level. (High level). In FIG. 5B, the voltage of the output signal of the reset output terminal XRSTO is set to the first level (low level) voltage before the start of the random extension process and almost simultaneously with the end of the fixed extension process. After changing from a low level threshold voltage VL to a voltage exceeding the low level threshold voltage VL, before starting the execution of the random extension process and after completing the fixed extension process, the voltage is further changed to a voltage exceeding the high level threshold voltage VH. The level is changed to the second level (high level).

  In addition, the microprocessor performs a random delay process in which a predetermined signal output (for example, reset output signal output) from the predetermined output terminal (for example, reset output terminal XRSTO) is performed before the execution of the game control program. Even if it can be executed before the end of (or during random delay processing), the same effect can be obtained.

  According to the gaming machine according to the above-described embodiment, it is possible to shift the timing of the predetermined signal output and the execution start timing of the game control program, so that a specific process of the game control process (for example, a soft random number update process, an initial value) In some cases, it is possible to prevent aiming of update processing and the like.

  The predetermined output terminal may be a terminal capable of outputting a reset signal. With such a configuration, for example, when a reset signal is connected to a predetermined electronic component, the electronic component can operate before game control, and the electronic component operates when an unauthorized radio wave is transmitted. It may be easier to detect fraud. In addition, since electronic components can operate before the start of the game control program, by making the operation start timing of the electronic components different from the execution start timing of the game control program, it is possible to aim at specific processing of the game control processing. There are cases where it can be prevented.

  Further, at least a security mode and a user mode may be provided, and the game control program may be a user program executed in the user mode.

  With such a configuration, it is possible to shift the timing of the predetermined signal output and the execution start timing of the user program, so that specific processing of game control processing (for example, soft random number update processing, initial value update processing, etc.) In some cases, it is possible to prevent sniper shooting.

  In addition, the execution start of the game control program may be performed after receiving at least one of a system reset and a user reset.

  With such a configuration, it is possible to shift a predetermined signal output timing and a game control program execution start timing at each system reset or user reset. Update processing, initial value update processing, and the like) may be prevented.

  In addition, a predetermined electronic component (for example, IC11 to IC14) having at least a predetermined input terminal is provided, and the predetermined input terminal (for example, reset input terminal) inputs the predetermined signal from the predetermined output terminal. Possible terminals may be used.

  With such a configuration, the electronic component can be operated before the start of the game control program, so that the operation start timing of the electronic component and the execution start timing of the game control program are considered to be different. In some cases, it is possible to prevent a specific process from being aimed.

  FIG. 129 is a diagram illustrating changes in the system clock signal, the address signal, the data signal, the control signal, and the reset output signal at the time of user reset. As described above, there are two types of user resets according to this embodiment: user reset due to timeout of WDT and user reset due to access outside the designated area. The user reset is set to be effective by setting the program management area. It works when there is.

  The user reset due to the WDT timeout is a reset that occurs based on the WDT timeout signal, and is configured to output a first fixed value (for example, E000h) as an address signal during the reset. On the other hand, the user reset due to access outside the designated area is a reset that occurs based on the travel prohibition signal outside the designated area, and during the reset, a second fixed value (for example, a value other than E000h, such as 8000h) is used as the address signal. Is output.

  When a user reset occurs, the CPU core, timer circuit, arithmetic circuit, input / output port, communication circuit, interrupt controller, etc. are initialized, and execution of the user program (game control program) is started from the reset address (0000h) and started. The watchdog timer that has been set is also cleared and restarted (automatically) regardless of the control program.

  As described above, when the predetermined condition is satisfied (for example, when the time-out period shown in FIG. 115 elapses), the microprocessor performs a predetermined signal (for example, a WDT activation signal (WDT time-out signal)) A designated area based on the execution of a watchdog timer (for example, WDT 314, first WDT 314a, second WDT 314b) capable of generating at least a storage area code other than a legally designated area. At least an out-of-designated area travel prohibition circuit (for example, out-of-designated-area travel prohibition circuit 3142) that can generate an out-of-designated travel prohibition signal, and after the predetermined out-of-designated area travel prohibition signal is generated During the security check that is initiated during the timing of Period during which the counter is stopped may be included at least.

  It should be noted that “the watchdog timer counter is stopped” according to the present invention means that when the counter is temporarily stopped, the counter temporarily stops after the counter is set to the initial value or 0. If the counter continues to count, but the counter is substantially stopped (does not time out) by continuing to clear and restart the counter before the counter times out, the counter value is set to the maximum security check time. This includes a case where the counter is substantially stopped (not timed out) by setting it longer than the processing time and avoiding a timeout during the security check. In addition, in the “period when the watchdog timer counter is stopped”, the system clock is set to a predetermined period from the occurrence of the out-of-designated area travel prohibition signal to the period from the occurrence of the out-of-designated area travel prohibition signal to immediately after the generation of the signal. After the clock has elapsed (for example, from the occurrence of the out-of-designated area travel prohibition signal to the falling edge or rising edge one clock after the system clock), part or all of the period from the rising edge of the output signal of the reset output terminal XRSTO Etc. are also included. Also, the WDT is built in the microcomputer, and at least the period during which the WDT counter is stopped is included in the security check that is started during the predetermined timing after the WDT timeout occurs, and the WDT is built in the microcomputer. In addition, at least a period during which the WDT counter is stopped is included in the security check that is started during the predetermined timing after the out-of-designated area travel prohibition signal is generated.

  With such a configuration, when performing reset processing based on the travel prohibition signal outside the designated area, the watchdog timer time-out can be stopped (automatically) without depending on the control program. In some cases, the reset process based on the prohibition signal can be performed quickly.

  Further, the pachinko machine 100 according to the present embodiment is a gaming machine including at least a CPU (for example, the CPU 304) and a ROM (for example, the ROM 306) in which at least a game control program is stored. Is a pachinko machine or a slot machine, and when a predetermined condition is satisfied (for example, when the timeout time shown in FIG. 115 elapses), a predetermined signal (for example, a WDT activation signal (WDT timeout signal), CPU A watchdog timer (for example, WDT 314, first WDT 314a, second WDT 314b) that generates at least an internal signal), and the CPU triggers the game control program at a predetermined address (for example, the generation of the predetermined signal). 62, and can be executed from the address 0000h shown in FIG. Are adjustable configuration time from the generation of a constant signal to the execution start of the game control program, it is the amusement machine according to claim.

  According to the pachinko machine 100 according to the present embodiment, the time until the game control program is executed can be changed, and the execution timing of the game control program (for example, the lottery timing for determination of success / failure) is grasped. In some cases, it is possible to prevent illegal acts and to perform stable game control.

  The watchdog timer according to the present invention includes both a CPU separate from the CPU and a built-in CPU. In the former case, the reset signal is input from the watchdog timer to the CPU, so the signal line is external. In the latter case, since the reset signal is wired inside the CPU, the signal line is not exposed to the outside. Therefore, in the latter case, it is possible to conceal whether or not the reset signal is generated based on the timeout of the WDT (whether or not the CPU is reset) and to grasp the execution timing of the game control program. In some cases, illegal acts can be prevented more reliably.

  The microprocessor further includes a microprocessor (for example, a basic circuit 302) including at least the CPU and the ROM, and the microprocessor has at least a predetermined output terminal (for example, a reset output terminal XRSTO), and the predetermined output terminal Can start at least at a predetermined timing, and the predetermined timing may be before the start of a random delay process performed before the execution of the game control program.

  With such a configuration, it is possible to shift the timing of the predetermined signal output and the execution start timing of the game control program. ) May be prevented.

  Further, the CPU changes the rising timing or falling timing (for example, a low level signal to a high level signal) of a signal (for example, a reset output signal output) from a predetermined output terminal (for example, a reset output terminal XRSTO). May be executed before the start of the random delay process performed before the execution of the game control program.

  With such a configuration, it is possible to make the time from the generation of the reset signal to the output of the predetermined signal constant while changing the time until the game control program is executed, and stable game control May be possible.

  The predetermined output terminal may be a terminal capable of outputting a reset signal. With such a configuration, for example, when a reset signal is connected to a predetermined electronic component, the electronic component can operate before game control, and the electronic component operates when an unauthorized radio wave is transmitted. It may be easier to detect fraud. In addition, since electronic components can operate before the start of the game control program, by making the operation start timing of the electronic components different from the execution start timing of the game control program, it is possible to aim at specific processing of the game control processing. There are cases where it can be prevented.

  Further, at least a security mode and a user mode may be provided, and the game control program may be a user program executed in the user mode.

  With such a configuration, it is possible to shift the timing of the predetermined signal output and the execution start timing of the user program, so that specific processing of game control processing (for example, soft random number update processing, initial value update processing, etc.) In some cases, it is possible to prevent sniper shooting.

  In addition, a register (for example, a fourth internal information register shown in FIG. 104) in which at least predetermined information indicating a reset factor (for example, information indicating whether or not the reset factor generated immediately before is a system reset) is set. The game control program may be configured not to include (do not execute) processing based on the predetermined information (for example, processing to write information read from the fourth internal information register to the general-purpose register). .

  With such a configuration, there is a case where it is possible to prevent an illegal act such as intentionally generating a reset of the CPU and aiming at an execution timing of a specific process (for example, a soft random number update process, an initial value update process, etc.). .

  Further, the microprocessor travels outside the designated area capable of generating at least a running prohibition signal outside the designated area based on the execution of the watchdog timer and a code in a storage area other than the legitimate designated area. At least a prohibition circuit (for example, a travel prohibition circuit 3142 outside the designated area), and during the security check that is started during the predetermined timing after the travel prohibition signal outside the designated area is generated, At least a period during which the counter of the timer is stopped may be included.

  With such a configuration, when performing reset processing based on the travel prohibition signal outside the designated area, the watchdog timer time-out can be stopped (automatically) without depending on the control program. In some cases, the reset process based on the prohibition signal can be performed quickly.

  Also, a game control including a random number circuit that changes a numerical value at a predetermined period, and a process of extracting a numerical value from the random number circuit based on the fact that a predetermined extraction condition is satisfied and performing a lottery regarding a game based on the numerical value And a microcomputer including a CPU for performing processing, a ROM in which the contents of the game control processing are stored in advance, and a RAM for temporarily storing data. A process that is executed when the power is shut off, and includes a process of storing predetermined data indicating that the process has been performed in a predetermined area of the RAM. When the predetermined data is stored, it is possible to return the game control process without performing an initialization process for initializing the RAM area. If the predetermined data is not stored, it is impossible to return the game control process without performing the initialization process, and the microcomputer is activated when the power is turned on. A time variation circuit for performing a time variation process for randomly varying the length of time from when a signal is input to when the game control process is started, and a code for a storage area other than a valid designated area are executed. A non-designated area running prohibition circuit for generating a non-designated area running prohibition signal based on the above, and in the case of a system reset that is executed based on the input of the start signal A process for checking whether the contents of the game control process stored in the ROM are abnormal by the microcomputer; and After the security check including the inter-process variation process is performed, the game control process is started, and in the case of a user reset that is executed based on the occurrence of the out-of-designated-area travel prohibition signal, the CPU Since the security check is not performed by the microcomputer, the time variation process is not performed, the game control process is started, and the CPU performs the game control process regardless of the system reset or the user reset. The game machine may be characterized in that no power interruption process is performed and the predetermined data is not stored in the predetermined area.

  In addition, the gaming machine (for example, the slot machine 1100) according to the present embodiment includes a CPU (for example, the CPU 1304), a ROM (for example, the ROM 1306) in which at least a control program is stored, and a RAM (for example, a RAM that can temporarily store data). , RAM 1308), and a gaming machine equipped with a microcomputer, the gaming machine is a slot machine, and the upper byte of the first address of the RAM is larger than the upper byte of the first address of the ROM The CPU has at least a first register (eg, a specific register), the CPU has at least a second register (eg, a flag register), and the first register has a plurality of methods. A register whose value can be set by any one of the methods, At least one is a first method, at least one of the plurality of methods is a second method, and the first method is a method of setting a value by a direct value, The second method is a method of setting the same value as the upper byte of the top address of the RAM as an initial value, and the CPU receives an LD instruction among functions for setting a value in the first register. As a function performed based on the above, the CPU has only a function for setting a value by the first method, and the CPU executes the LD instruction among the functions for setting a value in the first register. As a function other than the function performed based on the received, at least a function for setting a value by the second method, the second method is executed without depending on the control program, Control program , A program including at least an instruction to access the RAM using the first register in which a value is set by any one of the plurality of methods, and the second register is a flag register (for example, , F register), and one bit of the second register is a bit functioning as a first flag (for example, a zero flag), and one bit of the second register is a second flag ( For example, it is a bit that functions as a second zero flag).

  In addition, a gaming machine (for example, pachinko machine 100) according to the present embodiment includes a CPU (for example, CPU 304), a ROM (for example, ROM 306) in which at least a control program is stored, and a RAM (for example, a RAM that can temporarily store data). , RAM 308), and a gaming machine having a microcomputer built therein, the gaming machine is a pachinko machine, and the upper byte of the first address of the RAM is larger than the upper byte of the first address of the ROM The CPU has at least a first register (eg, a specific register), the CPU has at least a second register (eg, a flag register), and the first register has a plurality of methods. A register whose value can be set by any one of the methods, wherein at least one of the plurality of methods is: One method, at least one of the plurality of methods is a second method, the first method is a method of setting a value by a direct value, and the second method is: In this method, the same value as the upper byte of the top address of the RAM is set as an initial value, and the CPU is performed based on receiving an LD instruction among functions for setting a value in the first register. As a function, the CPU has only a function in which a value is set by the first method, and the CPU executes a function based on receiving the LD instruction among functions for setting a value in the first register. As a function other than the function to be displayed, it has at least a function in which a value is set by the second method. The second method is executed without depending on the control program. Direction The program includes at least an instruction for accessing the RAM using the first register in which a value is set by any one of the methods, and the second register is a flag register (for example, an F register) Yes, one bit of the second register is a bit that functions as a first flag (for example, a zero flag), and one bit of the second register is a second flag (for example, a second zero flag) It is a gaming machine characterized by being a bit that functions as

  According to the slot machine 1100 or the pachinko machine 100 according to the present embodiment, the same value as the upper byte of the start address of the RAM can be set as the initial value of the first register. When accessing the RAM, only the lower address of the RAM needs to be specified, and it may be possible to reduce the amount of program code and improve the processing speed.

  In addition, since it is possible to set the same value as the upper byte of the top address of the RAM as the initial value of the first register regardless of the control program, the operation to set the value in the first register after power-on It is possible to access the RAM without using the first register, and the problem that the information of the unintended address is accessed because the value of the first register is incorrect will occur. Sometimes it can be prevented.

  In addition, among the functions for setting a value in the first register, the function performed based on receiving the LD instruction has only a function for setting a value by a direct value. As a result, it is possible to avoid occurrence of address setting mistakes, data read / write mistakes to RAM, etc., and stable control (for example, game control) can be performed. There is.

  In addition, since the first register is frequently used for operations, it is possible to prevent the occurrence of a problem that an incorrect value is set in the first register via a register that stores an unintended operation result. There are cases where it is possible.

  In addition, since the value set in the first register can be easily confirmed visually on the source code, the coding review work and debugging efficiency can be improved, and the occurrence of mistakes is greater than before. In some cases, stable control (for example, game control) can be performed.

  In addition, the first register is used less frequently than other easy-to-use registers that allow both a set of values through the register and a set of values as direct values. There are cases where the efficiency of work and debugging can be increased.

  In addition, by providing a flag register having a bit that functions as a first flag register and a bit that functions as a second flag register, an instruction that changes the values of a plurality of flags including these two flags, An instruction that changes only one of the two flags can be executed, and combining these can complicate the relationship between the change in the contents of the flag register and the flow of program execution. In some cases, analysis is difficult and analysis of an illegal program can be prevented.

  The LD instruction may be a kind of load instruction for transferring a value to a register.

The first register (for example, a specific register) may be set to the initial value when a reset (for example, a system reset) occurs.
The reset may be a system reset.

  In addition, at least one of the plurality of methods is a third method, and the third method receives the LD instruction among functions for setting a value in the first register in the CPU. The third method may be a method using a function performed based on receipt of a stack operation instruction.

  Further, the microcomputer is capable of shifting to a user mode through a security mode, and the control program is executed by the CPU in the user mode, and whether the control program is a normal program in the security mode. It is good also as what is checked.

  The microcomputer includes at least a payout control (for example, payout control unit 600) provided with the microcomputer, and the payout control means is a control means capable of executing at least payout control for paying out a prize ball. The program may be a payout control program.

  The main control means (for example, the main control unit 1300 and the main control unit 300) provided with at least the microcomputer is provided, and the main control means can execute at least payout control for paying out a prize ball. Control means capable of transmitting at least a command (for example, a command including power-on information) to the means (for example, the payout control unit 600) may be used.

  In addition, a gaming machine (for example, pachinko machine 100) according to the present embodiment includes a CPU (for example, CPU 304), a ROM (for example, ROM 306) in which at least a game control program is stored, and a RAM (for which data can be temporarily stored) ( For example, the gaming machine is a pachinko machine or a slot machine, and the upper byte of the first address of the RAM is higher than the first address of the ROM. Larger than a byte, the CPU has at least a first register (for example, a specific register), and the first register is a register whose value can be set by any one of a plurality of methods. , At least one of the plurality of methods is a first method, and at least one of the plurality of methods. One is a second method, the first method is a method of setting a value by a direct value, and the second method is the same as the upper byte of the head address of the RAM as an initial value. Among the functions for setting a value in the first register, the CPU performs a function based on receiving a load instruction, and the value is set by the first method. Among the functions for setting a value in the first register, the CPU has a function other than the function performed based on the reception of the load instruction. At least a function for setting a value; the second method is executed without depending on the game control program; at least a part of the game control program is a first program; At least a part of the control program is a second program, at least a part of the game control program is a third program, and the third program is a program that is called at least from the first program. And the third program is a program that is called at least from the second program, and the third program has the value set by any one of the plurality of methods. A game machine comprising: a program including at least an instruction for accessing the RAM using a register.

  According to such a configuration, since it is possible to set the same value as the upper byte of the head address of the RAM as the initial value of the first register, when accessing the RAM using the first register, Only the lower address of the RAM needs to be specified, and there are cases where it is possible to reduce the amount of program code and improve processing speed.

  In addition, since it is possible to set the same value as the upper byte of the top address of the RAM as the initial value of the first register regardless of the control program, the operation to set the value in the first register after power-on It is possible to access the RAM without using the first register, and the problem that the information of the unintended address is accessed because the value of the first register is incorrect will occur. Sometimes it can be prevented.

  In addition, among the functions for setting a value in the first register, the function performed based on receiving the LD instruction has only a function for setting a value by a direct value. As a result, it is possible to avoid occurrence of address setting mistakes, data read / write mistakes to RAM, etc., and stable control (for example, game control) can be performed. There is.

  In addition, since the first register is frequently used for operations, it is possible to prevent the occurrence of a problem that an incorrect value is set in the first register via a register that stores an unintended operation result. There are cases where it is possible.

  In addition, since the value set in the first register can be easily confirmed visually on the source code, the coding review work and debugging efficiency can be improved, and the occurrence of mistakes is greater than before. In some cases, stable control (for example, game control) can be performed.

  In addition, the first register is used less frequently than other easy-to-use registers that allow both a set of values through the register and a set of values as direct values. There are cases where the efficiency of work and debugging can be increased.

  The second program may be a program called from the first program.

  The CPU may have at least a function of setting an initial value as a function other than a function performed based on receiving a load command among functions for setting a value in the first register. Good.

  The first register may be set to the initial value when a reset occurs.

  In addition, among the functions for setting a value in the first register, the CPU performs a function performed based on receiving a stack operation instruction as a function other than a function performed based on receiving a load instruction. It is good also as what has at least.

  The CPU includes at least a plurality of registers, at least one of the plurality of registers is the first register, and at least one of the plurality of registers is a second register. The second register may be a flag register.

  Further, the microcomputer may include at least a watch dog timer (for example, WDT 314).

  Further, the microcomputer includes at least an IAT circuit, and the IAT circuit is configured to output at least an out-of-designated area travel prohibition signal based on execution of a code in a storage area other than a valid designated area. It may be a circuit that can be generated.

  The microcomputer may include at least a random number generation circuit (for example, a random number generation circuit 318).

  In addition, the microcomputer can be shifted to a user mode through a security mode, and the program is executed by the CPU in the user mode, and whether the ROM program is a normal program in the security mode. It is good also as what is checked.

  The microcomputer may include a control unit (for example, the main control unit 300) provided with at least the microcomputer, and the control unit may execute at least a payout control for paying out a prize ball.

  The control means (hereinafter referred to as “first control means”) can transmit at least a command to a second control means (for example, the payout control unit 600), and the second control means The control means may be capable of executing at least a payout control for paying out a prize ball.

  Further, the CPU built in the microcomputer provided in the second control means may include the first register.

  The first control means is capable of transmitting a command to a third control means (for example, the first sub-control unit 400), and the third control means is an effect that produces a game. The CPU that can execute at least the control and that is built in the microcomputer provided in the third control means may not include the first register.

  In addition, a gaming machine (for example, pachinko machine 100) according to the present embodiment includes a CPU (for example, CPU 304), a ROM (for example, ROM 306) in which at least a control program is stored, and a RAM (for example, a RAM that can temporarily store data). , RAM 308), and a game machine having a microcomputer incorporating the same, wherein the game machine is a pachinko machine or a slot machine, and the CPU has at least a first register (for example, a specific register) The CPU has at least a second register (for example, a flag register), and the first register is a register whose value can be set by any one of a plurality of methods. At least one of the methods is a first method, and the first method is a method of setting a value by a direct value. Among the functions for setting a value in the first register, the CPU has only a function for setting a value by the first method as a function performed based on receiving an LD command, The second register is a flag register (for example, an F register), and one bit of the second register is a bit that functions as a first flag (for example, a zero flag), and the second register One bit is a bit that functions as a second flag (for example, a second zero flag), and the control program includes a program that includes an instruction to change the first flag (for example, the first flag according to an operation result). A game table including an instruction to turn off one flag).

  According to such a configuration, among the functions for setting a value in the first register, the function performed based on receiving the LD instruction has only a function for setting a value by a direct value. As a result that the value of the first register cannot be inadvertently changed, it is possible to avoid the occurrence of an address setting error or a data read / write error to the RAM, and stable control (for example, game control) May be able to do.

  In addition, since the first register is frequently used for operations, it is possible to prevent the occurrence of a problem that an incorrect value is set in the first register via a register that stores an unintended operation result. There are cases where it is possible.

  In addition, since the value set in the first register can be easily confirmed visually on the source code, the coding review work and debugging efficiency can be improved, and the occurrence of mistakes is greater than before. In some cases, stable control (for example, game control) can be performed.

  In addition, the first register is used less frequently than other easy-to-use registers that allow both a set of values through the register and a set of values as direct values. There are cases where the efficiency of work and debugging can be increased.

  In addition, by providing a flag register having a bit that functions as a first flag and a bit that functions as a second flag, an instruction that changes the values of a plurality of flags including these two flags, and two flags Instructions that change only one of them can be executed, and by combining these, the relationship between the change in the contents of the flag register and the flow of program execution can be complicated, and program analysis can be performed. In some cases, it may be difficult to prevent unauthorized programs from being analyzed.

  The first flag may be a first zero flag, and the second flag may be a second zero flag.

  In addition, by providing a flag register having a bit that functions as a first zero flag and a bit that functions as a second zero flag, an instruction that changes the values of a plurality of flags including these two zero flags, and two zero flags Instructions that change only one of them can be executed, and by combining these, the relationship between the change in the contents of the flag register and the flow of program execution can be further complicated, and program analysis In some cases, it is possible to prevent unauthorized programs from being analyzed.

  Further, the upper byte of the start address of the RAM may be larger than the upper byte of the start address of the ROM.

  Further, at least one of the plurality of methods is a second method, and the second method is a method of setting the same value as the upper byte of the top address of the RAM as an initial value, Among the functions for setting a value in the first register, the CPU has at least a function for setting a value by the second method as a function other than a function performed based on receiving an LD command. The second method may be a method that is executed without depending on the control program.

  The control program may be a program including at least an instruction for accessing the RAM using the first register in which a value is set by any one of the plurality of methods.

  According to such a configuration, when reading / writing RAM data, it is only necessary to specify the lower address of the RAM by fixing the specific register as a value indicating the upper address of the RAM, thereby reducing the amount of program code. As a result, it is possible to reduce the occurrence of coding errors as a result of not being able to change the value of a specific register carelessly.

  Further, the microcomputer is capable of shifting to a user mode through a security mode, and the control program is executed by the CPU in the user mode, and whether the control program is a normal program in the security mode. It may be the one where the check is performed.

  Further, the microcomputer includes at least a payout control means (for example, a payout control unit 600), and the payout control means is a control means capable of executing at least payout control for paying out a prize ball, The control program may be a payout control program.

  The main control means (e.g., the main control unit 300) provided with at least the microcomputer, the main control means for at least the payout control means capable of executing at least payout control for paying out a prize ball, It may be a control means capable of transmitting at least a command.

  The game stand according to the present invention can also be applied to a sealed pachinko machine or a medalless slot machine. In addition, the main control unit, the first sub control unit, and the second sub control unit may be configured as a single chip, or the main control unit and the first sub control unit may be configured to allow bidirectional communication. Good. Moreover, while enabling bidirectional communication between the main control unit and the first sub control unit, communication from the first sub control unit to the second sub control unit may be one-way communication.

  Further, the actions and effects described in the embodiments of the present invention only list the most preferable actions and effects resulting from the present invention, and the actions and effects according to the present invention are described in the embodiments of the present invention. It is not limited to what was done. Further, in some cases, the contents described in one configuration among the plurality of configurations described in the embodiments may be applied to other configurations to further widen the game. Therefore, for example, in the description related to the reset based on WDT, the WDT timeout signal (WDT activation signal) may be replaced with the out-of-designated area travel prohibition signal.

  The game machine according to the present invention can be applied to game machines represented by a spinning machine (slot machine), a ball game machine (pachinko machine), and the like.

DESCRIPTION OF SYMBOLS 100 Pachinko machine 208 Decoration symbol display device 208d Production area 212 1st special drawing display device 214 2nd special drawing display device 230 1st special drawing start port 232 2nd special drawing start port 2321 Blade member 234 Variable prize opening 2341 Door member 300 Main control unit 304 CPU
306 ROM
308 RAM
310 I / O
311 Timer circuit 312 Counter circuit 314 Reset control circuit 318 Random number generation circuit 400 First sub-control unit 404 CPU
406 ROM
408 RAM
500 Second sub-control unit 600 Dispensing control unit 1100 Slot machine 1300 Main control unit 1304 CPU
1306 ROM
1308 RAM
1310 I / O
1400 First sub-control unit 1500 Second control unit 100 Pachinko machine 100 'Slot machine 110'-112' Reel 130'-132 'Bet button 135' Start lever 137'-139 'Stop button 157' Liquid crystal display device 200 'Bet Button lamps 272 ′, 277 ′ Speaker 420 ′ Various lamps 300 ′ Main control unit 400 ′ First sub control unit

Claims (8)

CPU,
A ROM storing at least a control program;
RAM that can temporarily store data;
A game machine equipped with a microcomputer incorporating
The game table is a pachinko machine or a slot machine,
The CPU has at least a first register;
The CPU has at least a second register;
The first register is a register whose value can be set by any one of a plurality of methods,
At least one of the plurality of methods is a first method,
The first method is a method of setting a value by a direct value,
Among the functions for setting a value in the first register, the CPU has only a function for setting a value by the first method as a function performed based on receiving an LD command,
The second register is a flag register;
One bit of the second register is a bit that functions as a first flag,
One bit of the second register is a bit that functions as a second flag,
The control program is a program including an instruction to change the first flag.
A game stand characterized by that. The game stand according to claim 1,
The first flag is a first zero flag;
The second flag is a second zero flag.
A game stand characterized by that. The game stand according to claim 1 or 2,
The upper byte of the start address of the RAM is larger than the upper byte of the start address of the ROM,
A game stand characterized by that. It is a game stand as described in any one of Claims 1 thru | or 3, Comprising:
At least one of the plurality of methods is a second method,
The second method is a method of setting the same value as the upper byte of the top address of the RAM as an initial value,
Among the functions for setting a value in the first register, the CPU has at least a function for setting a value by the second method as a function other than a function performed based on receiving an LD command. Have
The second method is a method that is executed without depending on the control program.
A game stand characterized by that. The game table according to claim 4,
The control program is a program including at least an instruction for accessing the RAM using the first register in which a value is set by any one of the plurality of methods.
A game stand characterized by that. It is a game stand as described in any one of Claim 1 thru | or 5, Comprising:
The microcomputer can be shifted to the user mode through the security mode,
The control program is executed by the CPU in the user mode,
In the security mode, it is checked whether the control program is a normal program.
A game stand characterized by that. It is a game stand as described in any one of Claim 1 thru | or 6, Comprising:
A dispensing control means provided with at least the microcomputer;
The payout control means is a control means capable of executing at least payout control for paying out at least a prize ball,
The control program is a payout control program.
A game stand characterized by that. It is a game stand as described in any one of Claim 1 thru | or 6, Comprising:
A main control means provided with at least the microcomputer;
The main control means is a control means capable of transmitting at least a command to a payout control means capable of executing at least payout control for paying out a prize ball.
A game stand characterized by that.