JP6037978B2 - Method for controlling data packet communication device and data packet communication device - Google Patents

Description

  The present invention relates to a method for controlling a data packet communication device and a data packet communication device.

  There is Non-Patent Document 1 as a background art of the present invention. In Non-Patent Document 1, statistical information of an application operating on an Octeon (registered trademark) processor core for high-speed data processing (also referred to as bare metal, fast path, etc.) without an operating system (OS) is provided. In order to control from the control processor core, information is exchanged between the two using a shared memory.

  Management instructions to the control processor core are provided by a command line interface (CLI). Since the control processor core needs to be versatile enough to handle complicated management messages, the OS is operated.

Schmidt, A., "Profiling Bare-Metal Cores in AMP Systems", System, Software, SoC and Silicon Debug Conference (S4D), pp. 1-4, September 2012.

  The present invention solves a problem related to management of data processing in a data processing apparatus that is configured by a network processor or the like and includes a bare metal control core and a data processing core.

  The first problem is my simplification of information between the control / management system and the data system. In the conventional method, when control information and processing parameters are exchanged between the control core and the data processing core, especially when complicated control such as exclusive control is required between them, the control information In addition, there is a problem that exchange of processing parameters becomes complicated and difficult.

  The reason why the exchange of the control information and the processing parameter is complicated will be described below. The first reason is that the software differs between the data processing core and the control core. In other words, while the data processing core is used in bare metal suitable for high-speed processing, the control processor core needs to be versatile enough to handle complex management messages. It is that. Therefore, a shared memory for sharing data between the data processing core and the control core and a method for controlling an interface such as a network are different.

  The second reason is that the hardware architecture of the data processing core and the control core is different. In particular, the memory is completely virtualized in the control core, whereas the memory is not virtualized in the data processing core or the virtualization mechanism is simplified. It may be difficult to share. That is, one of the issues is to realize the control and management as described above based on a simple and low-cost method and further based on unquestionable parallel processing semantics.

  The second problem is speeding up of control and management. In the conventional method, the control core OS is interposed in the control / management processing in the control core and the control / management information I from the control core to the data processing core. Therefore, there is a problem that these processes are delayed or the speed is lowered. For example, when a server on the network is subjected to a denial-of-service attack (DoS) or the like, high-speed control is required. Therefore, speeding up such control and management is one issue. .

  In order to solve the above problems, the present invention employs the following configuration, for example. That is, data including an input of a data packet, a data processing device that processes the input data packet and outputs the processed data packet, and a control device that controls the data processing device A method for controlling a packet communication device, wherein the data processing device includes a plurality of bare metal cores and a data sharing device shared between the plurality of bare metal cores, At least one of the bare metal cores receives the input data packet, processes the received data packet, and includes the control data from the control request message when the control device receives the control request message. Create a control request packet and send the control request packet to the data processing device. And at least one of the plurality of bare metal cores receives the control request packet and transmits the control data included in the control request packet to another bare metal core via the data sharing apparatus. A method characterized by including a thing.

  According to the present invention, information between the control / management system and the data system can be simplified, and the control / management speed can be increased. Problems, configurations, and effects other than those described above will become apparent from the following description of embodiments.

1 is an explanatory diagram illustrating an example of an outline of a computer system in Embodiment 1. FIG. In Example 1, it is a block diagram which shows the structural example of a physical node. FIG. 3 is a block diagram illustrating a configuration example of a network processor in the first embodiment. In Example 1, it is an example of the simple control request message which a control board receives. In Example 1, it is an example of the control request packet corresponding to a simple control request message, and a control response packet. In Example 1, it is a sequence diagram which shows the example of control of the core for data processing by the simple control request message. In Example 1, it is an example of a MAC address correspondence table. 6 is a flowchart illustrating an example of a program selection process in the data processing core according to the first exemplary embodiment. 4 is a flowchart illustrating an example of processing for distributing control request packets received by an input processor to a plurality of queues in the first embodiment. In Example 2, it is an example of the connection type | mold control request message which a control board receives. In Example 2, it is an example of the control request packet corresponding to a connection type | mold control request message, and a control response packet. In Example 2, it is a sequence diagram which shows the example of control of the data processing core by a connection type | mold control request message. In Example 3, it is an example of the selection type | mold control request message which a control board receives. In Example 3, it is an example of the control request packet corresponding to a selection type | mold control request message, and a control response packet. In Example 4, it is an example of the repetition type | mold control request message which a control board receives. In Example 4, it is an example of the control request packet corresponding to a repetitive control request message, and a control response packet. In Example 6, it is a block diagram which shows the structural example of a control board when using a plug-in control program. In Example 6, it is a block diagram which shows the example of a structure of a control board and a general purpose core when using a plug-in control program. In Example 6, it is a flowchart which shows the example of a process when a plug-in control program exists and a control board receives a control request message.

  Embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that this embodiment is only an example for realizing the present invention, and does not limit the technical scope of the present invention. In each figure, the same reference numerals are given to common configurations.

  In this embodiment, the control core and the data processing core are used in bare metal, thereby realizing control and management by bare metal. As a result, the above-described problems caused by the heterogeneity of hardware (that is, the core structure) and software (OS and bare metal runtime routine) of the control core and the data processing core can be solved.

  That is, in the present embodiment, first, a bare metal core is also used for the control core, and the control information is processed with the bare metal. When the data processing processor receives the control request packet, the load distribution mechanism provided by the data processing processor is used to allocate the control request packet processing to one of the plurality of data processing cores. Thus, load distribution can be realized. Note that one bare metal core can perform both control processing and data processing, or can perform only control processing or only data processing. Whether a bare metal core performs control processing and data processing, only control processing, or only data processing can be changed by changing the type of program executed by the bare metal core.

  When the data processing apparatus includes cores that perform both control processing and data processing, the ratio of the number of cores that perform control processing and the number of cores that perform data processing can be dynamically changed. That is, dynamic load distribution can be realized, and consequently, the delay of the control process can be reduced and the bottleneck can be eliminated.

  By using a bare metal core for the control core, if a portable high-level language is prepared for describing data processing, the control program can be ported to another network processor or the like. Further, it becomes easy for the developer of the control program to describe the load distribution method in a high-level language, and it becomes easy to port the load distribution program together with the control program. Further, since the conventional control core can be eliminated, an LSI having a simple structure without the control core can be used, and the development cost can be reduced.

  Second, since the control core is used in bare metal, it is necessary to adapt the control process to the bare metal core. The data processing core has an architecture specialized for high-speed processing of data such as packets. Further, in the data processing core, a large number of data processing cores are integrated in one LSI, thereby realizing multi-parallel high-speed processing and at the same time reducing the cost. For this reason, the functions are limited compared to the general-purpose core used for control, and special hardware and instructions are used for speedup, making it difficult to perform complex control processing. .

  Therefore, in the present embodiment, in order to realize a complex control process using the data processing core, a general-purpose process for processing a complex control command from the outside (control protocol based on XML (Extensible Markup Language), etc.) A general-purpose computer such as a CPU (Central Processing Unit) or a PC is used.

  In this general-purpose CPU, the control commands exchanged on the control plane are converted into basic commands, disassembled, individual commands are translated into packets on the data plane, and communicated with the bare metal core. As a result, complicated control is realized. The general-purpose CPU realizes optimal control by decomposing commands with a granularity according to the architecture of the data processing core and the functions of the data processing core. The general-purpose CPU converts a variable-length control request message that requires complicated processing into a fixed-length control request packet that can be simply processed by converting the command. Further, the general-purpose CPU decomposes a command having a recursive structure or a repetitive structure into individual commands by decomposing the commands.

  Third, in this embodiment, when control / management information is exchanged between a bare metal control core and a bare metal data processing core, it is used between a plurality of data processing cores in data processing. Use data for bare metal. As such means, there are a shared memory, a bus, a network between cores (for example, an intra-chip network or SAN which is a network on an LSI) and the like. Since the core used for control and the data processing core have the same architecture and the same storage virtualization mechanism, data based on simple and unquestioning semantics can be realized. This data distribution means, such as shared memory, buses, and networks, are widely used and have established semantics, so they can be described in a high-level language. A program written in a high-level language can be easily ported to other types of network processors.

  Fourth, in order to give an external instruction to the bare metal control core, the same network interface as that used for I / O in the data processing core is used. Further, it is determined whether the packet is a data packet or a control request packet based on the identifier in the packet header. By using the same network interface, data packets and control request packets can be handled by one scheduler, and free load distribution can be easily realized. Further, since it is not necessary to use a hardware-dependent or vendor-dependent load distribution method, high portability can be realized by describing the load distribution method in a high-level language.

  FIG. 1 shows an example of an outline of a computer system in this embodiment. The computer system of this embodiment has a network virtualization function, and physical nodes 112-1 to 112-4 that transfer data packets, a network management device 111, an operator console 102, an end user PC 118-1, Including 118-2. The network 121 includes physical nodes 112-1 to 112-4 that are examples of data packet communication devices. The end user PCs 118-1 and 118-2 are connected to the network 121.

  The network management device 111 manages the entire network. The network management device 111 includes a CPU 142 and a main storage device 143. The operator can give a command for generating a virtual network to the network management apparatus 111 via the operator console 102.

  Note that the network management apparatus 111 can generate a plurality of virtual networks on one network 121. The network management device 111 gives a command to generate the components of the virtual network to the physical nodes 112-1 to 112-4 accordingly. As components of the virtual network, there are a virtual node and a virtual link (called a link sliver).

  Hereinafter, the physical nodes 112-1 to 112-4 and the end user PCs 118-1 and 118-2 will be referred to as the physical node 112 and the end-user PC 118, respectively, unless otherwise distinguished. The number of physical nodes 112 and end-user PCs 118 is not limited as long as the functions of this embodiment can be realized.

  FIG. 2 shows a configuration example of the physical node 112 in FIG. The physical node 112 includes packet processing boards 211-1 to 211-1, a control board 241, network interfaces (NIF) 251-1 to 251-n, and an in-device network 281. A control board 241, which is an example of a control device, controls each element in the physical node 112.

  The packet processing boards 211-1 to 211-1, the control board 241, and the network interface 251 are each connected by an in-device network 281. The packet processing board 211-i (i is an arbitrary number from 1 to 1) includes a network processor (NPU) 212-ij (j is an arbitrary number from 1 to m).

  The data packet input to the physical node 112 is processed by any one of the network processors 212-1 to 212-l and output from the physical node 112. When the physical node 112 receives a message for controlling these network processors 212-1 to 212-1, the control board 241 normally processes the message to control one of the network processors 212-ij. Send. Note that the control board 241 may not be used for control. In this case, a general-purpose core existing in each of the network processors 212-11 to 212-lm serves as the control board 241. The general-purpose core will be described later.

  The virtual node is generated on the physical node 112. A plurality of virtual nodes can be generated on one physical node 112. Further, virtual links (link slivers) are generated between virtual nodes (between physical nodes). The physical node 112 that is the end point of the virtual link does not need to be physically adjacent (it does not have to be directly connected to the physical link). That is, a virtual link can be generated between remote physical nodes 112.

  Hereinafter, when the packet processing boards 211-1 to 211-1, the network processors 212-11 to 212 -lm, and the network interfaces 251-1 to 251 to n are not particularly distinguished, the packet processing board 211 and the network processor 212, respectively. Will be referred to as a network interface 251. The number of the packet processing board 211, the network processor 212, and the network interface 251 is not limited as long as the functions of the present embodiment can be realized.

  FIG. 3 shows a configuration example of the network processor 212 in FIG. The network processor 212 includes an input processor 302, an output processor 303, a general-purpose core 311, an L1 cache 312, an L2 cache 313, data processing cores 321-1 to 321-n, main storage devices 322-1 to 322-n, and shared The memory 331, the memory controller 341, and the bus 361 are included.

  The input processor 302 includes input queues 304-1 to 304-l. The packet output from the intra-device network 281 is transferred to the input processor 302. The packet transferred to the input processor 302 passes through one of the input queues 304-1 to 304-l and the bus 361, and one of the data processing cores 321-1 to 321-n. Forwarded to

  The output processor 303 includes output queues 305-1 to 305-m. A packet output from one of the data processing cores 321-1 to 321-n passes through the bus 361 and one of the output queues 305-1 to 305-m, and further passes through the network interface 251. Via, it is transferred to the outside of the physical node 112.

  The bus 361 may be an on-chip network. Depending on the configuration of the network processor 212, the input queues 304-1 to 304-l and the output queues 305-1 to 305-m do not exist in the input processor 302, and the data processing cores 321-1 to 321-1 are not provided. 321-n may exist. In addition, both the control request packet and the data packet can be input to each of the input queues 304-1 to 304-l. However, only the control packet queue to which only the control request packet is input or only the data packet is input. There may be a queue for data packets to which.

  The shared memory 331, which is an example of a data sharing apparatus, is in the middle of control data and data processing, for example, between a control packet processing core, which will be described later, and data processing cores 321-1 to 321-n that perform packet data processing. It is used for sharing information generated in the system and for exchanging control signals. Main storage devices 322-1 to 322n are attached to the data processing cores 321-1 to 321-n, respectively. The shared memory 331 and the main storage devices 322-1 to 322-n may be general-purpose memories such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory). Although it can be used only for limited purposes such as CAM (content addressable memory) and TCAM (ternary content addressable memory), a higher-speed memory may be used. Further, the bus 361 can be used as an example of the data sharing apparatus.

  The data processing cores 321-1 to 321-n are cores of a small RISC (Reduced Instruction Set Computer) architecture optimized for simple packet data processing. Therefore, the data processing cores 321-1 to 321-n do not have complicated branch speed-up functions or advanced functions such as parallel computation, but at the same time perform high-speed packet processing such as specialized multithreading. It has a mechanism to execute The data processing cores 321-1 to 321-n may need to execute special instructions that are not supported in a general-purpose programming language for multi-thread control and the like.

  The general-purpose core 311 controls each element in the network processor 212, that is, the data processing cores 321-1 to 321-n, the input processor 302, the output processor 303, and the like. The general-purpose core 311 is a core of a relatively large-scale architecture optimized so that an OS such as Linux or Windows can be efficiently executed. The general-purpose core 311 may be composed of a plurality of cores.

  The memory controller 341 is connected to a main storage device 342 existing outside the network processor 212. As the main storage device 342, for example, a DRAM is used as a main medium. Since the general-purpose core 311 normally virtualizes this main memory, hardware such as an L1 cache 312 and an L2 cache 313 is attached. The main storage device 342 stores a program 351 executed by the data processing core 321, and the main storage device 322-1 attached to the shared memory 331 or the data processing cores 321-1 to 321 -n as necessary. Cached at ~ 322-n.

  In this embodiment, the general-purpose core 311 is used for loading the program 351 to the main storage device 342. As will be described later, during the operation of the data processing cores 321-1 to 321-n, the general-purpose core 311 is used. The control by 311 is not performed. Therefore, also in the present embodiment, the network is provided so that the loading of the program 351 to be processed using the general-purpose core 311 and the processing such as starting and stopping of the data processing core can be processed without using the general-purpose core 311. If the processor 212 is configured, a configuration without the general-purpose core 311 is possible.

  When the general-purpose core 311 is not provided, the program 351 may be loaded by direct memory access (DMA) from the outside of the network processor 212. The data processing core 321 may be started / stopped from the outside of the network processor 212 by input / output commands, a DMA program 351, or data exchange. By eliminating the general-purpose core 311, the LSI structure can be simplified and the development cost can be reduced.

  Hereinafter, when the input queues 304-1 to 304-l, the output queue 305-305-m, the data processing cores 321-1 to 321-n, and the main storage devices 322-1 to 322-n are not particularly distinguished, they are respectively input. The queue 304, the output queue 305, the data processing core 321, and the main storage device 322 are described. Note that the number of the input queue 304, the output queue 305, the general-purpose core 311, the data processing core 321, and the main storage device 322 is not limited as long as the functions of the present embodiment can be realized.

(Message contents in simple data processing control)
The data processing control method using the control request message will be described below. First, a simple control request message and the contents of a control request packet obtained by converting the simple control request message will be described with reference to FIGS. 4A and 4B. The physical node 112 performs communication outside the physical node 112 and communication inside the physical node 112 by Ethernet (registered trademark, hereinafter the same). The physical node 112 takes in only a packet having a specific address from the outside of the physical node 112 and rewrites the external MAC address included in the packet to the internal MAC address.

Such processing is required when virtualizing a network implemented using VLAN. A virtual link generated by such a method is called a VLAN link sliver. The VLAN link sliver and the GRE link sliver described later (virtual link using the Generic Routing Encapsulation (GRE) protocol which is an IETF standard) are described in, for example, the following documents.
Yasusi Kanada, Kei Shiraishi, and Akihiro Nakao, "Network-virtualization Nodes that Support Mutually Independent Development and Evolution of Node Components", 13th IEEE International Conference on Communication Systems (ICCS 2012), 2012-11-23.

  FIG. 4A shows an example of a control request message 411 including a control command 421 for generating a VLAN link sliver. The control command 421 associates an external MAC address 00-03-b0-00-00-11 of the physical node 112 with an internal MAC address 00-04--b0-00-00-01 of the physical node 112. , Command to create a VLAN link sliver.

  Note that a command that is decomposed into a state in which processing by the data processing core 321 is possible, such as the control command 421, is referred to as a basic command. <CNPUMAC> is a MAC address of a control interface (such as a data processing core 321) that receives a control request packet described later. <NeMIF> is an identifier of an interface that transmits a control command.

  FIG. 4B shows an example of a control request packet 412 corresponding to the control command 421 and a control response packet 417 corresponding to the control request packet 412. The control request packet 412 includes the three MAC addresses included in the control command 421. The control request packet 412 is an Ethernet packet, and the CNPUMAC stored at the head indicates a transfer destination of the control request packet 412, that is, a control packet processing core described later. As a method for determining the transfer destination of the control request packet 412, for example, there is a round robin or the like.

  NeMMAC represents the MAC address of the transmission source of the control request packet 412. type represents an Ethernet type field. This Ethernet packet has a dedicated format, and vlink_add (2-byte numerical value) indicates that the content of the control request packet 412 is a VLAN link sliver generation command. The two MAC addresses that follow are parameters of the VLAN link sliver generation command. The control response packet 417 for the control request packet 412 includes NeMMAC, CNPUMAC, type, and the response result (OK in FIG. 4B).

  Note that variable length data such as XML is often used for the control request message 411. When variable-length data is used for the control request message 411, it may be divided into a plurality of packets. Further, the control request message 411 is described as a character string, and in order to analyze the grammar, complicated processing such as syntax and semantic analysis processing is required, and it is not suitable for execution in the data processing core 321. .

  In contrast, the control request packet 412 has a fixed length, and one packet corresponds to one command. Therefore, the control request packet 412 can be easily used even in a bare metal data processing core 321 that does not have a complicated protocol function.

(Simple data processing control method)
FIG. 5 shows an example of a control sequence by the simple control request message 411 shown in FIG. 4A. FIG. 5 shows an example in which the control sequence is started by the operator console 102 by the operator, but the control sequence may be started by the network management apparatus 111.

  When the operator inputs a command to the operator console 102, the operator console 102 transmits a control request message 410 corresponding to the command to the network management apparatus 111 to the entire network 121 (S450).

  Upon receiving the control request message 410, the network management apparatus 111 creates a control request message 411 corresponding to the control request message 410 and transmits it to the control board 241 of each subordinate physical node 112 (S451).

  Note that the network management apparatus 111 may be configured not to transmit the control request message 411 to the physical node 112 that is not a control target. The control request message 411 transmitted to the physical node 112 is received by the control board 241 in the physical node 112, but may be received by the general-purpose core 311 in the network processor 212.

  The control board 241 creates a control request packet 412 by translating the control request message 411, and transfers the control request packet 412 to the input processor 302 of the network processor 212 in the physical node 112 (S452). ). The control request packet 412 transferred to the input processor 302 is stored in one of the input queues 304 until it can be processed in one of the data processing cores 321.

  In step S452, the control board 241 processes the control request message 411. However, a processor (such as a PC) outside the physical node 112 may perform the process. The control request message 411 includes a message related to all the packet processing boards 211 in the physical node 112 and a message related to only the specific packet processing board 211 in the physical node 112. In step S452, Different processing is required.

  When the control request message 411 relates to all the packet processing boards 211 in the physical node 112, the control board 241 applies the control request packet 412 to all the packet processing boards 211 in the physical node 112. Just send it. Further, the network management apparatus 111 may transmit the control request message 411 to all the general-purpose cores 311 included in the packet processing board 211 in the physical node 112.

  When the control request message 411 relates to a specific packet processing board 211 in the physical node 112, for example, the control board 241 selects the packet processing board 211 to be controlled, and one control request packet 412 is selected. The packet processing board 211 may be transmitted. Alternatively, the packet management board 211 to be controlled by the network management apparatus 111 may be selected, and one control request message 411 may be transmitted to the general-purpose core 311 included in the selected packet processing board 211.

  When the general-purpose core 311 receives the control request message 411 in step S451, the general-purpose core 311 transmits a control request packet 412 in step S452. At this time, the general-purpose core 311 once returns the control request packet 412 to the input queue 304 in the input processor 302. When the input queue 304 exists in each data processing core 321, the general-purpose core 311 transfers the control request packet 412 to each data processing core 321.

  Further, when processing is possible in any of the data processing cores 321, the data processing core 321 notifies the input processor 302 that processing is possible. The input processor 302 selects the data processing core 321 used for the control processing from the data processing core 321 that has transmitted the notification, and transfers the control request packet 412 (S453). Hereinafter, the data processing core 321 that performs control processing is referred to as a control packet processing core 401. A method by which the input processor 302 selects the control packet processing core 401 will be described later.

  The control packet processing core 401 uses the shared memory 331 to exchange a control signal included in the control request packet 412, control data, and the like with a data processing core 321 that performs packet data processing. Hereinafter, the data processing core that performs packet data processing is referred to as a data packet processing core 402.

  When the control packet processing core 401 needs to pass data included in the control request packet 412 such as parameters necessary for data processing to the data packet processing core 402, the control packet processing core 401 writes the data into the shared memory 331 (S454). . When the data / packet processing core 402 needs the data written in the shared memory 331, the data / packet processing core 402 reads the data (S455).

  Further, the data packet processing core 402 writes the statistical information generated during the data processing into the shared memory 331 (S456). When it is necessary for the control packet processing core 401 to receive data to be transmitted to the network management apparatus 111 from the data packet processing core 402, the control packet processing core 401 reads out the data written in the shared memory (S457).

  The control packet processing core 401 creates a control response packet 417 with the read value inserted, and transmits it to the output processor 303 (S458). The control response packet 417 transferred to the output processor 303 is stored in one of the output queues 305 until the control board 241 can receive the control response packet 417. The output processor 303 transmits the control response packet 417 to the control board 241 (S459). The control board 241 translates the received control response packet 417 into a control response message 418 and transmits it to the network management apparatus 111 (S460). The network management apparatus 111 creates a control response message 419 corresponding to the control response message 418 and transmits it to the operator console 102 (S461).

(Advantages of this data processing control method)
The data processing control method in this embodiment has the following three advantages. First, in the data exchange in the present embodiment, the control packet processing core 401 and the data packet processing core 402 operate on the same architecture and bare metal. Furthermore, since the means used for data exchange is general-purpose means such as the shared memory 331 and the bus 361 having established parallel processing semantics, there is an advantage that it is possible to easily guarantee the length of data exchange.

  Second, since the data processing control method in the present embodiment uses general-purpose means as a data exchange interface, the data exchange procedure can be described in a general-purpose programming language. That is, there is an advantage that the program 351 can be easily ported to another network processor 212 or the like.

  Third, in the data processing control method according to the present embodiment, the control packet processing core 401 can grasp the information in the data packet processing core 402 at high speed. Therefore, when receiving an attack such as a denial-of-service attack (DoS), the control packet processing core 401 has an advantage that it can immediately detect and respond to the attack.

  For example, the control packet processing core 401 collects statistical information from the data packet processing core 402 written in the shared memory 331, and grasps the characteristics of the attack when access to one port is concentrated. The control packet processing core 401 can instruct the data packet processing core 402 to discard the packet having the characteristic of the attack.

  The control packet processing core 401 cannot grasp the characteristics of the attack by simple calculation, but some network processors 212 perform such calculation by hardware. In this embodiment, it is also possible to allocate a data packet processing core 402 dedicated to attack feature grasp processing.

  The data packet processing core 402 can execute the original processing of the data packet and the preparation for such an attack in parallel. For this purpose, the same packet may be mirrored and passed to both. The input processor 302 or the like can perform such mirroring.

(Contents of MAC address correspondence table)
FIG. 6 shows a configuration example of the MAC address correspondence table 422 used in the data processing control method in this embodiment. The MAC address correspondence table 422 is shared, for example, between the control packet processing core 401 and the data packet processing core 402. Further, the data packet processing core 402 may access the MAC address correspondence table 422 alone, and the write request and the read request from the control packet processing core 401 may be processed via the interface between the two.

  As means for sharing the MAC address correspondence table 422 and means for single access from the data packet processing core 402, for example, SRAM, DRAM, CAM, TCAM, or the like is used.

  The control request message 411 described above includes an external MAC address 00-03-b0-00-00-11 of the physical node 112 and an internal MAC address 00-04-b0-00-00-01 of the physical node 112. Correspondingly, this is a command for generating a VLAN link sliver. That is, the row 711 is generated when the control packet processing core 401 receives the control request packet 412. Similarly, the other rows are generated when the control packet processing core 401 receives another control request packet.

  When the data packet arrives from the outside of the physical node 112, the data packet processing core 402 refers to the MAC address correspondence table 422 and reads out from the MAC address correspondence table 422. At this time, the data packet processing core 402 searches whether the MAC address of the transmission source of the data packet matches the registered external address, and if it matches, rewrites the external address to the corresponding internal address. As a result, a packet on the virtual link that has arrived from the outside of the physical node 112 is input to the inside of the physical node 112.

  Further, when the data packet arrives from the inside of the physical node 112, the data packet processing core 402 refers to the MAC address correspondence table 422 in the same manner as when the data packet arrives from the outside of the physical node 112. Read-out from the address correspondence table 422 is performed. The data packet processing core 402 searches whether or not the MAC address of the transmission source of the data packet matches the internal address registered in the MAC address correspondence table 422. Rewrite the address. As a result, the packet on the virtual link that has arrived from the inside of the physical node 112 is output to the outside of the physical node 112.

  It should be noted that both when the data packet arrives from outside the physical node 112 and when it arrives from inside, an external address included in the data packet or a data packet that does not have a line matching the internal address is illegal. Discarded as a bad packet. That is, a packet for which no corresponding virtual link exists is discarded.

  Whether the packet has arrived from the outside of the physical node 112 or from the inside is identified by which interface of the physical node 112 is reached, or is identified by the VLAN number. In the VLAN link sliver generation, the data packet processing core 402 does not write to the shared memory 331 in principle.

  However, depending on the content of the process, the data packet processing core 402 writes into the shared memory 331 in step S456. In step S457, the control packet processing core 401 reads the result written in the shared memory 331. The control packet processing core 401 puts the result on the control response packet 417 and responds to the control board 241 via the output processor 303.

  In step S 460, the control board 241 incorporates the content of the control response packet 417 into the control response message 418 and reports it to the network management apparatus 111. As a result, the information held by the data packet processing core 402 can be provided to the network management apparatus 111.

  In order to process a packet at a wire rate, the MAC address correspondence table 422 needs to exist on a high-speed memory. As a general-purpose memory, for example, SRAM can be used for the main memory 322 and the shared memory 331 attached to the data processing core 321, but CAM is suitable for expressing such a simple table. . The MAC address correspondence table 422 needs to be expressed by a data structure such as a hash or a tree in the SRAM. However, since it can be expressed more directly by using the CAM, it can be accessed much faster.

(Selection of processing program in data processing core)
In the present embodiment, since one data processing core 321 may handle both a data packet and a control request packet, the data processing core 321 has a data processing program or a program depending on the type of received packet, or It is necessary to select which of the control programs to execute.

  FIG. 7A is a flowchart showing a program selection process in the data processing core 321. This process is repeated each time the data processing core 321 receives a packet.

  First, the data processing core 321 is in a packet reception standby state (S1660). The data processing core receives the packet (S1661). The data processing core 321 determines the type of the packet by referring to a partial value of the packet header (S1662). When determining that the type of the received packet is a control request packet (S1662: control packet), the data processing core 321 executes the control program (S1663). When the data processing core 321 determines that the type of the received packet is a data packet (S1662: data packet), the data processing core 321 executes the data processing program (S1664).

  In order to enable this processing, the control board 241 needs to store a tag identifiable from the data packet in the header of the control request packet 412 when generating the control request packet 412. This is because the control request packet and the data packet may arrive from the same network interface 251. Therefore, when both arrive from different network interfaces 251, the determination in step S1662 can be omitted by adding the address of the network interface 251 to the control request packet, for example. Through the processing described above, the data processing core 321 can perform processing on both the control request packet and the data packet. Therefore, for example, if the method of mixed processing described later is used, the ratio between the control packet processing core 401 and the data packet processing core 402 can be dynamically changed. Dynamic load distribution is realized.

  In the present embodiment, the control program and the data processing program can be described in the same programming language. In the same programming language, data i between the two can be realized by using data sharing means such as the shared memory 331. Thus, the data I in the control program and the data processing program can be described according to unified semantics. Therefore, data with no doubt in terms of semantics is realized.

  In addition, since the control program and the data processing program can be described in the same programming language, the control program can be ported at the same time by developing a portable data processing program.

(Selection of control request packet transfer destination core)
Hereinafter, a method for selecting the control packet processing core 401 to which the control request packet is to be transferred from the data processing core 321 will be described. As described above, the data processing core 321 can execute data processing and simple control processing.

  That is, the data processing core 321 can execute a program common to all the data processing cores 321, that is, a program including both the data processing function and the control processing function. Further, the data processing core 321 can execute a program having only a data processing function or a program having only a control processing function.

  When executing the program including both the data processing function and the control processing function, the data processing core 321 refers to the packet header at the start of packet processing and determines the type of the packet. If the data processing core 321 determines that the received packet is a data packet, it executes a data processing function. When the data processing core 321 determines that the received packet is a control request packet, the control processing function is executed.

  FIG. 7B is a flowchart showing a process of distributing control request packets received by the input processor 302 to a plurality of input queues 304. Here, a case where both the control packet queue and the data packet queue exist as the input queue 304 will be described. First, the input processor 302 is in a packet reception standby state (S1600). When the input processor 302 receives the packet (S1611), the type of the packet is determined by referring to a partial value of the header of the packet (S1612).

  When the input processor 302 determines that the type of the received packet is a control request packet (S1612: control packet), the input processor 302 places the packet in the input queue 304 for one or more control packets (S1613). . When the input processor 302 determines that the type of the received packet is a data packet (S1612: data packet), the input processor 302 places the packet in the input queue 304 for one or more data packets (S1614). ).

  In order to enable this processing, the control board 241 needs to store a tag identifiable from the data packet in the header of the control request packet 412 when generating the control request packet 412. Therefore, when both arrive from different network interfaces 251, the determination in step S1662 can be omitted by adding the address of the network interface 251 to the control request packet, for example. By storing the packets separately in the control packet queue and the data packet queue by the above processing, the data processing and the control processing can be controlled independently. That is, it becomes possible to use a control-dedicated process and a data-dedicated process described later.

  The input processor 302 transmits a control request packet or a data packet from one of the input queues 304 to the data processing core 321, and the data processing core 321 that has received the packet processes the packet. This series of processing is repeated. As a series of processing methods, there are three types of processing methods: control-only processing, data-only processing, and mixed processing.

  The first is a method dedicated to control. In other words, when the data processing core 321 is executing a program including only the control processing function, the data processing core 321 is ready to process a new control request packet and enters the control packet queue. What is necessary is just to request | require to transmit a control request packet. This avoids accidental input of data packets. In addition, since the data processing core 321 for the control processing is always secured by this, there is an advantage that the resources for the control processing are secured and executed quickly even when the data processing load is high.

  The second is a data-only processing method. In other words, when the data processing core 321 is executing a program including only the data processing function, the data processing core 321 is ready to process a new data packet, and when the data processing core 321 is ready to process a new data packet, Can be requested to send a data packet. As a result, the control request packet is not input by mistake. This ensures resources for data processing even when the control processing load is high.

  The third method is a mixing process. That is, when the data processing core 321 is executing a program including both the data processing function and the control processing function, when it is ready to process a new packet, the control request packet from the control packet queue, or What is necessary is just to request | require to transmit a data packet from the queue for data packets. For example, if the data processing core 321 requests that the packet stored in the control packet queue and the data packet queue have a large number of accumulated packets, the control processing and the data processing are performed. Load distribution is realized. That is, when the control processing load is relatively high, a large core is used by the control processing, and when the data processing load is relatively high, the large core is used by the data processing. It becomes like this. Further, the data processing core 321 may preferentially process either the control request packet or the data packet.

  It is assumed that the control packet queue and the data packet queue do not exist in the input queue 304, that is, the case where both the control request packet and the data packet are input to all the input queues 304. At this time, according to the mixed processing method, since the data processing core 321 can process both the control request packet and the data packet, when the preparation for processing the new packet is ready, A request can be made to send a packet from the input queue 304. That is, according to the mixing processing method, the same processing can be performed even if the control packet queue and the data packet queue do not exist in the input queue 304.

(Concatenated data processing control method and message content)
A control command is basically composed of a combination of three types of structures: connection, selection, and repetition. This is the same as the control structure of a program or programming language. A control command including one of a connection type, a selection type, and a repetitive type is called a complex command. As described above, it is difficult to realize a complicated command in the data processing core 321. Therefore, the control board 241 decomposes a complicated command into a plurality of basic commands when generating a control request packet.

  In this embodiment, the control board 241 can process a control request message 811 including a complex articulated type including a plurality of basic commands.

  FIG. 8A shows a control request message 811 including two control commands 821 and 822 for generating a VLAN link sliver and one control command 823 for deleting a VLAN link sliver as an example of a concatenated control request message. Shimese. Control commands 821, 822, and 823 are all basic commands.

  The control command 821 generates a VLAN link sliver by associating the MAC address 00-03-b0-00-00-11 outside the physical node with the internal MAC address 00-04-b0-00-00-01. Command to do. The control command 822 generates a VLAN link sliver by associating the MAC address 00-03-b0-00-00-10 outside the physical node with the internal MAC address 00-04-b0-00-00-04. Command to do. The control command 823 deletes the VLAN link sliver corresponding to the MAC address 00-03-b0-00-00-21 outside the physical node and the internal MAC address 00-04-b0-00-00-21. Is commanded.

  FIG. 8B shows control request packets 812a to 812c corresponding to the control commands 821 to 823 and control response packets 817a to 817c corresponding to the control request packets 812a to 812c, respectively. The control request packet 812a includes three MAC addresses included in the control command 821.

  The control request packets 812a to 812c are Ethernet packets. Vlink_add in the control request packets 812a and 812b indicates that the content of the packet is a VLAN link sliver generation command. The two MAC addresses that follow are parameters of the VLAN link sliver generation command. When receiving these commands, the control packet processing core 401 generates the rows 711 and 712 of the MAC address correspondence table 422.

  Vlink_rem in the control request packet 812c indicates that the content of the packet is a VLAN link sliver deletion command. The subsequent two MAC addresses represent the parameters of the VLAN link sliver deletion command. The MAC address outside the physical node included in the control request packet 812c and the MAC address inside the physical node are the same as the values in the row 713 of the MAC address correspondence table 422, respectively. Therefore, when receiving the control request packet 812c, the control packet processing core 401 deletes the row 713 of the MAC address correspondence table 422.

  Control response packets 817a to 817c corresponding to the control request packets 812a to 812c include NeMMAC, CNPUMAC, type, and response result (OK in FIG. 9B).

  FIG. 9 shows an example of the control sequence of the articulated data processing shown in FIG. 8A. The operator console 102 transmits a control request message 810 including three control commands 821 to 823 to the network management apparatus 111 (S850). The network management apparatus 111 that has received the control request message 810 creates a control request message 811 corresponding to the control request message 810, and transmits the control request message 811 to the control board 241 of each physical node 112 (S851).

  The control board 241 that has received the control request message 811 translates the control request message 811 and decomposes it into three control request packets 812a to 812c. That is, the control board 241 translates the control request message 811, generates a first VLAN link sliver generation command as a control request packet 812 a, a second VLAN link sliver generation command as a control request packet 812 b, and a third The VLAN link sliver erase command is disassembled into a control request packet 812c.

  Steps S852 to S859 are the same as steps S452 to 459 of FIG. 4, and the operations of steps S452 to S459 are performed for the control request packet 812a. When Steps S852 to S859 are completed for the control request packet 812a, operations similar to Steps S852 to S859 are sequentially performed for the control request packets 812b and 812c.

  The control board 241 creates a control response message 818 by translating the control response packets 817a to 817c together, and transmits the control response message 818 to the network management apparatus 111 (S860). The network management device 111 creates a control response message 819 corresponding to the control response message 818, and transmits the control response message 819 to the operator console 102 (S861).

  As described above, the control board 241 can store the control request message 811 that cannot be stored in one packet until then, by translating and disassembling the concatenated control request message 811. It becomes like this. Therefore, the data processing core 321 has an advantage that the control request packets 812a to 812c can be easily processed. In addition, since the control process by the control request message 811 is completed in the same execution time as the data process, there is an advantage that the packet is appropriately scheduled.

  In this embodiment, the control command is broken down into different control request packets. However, if the data processing core 321 can process a plurality of control commands at the same time, it may be more efficient to transmit a plurality of control packets together. The control board 241 can change the disassembly method in consideration of the type and processing capability of the data processing core 321.

  In FIG. 9, since the control board 241 sequentially transmits the disassembled control commands to one data processing core 321, the number of data processing cores 321 used as the control packet processing core 401. And resources for data processing can be secured. The control board 241 can also transmit the disassembled control commands one by one to different data processing cores 321 in parallel. That is, the control command can be executed in parallel. In this case, however, the control request message 811 indicates that there is no dependency between the control commands, or the physical node 112 must determine. By executing the control commands in parallel, the processing speed is improved.

(Selective data processing control method and message contents)
In the present embodiment, the control board 241 can process the control request message 411a including a selection type control command.

  FIG. 10A shows a control request message 411a including a control command 1122 for generating a VLAN link sliver and a control command 1124 for deleting a GRE link sliver as an example of the selective control request message. The control commands 1122 and 1124 are all basic commands. In the control command 1121, when the VLAN is requested as the link sliver type, the control command 1122 is executed. When the GRE is requested in the control command 1123, the control command 1124 is executed. The control board 241 determines which command to select depending on its own static or dynamic state.

  FIG. 10B shows the contents of control request packets 412a and 412b corresponding to the control commands 1122 and 1124, and control response packets 417a and 417b corresponding to the control request packets 412a and 412b, respectively. The content of the control request packet 412a is the same as that of the control request packet 412 shown in FIG. 4B.

  The control request packet 412b includes the IP address, GRE key, and MAC address included in the control command 1124. “Link_add” in the control request packet 412b indicates that the content of the control request packet 412b is a GRE link sliver generation command. Then, the following three parameters are parameters of the GRE link sliver generation command. When the control packet processing core 401 receives these instructions, it generates a row of the GRE address correspondence table.

  The sequence of the selective data processing control is the same as that in FIG. However, in step S451, 411a is used instead of the control request message 411. In step S451, the control board 241 determines which branch of the control request message 411a is selected, and creates either the control request packet 412a or the control request packet 412b according to the determination. In steps S452 and S453, the control request packets 412a and 412b created in S451 are used instead of the control request packet 412.

  As described above, the control board 241 translates and decomposes the selection-type control request message 411a to delete the branch process. Therefore, the RISC architecture data processing core having no advanced branch optimization function has an advantage that processing can be performed without finding a pipeline. In addition, since the control process ends with an execution time comparable to that of the data process, there is an advantage that the packet is appropriately scheduled.

(Repetitive data processing control method and message contents)
In the present embodiment, the control board 241 can process a control request message 1311 including a repetitive control command as an example of the control request message.

  FIG. 11A shows a control request message 811d that repeatedly applies a control command 1322 for generating a VLAN link sliver as an example of a repetitive control request message. The control command 1321 specifies that the control command 1322 is repeated three times. The control command 1322 is a basic command. Here, the control command 1321 designates a fixed number of iterations, but it is also possible to designate a variable number of iterations.

  FIG. 11B shows the contents of control request packets 812d to 812f corresponding to three repetitions of the control command 1322 and control response packets 817d to 817f corresponding to the control request packets 812d to 812f, respectively. The content of the control request packet 812d is the same as that of the control request packet 412 shown in FIG.

  The sequence of iterative data processing control is the same as that in FIG. However, in step S851, a control request message 811d is used instead of the control request message 811. In steps S852 and S853, control request packets 812d to 812f are used instead of the control request packets 811a to 811c. In steps S858 and S859, control response packets 817d to 817f are used instead of the control response packets 817a to 817c.

  As described above, the iterative process is deleted by decomposing the iterative control request message 811d. Therefore, the RISC architecture data processing core 321 having no advanced branch optimization function has an advantage that processing can be performed without finding a pipeline. In addition, the control process ends in the same execution time as the data process, eliminating the danger of an infinite loop. Therefore, there is an advantage that the packet is scheduled appropriately and the forced stop is not necessary.

  In FIG. 9, the control board 241 sequentially transmits the disassembled control commands to one data processing core 321, but as with the concatenated control message, the control board 241 has the same number of disassembled control commands. It can also be transmitted in parallel to the data processing core 321. In this case, however, the control request message 811 indicates that there is no dependency between the control commands, or the physical node 112 must determine.

(General data processing control method and message contents)
Control commands consist of a combination of articulation, selection, and repetition. Therefore, the control board 241 can control any complicated control request message including a partial command by combining the above-described articulated data processing control method, selection type data processing control method, and iterative data processing control method. Can be broken down into request packets. A part of the control commands that are continuous are called partial commands.

  That is, when the control board 241 receives a control request message, the control board 241 performs different processing for each type of command included in the control request message. That is, first, when the control request message includes a basic command, the control board 241 processes by a simple data processing control method. Secondly, when the control request message includes an articulated control command, the control board 241 processes the articulated data processing control method. Third, when the control request message includes a selection-type control command, the control board 241 processes according to the selection-type data processing control method. Fourth, when the control request message includes a repetitive control command, the control board 241 processes the repetitive data processing control method.

  Fifth, when the control request message includes a more complicated control command, the control board 241 determines the command according to any of the above methods according to the top-level control structure, that is, the connection type, the selection type, or the repetition type. Decompose. Furthermore, the command is recursively decomposed by the lower control structure. This method is suitable for a decomposition method in a compiler or interpreter of a programming language.

  Further, as described above, the control board 241 cannot disassemble all the control commands included in the control request message and cause the control packet processing core 401 to execute them. For example, a command for controlling the operation of the control packet processing core 401, that is, a command for loading a program (to a storage device) into the control packet processing core 401, starting or stopping the control packet processing core 401, etc. 401 may not be executed.

  In such a case, the control board 241 needs to execute the process. Therefore, when the control board 241 receives the control request message 411 that does not include a command that can be processed by the data processing core 321, the control board 241 performs the processing. In addition, when the control board 241 receives the control request message 411 including a command that can be processed by the data processing core and a command that cannot be processed by the data processing core, the control board 241 transmits the former to the control packet processing core 401 as a control request packet. The latter is processed by the control board 241.

(Data processing program load and control processor configuration / processing)
A program 351 executed by the data processing core 321 is stored in the main storage device 342. The data processing core 321 can load the program 351 while the packet data processing is stopped or during operation.

  When the data packet processing core 402 loads the program 351, the program 351 is stopped so as not to execute the program being loaded or the program 351 replaced by the loading, or another program 351 is executed. To. The program 351 can be composed of a plurality of programs, and a plurality of data packet processing cores 402 can execute different programs 351.

  The configuration and processing method of the control board 241 for performing control corresponding to a plurality of programs executed in this way will be described with reference to FIGS. Different control may be required for the data packet processing core 402 that executes different programs. Therefore, in addition to the basic control program 1711, plug-in control programs 1712 and 1713 are used for the control board 241 that receives the control request message.

  FIG. 12 shows an example of the configuration of the control board 241 when the plug-in control program is used. The control board 241 includes a CPU 1701, a network interface 1703, and a memory 1702. The basic control program 1711 and plug-in control programs 1712 and 1713 are loaded into the memory 1702. That is, the basic control program 1711 and the plug-in control programs 1712 and 1713 are configured to coexist on one control board 241.

  FIG. 13 shows an example of the configuration of the control board 241 and the general-purpose core 311 when the plug-in control program is used. In FIG. 13, only the basic control program 1711 is loaded into the memory 1702 of the control board 241, and the plug-in control programs 1712 and 1713 are loaded into the memory 1702 b of the general-purpose core 311 mounted on the packet processing board 211. . The plug-in control programs 1712 and 1713 are transferred to, for example, a plurality of control boards 241, a control board in a separate housing from the control board 241, a general-purpose core mounted on a packet processing board in a separate housing from the control board 241, and the like. It can also be loaded.

  In FIG. 12 and FIG. 13, two plug-in control programs 1712 and 1713 are used, but the number is not limited as long as the functions of this embodiment can be realized. Some programs 351 can be processed only by the basic control program 1711.

  FIG. 14 is a flowchart showing processing when the plug-in control programs 1712 and 1713 exist and the control board 241 receives the control request message. The control board 241 takes out the partial commands included in the received control request message (S1911), and performs the following processing for each partial command.

  The control board 241 determines whether the extracted partial command is a command for the basic control program, that is, whether it can be processed by the basic control program 1711 (S1912). If the partial command is a basic control program command (S1912: Yes), the control board 241 processes the partial command by the basic control program 1711 (S1913). When the partial command is not a basic control program command but an extended command (S1912: No), the control board 241 uses the plug-in control program corresponding to the extended command among the plug-in control programs 1712 and 1713 to execute the partial command. Process.

  When the plug-in control programs 1712 and 1713 are in the same processor, the control board 241 calls the plug-in control programs 1712 and 1713 by an API (Application Programming Interface) or the like. On the other hand, when the plug-in control programs 1712 and 1713 are in different processors, the control board 241 calls the plug-in control programs 1712 and 1713 by socket communication or the like. According to the present embodiment, when a plurality of programs 351 are executed in the data processing core 321, the control board 241 can perform corresponding processing by the basic control program 1711 or the plug-in control programs 1712 and 1713. it can.

  When the general-purpose core 311 executes the plug-in control programs 1712 and 1713, the general-purpose core 311 receives the extension command from the control board 241 via the network, and processes the partial command by the program corresponding to the extension command. The general-purpose core 311 may execute the basic control program 1711 and the plug-in control programs 1712 and 1713. Thus, the general-purpose core 311 is included in the control device in the data packet communication device. Further, in FIG. 13, instead of the general-purpose core 311, a plurality of control boards 241, a control board in a separate housing from the control board 241, a general-purpose core mounted on a packet processing board in a separate housing from the control board 241, etc. When used, these are included in the control device in the data packet communication device.

  In addition, this invention is not limited to the Example mentioned above, Various modifications are included. For example, the above-described embodiments are described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. In addition, a part of the configuration of one embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of one embodiment. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  Each of the above-described configurations, functions, processing units, processing means, and the like may be realized by hardware by designing a part or all of them with, for example, an integrated circuit. Each of the above-described configurations, functions, and the like may be realized by software by interpreting and executing a program that realizes each function by the processor. Information such as programs, tables, and files for realizing each function can be stored in a memory, a hard disk, a recording device such as an SSD (Solid State Drive), or a recording medium such as an IC card, an SD card, or a DVD.

102 operator console, 111 network management device, 112 physical node, 211 packet processing board, 212 network processor, 241 control board, 251 network interface, 302 input processor, 303 output processor, 304 input queue, 305 output queue, 311 General-purpose core, 321 data processing core, 331 shared memory, 401 control packet processing core, 402 data packet processing core, 422 MAC address correspondence table, 1711 basic control program, 1712 plug-in control program

Claims (12)

A data packet including a data processing device that receives an input of a data packet, processes the input data packet, and outputs the processed data packet; and a control device that controls the data processing device A method for controlling a communication device, comprising:
The data processing device includes a plurality of bare metal cores and a data sharing device shared between the plurality of bare metal cores,
The method
At least one of the plurality of bare metal cores receives the input data packet and processes the received data packet;
When the control device receives the control request message, it creates a control request packet including control data from the control request message, and transmits the control request packet to the data processing device,
At least one of the plurality of bare metal cores receives the control request packet and transmits the control data included in the control request packet to another bare metal core via the data sharing device. A method characterized by including. The method of claim 1, comprising:
The plurality of bare metal cores include at least one first bare metal core that processes a control request packet and a data packet;
When the at least one first bare metal core determines that the type of the received packet is a data packet, it processes the received data packet;
When the at least one first bare metal core determines that the type of the received packet is a control request packet,
Transmitting the control data included in the control request packet to another bare metal core via the data sharing device. The method of claim 2, comprising:
The plurality of bare metal cores include a plurality of control packet processing cores for processing control packets, including the at least one first bare metal core,
The control request packet generated by the control device is distributed to the plurality of control packet processing cores. The method of claim 3, comprising:
The data processing apparatus includes a control packet queue for storing control request packets and a data packet queue for storing data packets.
The at least one first bare metal core receives the control request packet from the control packet queue;
The method wherein the at least one first bare metal core receives the data packet from the data packet queue. The method of claim 1, comprising:
The plurality of bare metal cores process control request packets without processing data packets, including at least one second bare metal core;
The data processing device includes a control packet queue for storing control request packets,
Wherein said at least one second bare-metal core, for receiving the control request packet from the queue for the control packets, and wherein the. The method of claim 1, comprising:
The method, wherein the control device translates the control request message into a plurality of basic commands, and creates a plurality of control request packets each including at least one basic command in the plurality of basic commands. The method of claim 6, comprising:
The plurality of bare metal cores execute a plurality of types of control programs,
The control device executes a basic control program and a plug-in control program for the basic control program,
The method, wherein the control device executes a program selected from the basic control program and the plug-in control program in accordance with a command included in the control request message. The method of claim 7, comprising:
The control device includes a first core mounted on the first board and a second core mounted on the second board,
The first core executes a basic control program to process a basic control program command included in the control request message;
The first core is included in the control request message and transfers an extension command different from the basic control program command to the second core via the network,
The second core executes the plug-in control program for the basic control program to process the extension command. The method of claim 6, comprising:
A method wherein one of the plurality of bare metal cores receives the plurality of basic commands sequentially. The method of claim 6, comprising:
Each of the plurality of bare metal cores of the plurality of bare metal cores receives at least one of the plurality of basic commands. The method of claim 6, comprising:
When the control request message includes a selection-type control command, the control device performs a condition determination in the selection-type control command, and when determined to be true in the condition determination, translates a first partial command, A method of translating the second partial command when it is determined to be false in the condition determination. Including a data processor that receives an input of a data packet, processes the input data packet, and outputs the processed data packet; and a control device that controls the data processor;
The data processing device includes a plurality of bare metal cores and a data sharing device shared between the plurality of bare metal cores,
At least one of the plurality of bare metal cores receives an input data packet, processes the received data packet,
The control device includes:
Upon receipt of the control request message, a control request packet including control data is created from the control request message, and the control request packet is transmitted to the data processing device,
At least one of the plurality of bare metal cores is
A data packet communication device, comprising: receiving the control request packet; and transmitting the control data included in the control request packet to another bare metal core via the data sharing device.

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