JP6036012B2 - Image display apparatus and method - Google Patents

Description

  The present invention relates to an image display apparatus and method for displaying an image on a display device after reducing the number of gradations of input image data.

  In order to obtain the number of gradations that can be displayed by the display device, for example, image data having a gradation number of 10 to 12 bits is reduced to a gradation number of 4 to 6 bits and then supplied to the display device to display an image. There are things to do. If low-gradation image data is displayed on the display device as it is, the gradation characteristics will deteriorate. Therefore, in order to increase the apparent number of gradations, processing such as error diffusion and dithering is performed, and pixels are increased to increase the resolution. Processing such as shifting is used.

JP-A-4-113308

  When various processes for improving the number of gradations and increasing the resolution are performed, image quality degradation may occur. Therefore, it is desired to improve gradation and resolution while suppressing the occurrence of image quality degradation.

  In order to meet such a demand, the present invention aims to provide an image display apparatus and method that can increase the apparent resolution while suppressing the occurrence of image quality degradation as much as possible by using a pixel shifting method. To do.

The present invention for solving the problems of the prior art described above, the first image data which have a first frame frequency, having said first frame frequency, and the first image data An image data generation unit that generates second image data in which the pixel position is shifted in the horizontal direction and the vertical direction; and the first and second image data are two times the first frame frequency. A double-speed conversion unit for converting to a frame frequency of 2, and an error diffusion process is performed on the first and second image data having the second frame frequency so that the first and second image data have given in the first error diffusion processing section for converting the number of bits in the second number of bits less than said first number of bits, the second converted first and second image data to the number of bits place with respect to the high-order bit A dither processing section for adding the dither consisting dither pattern, the first and second image data outputted from the dither processing unit are displayed alternately, and outputs the image displaying the first image data display devices and said first image data output from the dither processing unit position and a position for outputting the displayed image of the second image data has a wobbling function to displace so as to be mutually different positions The display device is configured to output the second image data output from the dither processing unit to a second position shifted in a horizontal direction and a vertical direction with respect to the first position. and a display device driver for driving the dither processing unit cyclically in accordance with a plurality of types of dither patterns in the first and the frame number of the second image data For the pair of frames within one frame period of the first frame frequency in the first and second image data having the second frame frequency, among the plurality of types of dither patterns An image display device characterized by selecting the same type of dither pattern is provided.

In the above image display device, the dither processing unit includes a plurality of values set corresponding to values of lower bits excluding the upper bits of the first and second image data converted into the second number of bits. A dither pattern is set, and a plurality of dither pattern sets are selected cyclically according to the frame numbers of the first and second image data, and selected according to the frame numbers of the first and second image data. It is preferable to select a dither pattern from the dither pattern set according to the value of the lower bit.

In the above image display device, the dither processing unit adds dither to the first and second image data converted into the second number of bits in an area composed of a plurality of pixels in each of the horizontal direction and the vertical direction. and area, each of the said from consisting pattern dither dither pattern to be added to the high-order bit of the pixel data, the dither indicated dither pattern selected according to the value of the lower bits in said each of the pixel data in the area it is preferred to add the to each pixel data.

Further, the present invention is to solve the problems of the prior art described above, the first image data which have a first frame frequency, having said first frame frequency, and said first image A generation step of generating second image data in which the pixel position of the data is shifted in the horizontal direction and the vertical direction; and the first and second image data are two times the first frame frequency. A frame frequency converting step for converting to a frame frequency of 2, and an error diffusion process is performed on the first and second image data having the second frame frequency so that the first and second image data are in the first bit number conversion step of converting the number of bits in said first number of second smaller than the number of bits the bit, the second of said converted to the number of bits the first and second image data having Place A dither adding step for adding the dither consisting predetermined dither pattern for the upper bits of the display to alternately display device the first and second image data dither is added, is displayed on the display device Further, the first image data is displayed at a first position, and the second image data displayed on the display element is displayed at a second position shifted in the horizontal and vertical directions with respect to the first position. And a wobbling step for wobbling a position to output an image, wherein the dither addition step cyclically selects a plurality of types of dither patterns according to frame numbers of the first and second image data, For a pair of frames in one frame period of the first frame frequency in the first and second image data having the second frame frequency Provides an image display method characterized by selecting the same type of dither pattern among the plurality of types of dither patterns.

In the above image display method, the dither addition step includes a plurality of values set in correspondence with values of lower bits excluding the upper bits of the first and second image data converted to the second number of bits. A dither pattern is set, and a plurality of dither pattern sets are selected cyclically according to the frame numbers of the first and second image data, and selected according to the frame numbers of the first and second image data. It is preferable to select a dither pattern from the dither pattern set according to the value of the lower bit.

In the above image display method, the dither addition step adds dither to a region composed of a plurality of pixels in the horizontal and vertical directions in the first and second image data converted to the second number of bits. and area, each of the said from consisting pattern dither dither pattern to be added to the high-order bit of the pixel data, the dither indicated dither pattern selected according to the value of the lower bits in said each of the pixel data in the area it is preferable to be added to each of the pixel data.

  According to the image display apparatus and method of the present invention, when an image is displayed on a display device using a pixel shifting method, the apparent resolution can be increased while suppressing the occurrence of image quality degradation as much as possible.

It is a block diagram which shows one Embodiment of the image display apparatus of this invention. It is a figure which shows the flame | frame by two image data from which the position of the pixel shifted | deviated. It is a figure for demonstrating the double speed conversion process by the double speed conversion parts 2a and 2b in FIG. It is a block diagram which shows the specific structure of the gradation conversion part 3 in FIG. It is a figure which shows the outline of the error diffusion process by the error diffusion process part 31 in FIG. FIG. 5 is a block diagram illustrating a specific configuration example of an error diffusion processing unit 31 in FIG. 4. FIG. 5 is a block diagram illustrating a specific configuration example of a dither processing unit 32 in FIG. 4. FIG. 8 is a diagram for explaining a frame counter signal, an X counter signal, and a Y counter signal generated by the timing generator 325 in FIG. 7. It is a figure which shows the example of the several dither pattern set which the dither processing part 32 in FIG. 4 uses. It is a figure which shows the dither pattern set which the dither processing part 32 in FIG. 4 uses with respect to a double speed frame. It is a figure which shows the specific structural example of the display device 5 in FIG. It is a perspective view which shows the specific structural example of the wobbling element 519 in FIG.

  Hereinafter, an image display apparatus and method according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  In FIG. 1, image data Da is input to the interpolation unit 1. The image data Da is 12 bits, for example. The interpolation unit 1 generates image data Db obtained by shifting the image data Da by 0.5 pixels in the horizontal method and the vertical direction. The interpolation unit 1 generates image data Db by generating an interpolation pixel with a plurality of pixels constituting the image data Da.

  If the frame fa by the image data Da is at the position indicated by the solid line shown in FIG. 2, the frame fb by the image data Db is at the position indicated by the broken line shifted by 0.5 pixels in the horizontal direction and the vertical direction. In FIG. 2, Px is a pixel. In FIG. 2, for the sake of simplicity, the number of pixels Px included in the frames fa and fb is smaller than the actual number.

  The interpolation unit 1 supplies the image data Da to the double speed conversion unit 2a as it is, and supplies the generated image data Db to the double speed conversion unit 2b.

  When the image data Da is high-resolution image data called 4K2K, image data having a relationship between the frame fa and the frame fb in FIG. 2 may be extracted from the high-resolution image data. In this case, instead of the interpolation unit 1, a separation unit that separates the image data Da and Db from high-resolution image data may be provided.

  That is, the image display device according to an embodiment has a first frame frequency, and shifts the positions of the first image data (image data Da) and the pixels of the first image data in the horizontal direction and the vertical direction. It is only necessary to have an image data generation unit that generates the second image data (image data Db). The interpolation unit 1 or the separation unit is an example of an image data generation unit.

  The double speed conversion unit 2a doubles the frame frequency of the input image data Da. If the frame of the image data Da is a frame fa1, fa2, fa3... As shown in FIG. 3A, the output of the double speed conversion unit 2a is the frames fa1, fa1,. fa2, fa2, fa3, fa3...

  Similarly, the double speed conversion unit 2b doubles the frame frequency of the input image data Db. If the frame of the image data Db is frames fb1, fb2, fb3... As shown in FIG. 3 (c), the output of the double speed conversion unit 2b is the frames fb1, fb1,. fb2, fb2, fb3, fb3...

  In this way, the double speed conversion units 2a and 2b convert the first and second image data (image data Da and Db) to a second frame frequency that is twice the first frame frequency.

  The gradation conversion unit 3 receives the double-speed converted image data shown in FIG. 3B and the double-speed converted image data shown in FIG. As shown in FIG. 3E, the gradation converting unit 3 selects the first half frame from FIG. 3B and the second half frame from FIG. 3D to select the frames fa1, fb1, and fa2. , Fb2, fa3, fb3... Are subjected to gradation conversion processing described later.

  As shown in FIG. 4, the gradation conversion unit 3 includes an error diffusion processing unit 31 and a dither processing unit 32. The error diffusion processing unit 31 multiplies the lower bits of the pixel data by a predetermined coefficient in each pixel of the input 12-bit image data and diffuses it to surrounding pixels, and outputs the image data as less than 12 bits. In this embodiment, the error diffusion processing unit 31 converts 12-bit image data into 6 bits.

  An outline of error diffusion processing by the error diffusion processing unit 31 will be described with reference to FIG. Among the pixels Px of the image data, a pixel of interest with hatching is defined as Pxi. A pixel at the same horizontal position as the target pixel Pxi one line above the target pixel Pxi is defined as PxB, a pixel on the left side of the pixel PxB is defined as PxA, and a pixel on the right side is defined as PxC. A pixel adjacent to the left of the target pixel Pxi is defined as PxD.

  The error diffusion processing unit 31 uses the lower bits (for example, lower 4 bits) of the pixel data of the pixels PxA, PxB, PxC, and PxD as error data, and multiplies the error data by the respective coefficients shown in FIG. And added to the pixel data of the target pixel Pxi. The gradation conversion unit 3 repeats the addition operation of FIG. 5A with each pixel Px of the image data as the target pixel Pxi.

  The target pixel Pxi to which the error data from the peripheral pixels is added becomes a pixel corresponding to the pixels PxA, PxB, PxC, and PxD by moving the target pixel Pxi. Then, the value obtained by multiplying the error data by the coefficient is diffused to the new target pixel Pxi.

  By repeating the above processing, as a result, the error diffusion processing unit 31 multiplies the lower bits in the target pixel Pxi by the respective coefficients shown in FIG. 5B, as shown in FIG. 5B. The value is diffused to the pixels PxA ′, PxB ′, PxC ′, and PxD ′.

  A specific configuration example of the error diffusion processing unit 31 that performs the above error diffusion processing will be described with reference to FIG. In FIG. 6, the storage unit 3101 stores coefficients CoA, CoB, CoC, and CoD that are multiplied by the lower bits of the pixel data of the pixels PxA, PxB, PxC, and PxD, respectively. In the example of FIG. 5A, the coefficient CoA is 1/16, the coefficient CoB is 5/16, the coefficient CoC is 3/16, and the coefficient CoD is 7/16.

  The multiplier 3102 multiplies the lower 4 bits extracted by the bit extraction unit 3122 by the coefficient CoD and supplies the result to the adder 3118. The multiplier 3103 multiplies the data obtained by delaying the lower 4 bits extracted by the bit extraction unit 3122 by 1 clock by the 1 clock delay unit 3109 by a coefficient CoC. The output of the multiplier 3103 is delayed by one clock by the one clock delay unit 3106 and supplied to the adder 3110.

  The multiplier 3104 multiplies the data obtained by delaying the lower 4 bits extracted by the bit extraction unit 3122 by one clock delay unit 3109 by one clock by a coefficient CoB. The output of the multiplier 3104 is delayed by one clock by the one-clock delay unit 3107 and supplied to the adder 3112.

  The multiplier 3105 multiplies the data obtained by delaying the lower 4 bits extracted by the bit extraction unit 3122 by one clock delay unit 3109 by one clock by a coefficient CoA. The output of the multiplier 3105 is delayed by one clock by the one clock delay unit 3108 and supplied to the adder 3114.

  The adder 3110 adds the output of the 1-clock delay device 3106 and 0 data, and the 1-clock delay device 3111 delays the output of the adder 3110 by 1 clock. The adder 3112 adds the output of the 1-clock delay device 3107 and the output of the 1-clock delay device 3111, and the 1-clock delay device 3113 delays the output of the adder 3112 by 1 clock.

  The adder 3114 adds the output of the 1-clock delay device 3108 and the output of the 1-clock delay device 3113, and the 1-clock delay device 3115 delays the output of the adder 3114 by 1 clock. The limiter 3116 limits the upper limit value of the output of the 1-clock delay unit 3115. The 1-line delay unit 3117 delays the output of the limiter 3116 by one horizontal line and supplies the delayed result to the adder 3118.

  The adder 3118 adds the output of the multiplier 3102 and the output of the one-line delay unit 3117, and the one-clock delay unit 3119 delays the output of the adder 3118 by one clock. The bit extraction unit 3120 discards the lower 4 bits of the input 12 bits and supplies the upper 8 bits to the adder 3121. The adder 3121 adds 12-bit data corresponding to the data shown in (e) of FIG. 3 and the upper 8-bit data from the bit extraction unit 3120.

  The bit extraction unit 3122 supplies the upper 9 bits of the 13 bits input to the adder 3121 to the adder 3123, and supplies the lower 4 bits to the error value converter 3124, the multiplier 3102, and the 1-clock delay unit 3109. To do. The error value converter 3124 outputs 0 if the input 4-bit data is less than or equal to the median value of the 4-bit data, and outputs 1 if the median value is exceeded.

  The adder 3123 adds 1 or 0 from the error value converter 3124 to the upper 9 bits from the bit extraction unit 3122. The bit extraction unit 3125 discards the lower 3 bits of the data from the adder 3123 and outputs the upper 6 bits as output data of the error diffusion processing unit 31. The 6-bit data output from the error diffusion processing unit 31 is input to the dither processing unit 32.

  A specific configuration and operation of the dither processing unit 32 will be described with reference to FIG. In FIG. 7, the bit extraction unit 321 supplies the upper 4 bits H of the 6-bit data output from the error diffusion processing unit 31 to the 1-clock delay unit 322 and the lower 2 bits L to the dither pattern reading unit 327. To supply.

  The timing generator 325 receives synchronization signals of the image data Da and Db that have been double-speed converted by the double-speed converters 2a and 2b. The timing generator 325 generates a timing signal including a frame counter signal, an X counter signal, and a Y counter signal based on the input synchronization signal.

  FIG. 8 shows a state in which the frame fa based on the image data Da shown in FIG. 2 sequentially shifts with time. Frame numbers are 1, 2, 3, 4, 5,... From the near side to the far side in FIG. This frame number is the same as the number at the end of the double speed frames fa1, fa2, fa3... Shown in FIG. The timing generator 325 generates a frame counter signal indicating the frame number.

  As shown in FIG. 8, the timing generator 325 repeatedly counts the pixel Px in the horizontal direction (X direction) from the left end of the screen as 0, 1, 2, 3, 0, 1, 2, 3, 0. A signal and a Y counter signal for repeatedly counting pixels Px (lines) in the vertical flat direction (Y direction) from the upper end of the screen as 0, 1, 2, 3, 0, 1, 2, 3, 0.

  Similarly, in the case of the frame fb based on the image data Db shown in FIG. 2, the timing generator 325 generates a frame counter signal indicating the frame numbers 1, 2, 3, 4, 5,. This frame number is the same as the number at the end of the double speed frames fb1, fb2, fb3... Shown in FIG. Similarly, in the case of the frame fb, the timing generator 325 generates an X counter signal that repeats 0 to 3 in the horizontal direction and a Y counter signal that repeats 0 to 3 in the vertical plane direction.

  The dither pattern storage unit 326 stores the dither patterns of the dither pattern sets 1 to 4 shown in FIG. Since the dither pattern when the L value of the lower 2 bits is 00 is common to the dither pattern sets 1 to 4, the dither pattern storage unit 326 stores 13 dither patterns.

  As can be seen from FIG. 8, the dither processing unit 32 uses an area of 16 pixels of 4 pixels in the horizontal direction and 4 pixels in the vertical direction as an area for adding dither. The dither pattern storage unit 326 stores a dither composed of 16 pixel regions of 4 pixels in the horizontal direction and 4 pixels in the vertical direction as a dither pattern.

  The dither pattern reading unit 327 receives the lower 2 bits L extracted by the bit extraction unit 321 and the frame counter signal, X counter signal, and Y counter signal generated by the timing generator 325.

  The dither pattern reading unit 327 selects one of the dither pattern sets 1 to 4 shown in FIG. 9 according to the frame counter signal. The dither pattern reading unit 327 selects the dither pattern set 1 if the frame number is 1, and selects the dither pattern set 2 if the frame number is 2.

  The dither pattern reading unit 327 selects the dither pattern set 3 if the frame number is 3, and selects the dither pattern set 4 if the frame number is 4. The dither pattern reading unit 327 selects the dither pattern set 1 if the frame number is 5, and selects the dither pattern set 2 if the frame number is 6.

  As described above, the dither pattern reading unit 327 cyclically selects the dither pattern sets 1 to 4 according to the frame numbers of the first and second image data (image data Da and Db).

  The dither pattern reading unit 327 selects one dither pattern from the selected dither pattern set according to the value of the lower 2 bits L of each pixel data. The dither pattern reading unit 327 generates a dither value “0” or “1” indicated by one selected dither pattern.

  A specific example will be described. In the case of the frame having the frame number 1 shown in FIG. 8, the dither pattern reading unit 327 selects the dither pattern set 1 based on FIG. In the region of 16 pixels surrounded by the thick solid line in FIG. 8, if the value of the lower 2 bits L of the pixel data at the position (X, Y) is (0, 0) is 00, the dither pattern reading unit 327 Since the dither pattern corresponding to the value 00 of the lower 2 bits L of the dither pattern set 1 is selected, the dither value is “0”.

  If the value of the lower 2 bits L of the pixel data at the position (X, Y) at (0, 0) is 01, the dither pattern reading unit 327 corresponds to the value 01 of the lower 2 bits L of the dither pattern set 1. Since the selected dither pattern is selected, the dither value is “1”. When the value of the lower 2 bits L of the pixel data at the position (X, Y) is (0, 0) is 10, the dither value is “1”, and (X, Y) is the position (0, 0). When the value of the lower 2 bits L of the pixel data is 11, the dither value is “0”.

  Each dither value indicated by the dither pattern read by the dither pattern reading unit 327 is delayed by one clock by the one-clock delay unit 328 and supplied to the adder 323. The adder 323 adds the upper 4 bits H delayed by one clock by the one clock delay unit 322 and the dither value delayed by one clock by the one clock delay unit 328. The 1-clock delay unit 324 delays the output of the adder 323 by 1 clock and outputs it as 4-bit data.

  In the present embodiment, as shown in FIG. 10, the dither pattern reading unit 327 uses the dither pattern set 1 for both the double speed frames fa1 and fb1, and uses the dither pattern set 2 for both the double speed frames fa2 and fb2. The dither pattern reading unit 327 uses the dither pattern set 3 for both the double speed frames fa3 and fb3, and uses the dither pattern set 4 for both the double speed frames fa4 and fb4.

  It is conceivable to assign the dither pattern sets as 1, 2, 3, 4, 1, 2,... To the double speed frames fa1, fb1, fa2, fb2, fa3, fb3. As shown in FIG. 10, the same dither pattern set is used for double-speed frames that are paired within one frame period of the image data Da and Db shown in (e).

  As described above, the dither pattern reading unit 327 performs a plurality of types of frames that are paired within one frame period of the first frame frequency in the first and second image data having the second frame frequency. Select a dither pattern of the same type from among the dither patterns.

  According to this embodiment, it is possible to make it difficult for image quality degradation, particularly image quality degradation in an oblique direction, to occur.

Returning to FIG. 1, data obtained by performing gradation conversion processing from 12-bit data to 4 bits as described above is input to the display device driving unit 4. The display device drive unit 4 drives the display device 5. Display device 5 includes a display device 517, and a wobbling device 519 for performing Rashi not a picture. The display element 517 is a liquid crystal display element as an example.

  A specific configuration example of the display device 5 will be described with reference to FIG. FIG. 11 shows a projection display device as an example of the display device 5. In FIG. 11, the light source LS includes a double-end type discharge lamp 501 and a reflector 502 that reflects light emitted from the discharge lamp 501 in the optical axis direction (Z direction). As the discharge lamp 501, a lamp that emits white light such as a high-pressure mercury lamp or a metal halide lamp is used.

  The reflector 502 has a rotating paraboloidal reflecting surface about the optical axis, reflects the light emitted from the discharge lamp 501 on the reflecting surface, and emits it as illumination light parallel to the optical axis. The reflector 502 may have a spheroidal reflection surface with the optical axis as an axis. In that case, a lens system that makes illumination light substantially parallel light is provided on the light emission side of the reflector 502.

  Light emitted from the light source LS passes through a cold filter 503 that cuts ultraviolet rays and infrared rays, and is incident on the first lens array 504. The first lens array 504 has a plurality of rectangular lens cells similar to the display areas of the reflective liquid crystal display elements 517b, 517g, and 517r arranged in the horizontal direction (X direction) and the vertical direction (Y direction). It is. The liquid crystal display elements 517b, 517g, and 517r correspond to the display element 517 in FIG.

  The first lens array 504 is configured so that the reflector 502 spatially divides the aperture from which the light beam is emitted. The illumination light emitted from the first lens array 504 is incident on the second lens array 505. The first and second lens arrays 504 and 505 are also referred to as a fly eye lens and a fly eye integrator.

  The second lens array 505 has the same configuration as the first lens array 504, and a plurality of rectangular lens cells similar to the display areas of the liquid crystal display elements 517b, 517g, and 517r are arranged in the X direction and the Y direction. Is.

  The first lens array 504 causes the illumination light to enter the lens cells of the second lens array 505 corresponding to the plurality of lens cells in the first lens array 504, and the first lens array 504 has the first lens array 505 on the first lens array 505. The same number of secondary light source images as the lens cells of the lens array 504 are formed.

  The illumination light emitted from the second lens array 505 is incident on the polarization conversion element 506. The polarization conversion element 506 emits indefinitely polarized light that randomly includes P-polarized light and S-polarized light as S-polarized light. The indefinite polarization may be aligned with the P polarization.

  S-polarized light emitted from the polarization conversion element 506 is incident on the overlapping lens 507. The superimposing lens 507 aligns the center of the image of each lens cell 504a of the first lens array 504 with the center of the liquid crystal display elements 517b, 517g, 517r, and aligns the image of each lens cell 504a with the liquid crystal display elements 517b, 517g, It acts to form an image in an overlapping state on the display surface 517r.

  The B / RG separation cross dichroic mirror 510 separates the S-polarized light emitted from the overlapping lens 507 into blue light and red / green light. The optical path of the blue light is bent by the B mirror 511, passes through the blue field lens 514b, the blue wire grid PBS 515b, and the blue wavelength plate 516b, and enters the blue liquid crystal display element 517b. The P-polarized light modulated and reflected by the blue liquid crystal display element 517b is reflected by the blue wire grid PBS 515b and travels toward the cross dichroic prism 518.

  The red / green light separated by the B / RG separation cross dichroic mirror 510 has its optical path bent by the RG mirror 512. The RG dichroic mirror 513 separates red / green light into red light and green light.

  The red light passes through the red field lens 514r, the red wire grid PBS 515r, and the red wavelength plate 516r, and enters the red liquid crystal display element 517r. The P-polarized light modulated and reflected by the red liquid crystal display element 517r is reflected by the red wire grid PBS 515r and travels toward the cross dichroic prism 518.

  The green light passes through the green field lens 514g, the green wire grid PBS 515g, and the green wavelength plate 516g, and enters the green liquid crystal display element 517g. The P-polarized light modulated and reflected by the green liquid crystal display element 517g is reflected by the green wire grid PBS 515g and travels toward the cross dichroic prism 518.

  The cross dichroic prism 518 combines the incident red light, blue light, and green light.

  The combined light emitted from the cross dichroic prism 518 enters the wobbling element 519. A specific configuration and operation of the wobbling element 519 will be described later.

  The projection lens 520 projects the combined light transmitted through the wobbling element 519 onto a screen (not shown). The liquid crystal display elements 517b, 517g, and 517r for red, blue, and green modulate the incident red light, blue light, and green light according to the red component, blue component, and green component of the video signal, respectively. A projected image corresponding to the video signal is displayed on the screen.

  A specific configuration and operation of the wobbling element 519 will be described with reference to FIG. As shown in FIG. 12, the wobbling element 519 has a two-layer structure in which a liquid crystal filter 5191 and a single crystal quartz plate 5192 are bonded together. In a state where the wobbling driving voltage Vwo (shown in FIG. 11) is not applied to the liquid crystal filter 5191, the light incident on the wobbling element 519 goes straight as it is and is emitted to the position P1, which is the first position.

  When the wobbling drive voltage Vwo is applied to the liquid crystal filter 5191, the light incident on the wobbling element 519 is bent in the traveling direction and emitted to the position P2, which is the second position.

  When the light incident on the wobbling element 519 is P-polarized light, the light emitted to the position P1 is P-polarized light, and the light emitted to the position P2 is S-polarized light.

  In a state where the wobbling driving voltage Vwo is not applied to the liquid crystal filter 5191, a projected image is displayed (output) at a position indicated by a solid line in FIG. 2, and in a state where the wobbling driving voltage Vwo is applied to the liquid crystal filter 5191, the broken line in FIG. The projected image is displayed (output) at the indicated position. As shown in FIG. 2, the pixel Px of the projected image is shifted by 0.5 pixels in the horizontal direction and the vertical direction, respectively, between the state where the wobbling driving voltage Vwo is not applied and the state where it is applied.

  For example, if a state where the wobbling driving voltage Vwo is not applied to the liquid crystal filter 5191 and a state where the wobbling driving voltage Vwo is applied to the liquid crystal filter 5191 are switched every 1 × speed frame, the projected image indicated by the solid line and the projected image indicated by the broken line in FIG. become.

  The degree to which the incident light is shifted when the wobbling drive voltage Vwo is applied to the wobbling element 519 depends on the configuration of the wobbling element 519. The wobbling element 519 is configured so that the projection image is shifted by 0.5 pixels in the horizontal direction and the vertical direction, respectively, between the state where the wobbling driving voltage Vwo is not applied and the state where it is applied.

  In the present embodiment, by performing pixel shifting by the wobbling element 519, the resolution can be increased twice as much as the root. According to the present embodiment, when the number of gradations of the image data Da is reduced and an image is displayed on the display device 5, it is possible to increase the apparent resolution while suppressing the occurrence of image quality degradation as much as possible.

  The present invention is not limited to the embodiment described above, and various modifications can be made without departing from the scope of the present invention. In the present embodiment, the liquid crystal display elements 517b, 517g, and 517r are used as the display elements in which a plurality of pixels are arranged in a matrix in the horizontal direction and the vertical direction. However, the display elements are not limited to the liquid crystal display elements.

  In the present embodiment, the projection type image display device is used, but a direct view type image display device may be used. However, the projection type image display apparatus is suitable for mounting a wobbling function. When the image display device is a projection type image display device, the configuration in FIG. 11 is merely an example, and the configuration of the projection type image display device is arbitrary.

1 Interpolation unit (image data generation unit)
2a, 2b Double speed conversion unit 3 Gradation conversion unit 4 Display device drive unit 5 Display device 31 Error diffusion processing unit 32 Dither processing unit 517, 517b, 517g, 517r Display element (liquid crystal display element)
519 Wobbling element

Claims (6)

A first image data which have a first frame frequency, having said first frame frequency, and a second image obtained by shifting positions of pixels of the first image data in the horizontal and vertical directions An image data generation unit for generating data;
A double speed conversion unit for converting the first and second image data into a second frame frequency that is twice the first frame frequency;
Error diffusion processing is performed on the first and second image data having the second frame frequency, and the first number of bits included in the first and second image data is set to the first number of bits. An error diffusion processing unit for converting to a smaller second bit number,
A dither processing unit for adding a dither composed of a predetermined dither pattern to predetermined high-order bits in the first and second image data converted into the second number of bits;
The first and second image data output from the dither processing unit are alternately displayed, and the position where the image displaying the first image data is output and the image displaying the second image data are output. A display device having a wobbling function to displace the position to be different from each other,
The first image data output from the dither processing unit is in a first position, and the second image data output from the dither processing unit is in a horizontal direction and a vertical direction with respect to the first position. A display device driving unit that drives the display device to output the shifted second position;
With
The dither processing unit
A plurality of types of dither patterns are cyclically selected according to the frame numbers of the first and second image data,
The same type of the plurality of types of dither patterns is used for frames paired within one frame period of the first frame frequency in the first and second image data having the second frame frequency. An image display device characterized by selecting a dither pattern. The dither processing unit
A plurality of dither patterns set corresponding to values of lower bits excluding the upper bits of the first and second image data converted into the second number of bits are set, and a plurality of dither pattern sets are Select cyclically according to the frame number of the first and second image data,
The image display according to claim 1, characterized in that among the dither pattern set selected in accordance with the first and the frame number of the second image data, selecting a dither pattern according to the value of the lower bit apparatus. The dither processing unit
A region composed of a plurality of pixels in the horizontal direction and the vertical direction in the first and second image data converted into the second number of bits is defined as a region to which dither is added, and the pixel data in each pixel data in the region is added. The pattern consisting of dither added to the upper bits is the dither pattern,
The image display apparatus according to claim 2, characterized in adding the dither indicated dither pattern selected according to the value of the lower-order bits of said each pixel data wherein each pixel data. A first image data which have a first frame frequency, having said first frame frequency, and a second image obtained by shifting positions of pixels of the first image data in the horizontal and vertical directions A generation step for generating data;
A frame frequency conversion step of converting the first and second image data into a second frame frequency that is twice the first frame frequency;
Error diffusion processing is performed on the first and second image data having the second frame frequency, and the first number of bits included in the first and second image data is set to the first number of bits. A bit number conversion step of converting to a second bit number smaller than
A dither addition step of adding a dither consisting of a predetermined dither pattern to predetermined upper bits in the first and second image data converted into the second number of bits;
The first and second image data added with dither are alternately displayed on a display element,
The first image data displayed on the display element is shifted to a first position, and the second image data displayed on the display element is shifted in a horizontal direction and a vertical direction with respect to the first position. A wobbling step for wobbling a position to output an image so as to be displayed at the second position;
Including
The dither addition step includes:
A plurality of types of dither patterns are cyclically selected according to the frame numbers of the first and second image data,
The same type of the plurality of types of dither patterns is used for frames paired within one frame period of the first frame frequency in the first and second image data having the second frame frequency. An image display method characterized by selecting a dither pattern. The dither addition step includes:
A plurality of dither patterns set corresponding to values of lower bits excluding the upper bits of the first and second image data converted into the second number of bits are set, and a plurality of dither pattern sets are Select cyclically according to the frame number of the first and second image data,
The image display according to claim 4, characterized in that among the dither pattern set selected in accordance with the first and the frame number of the second image data, selecting a dither pattern according to the value of the lower bit Method. The dither addition step includes:
A region composed of a plurality of pixels in the horizontal direction and the vertical direction in the first and second image data converted into the second number of bits is defined as a region to which dither is added, and the pixel data in each pixel data in the region is added. The pattern consisting of dither added to the upper bits is the dither pattern,
The image display method according to claim 5, characterized in adding the dither indicated dither pattern selected according to the value of the lower-order bits of the respective pixel data to each of the pixel data.

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