JP6035714B2 - SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE - Google Patents

SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE Download PDF

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Publication number
JP6035714B2
JP6035714B2 JP2011178390A JP2011178390A JP6035714B2 JP 6035714 B2 JP6035714 B2 JP 6035714B2 JP 2011178390 A JP2011178390 A JP 2011178390A JP 2011178390 A JP2011178390 A JP 2011178390A JP 6035714 B2 JP6035714 B2 JP 6035714B2
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Japan
Prior art keywords
bump
solder
stud bump
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2011178390A
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Japanese (ja)
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JP2013042005A (en
Inventor
悟 脇山
悟 脇山
尾崎　裕司
裕司 尾崎
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Sony Corp
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Sony Corp
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Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2011178390A priority Critical patent/JP6035714B2/en
Priority to KR1020120086059A priority patent/KR101996676B1/en
Priority to TW101128440A priority patent/TWI523175B/en
Priority to US13/568,574 priority patent/US9105625B2/en
Priority to CN2012102857034A priority patent/CN102956603A/en
Publication of JP2013042005A publication Critical patent/JP2013042005A/en
Priority to US14/790,146 priority patent/US20150303167A1/en
Application granted granted Critical
Publication of JP6035714B2 publication Critical patent/JP6035714B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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Description

本技術は、スタッドバンプを用いて接続される構成の半導体装置、半導体装置の製造方法、及び、電子機器に関する。   The present technology relates to a semiconductor device configured to be connected using a stud bump, a method for manufacturing the semiconductor device, and an electronic device.

半導体装置のフリップチップ接続技術として、Ａｕスタッドバンプを、ＳｎＡｇはんだバンプに接続する方法やＰｄで被覆したＳｎはんだバンプに接続する方法がある（特許文献１、特許文献２）。
Ａｕスタッドバンプを、半導体チップのＣｕ電極へ接続するフリップチップ接続技術（特許文献３）や、ＳｎめっきされたＣｕ電極へ接続するフリップチップ接続技術（特許文献４）がある。
また、Ａｕスタッドバンプに替わる、Ｃｕスタッドバンプが提案されている（特許文献５）。 As a flip-chip connection technique of a semiconductor device, there are a method of connecting Au stud bumps to SnAg solder bumps and a method of connecting to Sn solder bumps coated with Pd (Patent Documents 1 and 2).
There is a flip chip connection technique (Patent Document 3) for connecting Au stud bumps to a Cu electrode of a semiconductor chip and a flip chip connection technique (Patent Document 4) for connecting to an Sn plated Cu electrode.
Further, a Cu stud bump is proposed in place of the Au stud bump (Patent Document 5).

特開２００９−２１８４４２号公報JP 2009-218442 A 特開２００９−２３９２７８号公報JP 2009-239278 A 特開２００１−６０６０２号公報Japanese Patent Laid-Open No. 2001-60602 特開２００５−１７９０９９号公報JP 2005-179099 A 特開２０１１−２３５６８号公報JP 2011-23568 A

上述のスタッドバンプを用いたフリップチップ接続技術では、半導体装置の接続信頼性の向上が求められている。   In the flip-chip connection technology using the stud bump described above, improvement in connection reliability of a semiconductor device is required.

本技術は、接続信頼性の高い半導体装置、半導体装置の製造方法、及び、電子機器を提供するものである。   The present technology provides a semiconductor device with high connection reliability, a method for manufacturing the semiconductor device, and an electronic apparatus.

本技術の半導体装置は、半導体部材と、半導体部材上に形成されているＣｕスタッドバンプと、Ｃｕスタッドバンプと電気的に接続するはんだバンプとを備える。
また、本技術の半導体装置の製造方法は、半導体部材上にＣｕスタッドバンプを形成する工程と、Ｃｕスタッドバンプをはんだバンプにフリップチップ接続する工程とを有する。
また、本技術の電子機器は、上記半導体装置と、半導体装置の出力信号を処理する信号処理回路とを備える。 A semiconductor device of the present technology includes a semiconductor member, a Cu stud bump formed on the semiconductor member, and a solder bump that is electrically connected to the Cu stud bump.
Moreover, the manufacturing method of the semiconductor device of this technique has the process of forming Cu stud bump on a semiconductor member, and the process of flip-chip-connecting Cu stud bump to a solder bump.
In addition, an electronic apparatus of the present technology includes the semiconductor device and a signal processing circuit that processes an output signal of the semiconductor device.

上述の半導体装置及び半導体装置の製造方法によれば、Ｃｕスタッドバンプを用いてフリップチップ接続を行うことにより、低温接続においてもＣｕとはんだとの接続部分に強度の低い合金が発生しない。このため、Ｃｕスタッドバンプとはんだバンプとの接続部における接続不良を抑制し、接続信頼性を向上することができる。   According to the semiconductor device and the method for manufacturing the semiconductor device described above, by performing the flip chip connection using the Cu stud bump, an alloy having a low strength is not generated at the connection portion between the Cu and the solder even in the low temperature connection. For this reason, the connection failure in the connection part of Cu stud bump and a solder bump can be suppressed, and connection reliability can be improved.

本技術によれば、接続信頼性の高い半導体装置、及び、電子機器を提供することができる。   According to the present technology, a semiconductor device and an electronic device with high connection reliability can be provided.

Ａは、フリップチップ接続前のスタッドバンプとはんだバンプの構成を示す図である。Ｂは、フリップチップ接続後のスタッドバンプとはんだバンプの構成を示す図である。A is a figure which shows the structure of the stud bump and solder bump before flip-chip connection. B is a diagram showing the configuration of stud bumps and solder bumps after flip-chip connection. Ａは、フリップチップ接続前のスタッドバンプとはんだバンプの構成を示す図である。Ｂは、フリップチップ接続後のスタッドバンプとはんだバンプの構成を示す図である。A is a figure which shows the structure of the stud bump and solder bump before flip-chip connection. B is a diagram showing the configuration of stud bumps and solder bumps after flip-chip connection. 第１実施形態の半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device of 1st Embodiment. フリップチップ接続前のＣｕスタッドバンプの構成を示す図である。It is a figure which shows the structure of Cu stud bump before flip-chip connection. フリップチップ接続後のＣｕスタッドバンプとはんだバンプの構成を示す図である。It is a figure which shows the structure of Cu stud bump and solder bump after flip-chip connection. 第１実施形態の半導体装置のプロセスフローを示す図である。It is a figure which shows the process flow of the semiconductor device of 1st Embodiment. Ａ〜Ｃは、Ｃｕスタッドバンプの製造工程図である。AC is a manufacturing process diagram of a Cu stud bump. Ａ〜Ｄは、はんだバンプの製造工程図である。A to D are manufacturing process diagrams of solder bumps. Ａ〜Ｃは、Ｃｕスタッドバンプとはんだバンプによるフリップチップ接続の工程図である。FIGS. 4A to 4C are process diagrams of flip chip connection using Cu stud bumps and solder bumps. 第１実施形態の半導体装置のプロセスフローの変形例を示す図である。It is a figure which shows the modification of the process flow of the semiconductor device of 1st Embodiment. Ａ〜Ｃは、Ｃｕスタッドバンプとはんだバンプによるフリップチップ接続の工程図である。FIGS. 4A to 4C are process diagrams of flip chip connection using Cu stud bumps and solder bumps. 第１実施形態の半導体装置の変形例の構成を示す図である。It is a figure which shows the structure of the modification of the semiconductor device of 1st Embodiment. 第２実施形態の半導体装置の構成を示す断面図である。It is sectional drawing which shows the structure of the semiconductor device of 2nd Embodiment. 第２実施形態の半導体装置のプロセスフローを示す図である。It is a figure which shows the process flow of the semiconductor device of 2nd Embodiment. 第２実施形態の半導体装置のプロセスフローの変形例を示す図である。It is a figure which shows the modification of the process flow of the semiconductor device of 2nd Embodiment. 電子機器の構成を示す図である。It is a figure which shows the structure of an electronic device.

以下、本技術を実施するための形態例を説明するが、本技術は以下の例に限定されるものではない。
なお、説明は以下の順序で行う。
１．半導体装置の概要
２．半導体装置の第１実施形態
３．第１実施形態の半導体装置の製造方法
４．半導体装置の第２実施形態
５．第２実施形態の半導体装置の製造方法
６．電子機器 Hereinafter, exemplary embodiments for carrying out the present technology will be described, but the present technology is not limited to the following examples.
The description will be given in the following order.
1. 1. Outline of semiconductor device First Embodiment of Semiconductor Device 3. 3. Manufacturing method of semiconductor device according to first embodiment Second Embodiment of Semiconductor Device 5. 5. Manufacturing method of semiconductor device according to second embodiment Electronics

〈１．半導体装置の概要〉
半導体装置のフリップチップ接続の概要について説明する。
図１に、従来の一般的なＡｕスタッドバンプを用いたフリップチップ接続の構成を示す。図１Ａは、接続前のＡｕスタッドバンプ１１及びＳｎバンプ１２の構成を示す図である。図１Ｂは、接続後のＡｕスタッドバンプ１１及びＳｎバンプ１２の構成を示す図である。 <1. Overview of semiconductor devices>
An outline of flip chip connection of a semiconductor device will be described.
FIG. 1 shows a flip-chip connection configuration using a conventional general Au stud bump. FIG. 1A is a diagram illustrating the configuration of the Au stud bump 11 and the Sn bump 12 before connection. FIG. 1B is a diagram illustrating the configuration of the Au stud bump 11 and the Sn bump 12 after connection.

図１Ａに示すＡｕスタッドバンプ１１は、Ａｕワイヤを用いて形成されたＡｕバンプである。Ａｕスタッドバンプ１１は、半導体部材１３上に形成された電極１４上に形成されている。半導体部材１３は、Ａｕスタッドバンプ１１が形成されている電極１４上を除き、保護層１５により被覆されている。   Au stud bumps 11 shown in FIG. 1A are Au bumps formed using Au wires. The Au stud bump 11 is formed on the electrode 14 formed on the semiconductor member 13. The semiconductor member 13 is covered with a protective layer 15 except on the electrode 14 on which the Au stud bump 11 is formed.

また、図１Ａに示すＳｎバンプ１２は、Ｓｎ系はんだからなり、例えばＳｎＡｇはんだバンプ等からなる。Ｓｎバンプ１２は、配線基板１６上に形成された電極１７、電極１７上に形成されたアンダーバンプメタル（ＵＢＭ）１８上に形成されている。半導体部材１３は、ＵＢＭ１８が形成されている電極１７上を除き、保護層１９により被覆されている。   Further, the Sn bump 12 shown in FIG. 1A is made of Sn-based solder, for example, SnAg solder bump. The Sn bump 12 is formed on an electrode 17 formed on the wiring substrate 16 and an under bump metal (UBM) 18 formed on the electrode 17. The semiconductor member 13 is covered with a protective layer 19 except on the electrode 17 on which the UBM 18 is formed.

図１Ｂに示すように、Ａｕスタッドバンプ１１とＳｎバンプ１２とにより、半導体部材１３を配線基板１６上にフリップチップ接続する。
このとき、Ａｕスタッドバンプ１１とＳｎバンプ１２との接続は、接続信頼性を高めるために、３００℃以上で行う必要がある。
３００℃以下の接続では、図１Ｂに示すように、ＡｕのＳｎへの拡散により、接続部分にＳｎＡｕ４合金等の強度の低い金属間化合物（Inter Metallic Compound：ＩＭＣ）２０が生成する。このため、クラック２４等の発生により接続不良が低下し、信頼性の低下が懸念される。また、Ｓｎバンプ１２にＡｕスタッドバンプ１１が刺さった状態となるため、ＡｕのＳｎへの拡散を防ぐことは困難である。このため、接続部分でのＩＭＣ２０の発生を防ぐことが難しい。
上述のように、Ａｕスタッドバンプ１１とＳｎバンプ１２とによるフリップチップ接続では、３００℃以上の高温接続が必要とされ、接続信頼性の観点から低温接続が困難である。 As shown in FIG. 1B, the semiconductor member 13 is flip-chip connected to the wiring substrate 16 by the Au stud bump 11 and the Sn bump 12.
At this time, the connection between the Au stud bump 11 and the Sn bump 12 needs to be performed at 300 ° C. or higher in order to improve connection reliability.
In the connection at 300 ° C. or lower, as shown in FIG. 1B, due to diffusion of Au into Sn, an intermetallic compound (IMC) 20 having a low strength such as SnAu 4 alloy is generated in the connection portion. For this reason, connection failure is reduced due to the occurrence of cracks 24 and the like, and there is a concern that reliability may be reduced. Further, since the Au stud bump 11 is stuck in the Sn bump 12, it is difficult to prevent the diffusion of Au into Sn. For this reason, it is difficult to prevent the occurrence of IMC 20 at the connection portion.
As described above, the flip chip connection using the Au stud bump 11 and the Sn bump 12 requires a high temperature connection of 300 ° C. or more, and is difficult to connect at a low temperature from the viewpoint of connection reliability.

また、Ｓｎバンプを用いる替わりに、図２に示すように、Ｉｎ系の低融点はんだバンプを用いてＡｕスタッドバンプのフリップチップ接続を行うことが考えられている。図２Ａは、接続前のＡｕスタッドバンプ２１及びＩｎバンプ２２の構成を示す図である。図２Ｂは、接続後のＡｕスタッドバンプ２１及びＩｎバンプ２２の構成を示す図である。   Instead of using Sn bumps, it is considered to perform flip chip connection of Au stud bumps using In-based low melting point solder bumps as shown in FIG. FIG. 2A is a diagram illustrating the configuration of the Au stud bump 21 and the In bump 22 before connection. FIG. 2B is a diagram illustrating the configuration of the Au stud bump 21 and the In bump 22 after connection.

図２Ａに示すＡｕスタッドバンプ２１は、上述の図１Ａと同様の構成である。また、Ｉｎバンプは、Ｉｎ系はんだからなる。この方法では、強度の低いＳｎＡｕ４等の合金が発生しないため、２００℃以下の低温フリップチップ接続が可能である。
しかし、Ａｕスタッドバンプ２１とＩｎバンプ２２とを用いた接続では、ＡｕとＩｎとの間の拡散係数が大きいため、ＡｕＩｎ合金の成長を制御することが難しい。この結果、図２Ｂに示すように、ＡｕＩｎ合金２３の成長により、Ｉｎバンプの吸い上げが発生する。このため、Ａｕスタッドバンプ２１とＩｎバンプ２２とによるフリップチップ接続では、接続性を確保することが難しい。 The Au stud bump 21 shown in FIG. 2A has the same configuration as that of FIG. 1A described above. The In bump is made of In-based solder. In this method, since an alloy such as SnAu 4 having a low strength is not generated, a low-temperature flip chip connection at 200 ° C. or lower is possible.
However, in the connection using the Au stud bump 21 and the In bump 22, since the diffusion coefficient between Au and In is large, it is difficult to control the growth of the AuIn alloy. As a result, as shown in FIG. 2B, the growth of the AuIn alloy 23 causes the In bumps to be sucked up. For this reason, it is difficult to ensure connectivity in the flip chip connection using the Au stud bump 21 and the In bump 22.

上述のようにスタッドバンプを用いたフリップチップ接続では、接続信頼性の観点から、低温処理を行うことが困難であった。このため、半導体部材等に、耐熱性の低い材料が搭載されている場合には、接続信頼性の高いフリップチップ接続を適用することができない。そこで、耐熱性の低い材料が使用されている半導体装置等に対しても、低温での安定した接続が可能であり、且つ、接続信頼性の高いフリップチップ接続方法が求められている。   As described above, in flip chip connection using stud bumps, it is difficult to perform low-temperature processing from the viewpoint of connection reliability. For this reason, when a material having low heat resistance is mounted on a semiconductor member or the like, flip chip connection with high connection reliability cannot be applied. Therefore, there is a demand for a flip chip connection method that enables stable connection at a low temperature and high connection reliability even for a semiconductor device or the like using a material having low heat resistance.

〈２．半導体装置の第１実施形態〉
［イメージセンサ：構成］
以下、半導体装置の第１実施形態について説明する。図３に第１実施形態の半導体装置の構成を表す断面図を示す。第１実施形態は、半導体装置としてイメージセンサの例を挙げて説明する。図３は、ガラス基板上に実装されたイメージセンサからなる半導体装置３０の断面図である。 <2. First Embodiment of Semiconductor Device>
[Image sensor: configuration]
Hereinafter, a first embodiment of the semiconductor device will be described. FIG. 3 is a sectional view showing the configuration of the semiconductor device according to the first embodiment. In the first embodiment, an example of an image sensor will be described as a semiconductor device. FIG. 3 is a cross-sectional view of the semiconductor device 30 including an image sensor mounted on a glass substrate.

半導体装置３０は、イメージセンサを構成する半導体部材３１と、ガラス基板３２とを備えて構成されている。半導体部材３１は、半導体部材３１上に形成された電極４５と、電極４５上に形成されたＣｕスタッドバンプ４１とを備える。
また、ガラス基板３２は、ガラス基板上に形成されたフリップチップ接続用の電極４７と、電極４７上に形成されたアンダーバンプメタル（ＵＢＭ）４８と、ＵＢＭ４８上に形成された低融点はんだバンプ４４とを備える。さらに、ガラス基板３２上に形成された配線層３４と、配線層を被覆する保護層４９と、配線層３４と接続された外部接続用の電極３５と、外部接続用の電極３５上に形成されたはんだボール３６とを備える。
また、半導体部材３１とガラス基板３２との間には、Ｃｕスタッドバンプ４１とはんだバンプ４４との接続部を封止するアンダーフィル（ＵＦ）樹脂３３が設けられている。 The semiconductor device 30 includes a semiconductor member 31 constituting an image sensor and a glass substrate 32. The semiconductor member 31 includes an electrode 45 formed on the semiconductor member 31 and a Cu stud bump 41 formed on the electrode 45.
The glass substrate 32 includes flip-chip connection electrodes 47 formed on the glass substrate, under bump metal (UBM) 48 formed on the electrodes 47, and low melting point solder bumps 44 formed on the UBM 48. With. Furthermore, the wiring layer 34 formed on the glass substrate 32, the protective layer 49 covering the wiring layer, the electrode 35 for external connection connected to the wiring layer 34, and the electrode 35 for external connection are formed. Solder ball 36.
In addition, an underfill (UF) resin 33 is provided between the semiconductor member 31 and the glass substrate 32 to seal the connection portion between the Cu stud bump 41 and the solder bump 44.

半導体部材３１は、一般にイメージセンサとして使用される素子であり、例えば、ＣＣＤイメージセンサ、ＣＭＯＳイメージセンサ等の半導体素子である。半導体部材３１はガラス基板３２側に受光面を向けて設置されている。
また、半導体部材３１は、受光面と同じ面にガラス基板３２と接続される電極４５が形成されている。そして、この電極４５上に、フリップチップ接続用のＣｕスタッドバンプ４１が形成されている。Ｃｕスタッドバンプ４１は、はんだバンプ４４との接触面に合金層４３が形成されている。また、Ｃｕスタッドバンプ４１は、はんだバンプ４４と接触していない表面にめっき層４２を備える。 The semiconductor member 31 is an element that is generally used as an image sensor. For example, the semiconductor member 31 is a semiconductor element such as a CCD image sensor or a CMOS image sensor. The semiconductor member 31 is installed with the light receiving surface facing the glass substrate 32 side.
The semiconductor member 31 has an electrode 45 connected to the glass substrate 32 on the same surface as the light receiving surface. A Cu stud bump 41 for flip chip connection is formed on the electrode 45. The Cu stud bump 41 has an alloy layer 43 formed on the contact surface with the solder bump 44. Further, the Cu stud bump 41 includes a plating layer 42 on the surface not in contact with the solder bump 44.

ガラス基板３２は、例えば、イメージセンサに用いられるカバーガラスからなる。そして、ガラス基板３２上に、配線層３４によりフリップチップ接続用の電極４７と、外部接続用の電極３５とが接続されている。電極３５上には、外部機器接続用のはんだボール３６が形成されている。このはんだボール３６は、Ｓｎ系の二元系又は三元系はんだ等が用いられる。例えば、ＳｎＢｉ、ＳｎＩｎ、ＳｎＡｇＣｕ、ＳｎＺｎ及びＳｎＡｇ等が用いられる。なお、ガラス基板３２は、はんだボール３６の替わりに、Ａｕワイヤを用いたワイヤボンディングにより接続する構成としてもよい。   The glass substrate 32 is made of, for example, a cover glass used for an image sensor. On the glass substrate 32, an electrode 47 for flip chip connection and an electrode 35 for external connection are connected by a wiring layer 34. A solder ball 36 for connecting an external device is formed on the electrode 35. As the solder balls 36, Sn-based binary or ternary solder or the like is used. For example, SnBi, SnIn, SnAgCu, SnZn, SnAg, etc. are used. The glass substrate 32 may be connected by wire bonding using an Au wire instead of the solder ball 36.

［Ｃｕスタッドバンプ：構成］
次に、上述の半導体装置３０において、半導体部材３１上に形成するＣｕスタッドバンプ４１の構成を、図４に示す。図４に示すＣｕスタッドバンプ４１は、接続前の状態である。また、図５に半導体部材３１とガラス基板３２とを接続した後の、Ｃｕスタッドバンプ４１とはんだバンプ４４との構成を示す。 [Cu stud bump: composition]
Next, in the semiconductor device 30 described above, the configuration of the Cu stud bump 41 formed on the semiconductor member 31 is shown in FIG. The Cu stud bump 41 shown in FIG. 4 is in a state before connection. FIG. 5 shows the configuration of the Cu stud bump 41 and the solder bump 44 after the semiconductor member 31 and the glass substrate 32 are connected.

図４に示すように、Ｃｕスタッドバンプ４１は、半導体部材３１上の電極４５上に形成されている。半導体部材３１は、Ｃｕスタッドバンプ４１が形成されている電極４５上を除き、保護層４６により被覆されている。
また、Ｃｕスタッドバンプ４１は、表面がめっき層４２により被覆されている。
めっき層４２は、Ｃｕスタッドバンプ４１の酸化を防ぐための保護層となる。また、めっき層４２は、Ｃｕスタッドバンプ４１をフリップチップ接続した際に、表面のめっき層が、はんだバンプ４４内に速やかに拡散する材料によって構成する。
めっき層４２としては、例えば、無電解法によるフラッシュＮｉめっき層とフラッシュＡｕめっき層とからなるめっき層、又は、無電解Ｃｏめっき層を用いる。
めっき層４２は、例えば、各層の厚さが０．０１〜０．１μｍで形成される。 As shown in FIG. 4, the Cu stud bump 41 is formed on the electrode 45 on the semiconductor member 31. The semiconductor member 31 is covered with a protective layer 46 except on the electrode 45 where the Cu stud bump 41 is formed.
Further, the surface of the Cu stud bump 41 is covered with a plating layer 42.
The plating layer 42 serves as a protective layer for preventing the Cu stud bump 41 from being oxidized. The plating layer 42 is made of a material that allows the surface plating layer to quickly diffuse into the solder bump 44 when the Cu stud bump 41 is flip-chip connected.
As the plating layer 42, for example, a plating layer composed of a flash Ni plating layer and a flash Au plating layer by an electroless method or an electroless Co plating layer is used.
The plating layer 42 is formed with a thickness of each layer of 0.01 to 0.1 μm, for example.

また、ガラス基板３１上に設けられるはんだバンプ４４は、低融点はんだから構成される。低融点はんだとしては、例えば、Ｉｎの一元系はんだ材料、Ｓｎ−Ｂｉ、Ｓｎ−Ｉｎ、Ｂｉ−Ｉｎ等の二元系低融点はんだ材料、上記二元系材料にその他の金属が添加されたはんだ材料等を用いる。低融点はんだとしては、例えば、融点２００℃以下のはんだ材料を用いる。   The solder bumps 44 provided on the glass substrate 31 are made of low melting point solder. As the low melting point solder, for example, a single solder material of In, a binary low melting point solder material such as Sn-Bi, Sn-In, or Bi-In, or a solder obtained by adding other metals to the above binary material Materials are used. As the low melting point solder, for example, a solder material having a melting point of 200 ° C. or lower is used.

そして、半導体部材３１に形成されたＣｕスタッドバンプ４１を、ガラス基板３２のはんだバンプ４４に圧接することで、Ｃｕスタッドバンプ４１の先端が、はんだバンプ４４内に入り込む。そして、はんだバンプ４４にＣｕスタッドバンプ４１が刺さった状態で加熱することにより、図５に示すようにフリップチップ接続が行われる。   The tip of the Cu stud bump 41 enters the solder bump 44 by pressing the Cu stud bump 41 formed on the semiconductor member 31 against the solder bump 44 of the glass substrate 32. Then, by heating with the Cu stud bump 41 stuck in the solder bump 44, the flip chip connection is performed as shown in FIG.

図５に示すように、Ｃｕスタッドバンプ４１とはんだバンプ４４との接触面のめっき層４２は、フリップチップ接続の際に、はんだバンプ４４内に拡散される。また、Ｃｕスタッドバンプ４１とはんだバンプ４４との接触面には、Ｃｕとはんだとの合金層４３が形成される。このとき、はんだバンプ４４は全て合金化せず、ＵＢＭ４８上に合金化していないはんだバンプ４４が残存していることが好ましい。   As shown in FIG. 5, the plating layer 42 on the contact surface between the Cu stud bump 41 and the solder bump 44 is diffused into the solder bump 44 at the time of flip chip connection. An alloy layer 43 of Cu and solder is formed on the contact surface between the Cu stud bump 41 and the solder bump 44. At this time, it is preferable that all the solder bumps 44 are not alloyed and the solder bumps 44 that are not alloyed remain on the UBM 48.

上述の構成によれば、フリップチップ接続のスタッドバンプの材料にＣｕを用いることにより、低融点はんだバンプ４４との界面に機械的強度に劣る合金の発生を防ぐことができる。また、はんだバンプ４４として、低融点はんだを用いることにより、フリップチップ接続を低温で行うことができる。
例えば、はんだバンプ４４がＩｎからなる場合には、Ｃｕスタッドバンプ４１とはんだバンプ４４との界面にＩｎ３Ｃｕ７の金属間化合物等が形成される。Ｉｎ３Ｃｕ７の金属間化合物は、機械的強度を十分に有する。このため、低温フリップチップ接続においても、接続信頼性の低下を引き起こす強度の低い合金が発生しない。また、Ｃｕスタッドバンプと、上述の二元系低融点はんだ等との組み合わせにおいても、界面に機械的強度に劣る合金層が発生しない。このため、熱に弱い構成を備える半導体部材３１においても、フリップチップ接続を適用することができる。
従って、フリップチップ接続において、低温接続が可能であり、さらに、半導体装置の接続信頼性を向上することができる。 According to the above-described configuration, the use of Cu as the material for the flip-chip connection stud bump can prevent the generation of an alloy having poor mechanical strength at the interface with the low melting point solder bump 44. Further, by using a low melting point solder as the solder bump 44, flip chip connection can be performed at a low temperature.
For example, when the solder bump 44 is made of In, an intermetallic compound of In 3 Cu 7 or the like is formed at the interface between the Cu stud bump 41 and the solder bump 44. The intermetallic compound of In 3 Cu 7 has sufficient mechanical strength. For this reason, even in a low-temperature flip chip connection, an alloy having low strength that causes a decrease in connection reliability is not generated. In addition, even in the combination of the Cu stud bump and the above-described binary low melting point solder or the like, an alloy layer having inferior mechanical strength is not generated at the interface. For this reason, flip-chip connection can also be applied to the semiconductor member 31 having a heat-sensitive configuration.
Therefore, low-temperature connection is possible in flip-chip connection, and connection reliability of the semiconductor device can be improved.

〈３．第１実施形態の半導体装置の製造方法〉
上述の第１実施形態の半導体装置の製造方法について説明する。なお、以下の説明では、半導体装置に形成するスタッドバンプ周辺の構成のみを説明する。その他の構成は従来公知の方法により製造することができる。 <3. Manufacturing Method of Semiconductor Device of First Embodiment>
A method for manufacturing the semiconductor device according to the first embodiment will be described. In the following description, only the configuration around the stud bump formed in the semiconductor device will be described. Other configurations can be manufactured by a conventionally known method.

［製造方法：後ＵＦ樹脂プロセスフロー］
図６に、図３に示す半導体装置３０のプロセスフローを示す。
図６に示すように、公知の方法を用いて、半導体基体上に半導体部材３１を構成する、フォトダイオード、各種トランジスタ等の各素子や、配線等を形成する。このとき、フリップチップ接続を行うための外部接続用の電極４５を形成する。
半導体部材３１の外部機器との接続用の電極４５上に、Ｃｕスタッドバンプ４１を形成する。
形成したＣｕスタッドバンプ４１上に無電解めっき法を用いて、めっき層４２を形成する。
半導体基体の各種素子の形成面と反対側の面（裏面）を切削（バックグラインド：ＢＧ）し、裏面照射型の固体撮像素子を構成する半導体部材３１を形成する。
半導体基体をダイシング（ＤＣ）して半導体部材３１を個片化する。 [Manufacturing method: Post-UF resin process flow]
FIG. 6 shows a process flow of the semiconductor device 30 shown in FIG.
As shown in FIG. 6, by using a known method, each element such as a photodiode and various transistors, wirings, and the like constituting the semiconductor member 31 are formed on a semiconductor substrate. At this time, an external connection electrode 45 for performing flip chip connection is formed.
Cu stud bumps 41 are formed on the electrodes 45 for connecting the semiconductor member 31 to external devices.
A plating layer 42 is formed on the formed Cu stud bump 41 using an electroless plating method.
The surface (back surface) opposite to the surface on which the various elements of the semiconductor substrate are formed is cut (back grind: BG) to form the semiconductor member 31 constituting the back-illuminated solid-state imaging device.
The semiconductor substrate 31 is separated into pieces by dicing (DC) the semiconductor substrate.

また、公知の方法を用いてガラス基板３２上に配線層３４や、電極４７等を形成する。そして、電極４７上にＵＢＭ４８を形成する。
ＵＢＭ４８上に低融点はんだを用いてはんだバンプ４４を形成する。 Further, the wiring layer 34, the electrode 47, and the like are formed on the glass substrate 32 using a known method. Then, the UBM 48 is formed on the electrode 47.
Solder bumps 44 are formed on the UBM 48 using low melting point solder.

次に、Ｃｕスタッドバンプ４１をはんだバンプ４４に圧接（ボンディング）することで、ガラス基板３２に個片化した半導体部材３１をフリップチップ接続する。接続後、Ｃｕスタッドバンプ４１とはんだバンプ４４との接続部の周りにアンダーフィル（ＵＦ）樹脂３３を注入する。そして、注入したＵＦ樹脂３３を加熱して、ＵＦ樹脂を硬化（キュア）する。
以上の工程により、半導体装置３０を製造することができる。 Next, the Cu stud bump 41 is press-contacted (bonded) to the solder bump 44 so that the semiconductor member 31 separated into the glass substrate 32 is flip-chip connected. After the connection, an underfill (UF) resin 33 is injected around the connection portion between the Cu stud bump 41 and the solder bump 44. Then, the injected UF resin 33 is heated to cure (cure) the UF resin.
The semiconductor device 30 can be manufactured through the above steps.

［製造方法：Ｃｕスタッドバンプ］
上述の半導体装置３０のプロセスフローにおけるＣｕスタッドバンプの形成工程を、図７に示す製造工程図を用いて説明する。
図７Ａに示すように、キャピラリ５２を用いて半導体部材３１の電極４５上にＣｕワイヤ５１のボンディングを行う。そして、Ｃｕワイヤ５１を切断することにより、図７Ｂに示すように、Ｃｕスタッドバンプ４１を形成する。Ｃｕスタッドバンプ４１の形成工程では、例えば、径が１５〜３５μｍΦのＣｕワイヤ５１を用いて、３０〜７０μｍΦのＣｕスタッドバンプ４１を形成する。 [Production method: Cu stud bump]
A Cu stud bump forming process in the process flow of the semiconductor device 30 will be described with reference to a manufacturing process diagram shown in FIG.
As shown in FIG. 7A, the Cu wire 51 is bonded onto the electrode 45 of the semiconductor member 31 using the capillary 52. Then, the Cu stud 51 is formed by cutting the Cu wire 51 as shown in FIG. 7B. In the process of forming the Cu stud bump 41, for example, the Cu stud bump 41 having a diameter of 30 to 70 μmΦ is formed using a Cu wire 51 having a diameter of 15 to 35 μmΦ.

次に、図７Ｃに示すように、形成したＣｕスタッドバンプ４１の表面にめっき層４２を形成する。めっき層４２は、無電解めっき法を用いて形成する。例えば、Ｃｕスタッドバンプ４１表面に無電解めっき法により、フラッシュＮｉめっきを行う。そして、Ｎｉめっき層上に、フラッシュＡｕめっきを行う。このように、Ｎｉめっき層とＡｕめっき層とからなるめっき層４２を形成する。
めっき層４２は、例えば、Ｎｉめっき層とＡｕめっき層をそれぞれ０．０１〜０．１μｍの厚さに形成する。 Next, as shown in FIG. 7C, a plating layer 42 is formed on the surface of the formed Cu stud bump 41. The plating layer 42 is formed using an electroless plating method. For example, flash Ni plating is performed on the surface of the Cu stud bump 41 by electroless plating. Then, flash Au plating is performed on the Ni plating layer. Thus, the plating layer 42 composed of the Ni plating layer and the Au plating layer is formed.
As the plating layer 42, for example, a Ni plating layer and an Au plating layer are each formed to a thickness of 0.01 to 0.1 μm.

また、例えば、無電解めっき法を用いてＣｕスタッドバンプ４１表面に、めっき層４２としてＣｏめっきを行う。この場合、Ｃｏめっき層からなるめっき層４２を０．０１〜０．１μｍの厚さに形成する。
以上の工程により、半導体部材３１上にＣｕスタッドバンプ４１を形成する。 Further, for example, Co plating is performed as the plating layer 42 on the surface of the Cu stud bump 41 by using an electroless plating method. In this case, the plating layer 42 made of a Co plating layer is formed to a thickness of 0.01 to 0.1 μm.
The Cu stud bump 41 is formed on the semiconductor member 31 by the above process.

［製造方法：はんだバンプ］
次に、上述の半導体装置３０のプロセスフローにおけるはんだバンプの形成工程を、図８に示す製造工程図を用いて説明する。
図８Ａに示すように、電極４７及び保護層４９の表面にバリアメタル層５３を形成する。
バリアメタル層５３を形成する前に、電極４７の表面の酸化膜を逆スパッタにより除去する。その後、スパッタリング法を用いて電極４７上にＴｉ層を形成する。そして、Ｔｉ層を被覆するように、スパッタリング法を用いてＣｕ層を形成する。このように、Ｔｉ層とＣｕ層とからなるバリアメタル層５３を形成する。 [Manufacturing method: Solder bump]
Next, a solder bump forming process in the process flow of the semiconductor device 30 will be described with reference to a manufacturing process diagram shown in FIG.
As shown in FIG. 8A, a barrier metal layer 53 is formed on the surfaces of the electrode 47 and the protective layer 49.
Before forming the barrier metal layer 53, the oxide film on the surface of the electrode 47 is removed by reverse sputtering. Thereafter, a Ti layer is formed on the electrode 47 using a sputtering method. Then, a Cu layer is formed using a sputtering method so as to cover the Ti layer. Thus, the barrier metal layer 53 composed of the Ti layer and the Cu layer is formed.

次に、図８Ｂに示すように、バリアメタル層５３上に、レジスト層５４を形成する。そして、フォトマスク５５を用いてレジスト層５４に露光処理を行う。フォトマスク５５には、電極４７の形成部分に露光光を照射するパターンを用いる。   Next, as illustrated in FIG. 8B, a resist layer 54 is formed on the barrier metal layer 53. Then, an exposure process is performed on the resist layer 54 using the photomask 55. For the photomask 55, a pattern for irradiating exposure light onto a portion where the electrode 47 is formed is used.

次に、図８Ｃに示すように、レジスト層５４の露光部を除去した開口部内に、電解メッキ法を用いてアンダーバンプメタル（ＵＢＭ）４８とはんだバンプ４４を形成する。ＵＢＭ４８は、Ｎｉ、Ｔｉ、ＴｉＷ、Ｗ及びＣｕ等の電解メッキ法により形成する。また、はんだバンプ４４は、Ｉｎの一元系はんだ材料、Ｓｎ−Ｂｉ、Ｓｎ−Ｉｎ、Ｂｉ−Ｉｎ等の二元系低融点はんだ材料等を用いた電解めっき法により形成する。   Next, as shown in FIG. 8C, an under bump metal (UBM) 48 and a solder bump 44 are formed in the opening from which the exposed portion of the resist layer 54 is removed by using an electrolytic plating method. The UBM 48 is formed by electrolytic plating such as Ni, Ti, TiW, W and Cu. Further, the solder bumps 44 are formed by an electrolytic plating method using a single solder material of In, a binary low melting point solder material such as Sn-Bi, Sn-In, or Bi-In.

次に、図８Ｄに示すように、レジスト層５４を除去した後、表面に露出するバリアメタル層５３を除去する。さらに、リフローによりはんだバンプ４４を溶融して球状に形成する。
以上の工程により、ガラス基板３２上にはんだバンプ４４を形成する。 Next, as shown in FIG. 8D, after removing the resist layer 54, the barrier metal layer 53 exposed on the surface is removed. Further, the solder bumps 44 are melted and formed into a spherical shape by reflow.
The solder bumps 44 are formed on the glass substrate 32 through the above steps.

［製造方法：フリップチップ接続］
次に、上述の半導体装置３０のプロセスフローにおけるフリップチップ接続工程及びＵＦ樹脂封止工程を、図９に示す製造工程図を用いて説明する。
まず、図９Ａに示すように、Ｃｕスタッドバンプ４１の形成面とはんだバンプ４４の形成面とを対向させて、半導体部材３１とガラス基板３２との位置を合わせる。 [Manufacturing method: flip chip connection]
Next, the flip chip connecting process and the UF resin sealing process in the process flow of the semiconductor device 30 will be described with reference to the manufacturing process diagram shown in FIG.
First, as shown in FIG. 9A, the formation surface of the Cu stud bump 41 and the formation surface of the solder bump 44 are made to face each other, and the positions of the semiconductor member 31 and the glass substrate 32 are aligned.

次に、図９Ｂに示すように、Ｃｕスタッドバンプ４１とはんだバンプ４４とを位置合わせした状態で、半導体部材３１とガラス基板３２とを圧接してフリップチップ接続を行う。このとき、フリップチップ接続に合わせて、圧接と同時に加熱する。熱処理により、Ｃｕスタッドバンプ４１表面のめっき層４２がはんだバンプ４４に拡散する。また、熱処理により、Ｃｕスタッドバンプ４１とはんだバンプ４４との接続面に、合金層４３が発生及び成長する。
上述のフリップチップ接続において圧接時のバンプ単位に掛ける圧力（Bonding force）は、例えば、０．０１ｇｆ／ｂｕｍｐ〜１０ｇｆ／ｂｕｍｐである。また、フリップチップ接続の際の加熱温度は２００℃以下とする。また、加熱温度は、使用するはんだバンプ４４の融点以上の温度とする。例えば、はんだバンプ４４にＩｎ単体のはんだを用いた場合には、Ｉｎの融点である１５６℃以上に加熱する。 Next, as shown in FIG. 9B, in a state where the Cu stud bump 41 and the solder bump 44 are aligned, the semiconductor member 31 and the glass substrate 32 are pressed against each other to perform flip chip connection. At this time, heating is performed simultaneously with the pressure welding in accordance with the flip chip connection. Due to the heat treatment, the plating layer 42 on the surface of the Cu stud bump 41 diffuses into the solder bump 44. Further, the alloy layer 43 is generated and grows on the connection surface between the Cu stud bump 41 and the solder bump 44 by the heat treatment.
In the above-described flip-chip connection, the pressure applied to the bump unit during pressure contact (bonding force) is, for example, 0.01 gf / bump to 10 gf / bump. Further, the heating temperature at the time of flip chip connection is set to 200 ° C. or less. The heating temperature is set to a temperature equal to or higher than the melting point of the solder bump 44 to be used. For example, when In solder is used as the solder bump 44, it is heated to 156 ° C. or more which is the melting point of In.

次に、図９Ｃに示すように、Ｃｕスタッドバンプ４１とはんだバンプ４４との接続部分にアンダーフィル（ＵＦ）樹脂３３を塗布する。そして、ＵＦ樹脂３３を加熱して硬化する。ＵＦ樹脂３３は、半導体部材３１とガラス基板３２とを接着することにより、半導体装置の接着面の機械的な接続信頼性を向上させる。
以上の工程により、ガラス基板３２に半導体部材３１をフリップチップ接続することができる。 Next, as shown in FIG. 9C, an underfill (UF) resin 33 is applied to the connection portion between the Cu stud bump 41 and the solder bump 44. Then, the UF resin 33 is heated and cured. The UF resin 33 improves the mechanical connection reliability of the bonding surface of the semiconductor device by bonding the semiconductor member 31 and the glass substrate 32.
Through the above steps, the semiconductor member 31 can be flip-chip connected to the glass substrate 32.

上述のフリップチップ接続では、はんだバンプ４４に低融点はんだを用いることにより、２００℃以下で接続することができる。また、Ｃｕスタッドバンプ４１を用いることにより、低温フリップチップ接続でも強度の低い合金が発生しない。   In the above-described flip chip connection, by using a low melting point solder for the solder bump 44, the connection can be made at 200 ° C. or less. Further, by using the Cu stud bump 41, an alloy having low strength is not generated even at low temperature flip chip connection.

なお、上述の製造工程において、合金層を成長させる熱処理は、フリップチップ接続と同時に行わなくてもよい。例えば、半導体部材３１とガラス基板３２とを圧接してフリップチップ接続を行う工程の後に、別の工程においてアニール処理を行っても良い。このときのアニール処理も２００℃以下で行う。   In the above manufacturing process, the heat treatment for growing the alloy layer may not be performed simultaneously with the flip chip connection. For example, after the step of pressing the semiconductor member 31 and the glass substrate 32 to perform the flip chip connection, an annealing process may be performed in another step. The annealing process at this time is also performed at 200 ° C. or lower.

［変形例：先ＵＦ樹脂プロセスフロー］
次に、上述の半導体装置３０の製造方法の変形例を示す。この変形例では、ＵＦ樹脂によるフリップチップ接続部の封止を行う工程が、上述の製造方法と異なる。
図１０に、ＵＦ樹脂封止工程を変更したプロセスフローを示す。 [Variation: Prior UF resin process flow]
Next, a modification of the method for manufacturing the semiconductor device 30 will be described. In this modification, the step of sealing the flip chip connecting portion with UF resin is different from the above-described manufacturing method.
In FIG. 10, the process flow which changed the UF resin sealing process is shown.

図１０に示すように、公知の方法を用いて、半導体基体上に半導体部材３１を構成する、フォトダイオード、各種トランジスタ等の各素子や、配線等を形成する。このとき、フリップチップ接続を行うための外部接続用の電極４５を形成する。
半導体部材の外部機器との接続用の電極４５上に、Ｃｕスタッドバンプ４１を形成する。
形成したＣｕスタッドバンプ４１上に無電解めっき法を用いて、めっき層４２を形成する。
形成したＣｕスタッドバンプ４１上にアンダーフィル（ＵＦ）樹脂３３をラミネートする。
半導体基体の各種素子の形成面と反対側の面（裏面）を切削（バックグラインド：ＢＧ）し、裏面照射型の固体撮像素子を構成する半導体部材３１を形成する。
半導体基体をダイシング（ＤＣ）して半導体部材３１を個片化する。 As shown in FIG. 10, by using a known method, each element such as a photodiode and various transistors, wirings, and the like constituting the semiconductor member 31 are formed on a semiconductor substrate. At this time, an external connection electrode 45 for performing flip chip connection is formed.
Cu stud bumps 41 are formed on the electrodes 45 for connecting the semiconductor members to external devices.
A plating layer 42 is formed on the formed Cu stud bump 41 using an electroless plating method.
An underfill (UF) resin 33 is laminated on the formed Cu stud bump 41.
The surface (back surface) opposite to the surface on which the various elements of the semiconductor substrate are formed is cut (back grind: BG) to form the semiconductor member 31 constituting the back-illuminated solid-state imaging device.
The semiconductor substrate 31 is separated into pieces by dicing (DC) the semiconductor substrate.

また、公知の方法を用いてガラス基板３２上に配線層３４や、電極４７等を形成する。そして、電極４７上にＵＢＭ４８を形成する。
ＵＢＭ４８上に低融点はんだを用いてはんだバンプ４４を形成する。 Further, the wiring layer 34, the electrode 47, and the like are formed on the glass substrate 32 using a known method. Then, the UBM 48 is formed on the electrode 47.
Solder bumps 44 are formed on the UBM 48 using low melting point solder.

次に、Ｃｕスタッドバンプ４１をはんだバンプ４４に圧接（ボンディング）することで、ガラス基板３２に個片化した半導体部材３１をフリップチップ接続する。接続後、ＵＦ樹脂３３を加熱して硬化（キュア）する。
以上の工程により、半導体装置３０を製造することができる。 Next, the Cu stud bump 41 is press-contacted (bonded) to the solder bump 44 so that the semiconductor member 31 separated into the glass substrate 32 is flip-chip connected. After the connection, the UF resin 33 is heated and cured (cured).
The semiconductor device 30 can be manufactured through the above steps.

上述の半導体装置３０のプロセスフローにおけるＵＦ樹脂形成工程及びＵＦ樹脂封止工程を、図１１に示す製造工程図を用いて説明する。なお、以下の説明では、上述の半導体装置の製造方法と異なる工程のみを説明する。
まず、上述の工程によりＣｕスタッドバンプ４１にめっき層４２を形成（図７Ｃ）した後、図１１Ａに示すように、Ｃｕスタッドバンプ４１を覆うアンダーフィル（ＵＦ）樹脂３３を形成する。ＵＦ樹脂３３は、例えば、アンダーフィル樹脂を含む塗布液を用いたスピンコート法、又は、アンダーフィル樹脂のドライフィルムのラミネートにより形成する。 The UF resin forming step and the UF resin sealing step in the process flow of the semiconductor device 30 will be described with reference to the manufacturing process diagram shown in FIG. In the following description, only steps different from those of the semiconductor device manufacturing method described above will be described.
First, after the plating layer 42 is formed on the Cu stud bump 41 by the above-described process (FIG. 7C), an underfill (UF) resin 33 that covers the Cu stud bump 41 is formed as shown in FIG. 11A. The UF resin 33 is formed by, for example, a spin coating method using a coating solution containing an underfill resin, or by laminating a dry film of the underfill resin.

次に、図１１Ｂに示すように、Ｃｕスタッドバンプ４１の形成面とはんだバンプ４４の形成面とを対向させ、半導体部材３１とガラス基板３２との位置を合わせる。そして、図１１Ｃに示すように、半導体部材３１とガラス基板３２とを圧接してフリップチップ接続を行う。さらに、熱処理により、Ｃｕスタッドバンプ４１とはんだバンプ４１との接続面に合金層４３を成長させ、ＵＦ樹脂３３を硬化する。
以上の工程により、フリップチップ接続の前にＣｕスタッドバンプ４１を覆うＵＦ樹脂３３を形成し、ＵＦ樹脂３３をフリップチップ接続後に硬化する方法により、半導体装置３０を製造することができる。 Next, as shown in FIG. 11B, the formation surface of the Cu stud bump 41 and the formation surface of the solder bump 44 are opposed to each other, and the positions of the semiconductor member 31 and the glass substrate 32 are aligned. Then, as shown in FIG. 11C, the semiconductor member 31 and the glass substrate 32 are pressed to perform flip chip connection. Further, the alloy layer 43 is grown on the connection surface between the Cu stud bump 41 and the solder bump 41 by heat treatment, and the UF resin 33 is cured.
Through the above steps, the semiconductor device 30 can be manufactured by a method of forming the UF resin 33 covering the Cu stud bump 41 before the flip chip connection and curing the UF resin 33 after the flip chip connection.

［半導体装置の変形例］
上述の第１実施形態の半導体装置において、ガラス基板の代わりに配線基板を用いることができる。図１２に、配線基板を用いた半導体装置の構成を示す。 [Modification of semiconductor device]
In the semiconductor device of the first embodiment described above, a wiring board can be used instead of the glass substrate. FIG. 12 shows a configuration of a semiconductor device using a wiring board.

図１２に示す半導体装置は、イメージセンサを構成する半導体部材３１と、配線基板３７とを備えて構成されている。半導体部材３１は、半導体部材３１上に形成された電極４５と、電極４５上に形成されたＣｕスタッドバンプ４１とを備える。
また、配線基板３７は、配線基板３７上に形成されたフリップチップ接続用の電極４７と、電極４７上に形成されたアンダーバンプメタル（ＵＢＭ）４８と、ＵＢＭ４８上に形成された低融点はんだバンプ４４とを備える。さらに、ガラス基板３２上に形成された配線層３４と、配線層３４を被覆する保護層４９と、配線層３４と接続された外部接続用の電極３５と、外部接続用の電極３５上に形成されたはんだボール３６とを備える。
配線基板３７は、半導体部材３１の受光面上に透光性の光学部材３８、例えばガラス等を備える。そして、光学部材３８の周囲に沿っての配線基板３７上に、電極４７、ＵＢＭ４８及びはんだバンプ４４が形成されている。 The semiconductor device shown in FIG. 12 includes a semiconductor member 31 constituting an image sensor and a wiring board 37. The semiconductor member 31 includes an electrode 45 formed on the semiconductor member 31 and a Cu stud bump 41 formed on the electrode 45.
The wiring board 37 includes flip-chip connection electrodes 47 formed on the wiring board 37, under bump metal (UBM) 48 formed on the electrodes 47, and low melting point solder bumps formed on the UBM 48. 44. Furthermore, the wiring layer 34 formed on the glass substrate 32, the protective layer 49 covering the wiring layer 34, the external connection electrode 35 connected to the wiring layer 34, and the external connection electrode 35 are formed. Solder balls 36 are provided.
The wiring board 37 includes a light-transmitting optical member 38 such as glass on the light receiving surface of the semiconductor member 31. Electrodes 47, UBMs 48 and solder bumps 44 are formed on the wiring substrate 37 along the periphery of the optical member 38.

なお、図１２に示す半導体部材３１、及び、半導体部材３１のＣｕスタッドバンプ４１等の構成は、上述の第１実施形態と同様である。また、配線基板３７上に形成されるはんだバンプ４４、電極４７、及び、配線層３４等の構成は、上述の第１実施形態と同様である。   The configurations of the semiconductor member 31 and the Cu stud bump 41 of the semiconductor member 31 shown in FIG. 12 are the same as those in the first embodiment. The configurations of the solder bumps 44, the electrodes 47, the wiring layer 34, and the like formed on the wiring board 37 are the same as those in the first embodiment.

上述の変形例のように、Ｃｕスタッドバンプ４１を有する半導体部材３１をフリップチップ接続する対象は、フリップチップ接続に対応した電極と、この電極上に形成されたはんだバンプとを備える電子部品であれば特に限定されない。半導体部材がフリップチップ接続される電子部品としては、例えば、上述のガラス基板、配線基板の他に、半導体素子等であってもよい。   As in the above-described modification, the target to be flip-chip connected to the semiconductor member 31 having the Cu stud bump 41 is an electronic component including an electrode corresponding to the flip-chip connection and a solder bump formed on the electrode. If it does not specifically limit. The electronic component to which the semiconductor member is flip-chip connected may be, for example, a semiconductor element in addition to the glass substrate and the wiring substrate described above.

〈４．半導体装置の第２実施形態〉
次に、半導体装置の第２実施形態について説明する。図１３に第２実施形態の半導体装置を示す。
図１３に示す半導体装置６０は、第１半導体部材６１と第２半導体部材６２とからなる。そして、第２半導体部材６２上に、第１半導体部材６１がフリップチップ接続により搭載されている。 <4. Second Embodiment of Semiconductor Device>
Next, a second embodiment of the semiconductor device will be described. FIG. 13 shows a semiconductor device according to the second embodiment.
A semiconductor device 60 shown in FIG. 13 includes a first semiconductor member 61 and a second semiconductor member 62. The first semiconductor member 61 is mounted on the second semiconductor member 62 by flip chip connection.

第１半導体部材６１は、第１半導体部材６１上に形成された電極４５と、電極４５上に形成されたＣｕスタッドバンプ４１とを備える。なお、第１半導体部材６１は、上述の図３に示す第１実施形態の半導体部材３１と同様の構成であるため、詳細な説明を省略する。   The first semiconductor member 61 includes an electrode 45 formed on the first semiconductor member 61 and a Cu stud bump 41 formed on the electrode 45. Since the first semiconductor member 61 has the same configuration as the semiconductor member 31 of the first embodiment shown in FIG. 3 described above, detailed description thereof is omitted.

第２半導体部材６２は、フリップチップ接続用の電極４７と、電極４７上に形成されたアンダーバンプメタル（ＵＢＭ）４８と、ＵＢＭ４８上に形成された低融点はんだバンプ４４とを備える。さらに、第２半導体部材６２の端部には、外部接続用のワイヤボンディング用パッド電極６３を備える。第２半導体部材６２のワイヤボンディング用パッド電極６３によって、半導体装置６０が外部電子機器とワイヤボンディングにより電気的に接続される。また、フリップチップ接続用の電極４７とワイヤボンディング用パッド電極６３上を除く第２半導体部材６２の表面に保護層４９を備える。   The second semiconductor member 62 includes flip-chip connection electrodes 47, under bump metal (UBM) 48 formed on the electrodes 47, and low melting point solder bumps 44 formed on the UBM 48. Furthermore, a wire bonding pad electrode 63 for external connection is provided at the end of the second semiconductor member 62. The semiconductor device 60 is electrically connected to the external electronic device by wire bonding by the wire bonding pad electrode 63 of the second semiconductor member 62. Further, a protective layer 49 is provided on the surface of the second semiconductor member 62 except on the flip-chip connection electrode 47 and the wire bonding pad electrode 63.

Ｃｕスタッドバンプ４１は、表面がめっき層４２により被覆されている。めっき層４２としては、例えば、無電解法によるフラッシュＮｉめっき層とフラッシュＡｕめっき層とからなるめっき層、又は、無電解Ｃｏめっき層を用いる。
はんだバンプ４４は、低融点はんだから構成される。低融点はんだとしては、例えば、Ｉｎの一元系はんだ材料、Ｓｎ−Ｂｉ、Ｓｎ−Ｉｎ、Ｂｉ−Ｉｎ等の二元系低融点はんだ材料、上記二元系材料にその他の金属が添加されたはんだ材料等を用いる。
Ｃｕスタッドバンプ４１とはんだバンプ４４との接触面には、Ｃｕとはんだとの合金層４３が形成されている。 The surface of the Cu stud bump 41 is covered with a plating layer 42. As the plating layer 42, for example, a plating layer composed of a flash Ni plating layer and a flash Au plating layer by an electroless method or an electroless Co plating layer is used.
The solder bump 44 is made of low melting point solder. As the low melting point solder, for example, a single solder material of In, a binary low melting point solder material such as Sn-Bi, Sn-In, or Bi-In, or a solder obtained by adding other metals to the above binary material Materials are used.
An alloy layer 43 of Cu and solder is formed on the contact surface between the Cu stud bump 41 and the solder bump 44.

また、図１３に示す半導体装置６０は、第１半導体部材６１と第２半導体部材６２との間に、半導体部材同士の接続面全体を封止するアンダーフィル（ＵＦ）樹脂３３が設けられている。アンダーフィル樹脂３３により、第１半導体部材６１と第２半導体部材６２とが機械的に接続されている。そして、Ｃｕスタッドバンプ４１とはんだバンプ４４との接続部がＵＦ樹脂３３内に形成されている。このように、半導体装置６０では、第１半導体部材６１と第２半導体部材６２との間を満たすアンダーフィル樹脂３３によるフィレットが形成される。   Further, the semiconductor device 60 shown in FIG. 13 is provided with an underfill (UF) resin 33 that seals the entire connection surface between the semiconductor members between the first semiconductor member 61 and the second semiconductor member 62. . The first semiconductor member 61 and the second semiconductor member 62 are mechanically connected by the underfill resin 33. A connection portion between the Cu stud bump 41 and the solder bump 44 is formed in the UF resin 33. As described above, in the semiconductor device 60, a fillet made of the underfill resin 33 filling the space between the first semiconductor member 61 and the second semiconductor member 62 is formed.

〈５．第２実施形態の半導体装置の製造方法〉
［製造方法１：後ＵＦ樹脂プロセスフロー］
図１４に、図１３に示す半導体装置６０のプロセスフローを示す。
図１４に示すように、公知の方法を用いて、半導体基体上に第１半導体部材６１を構成する各種トランジスタ等の各素子や、配線等を形成する。このとき、フリップチップ接続を行うための外部接続用の電極４５を形成する。
第１半導体部材６１の外部機器との接続用の電極上に、Ｃｕスタッドバンプ４１を形成する。
形成したＣｕスタッドバンプ４１上に無電解めっき法を用いて、めっき層４２を形成する。
半導体基体の各種素子の形成面と反対側の面（裏面）を切削（バックグラインド：ＢＧ）する。そして、半導体基体をダイシング（ＤＣ）して第１半導体部材６１を個片化する。 <5. Manufacturing Method of Semiconductor Device of Second Embodiment>
[Manufacturing method 1: Post-UF resin process flow]
FIG. 14 shows a process flow of the semiconductor device 60 shown in FIG.
As shown in FIG. 14, each element such as various transistors constituting the first semiconductor member 61, wirings, and the like are formed on a semiconductor substrate using a known method. At this time, an external connection electrode 45 for performing flip chip connection is formed.
Cu stud bumps 41 are formed on the electrodes for connecting the first semiconductor member 61 to external devices.
A plating layer 42 is formed on the formed Cu stud bump 41 using an electroless plating method.
The surface (back surface) opposite to the surface on which the various elements of the semiconductor substrate are formed is cut (back grind: BG). Then, the first semiconductor member 61 is separated into pieces by dicing (DC) the semiconductor substrate.

また、公知の方法を用いて半導体基体上に第２半導体部材６２を構成する各種トランジスタ等の各素子や、配線等を形成する。このとき、第１半導体部材６１を搭載するための電極４７や、電極４７上にＵＢＭ４８を形成する。
ＵＢＭ４８上に低融点はんだを用いてはんだバンプ４４を形成する。
そして、半導体基体の各種素子の形成面と反対側の面（裏面）を切削（バックグラインド：ＢＧ）する。そして、半導体基体をダイシング（ＤＣ）して第２半導体部材６２を個片化する。 In addition, each element such as various transistors constituting the second semiconductor member 62, wiring, and the like are formed on the semiconductor substrate using a known method. At this time, the electrode 47 for mounting the first semiconductor member 61 and the UBM 48 are formed on the electrode 47.
Solder bumps 44 are formed on the UBM 48 using low melting point solder.
And the surface (back surface) opposite to the formation surface of various elements of the semiconductor substrate is cut (back grind: BG). Then, the semiconductor substrate is diced (DC) to divide the second semiconductor member 62 into individual pieces.

次に、Ｃｕスタッドバンプ４１をはんだバンプ４４に圧接（ボンディング）することで、第２半導体部材６２上に第１半導体部材６１をフリップチップ接続する。
フリップチップ接続後、Ｃｕスタッドバンプ４１とはんだバンプ４４との接続部を覆って、第１半導体部材６１と第２半導体部材との間にアンダーフィル（ＵＦ）樹脂３３を注入する。そして、注入したＵＦ樹脂３３を加熱して硬化（キュア）する。
以上の工程により、第２実施形態の半導体装置６０を製造することができる。
なお、Ｃｕスタッドバンプ４１の形成、はんだバンプ４４の形成、及び、フリップチップ接続は、上述の図７〜９に示す第１実施形態と同様の方法により行うことができる。 Next, the first semiconductor member 61 is flip-chip connected to the second semiconductor member 62 by pressing (bonding) the Cu stud bump 41 to the solder bump 44.
After the flip chip connection, an underfill (UF) resin 33 is injected between the first semiconductor member 61 and the second semiconductor member so as to cover the connection portion between the Cu stud bump 41 and the solder bump 44. Then, the injected UF resin 33 is heated and cured (cured).
Through the above steps, the semiconductor device 60 of the second embodiment can be manufactured.
The formation of the Cu stud bump 41, the formation of the solder bump 44, and the flip chip connection can be performed by the same method as in the first embodiment shown in FIGS.

［製造方法２：先ＵＦ樹脂プロセスフロー］
次に、上述の第２実施形態の半導体装置６０の製造方法の変形例を示す。この変形例では、ＵＦ樹脂による半導体部材同士の封止を行う工程が、上述の製造方法と異なる。
図１５に、ＵＦ樹脂封止工程を変更したプロセスフローを示す。 [Manufacturing method 2: Pre-UF resin process flow]
Next, a modification of the method for manufacturing the semiconductor device 60 of the second embodiment will be described. In this modification, the process of sealing semiconductor members with UF resin is different from the manufacturing method described above.
FIG. 15 shows a process flow in which the UF resin sealing process is changed.

図１５に示すように、公知の方法を用いて、半導体基体上に第１半導体部材６１を構成する各種トランジスタ等の各素子や、配線等を形成する。このとき、フリップチップ接続を行うための外部接続用の電極４５を形成する。
第１半導体部材６１の外部機器との接続用の電極上に、Ｃｕスタッドバンプ４１を形成する。
形成したＣｕスタッドバンプ４１上に無電解めっき法を用いて、めっき層４２を形成する。
形成したＣｕスタッドバンプ４１を覆って、第１半導体部材６１の全面にアンダーフィル（ＵＦ）樹脂３３をラミネートする。
半導体基体の各種素子の形成面と反対側の面（裏面）を切削（バックグラインド：ＢＧ）する。そして、半導体基体をダイシング（ＤＣ）して第１半導体部材６１を個片化する。 As shown in FIG. 15, each element such as various transistors constituting the first semiconductor member 61, wiring, and the like are formed on a semiconductor substrate using a known method. At this time, an external connection electrode 45 for performing flip chip connection is formed.
Cu stud bumps 41 are formed on the electrodes for connecting the first semiconductor member 61 to external devices.
A plating layer 42 is formed on the formed Cu stud bump 41 using an electroless plating method.
An underfill (UF) resin 33 is laminated on the entire surface of the first semiconductor member 61 so as to cover the formed Cu stud bump 41.
The surface (back surface) opposite to the surface on which the various elements of the semiconductor substrate are formed is cut (back grind: BG). Then, the first semiconductor member 61 is separated into pieces by dicing (DC) the semiconductor substrate.

また、公知の方法を用いて半導体基体上に第２半導体部材６２を構成する各種トランジスタ等の各素子や、配線等を形成する。このとき、第１半導体部材６１を搭載するための電極４７や、電極４７上のＵＢＭ４８を形成する。
ＵＢＭ４８上に低融点はんだを用いてはんだバンプ４４を形成する。
そして、半導体基体の各種素子の形成面と反対側の面（裏面）を切削（バックグラインド：ＢＧ）する。そして、半導体基体をダイシング（ＤＣ）して第２半導体部材６２を個片化する。 In addition, each element such as various transistors constituting the second semiconductor member 62, wiring, and the like are formed on the semiconductor substrate using a known method. At this time, the electrode 47 for mounting the first semiconductor member 61 and the UBM 48 on the electrode 47 are formed.
Solder bumps 44 are formed on the UBM 48 using low melting point solder.
And the surface (back surface) opposite to the formation surface of various elements of the semiconductor substrate is cut (back grind: BG). Then, the semiconductor substrate is diced (DC) to divide the second semiconductor member 62 into individual pieces.

次に、Ｃｕスタッドバンプ４１をはんだバンプ４４に圧接（ボンディング）することで、第２半導体部材６２上に第１半導体部材６１をフリップチップ接続する。接続後、ＵＦ樹脂を加熱して硬化する。
以上の工程により、第２実施形態の半導体装置６０を製造することができる。 Next, the first semiconductor member 61 is flip-chip connected to the second semiconductor member 62 by pressing (bonding) the Cu stud bump 41 to the solder bump 44. After the connection, the UF resin is heated and cured.
Through the above steps, the semiconductor device 60 of the second embodiment can be manufactured.

〈６．電子機器〉
［カメラ］
上述の実施形態の半導体装置は、例えば、半導体メモリや、デジタルカメラやビデオカメラ等のカメラシステム、撮像機能を有する携帯電話、又は、撮像機能を備えた他の機器等の電子機器に適用可能である。以下、電子機器の一構成例として、カメラを例に挙げ説明する。 <6. Electronics>
[camera]
The semiconductor device of the above embodiment can be applied to, for example, a semiconductor memory, a camera system such as a digital camera or a video camera, a mobile phone having an imaging function, or an electronic device such as another device having an imaging function. is there. Hereinafter, a camera will be described as an example of a configuration of the electronic device.

図１６に、静止画像又は動画を撮影することのできるビデオカメラの構成例を示す。
この例のカメラ７０は、固体撮像装置７１と、固体撮像装置７１の受光センサ部に入射光を導く光学系７２と、固体撮像装置７１及び光学系７２間に設けられたシャッタ装置７３と、固体撮像装置７１を駆動する駆動回路７４とを備える。さらに、カメラ７０は、固体撮像装置７１の出力信号を処理する信号処理回路７５を備える。 FIG. 16 shows a configuration example of a video camera that can capture still images or moving images.
The camera 70 of this example includes a solid-state imaging device 71, an optical system 72 that guides incident light to the light receiving sensor unit of the solid-state imaging device 71, a shutter device 73 provided between the solid-state imaging device 71 and the optical system 72, and a solid state And a drive circuit 74 for driving the imaging device 71. Furthermore, the camera 70 includes a signal processing circuit 75 that processes an output signal of the solid-state imaging device 71.

固体撮像装置７１は、上述のＣｕスタッドバンプを備える固体撮像素子がフリップチップ接続された半導体装置を用いて作製される。
光学系（光学レンズ）７２は、被写体からの像光（入射光）を固体撮像装置７１の撮像面（不図示）上に結像させる。これにより、固体撮像装置７１内に、一定期間、信号電荷が蓄積される。なお、光学系７２は、複数の光学レンズを含む光学レンズ群で構成してもよい。また、シャッタ装置７３は、入射光の固体撮像装置７１への光照射期間及び遮光期間を制御する。 The solid-state imaging device 71 is manufactured using a semiconductor device in which a solid-state imaging device including the above-described Cu stud bump is flip-chip connected.
The optical system (optical lens) 72 forms image light (incident light) from the subject on an imaging surface (not shown) of the solid-state imaging device 71. Thereby, signal charges are accumulated in the solid-state imaging device 71 for a certain period. The optical system 72 may be composed of an optical lens group including a plurality of optical lenses. The shutter device 73 controls the light irradiation period and the light shielding period of the incident light to the solid-state imaging device 71.

駆動回路７４は、固体撮像装置７１及びシャッタ装置７３に駆動信号を供給する。そして、駆動回路７４は、供給した駆動信号により、固体撮像装置７１の信号処理回路７５への信号出力動作、及び、シャッタ装置７３のシャッタ動作を制御する。すなわち、この例では、駆動回路７４から供給される駆動信号（タイミング信号）により、固体撮像装置７１から信号処理回路７５への信号転送動作を行う。   The drive circuit 74 supplies drive signals to the solid-state imaging device 71 and the shutter device 73. The drive circuit 74 controls the signal output operation to the signal processing circuit 75 of the solid-state imaging device 71 and the shutter operation of the shutter device 73 by the supplied drive signal. That is, in this example, a signal transfer operation from the solid-state imaging device 71 to the signal processing circuit 75 is performed by a drive signal (timing signal) supplied from the drive circuit 74.

信号処理回路７５は、固体撮像装置７１から転送された信号に対して、各種の信号処理を施す。そして、各種信号処理が施された信号（映像信号）は、メモリなどの記憶媒体（不図示）に記憶される、又は、モニタ（不図示）に出力される。   The signal processing circuit 75 performs various signal processes on the signal transferred from the solid-state imaging device 71. The signal (video signal) that has been subjected to various signal processing is stored in a storage medium (not shown) such as a memory, or is output to a monitor (not shown).

なお、本開示は以下のような構成も取ることができる。
（１）半導体部材と、前記半導体部材上に形成されているＣｕスタッドバンプと、前記Ｃｕスタッドバンプと電気的に接続するはんだバンプと、を備える半導体装置。
（２）前記Ｃｕスタッドバンプの表面に形成されためっき層を備える（１）に記載された半導体装置。
（３）前記はんだバンプが、Ｉｎ、ＳｎＢｉ、ＳｎＩｎ及びＢｉＩｎから選ばれる少なくとも１種類以上を含んで構成されている（１）又は（２）に記載された半導体装置。
（４）前記めっき層が、ＮｉとＡｕとのめっき層、又は、Ｃｏめっき層からなる（２）又は（３）に記載された半導体装置。
（５）半導体部材上にＣｕスタッドバンプを形成する工程と、前記Ｃｕスタッドバンプをはんだバンプにフリップチップ接続する工程と、を有する半導体装置の製造方法。
（６）無電解めっき法により前記Ｃｕスタッドバンプ表面にめっき層を形成する工程を有する（５）に記載の半導体装置された製造方法。
（７）フリップチップ接続時に２００℃以下で加熱する、又は、フリップチップ接続後に２００℃以下の加熱を行う（５）又は（６）に記載された半導体装置の製造方法。
（８）（１）〜（４）に記載された半導体装置と、前記半導体装置の出力信号を処理する信号処理回路と、を備える電子機器。 In addition, this indication can also take the following structures.
(1) A semiconductor device comprising a semiconductor member, a Cu stud bump formed on the semiconductor member, and a solder bump electrically connected to the Cu stud bump.
(2) The semiconductor device according to (1), comprising a plating layer formed on a surface of the Cu stud bump.
(3) The semiconductor device according to (1) or (2), wherein the solder bump includes at least one selected from In, SnBi, SnIn, and BiIn.
(4) The semiconductor device according to (2) or (3), wherein the plating layer is a plating layer of Ni and Au or a Co plating layer.
(5) A method for manufacturing a semiconductor device, comprising: a step of forming a Cu stud bump on a semiconductor member; and a step of flip-chip connecting the Cu stud bump to a solder bump.
(6) The method for manufacturing a semiconductor device according to (5), including a step of forming a plating layer on the surface of the Cu stud bump by an electroless plating method.
(7) The method for manufacturing a semiconductor device according to (5) or (6), wherein heating is performed at 200 ° C. or lower during flip-chip connection, or heating is performed at 200 ° C. or lower after flip-chip connection.
(8) An electronic apparatus comprising the semiconductor device according to (1) to (4) and a signal processing circuit that processes an output signal of the semiconductor device.

１１，２１ Ａｕスタッドバンプ、１２ Ｓｎバンプ、１３，３１ 半導体部材、１４，１７，３５，４５ 電極、１５，１９ 保護層、１６，３７ 配線基板、１８，４８ アンダーバンプメタル（ＵＢＭ）、２０ 金属間化合物（ＩＭＣ）、２２ Ｉｎバンプ、２３ ＡｕＩｎ合金、３０，６０ 半導体装置、３２ ガラス基板、３３ アンダーフィル（ＵＦ）樹脂、３４ 配線層、３６ はんだボール、３８ 光学部材、４１ Ｃｕスタッドバンプ、４２ めっき層、４３ 合金層、４４ バンプ、４７ 電極、４６，４９ 保護層、５１ Ｃｕワイヤ、５２ キャピラリ、５３ バリアメタル層、５５ フォトマスク、５４ レジスト層、６１ 第１半導体部材、６２ 第２半導体部材、６３ 電極、７０ カメラ、７１ 固体撮像装置、７２ 光学系、７３ シャッタ装置、７４ 駆動回路、７５ 信号処理回路   11, 21 Au stud bump, 12 Sn bump, 13, 31 semiconductor member, 14, 17, 35, 45 electrode, 15, 19 protective layer, 16, 37 wiring board, 18, 48 under bump metal (UBM), 20 metal Intermetallic compound (IMC), 22 In bump, 23 AuIn alloy, 30, 60 semiconductor device, 32 glass substrate, 33 underfill (UF) resin, 34 wiring layer, 36 solder ball, 38 optical member, 41 Cu stud bump, 42 Plating layer, 43 Alloy layer, 44 Bump, 47 Electrode, 46, 49 Protective layer, 51 Cu wire, 52 Capillary, 53 Barrier metal layer, 55 Photomask, 54 Resist layer, 61 First semiconductor member, 62 Second semiconductor member , 63 electrodes, 70 cameras, 71 solid-state imaging devices, 72 optical systems, 7 Shutter device, 74 driving circuit, 75 a signal processing circuit

Claims (6)

半導体部材と、
前記半導体部材上に形成されたＣｕスタッドバンプと、
前記Ｃｕスタッドバンプの表面に形成された、ＮｉとＡｕとのめっき層、又は、Ｃｏめっき層と、
前記Ｃｕスタッドバンプと電気的に接続する、Ｉｎ、ＳｎＢｉ、ＳｎＩｎ及びＢｉＩｎから選ばれる少なくとも１種類以上を含んで構成されているはんだバンプと、を備え、
前記Ｃｕスタッドバンプの先端が、前記はんだバンプ内に入り込み、
前記Ｃｕスタッドバンプと前記はんだバンプとの接触面にＣｕとはんだとの合金層が形成され、
前記Ｃｕスタッドバンプの前記はんだバンプと接触していない表面に前記めっき層を有する
半導体装置。 A semiconductor member;
And Cu stud bump made form on the semiconductor member,
A plated layer of Ni and Au, or a Co plated layer formed on the surface of the Cu stud bump;
The Cu connecting stud bump and electrically, an In, SnBi, Bei example a solder bump is configured to include at least one or more selected from SnIn and BiIn, and
The tip of the Cu stud bump enters the solder bump,
An alloy layer of Cu and solder is formed on the contact surface between the Cu stud bump and the solder bump,
The semiconductor device which has the said plating layer in the surface which is not contacting the said solder bump of the said Cu stud bump . 前記はんだバンプは、アンダーバンプメタル上に形成されている請求項１に記載の半導体装置。 The semiconductor device according to claim 1 , wherein the solder bump is formed on an under bump metal. 前記Ｃｕスタッドバンプの先端が、前記はんだバンプ内に入り込み、前記Ｃｕスタッドバンプと前記はんだバンプとの接触面にＣｕとはんだとの合金層が形成され、前記アンダーバンプメタル上に合金化していない前記はんだバンプが残存している請求項２に記載の半導体装置。 The tip of the Cu stud bump enters the solder bump, an alloy layer of Cu and solder is formed on the contact surface between the Cu stud bump and the solder bump, and is not alloyed on the under bump metal. The semiconductor device according to claim 2 , wherein solder bumps remain. 半導体部材上にキャピラリを用いてＣｕスタッドバンプを形成する工程と、
前記Ｃｕスタッドバンプの表面にＮｉとＡｕとのめっき層、又は、Ｃｏめっき層を形成する工程と、
前記Ｃｕスタッドバンプを、Ｉｎ、ＳｎＢｉ、ＳｎＩｎ及びＢｉＩｎから選ばれる少なくとも１種類以上を含んで構成されているはんだバンプにフリップチップ接続する工程と、を有し、
前記フリップチップ接続時に２００℃以下で加熱する、又は、フリップチップ接続後に２００℃以下の加熱を行い、
前記加熱により前記はんだバンプ内に入り込んだ前記Ｃｕスタッドバンプの面に、Ｃｕとはんだとの合金層を形成し、
前記Ｃｕスタッドバンプの前記はんだバンプと接触していない表面に前記めっき層を残存させる
半導体装置の製造方法。 Forming a Cu stud bump using a capillary on a semiconductor member;
Forming a plating layer of Ni and Au or a Co plating layer on the surface of the Cu stud bump;
The Cu stud bump, possess an In, SnBi, a step of flip-chip connected to the solder bumps that are configured to include at least one or more selected from SnIn and BiIn, and
Heat at 200 ° C. or lower when the flip chip is connected, or heat at 200 ° C. or lower after the flip chip connection,
An alloy layer of Cu and solder is formed on the surface of the Cu stud bump that has entered the solder bump by the heating,
A method of manufacturing a semiconductor device , wherein the plating layer is left on a surface of the Cu stud bump that is not in contact with the solder bump . 前記めっき層を無電解めっき法により形成する請求項４に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 4 , wherein the plating layer is formed by an electroless plating method. 半導体部材と、前記半導体部材上に形成されたＣｕスタッドバンプと、前記Ｃｕスタッドバンプの表面に形成された、ＮｉとＡｕとのめっき層、又は、Ｃｏめっき層と、前記Ｃｕスタッドバンプと電気的に接続する、Ｉｎ、ＳｎＢｉ、ＳｎＩｎ及びＢｉＩｎから選ばれる少なくとも１種類以上を含んで構成されているはんだバンプとからなり、前記Ｃｕスタッドバンプの先端が、前記はんだバンプ内に入り込み、前記Ｃｕスタッドバンプと前記はんだバンプとの接触面にＣｕとはんだとの合金層が形成され、前記Ｃｕスタッドバンプの前記はんだバンプと接触していない表面に前記めっき層を有する半導体装置と、
前記半導体装置の出力信号を処理する信号処理回路と、を備える
電子機器。

A semiconductor element, said semiconductor and Cu stud bump made form on member, which is formed on the surface of the Cu stud bump, plating layer of Ni and Au, or a Co plating layer, the Cu stud bump electrically to connect, an in, SnBi, Ri Do and a solder bump is configured to include at least one or more selected from SnIn and BiIn, the tip of the Cu stud bump enters into the solder bump, the Cu A semiconductor device in which an alloy layer of Cu and solder is formed on a contact surface between the stud bump and the solder bump, and the plating layer is provided on a surface of the Cu stud bump that is not in contact with the solder bump ;
An electronic device comprising: a signal processing circuit that processes an output signal of the semiconductor device.

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