JP6032118B2

JP6032118B2 - Display device

Info

Publication number: JP6032118B2
Application number: JP2013094791A
Authority: JP
Inventors: 昌美北野
Original assignee: 日亜化学工業株式会社
Priority date: 2013-04-26
Filing date: 2013-04-26
Publication date: 2016-11-24
Anticipated expiration: 2033-04-26
Also published as: JP2014215565A

Description

The present invention relates to a display device.

In the display device of the dynamic lighting control system, the light emitting element is turned on by drawing a current from the drive line during a voltage application period to the common line. However, even when current is not drawn from the drive line, if the current leaks from the common line to the drive line (parasitic capacitance), the light emitting element is erroneously turned on. In view of this, a display device that charges a parasitic capacitance on a drive line during a period in which no current is drawn from the drive line has been proposed (see Non-Patent Document 1).

"TLC5944", [online], 07 Jul 2009, Texas Instruments Incorporated. [Search April 4, 2013] Internet <URL: http://www.ti.com/lit/ds/symlink/tlc5944.pdf>

However, the conventional display device has not been designed so that the charging of the parasitic capacitance on the drive line is necessarily completed before the voltage application period to the common line starts. For this reason, in the conventional display device, current may not be drawn through the drive line even though the voltage application period to the common line has started.

In view of the above, an object of the present invention is to provide a display device designed so that the charging of the parasitic capacitance on the drive line is always completed before the voltage application period to the common line starts.

The present invention solves the above problems by the following means.

The present invention is based on a plurality of light emitting elements, a plurality of common lines and a plurality of drive lines connected to the plurality of light emitting elements, a source driver that outputs a timing signal, and a timing signal output from the source driver. And a plurality of first switches connecting the plurality of common lines to the voltage supply unit in a time-division manner with a predetermined time interval, and a plurality of second switches connecting the plurality of drive lines to the voltage supply unit. And the plurality of second switch sections open and close based on a timing signal output from the source driver, and voltage the plurality of drive lines within the predetermined time interval. The display device is connected to a supply unit.

1 is a schematic circuit diagram of a display device according to a first embodiment of the present invention. 3 is a timing chart according to the first embodiment of the present invention. It is a schematic circuit diagram of the display apparatus which concerns on 2nd Embodiment of this invention. It is a timing chart which concerns on 2nd Embodiment of this invention. It is a schematic circuit diagram of the display apparatus which concerns on 3rd Embodiment of this invention. It is a timing chart which concerns on 3rd Embodiment of this invention.

EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated, referring attached drawing.

[First Embodiment]
FIG. 1 is a schematic circuit diagram of a display device according to the first embodiment of the present invention, and FIG. 2 is a timing chart according to the first embodiment of the present invention.

As shown in FIGS. 1 and 2, the display device according to the first embodiment of the present invention includes a plurality of light emitting elements (LED1 to 4) and a plurality of common lines connected to the plurality of light emitting elements (LED1 to 4). (COM1, COM2) and a plurality of drive lines (S1, S2), a source driver that outputs a timing signal, and a plurality of common lines (COM1, COM2) that are opened and closed based on a timing signal output from the source driver. A plurality of first switches (SW11, SW12) connected to the voltage supply unit in a time-division manner with a time interval X and a plurality of second switches connecting the plurality of drive lines (S1, S2) to the voltage supply unit Unit (SW21, SW22), and a plurality of second switch units (SW21, SW22) are connected to a timing signal output from the source driver. Zui opened and closed, is a display device for connecting a plurality of drive line (S1, S2) to the voltage supply unit in a predetermined time interval X. Hereinafter, it demonstrates in order.

(Multiple light emitting elements: LEDs 1 to 4)
As the plurality of light emitting elements, for example, light emitting diodes (LEDs 1 to 4) are used as shown in FIG. The plurality of light emitting elements (LED1 to LED4) are connected to a plurality of common lines (COM1, COM2) and a plurality of drive lines (S1, S2).

(Common line, drive line: COM1, COM2, S1, S2)
For example, copper foil is used for the common lines (COM1, COM2) and the drive lines (S1, S2).

(Source driver)
For example, an IC chip is used as the source driver. The source driver outputs a timing signal to each of the plurality of first switch units (SW11, SW12).

(First switch part: SW11, SW12)
For the first switch unit (SW11, SW12), for example, a p-channel FET (Field Effect Transistor) that is closed in a period during which the gate voltage is at the L level (L period) is used. The plurality of first switch units (SW11, SW12) open and close based on the timing signal output from the source driver, and supply the voltages to the plurality of common lines (COM1, COM2) at a predetermined time interval X in a time-sharing manner. Connect to the part. Thereby, voltages are sequentially applied to the plurality of common lines (COM1, COM2). Note that “CM1” and “CM2” in FIG. 2 indicate input signals (eg, FET gate signals) of the first switch unit (SW11, SW12).

(Second switch part: SW21, SW22)
For the second switch unit (SW21, SW22), for example, a p-channel FET that closes in a period (L period) in which the gate voltage becomes L level is used. The plurality of second switch sections (SW21, SW22) are opened and closed by the output signal of the NAND circuit to which the timing signal output from the source driver is input, and the plurality of drive lines (S1, S2) within a predetermined time interval X. To the voltage supply. Thereby, the parasitic capacitances (C1, C2) on the plurality of drive lines (S1, S2) are charged. Note that “CHARGE” in FIG. 2 indicates an input signal (eg, gate signal of FET) of the second switch unit (SW21, SW22).

(Sink driver)
For example, an IC chip is used as the sink driver. The sink driver draws current from all or part of the drive lines (S1, S2). Thereby, among the light emitting elements connected to the common line to which the voltage is applied, the light emitting elements connected to the drive line into which the current is drawn are turned on.

As described above, in the display device according to the first embodiment of the present invention, the parasitic capacitances (C1, C2) on the drive lines (S1, S2) are charged based on the timing signal output from the source driver. For this reason, the charging of the parasitic capacitances (C1, C2) on the drive lines (S1, S2) is always completed before the voltage application period to the common lines (COM1, COM2) starts. Therefore, according to the first embodiment of the present invention, the period from the beginning to the end of the voltage application period to the common lines (COM1, COM2) is utilized as a period during which current can be drawn from the drive lines (S1, S2). Therefore, by setting the lighting time finely and changing the brightness of the light emitting element finely, the display device can display with rich expressive power.

When the second switch unit (SW21, SW22) is configured by an element such as the FET, the second switch unit (SW21, SW22) may open and close with a delay of several nanoseconds from the timing signal. Therefore, in this case, the plurality of drive lines (S1, S2) are connected to the voltage supply unit with a delay of about several nanoseconds from the beginning of the predetermined time interval X, and about several nanoseconds from the end of the predetermined time interval X. Disconnected after a delay. Therefore, when considered on the scale of several nanoseconds, the charging period (the end) of charging the parasitic capacitances (C1, C2) on the drive lines (S1, S2) is applied to the common lines (COM1, COM2). It will overlap for a few nanoseconds with respect to the period.

However, since this level of overlap does not have a particular adverse effect on the display device according to the first embodiment of the present invention and is in the error range, the first embodiment of the present invention has such an error. Even in such a case, it is considered that a plurality of drive lines (S1, S2) are connected to the voltage supply unit within the predetermined time interval X.

[Second Embodiment]
FIG. 3 is a schematic circuit diagram of a display device according to the second embodiment of the present invention, and FIG. 4 is a timing chart according to the second embodiment of the present invention.

As shown in FIG. 3, the display device according to the second embodiment of the present invention is different from the display device according to the first embodiment of the present invention in that it includes a switch control unit.

As shown in FIG. 4, in the display device according to the second embodiment of the present invention, the switch control unit uses the output signal of the NAND circuit to which the timing signal output from the source driver is input, at a predetermined time interval. A signal for shortening the switch closing period from X (e.g., when the above-described p-channel FET is used for the second switch unit, the signal for operating the second switch unit to be “L period = XY”) ) And output to the second switch unit (SW21, SW22).

According to the display device according to the second embodiment of the present invention, the plurality of second switch units (SW21, SW22) are opened earlier by the time interval Y than the end of the predetermined time interval X, so that the drive lines (S1, S2) The charging period (the end) of charging the upper parasitic capacitances (C1, C2) should not overlap even a few nanoseconds with respect to the voltage application period (beginning) to the common lines (COM1, COM2). Thus, the time interval Y is ensured between both periods.

Therefore, according to the second embodiment of the present invention, the period from the beginning to the end of the voltage application period to the common lines (COM1, COM2) is more utilized as a period during which current can be drawn from the drive lines (S1, S2). Therefore, by setting the lighting time more finely and changing the brightness of the light emitting element more finely, the display device can display with rich expressive power.

In the second embodiment of the present invention, for example, an FPGA (Field Programmable Gate Array) can be used as the switch control unit.

[Third Embodiment]
FIG. 5 is a schematic circuit diagram of a display device according to the third embodiment of the present invention, and FIG. 6 is a timing chart according to the third embodiment of the present invention.

As shown in FIG. 5, the display device according to the third embodiment of the present invention is different from the display device according to the second embodiment of the present invention in that the switch control unit includes a NOT circuit, a counter IC, and an OR circuit. Is different.

As shown in FIG. 6, in the display device according to the third embodiment of the present invention, the switch control unit uses the output signal of the NAND circuit to which the timing signal output from the source driver is input, at a predetermined time interval. A signal that shortens the closing period of the switch from X (e.g., when the above-described p-channel FET is used for the second switch section, the second switch section operates so that “L period = XYZ”) To be output to the second switch unit (SW21, SW22).

According to the display device according to the third embodiment of the present invention, the plurality of second switch units (SW21, SW22) are closed with a delay of the time interval Z from the start of the predetermined time interval X, and the predetermined time interval X The charging period for charging the parasitic capacitances (C1, C2) on the drive lines (S1, S2) is the voltage application period to the common lines (COM1, COM2). Even in the case of a few nanoseconds with respect to (beginning), the time interval Y is secured between both periods.

Therefore, according to the third embodiment of the present invention, the period from the beginning to the end of the voltage application period to the common lines (COM1, COM2) is more utilized as a period during which current can be drawn from the drive lines (S1, S2). Therefore, by setting the lighting time more finely and changing the brightness of the light emitting element more finely, the display device can display with rich expressive power.

Note that the form of opening and closing based on the timing signal output from the source driver includes the form of opening and closing with the output signal of the NAND circuit to which the timing signal output from the source driver is input, and the timing signal output from the source driver. In addition to the form that opens and closes with the signal generated using the output signal of the NAND circuit to which is input, the form that opens and closes with the timing signal output from the source driver itself, and the timing signal that is output from the source driver Various forms that open and close due to timing signals are included, such as forms that open and close with the generated signal.

As mentioned above, although embodiment of this invention was described, these description is related with an example of this invention, and this invention is not limited at all by these description. For example, the number of common lines and drive lines, the number of light emitting elements, the number of first switch portions and second switch portions, and the like do not limit the present invention. 1, 3, and 5 show a mode in which the common line and the drive line are connected to different voltage supply units, the common line and the drive line may be connected to the same voltage supply unit. Good.

COM1, 2 Common line S1, Drive line LED1-4 Light emitting elements SW11, 12 First switch unit SW21, 22 Second switch unit CM1, 2 Input signal CHARGE of the first switch unit CHARGE Input signal C1, 2 of the second switch unit Parasitic capacitance on drive line X Time interval Y Time interval Z Time interval

Claims

A plurality of light emitting elements, a plurality of common lines and a plurality of drive lines connected to the plurality of light emitting elements, a source driver for outputting a timing signal, and opening and closing based on a timing signal output from the source driver A plurality of first switch sections for connecting a plurality of common lines to the voltage supply section in a time-division manner at a predetermined time interval; and a plurality of second switch sections for connecting the plurality of drive lines to the voltage supply section. A display device comprising:
The plurality of second switch sections open and close based on a timing signal output from the source driver, and connect the plurality of drive lines to a voltage supply section within the predetermined time interval. .
The display device according to claim 1, wherein the plurality of second switch units are opened earlier than an end of the predetermined time interval.