JP6032024B2 - Computer system, computer system startup method, and program - Google Patents

Description

  The present invention relates to a computer system, a computer system activation method, and a program, and more particularly, to a computer system constructed by connecting a plurality of devices distributed on a network.

  A method of constructing a distributed system by distributing a CPU (Central Processing Unit) device group and an IO (Input / Output) device on a network and connecting them via a network as described in Patent Document 1 There is. Here, the CPU device group includes a CPU, a memory, and a chip set. By distributing devices on the network, devices can be freely connected. Therefore, the extensibility of the computer system can be improved by releasing the distance restriction and the frame restriction. Furthermore, Patent Document 1 discloses that an IO device belongs to a computer system realized by the CPU device group by making the group ID (identifier) of the IO device the same as the group ID of the CPU device group to which the IO device group ID is to belong. doing.

  By the way, Patent Document 2 discloses a POS (Point-of-Sale) terminal activation process. Patent Document 3 discloses a degeneration function in a multiprocessor system. The degeneration function disconnects the processor in which a hard error has occurred from the system and operates the system only with a normal processor.

JP 2012-146088 A JP 2010-231381 A JP-A-4-181435

  In a computer system constructed by connecting a plurality of devices distributed on a network, the network state between the remote device and the CPU device group to be incorporated in the computer system, the remote power state There is a possibility that the computer system may start up without incorporating the remote device due to various causes such as failure of the remote device.

  The present invention has been made to solve such problems, and a computer system constructed by connecting a plurality of devices distributed on a network is started with a system configuration not intended by the user. It is an object of the present invention to provide a computer system, a computer system activation method, and a program that can prevent the occurrence of the problem.

  A computer system according to the present invention includes a CPU side bridge and a CPU connected to a network via the CPU side bridge. An IO device is connected to the network via an IO side bridge. The CPU starts a startup operation based on the BIOS, and stops the startup operation based on a connection state between the CPU side bridge and the IO side bridge.

  In the computer system activation method according to the present invention, the CPU starts the activation operation based on the BIOS, and based on the connection state between the CPU side bridge connecting the CPU to the network and the IO side bridge connecting the IO device to the network. The CPU stops the starting operation.

  The program according to the present invention causes a computer system to execute a startup method. In the booting method, the CPU starts a booting operation based on the BIOS, and based on the connection state between the CPU side bridge connecting the CPU to the network and the IO side bridge connecting the IO device to the network, the CPU Stop the startup operation.

  According to the present invention, a computer system that can prevent a computer system constructed by connecting a plurality of devices distributed on a network from starting up with a system configuration that is not intended by the user can be prevented. An activation method and a program can be provided.

1 is a block diagram showing a configuration of a computer system according to a first exemplary embodiment. 3 is a flowchart illustrating a computer system activation method according to the first embodiment; FIG. 3 is a block diagram illustrating a configuration of a computer system according to a second embodiment. FIG. 3 is a block diagram illustrating a configuration of a CPU device group according to a second embodiment. FIG. 3 is a block diagram showing a configuration of an IO device group according to a second exemplary embodiment. FIG. 3 is a block diagram illustrating a configuration of a CPU-side bridge according to a second exemplary embodiment. It is a conceptual diagram explaining operation | movement of the bridge part of CPU side bridge | bridging. The data structure of the connection management table which a CPU side bridge | bridging has is shown. FIG. 4 is a block diagram showing a configuration of an IO side bridge according to a second exemplary embodiment; It is a conceptual diagram of a virtual computer internal bus switch formed by a CPU side bridge and an IO side bridge. FIG. 10 is a sequence diagram illustrating a computer system activation method according to the second embodiment; 6 is a flowchart illustrating processing executed by a computer system activation method according to a second exemplary embodiment;

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
Referring to FIG. 1, the computer system according to the first embodiment includes a CPU (Central Processing Unit) 111 and a CPU side bridge 114. The CPU 111 is connected to the network 3 via the CPU side bridge 114. The network 3 is, for example, the Internet. An IO (Input / Output) device 212 to be incorporated in the computer system according to the first embodiment is connected to the network 3 via the IO-side bridge 211.

  Referring to FIG. 2, the computer system activation method according to the first embodiment includes steps S10 and S20. In step S10, the CPU 111 starts an activation operation based on BIOS (Basic Input / Output System). In step S <b> 20, the CPU 111 stops the activation operation based on the connection state between the CPU side bridge 114 and the IO side bridge 211. The CPU 111 executes the computer system activation method according to the first embodiment based on the BIOS as a computer program.

  According to this embodiment, it is possible to prevent the computer system from starting up in a state where the CPU side bridge 114 and the IO side bridge 211 are not connected. Therefore, it is possible to prevent a computer system constructed by connecting the CPU 111 and the IO device 212 as a plurality of devices distributed and arranged on the network 3 from starting up with a system configuration not intended by the user.

  If the computer system is activated without the IO device 212 arranged on the remote side with respect to the CPU 111 being activated, an unnecessary restart must be performed after the activation. In this case, since the configuration information setting file of the application or OS (Operating System) used in the computer system is recorded or modified based on an unintended system configuration, a failure may occur in the computer system. According to the present embodiment, unnecessary restart and system failure can be prevented.

(Embodiment 2)
Next, a computer system and its startup method according to the second embodiment will be described. In the following, description of matters common to the first embodiment may be omitted.

  As shown in FIG. 3, the CPU device groups 11 to 19 are connected to the network 3, and the IO device groups 21 to 29 are connected to the network 3. The IO device groups 21 to 29 are connected to the CPU device group 11 via the network 3. The computer system according to the second embodiment includes a CPU device group 11, a network 3, and one or a plurality of IO device groups selected from the IO device groups 21 to 29.

  The configuration of the CPU device group 11 will be described with reference to FIG. The CPU device group 11 includes a CPU 111, a memory 112, a chip set 113, a CPU side bridge 114, and a recording device 115. The memory 112 is, for example, a RAM (Random Access Memory). The recording device 115 is, for example, a ROM (Read Only Memory) or a flash memory. The recording device 115 stores a BIOS 151, an OS 152, and an application 153. The BIOS 151, the OS 152, and the application 153 are computer programs. The input device 131 is connected to the chip set 113 via a USB (Universal Serial Bus) card 133. The display device 132 is connected to the chip set 113 via the graphic card 134. The input device 131 is, for example, a keyboard. The CPU 111, the memory 112, the chip set 113, the CPU side bridge 114, the recording device 115, the USB card 133, and the graphic card 134 are accommodated in a common housing (not shown), for example, and are supplied from a common power source (not shown). Drive power is supplied. The input device 131 and the display device 132 may be integrated to form a touch panel.

  The CPU 111 and the memory 112 are connected to each other via the memory bus 121. The CPU 111 and the chip set 113 are connected to each other via a computer internal bus 122 such as a PCIe (Peripheral Component Interconnect Express (registered trademark)) bus. The chip set 113 and the CPU side bridge 114 are connected to each other via a computer internal bus 123 such as a PCIe bus. The chip set 113 and the recording device 115 are connected to each other via a bus 124 adapted to the recording device 115. The CPU side bridge 114 and the network 3 are connected to each other via an L2 network (Layer 2 Network) 125 such as Ethernet (registered trademark). The CPU 111 is connected to the network 3 via the CPU side bridge 114.

  The CPU device group 11 may include a plurality of CPUs 111, a plurality of memories 112, a plurality of chip sets 113, a plurality of CPU-side bridges 114, and a plurality of recording devices 115. The computer internal bus 122 may be a CPU bus. The CPU 111 and the CPU side bridge 114 may be connected to each other via a computer internal bus such as a PCIe bus instead of the chip set 113. The CPU 111 and the recording device 115 may be connected to each other via a bus suitable for the recording device 115 without using the chip set 113. The configuration of the CPU device group other than the CPU device group 11 is the same as that of the CPU device group 11.

  The configuration of the IO device group 21 will be described with reference to FIG. The IO device group 21 includes an IO device 212 and an IO side bridge 211. The IO device 212 and the IO-side bridge 211 are connected to each other via a computer internal bus 213 such as a PCIe bus. The IO side bridge 211 and the network 3 are connected to each other via an L2 network 214 such as Ethernet. The IO device group 21 may include a plurality of IO-side bridges 211 and a plurality of IO devices 212. The IO device 212 is connected to the network 3 via the IO side bridge 211. The configuration of the IO device group other than the IO device group 21 is the same as that of the IO device group 21.

  The configuration of the CPU side bridge 114 will be described with reference to FIG. The CPU side bridge 114 includes a bridge unit 141 and a connection management unit 142. The bridge unit 141 bridges between the computer internal bus 123 and the L2 network 125. In order to operate as a PCIe device, the bridge unit 141 includes a configuration register 160 such as a PCI (Peripheral Component Interconnect (registered trademark)) configuration register. The connection management unit 142 includes a connection management table 170 for registering connection partners in advance.

  The operation of the bridge unit 141 will be described with reference to FIG. When transferring data from the CPU 111 side to the network 3 side, that is, from the computer internal bus 123 side to the L2 network 125 side, the bridge unit 141 adds a header 82 corresponding to the destination to the packet 81 received via the computer internal bus 123. These are encapsulated and transmitted through the L2 network 125. When transferring data from the network 3 side to the CPU 111 side, that is, from the L2 network 125 side to the computer internal bus 123 side, the bridge unit 141 removes the header 92 added to the packet 91 received via the L2 network 125. The packet 91 is transmitted through the computer internal bus 123. Here, the packets 81 and 91 are, for example, PCIe packets. The headers 82 and 92 are, for example, Ethernet frame headers.

  The connection management table 170 provided in the connection management unit 142 will be described with reference to FIG. Here, the same grouping ID (identifier) is set in each of the CPU side bridge 114 of the CPU device group 11 and the IO side bridges 211 to 251 of the IO device groups 21 to 25. Therefore, the CPU side bridge 114 can be connected to each of the IO side bridges 211 to 251. In the connection management table 170, IO side bridges 211 to 251 of the IO device groups 21 to 25 are registered. For example, when the CPU device group 11 is operating based on the OS 152, the user specifies the MAC (Media Access Control) addresses of the IO-side bridges 211 to 251 using the input device 131, and the IO-side bridges 211 to 251. Register. Alternatively, the CPU 111 automatically registers the IO side bridges 211 to 251 based on the application 153. The connection management unit 142 manages the connection between the IO side bridges 211 to 251 registered in the connection management table 170 and the CPU side bridge 114.

  Further, in the connection management table 170, whether or not a user is designated is set for each of the IO-side bridges 211 to 251. For the IO side bridges 211 to 241, the user designation is “present”. For the IO-side bridge 251, the user designation is “none”. For example, the user uses the input device 131 to set the presence / absence of user designation.

  In the connection management table 170, determination conditions for determining the interconnection between the IO side bridges 211 to 251 and the CPU side bridge 114 are registered. For example, when the user selects one of the conditions 1 to 3 using the input device 131, the selected condition is set in the connection management table 170 as a determination condition. When the condition 1 is set, the connection management unit 142 determines “connected” if at least one of the registered IO-side bridges 211 to 251 and the CPU-side bridge 114 are connected. When the condition 2 is set, the connection management unit 142 determines “connected” if all the registered IO-side bridges 211 to 251 and the CPU-side bridge 114 are connected. When the condition 3 is set, the connection management unit 142 determines “connected” if all of the IO side bridges 211 to 241 whose user designation is “present” and the CPU side bridge 114 are connected. judge. Note that determining “connected” is equivalent to determining not to stop the startup operation based on the BIOS 151.

  The configuration of the IO side bridge 211 will be described with reference to FIG. The IO-side bridge 211 includes a bridge unit 215 and a connection management unit 216. The bridge unit 215 bridges between the computer internal bus 213 and the L2 network 214. The bridge unit 215 includes a configuration register 217 such as a PCI configuration register in order to operate as a PCIe device. The connection management unit 216 includes a connection management table 218 for registering connection partners in advance.

  The operation of the bridge unit 215 is the same as the operation of the bridge unit 141. Specifically, when transferring data from the IO device 212 side to the network 3 side, that is, from the computer internal bus 213 side to the L2 network 214 side, the bridge unit 215 addresses the packet received via the computer internal bus 213 as the destination. Corresponding headers are added, and these are encapsulated and transmitted via the L2 network 214. When transferring data from the network 3 side to the IO device side 212 side, that is, from the L2 network 214 side to the computer internal bus 213 side, the bridge unit 215 removed the header added to the packet received via the L2 network 214. Thereafter, the packet is transmitted via the computer internal bus 213. Here, the packet is, for example, a PCIe packet. The header is, for example, an Ethernet frame header. Further, the operation of the connection management unit 216 is the same as the operation of the connection management unit 142.

  Referring to FIG. 10, when the CPU side bridge 114 and the IO side bridge 211 are connected to each other, the CPU side bridge 114 and the IO side bridge 211 are connected to a virtual computer internal bus switch 500 (for example, a virtual PCIe switch). ). At this time, the CPU side bridge 114 performs an operation corresponding to the upstream port of the computer internal bus switch 500, and the IO side bridge 211 performs an operation corresponding to the downstream port of the computer internal bus switch 500. . As a result, the CPU side bridge 114 and the IO side bridge 211 operate as a virtual computer internal bus switch 500. Similarly, when the IO side bridge other than the IO side bridge 211 and the CPU side bridge 114 are connected to each other, a virtual computer internal bus switch is formed.

  Next, a computer system activation method according to the second embodiment will be described. Here, as an example, a case where condition 3 is set in the connection management table 170 will be described. In this case, the device groups to be incorporated into the computer system according to the second embodiment are the CPU device group 11 and the IO device groups 21 to 24. The operation of the computer system depends on the interconnection state between the CPU side bridge 114 and the IO side bridges 211 to 241. This interconnection state depends on the power supply state of the IO device groups 21 to 24, the presence / absence of the failure of the IO device groups 21 to 24, the operating state of the network 3, and the presence / absence of the failure of the network 3. Interconnection between the CPU side bridge 114 and the IO side bridges 211 to 241 due to the power-off state of the IO device groups 21 to 24, the failure of the IO device groups 21 to 24, the non-operation of the network 3, or the failure of the network 3 May not be possible. The user can use the input device 131 and the display device 132 near the CPU device group 11.

  As illustrated in FIG. 11, the computer system activation method according to the second embodiment includes steps S <b> 30 to S <b> 80. When the user operates the power button (not shown) to power on the CPU device group 11 (S30), the CPU 111, the memory 112, the chipset 113, the CPU side bridge 114, and the recording device 115 are activated. In response to power-on, the BIOS 151 is loaded into the memory 112, and the CPU 111 starts an activation operation based on the BIOS 151 (S40). The connection management unit 142 of the CPU side bridge 114 tries to interconnect with the connection management units (for example, the connection management unit 216) of the IO side bridges 211 to 241 whose user designation is “present” (S70). The connection management unit 142 records the result of step S70 as the current interconnection state in the portion for recording the interconnection state of the configuration register 160 (S80). When connection to all of the IO-side bridges 211 to 241 for which the user designation is “present” is established, the connection management unit 142 records “connected” in the configuration register 160. If connection to at least one of the IO side bridges 211 to 241 is not possible, the connection management unit 142 records “not connected” in the configuration register 160.

  The CPU 111 sequentially checks the memory 112, the chipset 113, the CPU side bridge 114, and the recording device 115 during the startup operation based on the BIOS 151. For example, the CPU 111 accesses the CPU-side bridge 114 using PCI configuration access. More specifically, the CPU 111 writes the setting in the configuration register 160 based on the BIOS 151, accesses the current interconnection state recorded in the portion of the configuration register 160 where the interconnection state is recorded, and accesses the current mutual connection state. A connection state is acquired (S50). The CPU 111 executes processing based on the current interconnection state (S60).

  CPU111 performs step S40, S50, and S60 based on BIOS151 as a computer program. On the other hand, the CPU-side bridge 114 executes steps S70 and S80 without depending on the BIOS 151.

  As shown in FIG. 12, step S60 includes steps S61 to S68. The subsequent processing differs depending on the current interconnection state acquired from the configuration register 160 (S61). When the current interconnection state acquired from the configuration register 160 is “connected”, the CPU 111 continues the activation operation based on the BIOS 151 (S62) and activates the OS 152 (S63). If “connected” cannot be acquired as the current interconnection state in step S50, for example, if the current interconnection state acquired from the configuration register 160 is “not connected”, the CPU 111 temporarily activates the activation operation. (S64) and the user is notified of the connection failure (S65). In step S64, the CPU 111 interrupts the starting operation. In step S65, for example, the CPU 111 causes the display device 132 to display that the connection set in the connection management table 170 is not established. At this time, the CPU 111 may use a beep sound. As described above, the CPU 111 determines whether to stop the activation operation based on the determination condition registered in the connection management table 170.

  In step S66, the CPU 111 waits for a key input from the user. The user can perform key input using the input device 131 and can operate the power button to power off the CPU device group 11. If the user inputs a “continuation of activation” key, the CPU 111 resumes the activation operation (S67), and proceeds to step S62. If there is another key input from the user, the CPU 111 stops the activation operation and executes a process corresponding to the key input (S68). For example, the CPU 111 displays a system setup menu on the display device 132 or executes reboot. When the user operates the power button to power off the CPU device group 11, the CPU device group 11 including the CPU 111 stops operating.

  The case where the user is near the CPU device group 11 has been described above, but the user may be near any one of the IO device groups 21 to 24. For example, when the user is near the IO device group 21, the input device 131 used by the user is connected to one IO device 212 as a USB card, and the display device 132 used by the user is another IO device as a graphic card. Connected to device 212. In this case, when the CPU device group 11 is operating based on the OS 152 and the user selects the restart using the input device 131, the CPU device group 11 is powered on (S30).

  In the above example, the program can be stored and provided to a computer using various types of non-transitory computer readable media. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

3 Network 11-19 CPU device group 111 CPU
114 CPU side bridge 122, 123 Computer internal bus 131 Input devices 211-241 IO side bridge 212 IO device 213 Computer internal bus 151 BIOS
160 Configuration register 170 Connection management table 500 Virtual computer internal bus switch

Claims (8)

CPU side bridge,
A CPU connected to the network via the CPU side bridge,
An IO device is connected to the network via an IO side bridge,
The CPU starts a startup operation based on a BIOS, and stops the startup operation based on a connection state between the CPU side bridge and the IO side bridge. The computer system according to claim 1,
The CPU is connected to the CPU-side bridge via a first computer internal bus,
The IO device is connected to the IO-side bridge via a second computer internal bus,
The CPU side bridge and the IO side bridge form a virtual computer internal bus switch. The computer system according to claim 1 or 2,
The CPU side bridge includes a connection management table in which a plurality of IO side bridges including the IO side bridge are registered,
The CPU stops the activation operation based on a connection state between the CPU side bridge and the plurality of IO side bridges,
The connection management table registers conditions for stopping or not stopping the startup operation,
A computer system further comprising an input device for setting the condition. A computer system according to claim 3,
The input device, as the condition, does not stop the startup operation when the CPU side bridge is connected to any of the plurality of IO side bridges, or the CPU side bridge does not stop the plurality of IO sides. A computer system that selects not to stop the startup operation when connected to all of the bridges. The computer system according to claim 1 or 2,
The CPU side bridge includes a register and a connection management table in which the IO side bridge is registered,
The CPU side bridge attempts to interconnect with the IO side bridge in response to power-on to the CPU and a CPU device group including the CPU side bridge, and records the result of the interconnection attempt in the register. ,
The CPU starts the start-up operation in response to the power-on, accesses the result recorded in the register during the start-up operation, and stops the start-up operation based on the result. A computer system according to claim 3 or 4,
The CPU side bridge includes a register,
The CPU-side bridge attempts to interconnect with the plurality of IO-side bridges in response to power-on to the CPU and a CPU device group including the CPU-side bridge, and the result of the interconnection attempt is stored in the register. Record,
The CPU starts the start-up operation in response to the power-on, accesses the result recorded in the register during the start-up operation, and stops the start-up operation based on the result. CPU starts booting operation based on BIOS,
A computer system activation method in which the CPU stops the activation operation based on a connection state between a CPU side bridge that connects the CPU to a network and an IO side bridge that connects an IO device to the network. CPU starts booting operation based on BIOS,
A program that causes a computer system to execute a startup method in which the CPU stops the startup operation based on a connection state between a CPU side bridge that connects the CPU to a network and an IO side bridge that connects an IO device to the network.

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