JP6025341B2 - DC-DC converter - Google Patents

Description

  The present invention relates to a DC-DC converter, and more particularly to a DC-DC converter having an overcurrent protection function.

  In many cases, the DC-DC converter is provided with an overcurrent protection (OCP) function that turns off a switch element connected to the inductor when the inductor current exceeds a predetermined upper limit value.

  Japanese Patent Laid-Open No. 2002-84742 describes three types of methods for detecting the inductor current. The first method is a method of inserting a resistance element (sense resistor) for detecting an inductor current on the output part side or the input part side of the DC-DC converter. The second method is a method in which the on-resistance of the switch element is used instead of the sense resistor. The third method is a method of detecting a voltage drop due to the DC resistance component of the inductor.

JP 2002-84742 A

  By the way, the inductor current gradually increases when the switch element is in the on state, and gradually decreases when the switch element is in the off state. Therefore, the average value of the inductor current (equal to the actual output current) is different from the maximum value of the inductor current. The difference between the output current value and the maximum value of the inductor current changes according to the input voltage and the output voltage.

  On the other hand, the overcurrent protection described in the above document works when the detected value of the inductor current reaches the upper limit value, that is, when the maximum value of the inductor current reaches the upper limit value. Therefore, if the input voltage or the output voltage changes, there arises a problem that the level of the output current for which the overcurrent protection works changes.

  The present invention has been made in consideration of the above-mentioned problems, and its object is to provide a function that can function at a substantially constant output current level regardless of changes in the input voltage or output voltage of the DC / DC converter. A DC-DC converter having a current protection mechanism is provided.

  In one aspect, the present invention is a DC-DC converter, wherein an input node to which an input voltage is applied, a ground node to which a ground voltage is applied, an output node for outputting an output voltage, a switching element, an inductor, And a control circuit. One end of the switching element is connected to the input node or the ground node. The inductor is connected to the other end of the switching element, and the magnitude of the flowing current changes according to the switching element being turned on and off. The control circuit controls the output voltage by switching on and off of the switching element. The control circuit further performs overcurrent control for turning off the switching element when the inductor current flowing through the inductor exceeds the upper limit value. The upper limit value is larger as the absolute value of the difference between the input voltage and the output voltage is larger.

  Preferably, the DC-DC converter further includes a resistance element that is connected in series with the switching element and through which an inductor current flows via the switching element when the switching element is in an ON state. In this case, the control circuit includes an upper limit voltage generation unit that generates an upper limit voltage corresponding to the upper limit value having a magnitude corresponding to the absolute value of the difference between the input voltage and the output voltage, And a comparator for comparing the voltage. Said switching element switches to an OFF state according to the output of a comparator.

  Preferably, the control circuit includes an upper limit voltage generation unit that generates an upper limit voltage corresponding to the upper limit value having a magnitude corresponding to an absolute value of a difference between the input voltage and the output voltage, and an ON voltage and an upper limit of the switching element. And a comparator for comparing the voltage. In this case, the switching element is switched to an off state according to the output of the comparator.

  Preferably, the control circuit further includes an output voltage control unit and a logic gate. The output voltage control unit outputs a signal for switching the switching element to the OFF state by current mode control based on the voltage proportional to the inductor current and the output voltage of the DC-DC converter. Or an output voltage control part outputs the signal for switching a switching element to an OFF state by voltage mode control based on the output voltage of a DC-DC converter. The logic gate performs a logical operation of the output signal of the output voltage control unit and the output signal of the comparator, and outputs the logical operation result as a signal for turning off the switching element.

  According to the present invention, overcurrent protection can be performed at a substantially constant output current level regardless of changes in the input voltage or output voltage of the DC / DC converter.

It is a block diagram which shows the structure of the DC-DC converter 1 by Embodiment 1 of this invention. It is a figure which shows an example of a structure of the voltage control voltage source 16 of FIG. It is a figure which shows the other structural example of the voltage control voltage source 16 of FIG. As a comparative example of Embodiment 1, it is a figure which shows the signal waveform of each part of the DC-DC converter 1 of FIG. 1 when the overcurrent protection voltage Vocp is fixed fixed. FIG. 2 is a diagram illustrating signal waveforms of respective parts of the DC-DC converter 1 of FIG. 1 in the case of the first embodiment. It is a block diagram which shows the structure of the DC-DC converter 2 by the modification of Embodiment 1 of this invention. It is a block diagram which shows the structure of the DC-DC converter 3 by Embodiment 2 of this invention. It is a block diagram which shows the structure of the DC-DC converter 4 by Embodiment 3 of this invention. It is a figure which shows the signal waveform of each part of the DC-DC converter 4 of FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
[Configuration of DC-DC Converter 1]
FIG. 1 is a block diagram showing a configuration of a DC-DC converter 1 according to Embodiment 1 of the present invention.

  Referring to FIG. 1, DC-DC converter 1 includes an input node ND1, a ground node ND2, an output node ND3, a converter 10 that performs DC voltage conversion, and a control circuit 11. Input voltage Vin is applied to input node ND1, and ground voltage GND is applied to ground node ND2. A load 9 is connected between output node ND3 for outputting output voltage Vout and ground node ND2. An output current Io flows through the load 9.

(Configuration of the conversion unit 10)
The conversion unit 10 is a circuit called a so-called step-down chopper, and generates an output voltage Vout by stepping down the input DC voltage Vin. The conversion unit 10 detects a positive-channel metal oxide semiconductor (PMOS) transistor TR1, a negative-channel MOS (NMOS) transistor TR2, an inductor L, a smoothing capacitor C1, and an inductor current IL as switching elements. Resistance element R1.

  Transistors TR1 and TR2 are connected in series between input node ND1 and ground node ND2 in this order. Inductor L is connected between connection node ND4 of transistors TR1 and TR2 and output node ND3. Capacitor C1 is connected between output node ND3 and ground node ND2.

  The transistor TR2 is used as a synchronous rectifier, and is turned on / off by the control circuit 11 so as to be turned off when the transistor TR1 is turned on. A diode may be provided instead of the transistor TR2. In this case, the cathode of the diode is connected to the connection node ND4, and the anode of the diode is connected to the ground node ND2.

  Resistance element R1 is inserted between the source of transistor TR1 and input node ND1. The resistance element R1 is provided for detecting the inductor current IL flowing through the inductor L when the transistor TR1 is in the on state.

(Configuration of control circuit 11: current mode control)
The control circuit 11 generates a total voltage (denoted as Vsum) of the voltage proportional to the inductor current IL flowing through the inductor L and the slope voltage generated by the slope compensation circuit 14. Further, the control circuit 11 generates an error voltage Ve based on a difference between the voltage proportional to the output voltage Vout and a predetermined reference voltage Vref, and compares the error voltage Ve with the total voltage Vsum to switch the transistor TR1 to an off state. Perform mode control. Specifically, the control circuit 11 includes an error amplifier EAMP, a slope compensation circuit 14, an adder 13, a first comparator CMP1, an OR gate 15, an RS flip-flop FF, and a drive circuit DRV. .

  The error amplifier EAMP receives the reference voltage Vref at the + terminal, receives the output voltage Vout or the voltage obtained by dividing the output voltage Vout by resistance at the − terminal, and outputs an error voltage Ve obtained by amplifying the difference between them to the comparator CMP1. A feedback compensation circuit (phase compensation circuit) may be provided after the error amplifier EAMP, and the output of the feedback compensation circuit may be output as an error voltage Ve to the comparator CMP1.

  The slope compensation circuit 14 gradually increases from when the transistor TR1 is turned on (when the inverted output / Q is at the low level (L level)), and is 0 when the transistor TR1 is switched to the off state. A slope voltage that is reset to The generated slope voltage is output to the adder 13. In the current mode control, it is known that the inductor current becomes unstable when the current-carrying rate of the inductor exceeds 50%, and the slope voltage is used for stabilization.

  The adder 13 compares the total voltage Vsum of the voltage applied to the resistance element R1 (the potential difference between the potential Vin of the input node ND1 and the potential of the connection node ND5 between the resistance element R1 and the transistor TR1) and the slope voltage with the comparator CMP1. Output to. The voltage applied to the resistance element R1 is proportional to the inductor current IL.

  The comparator CMP1 compares the total voltage Vsum and the error voltage Ve, and outputs a signal that becomes a high level (H level) when the total voltage Vsum exceeds the error voltage Ve.

  The error amplifier EAMP, the slope compensation circuit 14, the adder 13, and the comparator CMP1 constitute an output voltage control unit 50. The output voltage control unit 50 is a signal for switching the transistor TR1 to the OFF state by current mode control based on the voltage proportional to the inductor current IL (voltage applied to the resistance element R1) and the output voltage Vout of the DC-DC converter 1. And output to the OR gate 15.

  The RS flip-flop FF receives the clock signal CLK at the set terminal S and the output of the first comparator CMP1 through the OR gate 15 at the reset terminal R. The flip-flop FF is set when the clock signal CLK is switched to H level (at the rising edge of the clock signal CLK), and is reset when the output of the first comparator CMP1 is switched to H level. become.

  Drive circuit DRV outputs a signal obtained by amplifying the inverted output / Q of flip-flop FF to the gates of transistors TR1 and TR2. Therefore, when the flip-flop FF is in the set state, the transistor TR1 is in the on state and the transistor TR2 is in the off state. When the flip-flop FF is in a reset state, the transistor TR1 is in an off state and the transistor TR2 is in an on state.

  When the flip-flop FF is switched from the set state to the reset state in order to prevent a through current through the transistors TR1 and TR2, the drive circuit DRV first turns off the transistor TR1, and then turns on the transistor TR2. It is desirable to control to turn on. When the flip-flop FF is switched from the reset state to the set state, it is desirable that the drive circuit DRV performs control so that the transistor TR2 is turned off first and then the transistor TR1 is turned on.

(Configuration of control circuit 11: overcurrent protection)
The control circuit 11 further includes a voltage control voltage source 16 and a second comparator CMP2 as a configuration for overcurrent protection (OCP).

  The voltage control voltage source 16 generates an overcurrent protection voltage Vocp corresponding to the absolute value of the voltage difference between the input voltage Vin and the output voltage Vout. The overcurrent protection voltage Vocp increases as the absolute value of the voltage difference between the input voltage Vin and the output voltage Vout increases.

  The second comparator CMP2 compares the reference potential (Vin−Vocp) for overcurrent protection with the potential of the connection node ND5 of the resistance element R1 and the transistor TR1. In the comparator CMP2, when the potential of the connection node ND5 becomes smaller than the reference potential (Vin−Vocp), that is, the voltage applied to the resistance element R1 (the value obtained by multiplying the resistance value of the resistance element R1 by the inductor current IL). When the overcurrent protection voltage Vocp is exceeded, an H level signal is output.

  The output of the second comparator CMP2 is input to the reset terminal R of the flip-flop FF via the OR gate 15. The OR gate 15 calculates the logical sum of the output of the output voltage controller 50 (that is, the output of the first comparator CMP1) and the output of the second comparator CMP2, and outputs the logical operation result to the flip-flop FF. Is output to the reset terminal R. Therefore, when the voltage applied to the resistance element R1 exceeds the overcurrent protection voltage Vocp, the flip-flop FF is reset, and the transistor TR1 is switched off.

[Configuration Example of Voltage Control Voltage Source 16]
FIG. 2 is a diagram showing an example of the configuration of the voltage control voltage source 16 of FIG. Referring to FIG. 2, voltage control voltage source 16 includes a transconductance amplifier TA and a resistance element 21.

  Transconductance amplifier TA receives output voltage Vout at the + terminal and input voltage Vin at the − terminal. A current Id proportional to the voltage difference between the positive terminal and the negative terminal is output. When the voltage input to the − terminal is larger than the voltage input to the + terminal, the transconductance amplifier TA functions as a current sink that absorbs the current Id.

  Resistance element 21 is connected between the output node of transconductance amplifier TA and input node ND1 (input voltage Vin). The voltage generated in the resistance element 21 by the current Id corresponds to the overcurrent protection voltage Vocp.

  FIG. 3 is a diagram showing another configuration example of the voltage control voltage source 16 of FIG. The voltage control voltage source 16 shown in FIG. 3 is a circuit that converts the output of the differential amplifier AMP1 based on the ground voltage GND into a voltage based on the input voltage Vin and outputs the converted voltage. Specifically, referring to FIG. 3, the voltage control voltage source 16 includes a differential amplifier AMP1, resistance elements 23 and 24, an NPN bipolar transistor 26, a PNP bipolar transistor 25, and a constant current source. 22.

  The input voltage Vin is input to the + terminal of the differential amplifier AMP1, and the output voltage Vout is input to the − terminal of the differential amplifier AMP1. Resistance element 23, bipolar transistor 26, and resistance element 24 are connected in series between input node ND1 and ground node ND2 in this order. Constant current source 22 and bipolar transistor 25 are connected in series between input node ND1 and ground node ND2 in this order. The base of the bipolar transistor 26 is connected to a connection node between the constant current source 22 and the bipolar transistor 25 (emitter of the bipolar transistor 25). An output voltage (a voltage obtained by amplifying Vin−Vout) of the differential amplifier AMP1 is input to the base of the bipolar transistor 25.

  According to the voltage control voltage source 16 having the above configuration, when the output voltage of the differential amplifier AMP1 (that is, the base voltage of the bipolar transistor 25) increases, the collector current of the bipolar transistor 25 decreases. Will increase. As a result, the collector current (that is, the current flowing through the resistance element 23) of the bipolar transistor 26 increases, so that the voltage applied to the resistance element 23 increases. A voltage applied to the resistance element 23 (that is, a potential difference between the potential Vin of the input node ND1 and the collector potential of the transistor 26) is input to the comparator CMP2.

[Effect of Embodiment 1]
Next, the effect of changing the magnitude of the overcurrent protection voltage Vocp by providing the voltage control voltage source 16 will be described.

  FIG. 4 is a diagram showing signal waveforms of respective parts of the DC-DC converter 1 of FIG. 1 when the overcurrent protection voltage Vocp is fixed as a comparative example of the first embodiment. The graph of FIG. 4 shows, sequentially from the top, the waveform of the clock signal CLK input to the flip-flop FF of FIG. 1, the waveform of the inductor current IL, and the input potential of the negative terminal of the comparator CMP2 (potential of the node ND5). .

  Here, FIG. 4A and FIG. 4B differ in the magnitude of the input voltage Vin. That is, FIG. 4A shows a case where the potential difference between the input voltage Vin and the output voltage Vout is relatively small (for example, Vin = 4V, Vout = 3V). FIG. 4B shows a case where the potential difference between the input voltage Vin and the output voltage Vout is relatively large (for example, Vin = 12V, Vout = 3V).

  Further, in the case of the comparative example shown in FIGS. 4A and 4B, the magnitude of the overcurrent protection voltage Vocp is assumed to be constant regardless of the input voltage Vin and the output voltage Vout. Assume that the flip-flop FF is reset when the voltage exceeds the overcurrent protection voltage Vocp.

Referring to FIG. 4, inductor current IL increases during a period when transistor TR1 is on (time t1-t2, time t3-t4, time t11-t12, time t13-t14). In the case of a step-down chopper, the increase rate ΔIL / Δt of the inductor current IL during these periods is expressed as follows:
ΔIL / Δt = (Vin−Vout) / Lo (1)
It is expressed as

During the period when the transistor TR1 is off (time t2 to t3, time t4 to t5, time t12 to t13, time t14 to t15), the inductor current IL decreases. In the case of a step-down chopper, the increase rate ΔIL / Δt of the inductor current IL during these periods is expressed as follows:
ΔIL / Δt = −Vout / Lo (2)
It is expressed as

  Therefore, as shown in FIGS. 4A and 4B, as the potential difference between the input voltage Vin and the output voltage Vout increases (that is, in FIG. 4B), the maximum and minimum values of the inductor current IL are increased. The difference is widened. As a result, the actual output current Io supplied to the load 9 in FIG. 1 is larger in FIG. 4 (A) and smaller in FIG. 4 (B). This means that the current level at which the overcurrent protection substantially works is different between FIG. 4 (A) and FIG. 4 (B).

  FIG. 5 is a diagram showing signal waveforms of respective parts of the DC-DC converter 1 of FIG. 1 in the case of the first embodiment. The difference from the case of FIG. 4 is that the magnitude of the overcurrent protection voltage Vocp changes depending on the input voltage Vin and the output voltage Vout. Specifically, the overcurrent protection voltage Vocp1 in the case of FIG. 5A in which the difference between the input voltage Vin and the output voltage Vout is relatively small has a relatively large difference between the input voltage Vin and the output voltage Vout. It is smaller than the overcurrent protection voltage Vocp2 in the case of (B). The other points in FIG. 5 are the same as those in the case of FIG.

  Thus, the overcurrent protection reference current level Iocp1 corresponding to the overcurrent protection voltage Vocp1 in the case of FIG. 5A is the overcurrent protection reference current corresponding to the overcurrent protection voltage Vocp2 in the case of FIG. It becomes lower than level Iocp1. As a result, the output current Io actually supplied to the load is almost the same in the case of FIG. 5A and the case of FIG. 5B. That is, the current level at which substantial overcurrent protection works is substantially the same in FIG. 5 (A) and FIG. 5 (B).

<Modification of Embodiment 1>
FIG. 6 is a block diagram showing a configuration of DC-DC converter 2 according to a modification of the first embodiment of the present invention.

  6 is different from the converter 10 of the DC-DC converter 1 of FIG. 1 in that the converter 10A of the DC-DC converter 2 of FIG. 6 does not include the resistance element R1. One input node of the adder 13 is connected to a connection node ND4 between the transistor TR1 and the inductor L. Therefore, in the case of the DC-DC converter 2 shown in FIG. 6, the inductor current IL is detected using the ON resistance of the transistor TR1 (as the ON voltage of the transistor TR1). The other points of FIG. 6 are the same as those of FIG. 1, and therefore, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  1 and 6 show a non-insulated DC-DC converter 1 as the conversion unit 10, but the present invention is also applied to an insulated DC-DC converter instead. Can do.

<Embodiment 2>
FIG. 7 is a block diagram showing a configuration of a DC-DC converter 3 according to Embodiment 2 of the present invention. The DC-DC converter 3 of FIG. 7 includes a control circuit 30 that switches on and off the transistors TR1 and TR2 by voltage mode control instead of the control circuit 11 that switches on and off the transistors TR1 and TR2 by current mode control. This is different from the DC-DC converter 1 of FIG. 7 is the same as that of FIG. 1, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

(Configuration of control circuit 30: voltage mode control)
Referring to FIG. 7, the control circuit 30 generates an error voltage Ve based on a difference between a voltage proportional to the output voltage Vout and a predetermined reference voltage Vref, and the error voltage Ve and the triangular wave generated by the triangular wave generator 31 Thus, voltage mode control for switching on and off of the transistors TR1 and TR2 is performed. Specifically, the control circuit 30 includes an error amplifier EAMP, a first comparator CMP1, a triangular wave generator 31, an inverter 32, an OR gate 15, an RS flip-flop FF, and a drive circuit DRV.

  The error amplifier EAMP receives the reference voltage Vref at the + terminal, receives the output voltage Vout or the voltage obtained by dividing the output voltage Vout by resistance at the − terminal, and outputs an error voltage Ve obtained by amplifying the difference between them to the comparator CMP1. A feedback compensation circuit (phase compensation circuit) may be provided after the error amplifier EAMP, and the output of the feedback compensation circuit may be output as an error voltage Ve to the comparator CMP1.

  The comparator CMP1 compares the error voltage Ve with the triangular wave generated by the triangular wave generator 31, outputs an H level signal when the error voltage Ve exceeds the triangular wave voltage level, and the error voltage Ve is the triangular wave voltage level. An L level signal is output in the following cases.

  The output of the comparator CMP1 is input to the set terminal S of the flip-flop FF, and is also input to the reset terminal R of the flip-flop FF via the inverter 32 and the OR gate 15. Therefore, when the output of the comparator CMP1 changes from L level to H level, the flip-flop FF is switched to the set state, and when the output of the comparator CMP1 changes from H level to L level, the flip-flop FF is in the reset state. Switch to.

  The error amplifier EAMP, the triangular wave generator 31, the comparator CMP1, and the inverter 32 constitute an output voltage control unit 51. The output voltage control unit 51 generates a signal for switching the switching element TR1 to the ON state by voltage mode control based on the output voltage Vout of the DC-DC converter 3, and outputs the signal to the set terminal S of the flip-flop FF. A signal for switching the switching element TR1 to the off state is generated and output to the OR gate 15.

  Drive circuit DRV outputs a signal obtained by amplifying the inverted output / Q of flip-flop FF to the gates of transistors TR1 and TR2. Therefore, when the flip-flop FF is in the set state, the transistor TR1 is in the on state and the transistor TR2 is in the off state. When the flip-flop FF is in a reset state, the transistor TR1 is in an off state and the transistor TR2 is in an on state.

(Configuration of control circuit 30: overcurrent protection)
The control circuit 11 further includes a voltage control voltage source 16 and a second comparator CMP2 as a configuration for overcurrent protection (OCP). Since these configurations and operations are the same as those in FIG. 1, description thereof will not be repeated.

  The OR gate 15 calculates the logical sum of the output of the output voltage control unit 51 (that is, the output of the inverter 32) and the output of the second comparator CMP2, and outputs the logical operation result to the reset terminal R of the flip-flop FF. Output to. Therefore, when the output of the first comparator CMP1 constituting the output voltage control unit 51 becomes L level or when the output of the second comparator CMP2 becomes H level, the OR gate 15 becomes H A level signal is output to the reset terminal R of the flip-flop FF. As a result, the flip-flop FF is reset and the transistor TR1 is switched off.

  In the case of voltage mode control, as in the case of current mode control, overcurrent protection can be performed at a substantially constant output current level regardless of changes in the input voltage or output voltage of the DC / DC converter.

<Embodiment 3>
FIG. 8 is a block diagram showing the configuration of the DC-DC converter 4 according to the third embodiment of the present invention. The DC-DC converter 4 of the third embodiment is different from that of the first embodiment in that a step-up chopper is provided as the conversion unit 40. Specifically, referring to FIG. 8, DC-DC converter 3 includes an input node ND1, a ground node ND2, an output node ND3, a converter 40 that performs DC voltage conversion, and a control circuit 41. Input voltage Vin is applied to input node ND1, and ground voltage GND is applied to ground node ND2. A load 9 is connected between output node ND3 for outputting output voltage Vout and ground node ND2. An output current Io flows through the load 9.

(Configuration of the conversion unit 40)
The conversion unit 40 is a circuit called a so-called boost chopper, and generates an output voltage Vout by boosting the input DC voltage Vin. The conversion unit 40 includes an NMOS transistor TR3 as a switching element, an NMOS transistor TR4 as a synchronous rectifying element, an inductor L, a smoothing capacitor C1, and a resistance element R1 for detecting the inductor current IL.

  Inductor L, transistor TR3, and resistance element R1 are connected in series between input node ND1 and ground node ND2 in this order. Transistor TR4 is connected between connection node ND4 and output node ND3 of inductor L and transistor TR3. Capacitor C1 is connected between output node ND3 and ground node ND2.

  A diode may be provided in place of the transistor TR4 as the synchronous rectifier. In this case, the anode of the diode is connected to the connection node ND4, and the cathode of the diode is connected to the output node ND3.

(Configuration of control circuit 41: current mode control)
The control circuit 41 generates a total voltage (denoted as Vsum) of the voltage proportional to the inductor current IL flowing through the inductor L and the slope voltage generated by the slope compensation circuit 14. Further, the control circuit 41 generates an error voltage Ve based on the difference between the voltage proportional to the output voltage Vout and a predetermined reference voltage Vref, and compares the error voltage Ve with the total voltage Vsum to turn off the transistor TR3. Perform mode control. Specifically, the control circuit 41 includes an error amplifier EAMP, a slope compensation circuit 14, an adder 13, a first comparator CMP1, an OR gate 15, an RS flip-flop FF, a drive circuit DRV, and an inverter. 43.

  The error amplifier EAMP receives the reference voltage Vref at the + terminal, receives the output voltage Vout or the voltage obtained by dividing the output voltage Vout by resistance at the − terminal, and outputs an error voltage Ve obtained by amplifying the difference between them to the comparator CMP1. A feedback compensation circuit (phase compensation circuit) may be provided after the error amplifier EAMP, and the output of the feedback compensation circuit may be output as an error voltage Ve to the comparator CMP1.

  The slope compensation circuit 14 gradually increases from the time when the transistor TR3 is switched on (when the output Q is at the H level), and is reset to 0 when the transistor TR3 is switched to the off state. Is generated. The generated slope voltage is output to the adder 13.

  The adder 13 outputs the total voltage Vsum of the voltage applied to the resistance element R1 (voltage proportional to the inductor current IL) and the slope voltage to the comparator CMP1.

  The comparator CMP1 compares the total voltage Vsum and the error voltage Ve, and outputs a signal that becomes H level when the total voltage Vsum exceeds the error voltage Ve.

  The error amplifier EAMP, the slope compensation circuit 14, the adder 13, and the comparator CMP1 constitute an output voltage control unit 52. The output voltage control unit 52 outputs a signal for switching off the transistor TR3 by current mode control based on the voltage proportional to the inductor current IL (voltage applied to the resistance element R1) and the output voltage Vout of the DC-DC converter 4. Generated and output to the OR gate 15.

  The RS flip-flop FF receives the clock signal CLK at the set terminal S and the output of the first comparator CMP1 through the OR gate 15 at the reset terminal R. The flip-flop FF is set when the clock signal CLK is switched to H level (at the rising edge of the clock signal CLK), and is reset when the output of the first comparator CMP1 is switched to H level. become.

  Drive circuit DRV outputs a signal obtained by amplifying output Q of flip-flop FF to the gate of transistor TR3 and to the gate of transistor TR4 via inverter 43. Therefore, when the flip-flop FF is in the set state, the transistor TR3 is in the on state and the transistor TR4 is in the off state. When the flip-flop FF is in the reset state, the transistor TR3 is in the off state and the transistor TR4 is in the on state.

(Configuration of control circuit 41: overcurrent protection)
The control circuit 41 further includes a voltage control voltage source 16 and a second comparator CMP2 as a configuration for overcurrent protection (OCP).

  The voltage control voltage source 16 generates an overcurrent protection voltage Vocp corresponding to the absolute value of the voltage difference between the input voltage Vin and the output voltage Vout. The overcurrent protection voltage Vocp increases as the absolute value of the voltage difference between the input voltage Vin and the output voltage Vout increases.

  The second comparator CMP2 compares the overcurrent protection voltage Vocp with the potential of the connection node ND5 between the resistance element R1 and the transistor TR3 (voltage applied to the resistance element R1). The comparator CMP2 outputs an H level signal when the voltage applied to the resistance element R1 (the value obtained by multiplying the inductor current IL by the resistance value of the resistance element R1) exceeds the overcurrent protection voltage Vocp.

  The output of the second comparator CMP2 is input to the reset terminal R of the flip-flop FF via the OR gate 15. The OR gate 15 calculates the logical sum of the output of the output voltage control unit 52 (that is, the output of the first comparator CMP1) and the output of the second comparator CMP2, and outputs the logical operation result to the flip-flop FF. To the reset terminal R of Therefore, when the voltage applied to the resistance element R1 exceeds the overcurrent protection voltage Vocp, the flip-flop FF is reset and the transistor TR3 is switched off.

[Effect of Embodiment 3]
FIG. 9 is a diagram showing signal waveforms at various parts of the DC-DC converter 4 of FIG.

  The graph of FIG. 9 shows, sequentially from the top, the waveform of the clock signal CLK input to the flip-flop FF of FIG. 1, the waveform of the inductor current IL, and the input potential of the positive terminal of the comparator CMP2 (the potential of the node ND5). .

  Here, the magnitude of the output voltage Vout differs between FIG. 9A and FIG. That is, FIG. 9A shows a case where the absolute value of the potential difference between the input voltage Vin and the output voltage Vout is relatively small (for example, Vin = 3V, Vout = 4V). FIG. 9B shows a case where the absolute value of the potential difference between the input voltage Vin and the output voltage Vout is relatively large (for example, Vin = 3V, Vout = 12V).

  Further, the magnitude of the overcurrent protection voltage Vocp varies depending on the input voltage Vin and the output voltage Vout. Specifically, the overcurrent protection voltage Vocp1 when the absolute value of the difference between the input voltage Vin and the output voltage Vout is relatively small (A) is compared with the absolute value of the difference between the input voltage Vin and the output voltage Vout. It is smaller than the overcurrent protection voltage Vocp2 in the case of a relatively large (B). The flip-flop FF is reset when the + terminal input (voltage applied to the resistance element R1) of the comparator CMP2 exceeds the overcurrent protection voltages Vcop1 and Vocp2.

Referring to FIG. 9, inductor current IL increases during a period when transistor TR3 is on (time t1-t2, time t3-t4, time t11-t12, time t13-t14). In the case of the step-up chopper, the increase rate ΔIL / Δt of the inductor current IL during these periods is given by assuming that the inductance value of the inductor L is Lo.
ΔIL / Δt = Vin / Lo (3)
It is expressed as

In the period during which the transistor TR3 is off (time t2 to t3, time t4 to t5, time t12 to t13, time t14 to t15), the inductor current IL decreases. In the case of the step-up chopper, the increase rate ΔIL / Δt of the inductor current IL during these periods is given by assuming that the inductance value of the inductor L is Lo.
ΔIL / Δt = (Vin−Vout) / Lo (4)
It is expressed as

  Therefore, as shown in FIGS. 9A and 9B, as the potential difference between the input voltage Vin and the output voltage Vout increases (that is, in FIG. 9B), the maximum value and the minimum value of the inductor current IL are increased. The difference is widened.

  Here, since the overcurrent protection voltage is different between FIG. 9A and FIG. 9B, the reference current level Iocp1 of the overcurrent protection corresponding to the overcurrent protection voltage Vocp1 in the case of (A) is (B) In this case, the reference current level Iocp1 of the overcurrent protection corresponding to the overcurrent protection voltage Vocp2 becomes lower. As a result, the output current Io actually supplied to the load is almost the same in the case of FIG. 9A and the case of FIG. 9B. That is, the current level at which overcurrent protection works is substantially the same in FIG. 9A and FIG. 9B.

  As described above, in the case of the step-up chopper, as in the case of the step-down chopper, overcurrent protection can be performed at a substantially constant output current level regardless of changes in the input voltage or output voltage of the DC / DC converter. .

  As described with reference to FIG. 6, also in the case of the DC-DC converter 4 of FIG. 8, the inductor current IL can be detected using the on-resistance of the NMOS transistor TR3 without providing the resistance element R1. .

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1, 2, 3, 4 DC-DC converter, 9 load, 10, 10A, 40 conversion unit, 11, 30, 41 control circuit, AMP1 differential amplifier, 13 adder, 14 slope compensation circuit, 15 OR gate, 16 Voltage control voltage source, 31 triangular wave generator, 50, 51, 52 output voltage control unit, C1 capacitor, CLK clock signal, CMP1, CMP2 comparator, DRV drive circuit, EAMP error amplifier, FF flip-flop, IL inductor current, Io Output current, L inductor, ND1 input node, ND2 ground node, ND3 output node, Vin input voltage, Vout output voltage, GND ground voltage.

Claims (3)

An input node to which an input voltage is applied;
A ground node to which a ground voltage is applied; and
An output node for outputting an output voltage;
A switching element having one end connected to the input node or the ground node;
An inductor connected to the other end of the switching element, the magnitude of the current flowing according to the switching element being turned on and off;
A control circuit for controlling the output voltage by switching on and off of the switching element,
The control circuit includes:
A comparator in which a voltage corresponding to a current flowing through the switching element is input to a first input terminal, and a reference voltage is input to a second input terminal;
A flip-flop set by a clock signal and reset by the output of the comparator;
A driver unit that turns on and off the switching element according to the output of the flip-flop,
The DC-DC converter , wherein the reference voltage is larger as an absolute value of a difference between the input voltage and the output voltage is larger . A resistance element that is connected in series with the switching element and through which a current that flows through the switching element flows when the switching element is in an ON state;
The control circuit includes:
Further comprising a reference voltage generator for generating said reference voltage having a magnitude corresponding to the absolute value of the difference between the input voltage and the output voltage,
2. The DC-DC converter according to claim 1, wherein a voltage applied to the resistance element is input to the first input terminal of the comparator as a voltage corresponding to a current flowing through the switching element . The control circuit includes:
Further comprising a reference voltage generator for generating said reference voltage having a magnitude corresponding to the absolute value of the difference between the input voltage and the output voltage,
2. The DC-DC converter according to claim 1, wherein an ON voltage of the switching element is input to the first input terminal of the comparator as a voltage corresponding to a current flowing through the switching element .

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