JP6024968B2 - Differential amplifier and signal amplifier using the same - Google Patents

Description

  The present invention relates to a high-precision and low-cost differential amplifier, and further relates to a signal amplifier using the differential amplifier.

  In a measurement system for a sensor, an industrial machine, etc. (apparatus using a wide range of signal amplifiers), a high-precision amplifier with low offset voltage and noise is required. When such measurement is performed simultaneously at multiple points, an arrayed sensor is used. However, in order to realize highly accurate measurement, it is necessary to simultaneously array the measurement unit. Therefore, there is a demand for a small and low cost amplifier with high accuracy. Here, the offset voltage is obtained by dividing the output voltage that appears slightly when the input voltage to the amplifier is 0 by the amplification factor of the amplifier. In an ideal differential amplifier, if the differential input voltage is 0, the output voltage is 0. However, in reality, a slight output voltage is generated due to variations in manufacturing characteristics. Then, the voltage that appears at the output of the amplifier at this time divided by the amplification factor of the amplifier is called an “input conversion offset voltage”. In general, this is simply called an “offset voltage”. Will follow this example.

  In the prior art, for example, in Patent Document 1, the amplifier includes a plurality of parallel paths, and weighting is performed in each path, and each output is added or subtracted. These weighting coefficients are adjusted so that the influence of the offset voltage is minimized in the output. The adjustment is appropriately performed by an adjustment unit including a sample and hold circuit and an analog / digital converter (hereinafter may be referred to as an A / D converter).

  In Patent Document 2, a digital / analog converter (hereinafter, sometimes referred to as a D / A converter) having a constant adjustment step size is used, and two paths (positive and negative) of the differential amplifier are used. ) The bias current is adjusted so that the offset voltage is reduced for each.

  Further, in Non-Patent Document 1, in order to reduce the influence of the offset voltage, the error caused by the offset voltage is integrated at the output and negatively fed back to the input side to dynamically reduce the influence of the error caused by the offset voltage. doing.

  On the other hand, in Non-Patent Document 2, bandpass filters are provided in the input stage and the output stage, and double-correlation sampling (Correlated Double Sampling: CDS) technology is applied to reduce high-frequency noise caused by the offset voltage. doing.

WO2006 / 093177 JP 2009-278231 A

R. Wu, et al. , IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3232-3243 M.M. Belloni, et al. , IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2521-2529

  The background art as described above can effectively reduce the error due to the offset voltage, but in any case, an A / D converter, a D / A converter, and an integration are included in the detection unit for reducing the error. And a mounting area becomes large.

  Moreover, the following subjects can be raised in each of the documents cited as the prior art documents. In the technique described in Patent Document 1, a sample hold circuit and an A / D converter for determining an optimum coefficient for each path are necessary as an adjustment unit, and a resistance element and a switch for adjusting the coefficient are provided. Since many must be mounted, the entire area is increased and the cost is increased.

  The technique described in Patent Document 2 requires a D / A converter for adjusting the current in each of the two paths of the differential amplifier, which increases power consumption and circuit area and increases costs.

  In the technique described in Non-Patent Document 1, power consumption, noise, and circuit area increase due to the sub-blocks used for error reduction due to the offset voltage.

  In the technique described in Non-Patent Document 2, a large capacity is required to configure a bandpass filter, which causes an increase in circuit area.

  The present invention solves the above-mentioned problems related to power and cost in a differential amplifier.

  Therefore, the present inventors have developed the present invention as a result of researches to solve the above problems.

  That is, the differential amplifier of the present invention includes an amplified signal output unit, a detection unit, a reference voltage changeover switch, and a control unit, and the amplified signal output unit is connected to two input signal paths of a positive electrode and a negative electrode. An amplifier group composed of a plurality of amplifiers connected in parallel to each other, and an input to a part or all of the amplifier group are selectively connected to function as either the positive side or the negative side. And a switch group that selectively switches between connection and disconnection, and outputs the positive and negative amplified signals by the amplifier group as a single unit, and the detection unit is output from the amplified signal output unit The offset voltage is detected, and the reference voltage switch switches the input signal input to the amplified signal output unit to the reference voltage. The control unit outputs an enable signal for switching the reference voltage switching switch and a control signal for controlling switching of the switch group, and stores an offset voltage value detected by the detection unit, The control unit selects a plurality of combinations having the same number of positive and negative sides among a plurality of amplifiers constituting the amplifier group, and sequentially switches the switch group so as to correspond to each combination by the control signal. The switch group combination when the offset voltage detected by the detection unit is minimized is determined and maintained.

  With the above configuration, a normal differential amplifier has two input signal paths of a positive electrode (Vip) and a negative electrode (Vim). Among a plurality of amplifiers connected in parallel to this input signal path By selecting the same number of amplifiers on the positive side and the negative side, the amplifier group can be divided into two sets, and the amplifier group divided into the two sets can minimize the overall offset voltage. Can do. In other words, each amplifier has its own offset voltage, and these have manufacturing variations according to a certain standard deviation (average 0). The component and the negative difference component are canceled out to reduce the offset voltage difference component as a whole. By setting the number of amplifiers constituting the amplifier group to an even number (for example, n), half of the amplifiers can be selected as the positive side, and the remaining can be selected as the negative side. It is possible to reduce the influence of the offset voltage by dividing into two and selecting a combination having the smallest difference component from the combinations. This method is an invention characterized in that it uses the manufacturing statistical variation of the differential amplifier circuit to reduce its own influence.

  In the above invention, the amplified signal output unit includes an even number of paths formed by branching the input signal path, and the even number of amplifiers are individually provided for the even number of paths. The switch group selectively switches the input / output before and after the even number of amplifiers to either the positive side or the negative side, and the control signal for controlling the switching of the switch group by the control unit is The even number of paths may be a signal for switching the switch group so as to form two equal numbers of paths.

  In the above configuration, the two input signal paths of the positive electrode (Vip) and the negative electrode (Vim) are divided into an even number of paths (for example, n paths) in advance, and each is combined into two sets of paths. Thus, the offset voltage is reduced. Each amplifier connected to the path divided into n has a unique offset voltage as described above, and by combining these, the difference component of the offset voltage as a whole can be reduced. It is.

  The above-mentioned even number of amplifiers or paths may be selected in advance by changing the connection between the positive side and the negative side and selecting a combination in which the numbers connected to the positive side and the negative side are the same. It may be configured to determine what should be connected to the negative side and select a combination within that range.

  Further, the amplifier group provided in the amplified signal output unit is not limited to a configuration including only a plurality of amplifiers connected in parallel to the input signal path, and may be configured to be connected in a plurality of stages. . For example, the first stage can be constituted by a plurality of amplifiers, and the second stage can be constituted by a single amplifier. With such a multi-stage connection, the offset voltage of the second stage amplifier can be canceled by the offset voltage of the first stage amplifier group, and the amplified signal can be selected by selecting the combination of the first stage amplifier group. The offset voltage of the entire output unit can be minimized. In this case, the first stage may be composed of an even number of transistors, and the second stage may be a single (or a small number) of amplifiers. Even in the case where a transistor is used in the first stage, as in the case where the plurality of amplifiers are used, manufacturing variations of the transistor can be used.

  Further, when a plurality of amplifiers constituting an amplifier group are divided into two groups of a positive side and a negative side in advance, when determining the combination of the two amplifier groups, the power supply for each amplifier (in the case of a transistor) The tail current source) may be connected or disconnected by a switch.

  As the configuration of the control unit in the differential amplifier of each configuration described above, a controller that outputs a sign change signal and a minimum value update signal, a lookup table that generates a combination pattern of the amplifier or transistor and outputs a lookup signal; A register that stores the combination that minimizes the offset voltage output from the detector; a multiplexer that selects whether to invert the lookup signal based on a sign change signal output from the controller; A switch for allocating either a combination output from the multiplexer or a combination stored in the register to a control signal for controlling switching of the switch may be provided. With such a configuration, it is possible to output an appropriate control signal for the switch of the amplified signal output unit.

  In addition, as a configuration of the detection unit in the differential amplifier of each configuration described above, the configuration includes a single comparator, and the controller outputs the sign change signal and the minimum value update signal according to a value output from the comparator. Can be configured to determine. With such a configuration, the minimum value can be determined while referring to the offset voltage output from the detection unit.

  Further, in each of the above configurations, the control unit includes a clock generator, and the detection unit is connected in series with the sampling capacitor for accumulating the sampling capacity, the preamplifier connected in series with the sampling capacitor, and the preamplifier. A latched comparator, a first changeover switch for connecting or disconnecting the signal from the amplified signal output unit to the sampling capacitor, and a reference voltage for connecting or disconnecting the sampling voltage to the sampling capacitor. A second changeover switch and a third changeover switch for short-circuiting or disconnecting the input and output of the preamplifier, the first, second and third changeover switches being output from the clock generator Can be controlled by the clock signal That. With the above configuration, the detector can be provided with a sample hold function and an auto zero function, and each switch in the detection unit can be operated by the control unit.

  In each of the above configurations, the control signal for controlling the switching of the switch by the control unit may include a signal for repeating the connection and disconnection inversion operations in accordance with the chopping frequency together with the signal for the switch. . Thereby, low frequency noise including an offset voltage can be modulated to a high frequency and separated from the frequency of the desired signal.

  The present invention according to the signal amplifying apparatus uses any one of the differential amplifiers described above, and includes at least one signal output unit that outputs an analog signal to the amplified signal output unit, and at least one signal output unit. An analog-to-digital converter that has a comparator and converts the signal amplified by the amplified signal output unit into a digital signal, and the detection unit uses the comparator of the analog-to-digital converter, The control unit detects an offset voltage based on the signal output from the analog / digital converter, and the control unit outputs a combination that minimizes the offset voltage based on the signal output from the detection unit to the amplified signal output unit. It is what is characterized by.

  According to the above configuration, the offset voltage in the amplified signal output unit can be set to the minimum, and the offset voltage output from the amplified signal output unit is determined using the comparator of the A / D converter. It is possible to eliminate the redundancy between the control unit and the detection unit.

  Further, the present invention related to a signal amplifying apparatus is a signal amplifying apparatus that uses any one of the differential amplifiers described above to individually amplify signals output from a plurality of devices, and is output from the plurality of devices. A plurality of amplified signal output units that individually input signals, a plurality of detection units that individually detect outputs of the respective amplified signal output units, and a plurality of the amplified signal output units and detection units, And a single control unit that individually controls the amplified signal output unit while selecting the amplified signal output unit and the detection unit.

  According to the above configuration, when processing signals output from a plurality of sensor devices are processed by individual amplified signal output units, individual offset voltages are set to a minimum by a common (single) control unit. Therefore, an analog front-end array can be realized at a low cost. Note that a register may be provided for each amplified signal output unit in order to hold a combination that minimizes the offset voltage in each amplified signal output unit.

  According to the differential amplifier of the present invention, a detection unit for obtaining a combination that minimizes the offset voltage can be realized with a single comparator and a simple digital circuit. The cost can be reduced. Also, a signal amplifying apparatus using this differential amplifier can be realized with a small area and low cost.

It is explanatory drawing which shows the 1st Example of this invention concerning a differential amplifier. It is explanatory drawing which shows the operation | movement aspect of the 1st Example of this invention concerning a differential amplifier. It is explanatory drawing which shows the 2nd Example of this invention concerning a differential amplifier. It is explanatory drawing which shows the 3rd Example of this invention concerning a differential amplifier. It is a flowchart which shows operation | movement of the 3rd Example of this invention concerning a differential amplifier. It is explanatory drawing which shows the 4th Example of this invention concerning a differential amplifier. It is explanatory drawing which shows the operation | movement aspect of the detector in the 4th Example of this invention concerning a differential amplifier. It is a timing chart which shows the example of operation | movement of the whole 4th Example of this invention concerning a differential amplifier. It is explanatory drawing which shows the amplified signal output part in the 5th Example of this invention concerning a differential amplifier. It is a graph which shows the frequency characteristic in the calibration in the 5th Example of this invention concerning a differential amplifier. It is explanatory drawing which shows the 6th Example of this invention concerning a differential amplifier. It is explanatory drawing which shows the 7th Example of this invention concerning a differential amplifier. It is explanatory drawing which shows the wireless sensor node which is an Example of this invention concerning a signal amplifier. It is explanatory drawing which shows the analog front end array which is an Example of this invention concerning a signal amplifier.

Hereinafter, the details of the present invention will be described with reference to the drawings. In addition, although several Example is listed as a form for implementing this invention, it does not intend that this invention is limited to these Examples.
[Embodiment of the invention concerning a differential amplifier]

FIG. 1 is a diagram showing the overall configuration of a differential amplifier with a reduced offset voltage according to the present invention. The differential amplifier 100 shown in the figure is roughly divided to amplify the differential input signals Vip and Vim with a gain Av, and the output signal Vout is multiplied by the gain of the differential input signal, that is, Vout = Av (Vip -Vim), an amplification signal output unit 101 for obtaining an offset voltage, a detection unit 102 for detecting an offset voltage, and individual amplifiers 111a, 111b,. , 111n is configured by a control unit 103 for determining the combination.

  The amplified signal output unit 101 is composed of an even number of n paths, and each of the amplifiers 111a, 111b,..., 111n (n equal to the number of paths) having different offset voltages due to manufacturing variations. Are connected in parallel. Having different offset voltages due to manufacturing variations means that each of the amplifiers 111a to 111n has a unique offset voltage, and these have manufacturing variations according to a certain standard deviation (average 0). Means that Note that the offset voltage unique to each of the amplifiers 111a to 111n is Vos. 1, Vos. 2, ..., Vos. Shown as n. The inputs (Vip, Vim) of the n amplifiers 111a to 111n are connected to the common input terminals 104a and 104b via the switches 105a and 105b, respectively, and outputs (Vop) of the n amplifiers 111a to 111n. , Vom) are connected to common output terminals 106a and 106b, respectively.

In addition, each of the amplifiers 111a to 111n includes switches 113a, 112b,. , 113b,..., 113n are interposed, and switches 114a, 114b,. , 115n are interposed. These switches 112a to 112n, 113a to 113n, 114a to 114n, 115a to 115n are all determined by a control signal (switching signal (sel)) obtained from the control unit 103. For example, when a positive-side signal is input to the first amplifier 111a (when setting a positive-side path), the positive-side switch 112a connected to the first amplifier 111a is set in a connected state, and the negative-side signal is input. In order to connect the first amplifier 111a to the positive input terminal 104a and to output the same positive side on the output side, the switch 113a on the positive side is turned off. The corresponding bit of the switching signal (sel) is set so that the negative switch 115a is disconnected and the output is connected to the positive output terminal 106a. In this way, the differential input Vop-Vom is observed by controlling the amplifiers 111a to 111n connected to each path to be connected to either the positive side or the negative side according to the bit arrangement of the switching signal (sel). In such a case, a combination that reduces the amplified offset voltage can be found. Such an optimal bit arrangement of the switching signal (sel) that minimizes the offset voltage is stored in a memory (register) provided in the control unit 103. Note that the number of bits of the switching signal (sel) is the same as the number of divided paths. That is, for example, when there are 12 amplifiers 111a to 111n, the number of bits is divided into 12 paths, and a corresponding bit is set for each. Is done. In addition, when the positive side and the negative side are divided into the same number and all the amplifiers 111a to 111n are used, of the n bits of the switching signal (sel), n / 2 bits are 0, and the remaining n / 2 bits are Therefore, the number of combinations in the case of n paths is _n C _{n / 2} . For example, in the case of 12 passes, there are 924 ways. A combination showing the smallest offset voltage is selected from these combinations. However, in the above example, there is no combination that has 5 on the positive side and 7 on the negative side. This is because the differential input is out of balance and does not function properly.

A method for searching for a combination that minimizes the offset voltage (hereinafter referred to as calibration) is as follows. First, the calibration enable signal (ENBL) is turned on (hereinafter, this state may be referred to as “High state”, “High state”, or simply “H”), thereby enabling input (Vip, Vim). ) Switches 105 a and 105 b provided on the side are electrically disconnected from the amplified signal output unit 101, while the switches 107 a and 107 b interposed between the arbitrary reference voltage (Vref) and the amplified signal output unit 101 are operated. A reference voltage is input to the differential amplifier 101. In this state, when the offset voltage is 0, the difference signal is 0, so the output voltage (Vout) is also 0. Therefore, it is possible to estimate the offset voltage at the output voltage (Vout) by fixing both differential inputs to the same reference voltage (Vref). In this calibration mode, for the _n C _{n / 2} combinations, the combination pattern by the switching signal (sel) is sequentially set, the offset voltage in the output voltage (Vout) for each pattern is detected by the detection unit, and amplified. The signal output unit 101 searches for a combination that minimizes the offset voltage. A combination of the detected offset voltage value and the switching signal (sel) is stored in the amplified signal output unit 101, and a minimum value is shown by performing these operations according to the switching signal (sel) of all combinations. The combination of offset voltages is determined.

  On the other hand, when the input signal (Vip, Vim) is amplified after calibration is completed (offset voltage minimization), the calibration enable signal (Enbl) is turned off (hereinafter referred to as “Low state”). In this case, the input to the amplified signal output unit 101 is restored from the reference voltage (Vref) to the input signal (Vip, Vim). In the meantime (Enbl = L), as shown in FIG. 2, the amplifiers 111a to 111n connected to the n paths are divided into the same number on the positive side and the negative side, and the n paths are also divided into two sets of paths ( (Positive side and negative side). The switching signal (sel), which is the output of the control unit 103 at this time, modulates low frequency noise including an offset voltage to a high frequency by repeatedly inverting the connection and disconnection according to the chopping frequency (fch). And since it can isolate | separate from the frequency of a desired signal, highly accurate signal amplification is attained. A technique for performing such modulation is called a chopper stabilization technique and is a general technique. The offset voltage reduction method of the present invention is highly compatible with such a chopper stabilization technique. In FIG. 2, the enable switch and the control unit are omitted.

  Here, the operation principle of the chopper stabilization technique will be briefly described. First, when the chopper stabilization technique is not applied, the offset voltage and the low frequency noise exist in the same frequency band as the desired input signal (Vip-Vim), which are amplified together. Accurate signal amplification is impossible. On the other hand, when the input signal is modulated before the signal amplification by the chopping frequency (fch), the input signal is modulated to a frequency band different from the offset voltage, and these are amplified, and then the chopping frequency (fch) is changed. Thus, by demodulating, an output signal (Vout) in a state separated from the offset voltage is obtained. Note that the offset voltage of the differential amplifier originally becomes high frequency noise at the chopping frequency (fch), but by reducing the offset voltage by the method of the present invention, the high frequency noise in the output voltage is also reduced.

  As described above, according to the configuration shown in the first embodiment, amplified signal output is performed using variations in inherent offset voltages of a plurality (even number) of amplifiers 111a to 111n provided in the amplified signal output unit 101. The offset voltage in the entire unit 101 can be eliminated. In other words, the individual amplifiers 111a to 111n do not have intentional differences in design characteristics (electrical characteristics), and are inevitably produced in the manufacture of a plurality of amplifiers 111a to 111n that are identical in design. An offset voltage that uses variation in offset voltage, and the same number of amplifiers on the positive side and the negative side among the plurality of amplifiers 111a to 111n is divided into two sets of amplifier groups, thereby causing an offset that varies on the positive side. By offsetting the voltage and the offset voltage that varies on the negative side, the offset voltage is reduced as a whole. And since the magnitude | size of the separate offset voltage which each amplifier 111a-111n has differs, the degree of the dispersion | variation on a positive side and a negative side also changes by changing those combinations, and both are balanced. By finding the combination, the overall offset voltage can be minimized. This is the central idea of the present invention. The effect of the present invention can be realized by a simple detection unit 102 and control unit (digital circuit) 103 as a calibration mechanism, and a large-scale circuit system for calibration as in the prior art can be realized. This is in that a differential amplifier with a low offset voltage can be realized at low power and low cost.

  FIG. 3 is a diagram showing an outline of the second embodiment. As shown in this figure, in the second embodiment, amplifier groups (a plurality of amplifiers 111a to 111n) provided in the amplified signal output unit 101 of the first embodiment (FIG. 1) are replaced with first-stage amplifier groups 211a to 211n. This is an embodiment in the case of being configured with the second stage amplifier 216. The first-stage amplifier groups 211a to 211n are each realized by a single transistor. Here, in contrast to FIG. 1, the gate terminals of the respective transistors 211a to 211n are connected to the input side, the drain terminals are connected to the output side, and a switch group is provided for distributing to the positive side and the negative side. . The source terminals are all common and are connected to the tail current source (IT). On the output side, there is an amplifier 216 at the next stage, which is operated and amplified to output an output signal (Vout). The detection unit 202 and the control unit 203 are the same as those in the first embodiment (FIG. 1).

  Also in this embodiment, variation in electrical characteristics in manufacturing is used. The same number is selected from the transistors 211a to 211n on the positive side and the negative side, and the combination of these is changed to change the second. The offset voltage as a whole of the amplified signal output unit 201 including the stage amplifier 216 can be reduced. As an effect of this configuration, in general, the offset voltage of the differential amplifier is often caused by variations in the characteristics of the transistors in the input stage.By making the circuit block to be divided and paralleled as small as possible by a single transistor, The circuit area can be reduced, and the cost can be reduced.

  The outputs (Vout) in Examples 1 and 2 (FIGS. 1 and 3) both take the form of a single output (single end output), but these are differential outputs (differential end outputs). I agree.

FIG. 4 is a diagram showing an outline of the third embodiment. The third embodiment shows an example in which the detection unit 102 and the control unit 103 of the differential amplifier 100 in the above-described first embodiment are embodied. That is, as shown in this figure, the third embodiment uses one comparator 321 as the detection unit 302. The control unit 303 includes a controller 331, a memory (register) 332, a lookup table 333, and a multiplexer 334. The switch 335 and the inverter 336 are provided. Here, the lookup table 333 is a functional block that generates all patterns that can be taken by the control signal (switching signal (SEL)). As described in the first embodiment, the switches 112a to 112n, 113a to 113n, The number of bits for switching (H and L) between 114a to 114n and 115a to 115n is always the same number. As an example, there are _n C _{n / 2} patterns for the division number n. The controller 331 of the control unit 303 receives an input of the determination result from the comparator 321 of the detection unit 302, outputs a sign change signal (POL_chng) to the multiplexer 334 according to the result, and a minimum value update signal (MinReg_update). Is output to the memory (register) 332. The memory (register) 332 holds the minimum value of the offset voltage together with the bit pattern output to the switching signal (SEL). The configuration of the differential amplifier 101 displayed as a single amplifier in the figure is the same as that in the first embodiment (FIG. 1), but the configuration is omitted for the sake of space.

  The operation at the time of calibration (ENBL = H) in the embodiment of FIG. 4 is to process a signal according to the flowchart of FIG. First, the initial value of the bit arrangement pattern is given to the switching signal (SEL) from the lookup table 333 (S1), and the amplified signal output unit 101 amplifies the offset voltage for this combination with an arbitrary gain. The polarity of Vout = Vop−Vom at this time is confirmed through the determination of the comparator 302 (S2). If this is negative, the sign change signal output (POL_chng) of the controller 331 outputs the H state (S3). In response to this, the multiplexer 334 substitutes the signal of the all bit inversion of the output signal of the lookup table 333 into SEL (S4). If Vout is positive, it is not necessary to substitute the inverted signal for SEL.

  At this time, the amplified offset voltage detected by the detector 302 is sampled as an A voltage Vos, a (Vos, a> 0) (S5). The memory (register) 332 is provided to store the combination pattern of the switching signal (SEL) that minimizes the offset voltage, stores the signal output from the multiplexer 334, and the current combination stored there. Is substituted into SEL (S6). The amplified offset voltage for the combination at this time is sampled as B voltage Vos, b (Vos, b> 0) (S7), and the previous A voltage Vos, a and B voltage Vos, b are compared (S8). ).

  In the above comparison, if the A voltage Vos, a is a value smaller than the B voltage Vos, b (Vos, a <Vos, b), the previous combination output from the lookup table 333 is set to the minimum offset voltage. The combination pattern is substituted into the memory (register) 332 (S9, S12). However, at this time, the state of the sign change signal (POL_chng) is confirmed (S10), and when the state of the sign change signal is H, the pattern in which the output signal of the lookup table 333 is inverted for all bits. Is substituted into the memory (register) 332 as a combination pattern that minimizes the offset voltage (S11). By repeating the above operation for all patterns that can be output by the lookup table 333 (S13), it is possible to search for a combination pattern of the switching signal (SEL) that truly minimizes the offset voltage.

  The feature of this embodiment is that the calibration can be realized by using a single comparator without using a large-scale circuit such as an A / D converter as the detection unit 302, so that the area can be reduced, that is, the cost can be reduced. Is possible.

  FIG. 6 is a diagram showing an outline of the fourth embodiment. In the fourth embodiment, the detection unit 302 and the control unit 303 in the third embodiment described above are further embodied. That is, as shown in this figure, the fourth embodiment has a configuration in which the detection unit 402 has a sample hold function and an auto zero function, and the first switch 422a provided continuously in the amplified signal output unit 101. , 422b, second switches 423a and 423b provided continuously to the reference voltage (Vref), sampling capacitors 424a and 424b for accumulating sampling capacitors, a preamplifier 425, and a connection between the input and output of the preamplifier 425 Third switches 426a and 426b, and a latched comparator 421 is provided as a comparator. The control unit 403 is provided with a clock generator 436.

  The first switches 422a and 422b are switches that connect the terminals of the capacitors 424a and 424b and the amplified signal output unit 101, and are controlled by a clock (SMPL) generated by the clock generator 436 of the control unit 403. The switches 423a and 423b connect the same terminals of the sampling capacitors 424a and 424b and the reference voltage (Vref), and are similarly controlled by a clock (POL_chck) generated by the clock generator 436 of the control unit 403. Is. The other terminals of the sampling capacitors 424a and 424b are connected to the input terminal of the preamplifier 425. The third switches 426a and 426b for connecting the input and output of the preamplifier 425 are switches for short-circuiting the input and output of the preamplifier 425, and are generated by a clock (AZ) generated by the clock generator 436 of the control unit 403. It is controlled. Further, the output of the preamplifier 425 and the input of the latched comparator 421 are connected to each other and controlled by the clock (LATCH) generated by the clock generator 436 of the control unit 403, and the output (compo) of the latched comparator 421. Is the output of the detection unit 402.

  Here, the search for the combination pattern that minimizes the offset voltage by the detection unit 402 and the control unit 403 is performed according to the flowchart of FIG. 5, and the operation is shown in FIG. First, as shown in FIG. 7A, the output (Vout) of the amplified signal output unit 101 when the output (LUTout) of the lookup table according to a certain combination pattern is set to the switching signal (SEL) To do. The switches 422a and 422b and the switches 426a and 426b provided between the input and output of the preamplifier 425 that are continuously provided in the amplified signal output unit 101 are connected by setting the clock (SMPL, AZ) to a high state. As a result, the offset voltage amplified by the capacitors 424a and 424b is sampled. Next, as shown in FIG. 5B, the switches 423a and 423b provided continuously to the reference voltage (Vref) are switched by the clock (POL_chck) so as to connect one terminal of the capacitors 424a and 424b, and the preamplifier The switches 426a and 426b between the input and output of 425 open the preamplifier 425 by setting the clock (AZ) to the low state, and perform the comparison operation of the latched comparator 421 by setting the clock (LATCH) to the high state. Based on the output result of the comparator 421, it is determined whether the output (Vout) of the amplified signal output unit 101 is positive or negative.

  In response to this result, as shown in the flowchart of FIG. 5, the codes are switched by inverting all bit patterns to be substituted into the switching signal (SEL) as appropriate, and sampling is performed again as shown in FIG. 7C. (The connection is the same as in FIG. 2A). Next, according to FIG. 5, the combination pattern that minimizes the current offset voltage stored in the memory (register) is substituted into the switching signal (SEL), and as shown in FIG. Is set to the high state, the clock (AZ) is set to the low state, and the comparison is performed so that the combination pattern output from the current look-up table and the combination pattern that minimizes the offset voltage stored in the memory (register) And the memory (register) is updated / non-updated as appropriate.

  An example of a time chart representing the above operation is shown in FIG. In addition, (a)-(d) described in the upper column in FIG. 8 is made to correspond to the state of FIG. 7 (a)-(d), respectively, and is repeated hereafter.

  FIG. 9 is a diagram illustrating the fifth embodiment. The fifth embodiment is for setting the gain during calibration to an arbitrarily high gain. In the fourth embodiment (FIG. 6), a smaller offset voltage is detected by the detector 402 while searching for a combination that provides the minimum offset voltage using the operation procedure during calibration (FIGS. 7 and 8). In order to detect, it is necessary to increase the gain of the amplified signal output unit 101. However, in general, the higher the gain is set, the narrower the frequency band that can be amplified (gain × band is constant), and it becomes impossible to follow the speed of the clock frequency at which the control unit 403 operates. This means that the follow-up speed of Vout as shown in the timing chart of FIG. 8 is reduced, and much time is required for calibration. The band in the amplified signal output unit 101 is limited by the capacitance (Cc) of the phase compensation capacitor, which is calculated from the conditions for stable operation when a 1 × buffer circuit is configured by feedback.

  Therefore, as shown in FIG. 9, during calibration, feedback using resistors R1 and R2 is applied so as to set an arbitrary high gain (for example, about 1000 times, that is, about 60 dB), and even stable operation is performed in this state. It is only necessary to reduce the capacitance (Cc) of the phase compensation capacitors C1 and C2, thereby extending the band. Specifically, as shown in the figure, phase compensation capacitors C1 and C2 are connected in parallel, and one of the capacitors C2 is provided with a switch Swcc. The switch Swcc is connected (ie, disconnected during calibration) by an inverted signal of a signal (Enbl) that is in a high state during calibration. When the switch Swcc is disconnected, the capacitance Cc of the phase compensation capacitor (= the capacitance of C1 + the capacitance of C2) is reduced to one capacitor C1, and an arbitrary high gain setting is used for feedback. The switch Swc is realized by feedback of the resistors R1 and R2 with the signal (Enbl) being connected during calibration. Note that the amplified signal output unit 101 shown in FIG. 9 is configured to include two stages of amplified signal output units 101a and 101b, but the number of stages is not limited, and the second embodiment described above. As described above, the first-stage amplified signal output unit 101a may be configured by the first-stage amplifier group, and the second-stage amplified signal output unit 101b may be configured by the second-stage amplifier.

  FIG. 10 shows changes in frequency characteristics in this example. The solid line in the figure represents the gain characteristic of the amplified signal output unit 101 during signal processing (when calibration is not being performed), and the broken line represents the outline of the gain characteristic during calibration. If an arbitrary gain Ac (60 dB in the figure) is only set, the frequency band is f1 in the figure, resulting in redundant calibration time. On the other hand, by reducing the capacitor capacitance Cc (by switching with the switch Swcc), the frequency band can be expanded to f2 in the figure.

  FIG. 11 shows a sixth embodiment. The sixth embodiment is a modification of the first embodiment. In the first embodiment, an even number (N) of amplifiers 111a to 111n are each provided with a switch for switching between positive and negative on the input terminal side (FIG. 1). In the sixth embodiment, as shown in the figure, an amplifier to be used is selected by turning on / off the power supply of the amplifier itself. At this time, the input terminals are assigned to positive and negative in advance, and M (<N / 2) so that the influence of the offset voltage on the differential output (Vout) is minimized by the output digital signal (Sel) of the control unit 503. Amplifiers (the same number on the positive and negative sides) are selected. At this time, the output terminal side is electrically connected / disconnected by a similar signal (Sel). Since the amplifiers 511a to 511n have their input terminals fixed to either positive or negative (Vip or Vim) in advance, the number of combination patterns is small compared to the configuration of the first embodiment (FIG. 1), and the effect of reducing the offset voltage is However, since the switch for selecting a combination (112a to 112n and 113a to 113n in FIG. 1) is not inserted into the input terminal, the input impedance can be increased, and sampling can be performed in an application such as an A / D converter. Since it is difficult to leave an error, it can be used for an input stage of a comparator (comparator).

  The operation algorithm at the time of calibration in this embodiment is the same as described above.

  FIG. 12 shows a seventh embodiment. The seventh embodiment is a modification of the sixth embodiment (FIG. 11). That is, as shown in the figure, the amplifiers 611a to 611n of the amplified signal output unit 601 are configured to be realized by MOSFETs. In this case, switching on the power supply voltage side means switching the connection with the tail current source IT on the source terminal side of the MOSFET. Further, as shown in the second embodiment, the second amplifier 616 is provided in the next stage and is configured to be amplified. Also in this case, the operations and algorithms of the detection unit 602 and the control unit 603 are the same as described above.

  In the above configuration, as in the case of the sixth embodiment (FIG. 11), no switch for selecting a combination is provided on the input side (the gate terminal side of the MOSFETs 611a to 611n). For this reason, since it becomes possible to make input impedance high compared with the structure of Example 1 (FIG. 1) or Example 2 (FIG. 3), a comparator (comparator) in an A / D converter, In addition, it can be used as an amplifier circuit that requires high input impedance.

  The configuration of the seventh embodiment is not limited to that shown in FIG. That is, the configuration of FIG. 12 is configured such that the switch on the source terminal side is inserted between the tail current source IT, but the same applies to a configuration in which this tail current IT is not present and is short-circuited to the power supply voltage. The effect is obtained.

  As described above, a plurality of embodiments according to the differential amplifier have been described. However, these are merely examples, and the present invention is not limited thereto. The differential amplifier of the present invention uses a plurality of amplifiers to form two sets of amplifier groups of the same number on the positive side and the negative side, thereby collecting the inherent offset voltages (variations) of individual amplifiers. The two offset amplifier groups are divided into a positive side and a negative side, and the two are canceled out to reduce the offset voltage as a whole. The number of amplifiers and the arrangement method are arbitrary.

Next, an embodiment of the present invention relating to a signal amplifying apparatus using the above-described differential amplifier will be described. As an example, a wireless sensor node is illustrated in Example 8 described later, and an analog front-end array is illustrated in Example 9.
[Embodiment of the invention concerning a signal amplifier]

  FIG. 13 is a diagram illustrating the wireless sensor node according to the eighth embodiment. This wireless sensor node includes a low noise amplifier (LNA) configured by any one of the amplification signal output units 101 to 601 described above, and a control unit and a detection unit for offset voltage reduction therefor include an A / D. It is in the form of sharing something for the comparator (Comp) in the converter (ADC). That is, as shown in FIG. 13, the low noise amplifier (LNA) 701 is connected so that the output signals of a plurality of sensors 708 can be input. A D converter (ADC) 709 is connected to be input. The control signal of the control unit 703 is output to the low noise amplifier (LNA) 701 and the A / D converter (ADC) 709, and the output value of the A / D converter (ADC) 709 is detected. The unit 702 is configured to be input. At this time, as an operation at the time of calibration, the low noise amplifier (LNA) 701 and the comparator (Comp) 791 are calibrated independently, and the offset voltage of the low noise amplifier (LNA) 701 is detected by A / D conversion. The result of the output (Dout) of the detector (ADC) 709 is used (that is, the detector 702 that operates specifically for the low noise amplifier (LNA) 701 is not provided). Thereby, the redundancy of the detection unit 702 and the control unit 703 can be eliminated, and downsizing and cost reduction are possible. Note that this embodiment includes a transmitter Tx, a receiver Rx, and an antenna Ant, and transmits an output value of an A / D converter (ADC) 709 and receives radio waves to perform wireless communication. It is possible.

  FIG. 14 is a diagram illustrating an analog front-end array according to the ninth embodiment. The ninth embodiment shows an example in which the differential amplifier having any one of the structures described above is arrayed and implemented as an analog front end for various array sensors.

  This embodiment includes an analog front-end array 800 that individually receives outputs of a sensor array 808 composed of a plurality of sensor devices, and a single control unit 803. Here, the analog front end array 800 includes an analog front end 801 composed of a plurality of channels, and each of the analog front ends 801 is realized by using any one of the above-described amplified signal output units 101 to 601. A low noise amplifier (LNA) 811 and an A / D converter (ADC) 809 having a comparator are provided, and switching control of the low noise amplifier (LNA) 811 is made possible by a control signal output from the control unit 803. The offset voltage output from the low noise amplifier (LNA) 811 or output from the A / D converter (ADC) 809 is individually input to the control unit 803 via the detection units 802a and 802b. It has come to be. Therefore, a signal processing circuit group capable of correcting the offset voltage as described above, and detection units 802a and 802b (Det1 and Det2 in the figure) corresponding to each of these signal processing circuit groups are incorporated in each analog front end 801. In addition, registers 832a and 832b (Reg1 and Reg2 in the figure) for storing the combination that provides the minimum offset voltage are also incorporated. Therefore, the configuration of the ninth embodiment is different from before, and does not include a register in the control unit 803 but is included individually in each channel.

  As an operation, during the calibration period, calibration is sequentially performed by applying a common combination pattern generated by the shared control unit 803. At this time, the register update in each channel occurs in different combinations, and therefore is performed independently (because the state of variation varies depending on each channel). In this way, by using the amplifier and the offset voltage reduction method of the present invention, when the array is made, most of the elements that should constitute the control unit 803 can be shared, and an analog front-end array can be realized at a lower cost. it can.

  Although the above two examples have been described as embodiments of the present invention relating to signal amplifiers, it should be understood that the present invention is not limited to these embodiments. Furthermore, in the description of the embodiments of any of the inventions, some of the drawings to be referred to are omitted or simplified for convenience of explanation, but are appropriately modified based on the spirit of the present invention. Can be configured. In particular, the switches provided at various places in the drawing showing the embodiments of the invention relating to the differential amplifier are shown as physical switch structures, but can be configured to operate connection and disconnection depending on the presence or absence of a gate voltage by a transistor. .

  The present invention is a fundamental technology that can be used for any application that amplifies, detects, and converts a differential signal (differential input). For example, it can be used for various electronic circuits such as sensor front end, environmental monitor, analog filter, A / D converter, D / A converter, etc. Cost reduction is expected in applications such as instrumentation amplifiers, which are high-precision measurement amplifiers combining op amps with resistors, and comparators used in data converters. In particular, it is useful for realizing low-cost ICs with multiple channels of operational amplifiers (or instrumentation amplifiers) mounted on a single chip.

100, 200 Differential amplifier 101, 201 Amplified signal output unit 101a First stage amplified signal output unit 101b Second stage amplified signal output unit 102, 202 Detection unit 103, 203 Control unit 104a, 104b Input terminals 105a, 105b Input Side switches 106a, 106b Output terminals 107a, 107b Switches 111a, 111b, 111n with reference power supply Amplifiers 112a, 112b, 112n Positive side switches 113a, 113b, 113n Negative side switches 114a, 114b on the input side 114n Positive side switches 115a, 115b, 115n on the output side Negative side switches 211a, 211b, 211n on the output side Transistors (first amplifier)
212a, 212b, 212n Positive side switches 213a, 213b, 213n on the input side Negative side switches 214a, 214b, 214n on the input side Positive side switches 215a, 215b, 215n Negative side switch 216 on the output side Amplifier (second amplifier)
302, 402 Detection unit 303, 403 Control unit 321, 421 Comparator 331, 431 Controller 332, 432 Memory (register)
333, 433 Look-up table 334, 434 Multiplexer 335, 435 Switch 336, 436 Inverter 437 Clock generator 422a, 422b First switch 423a, 423b Second switch 424a, 424b Reference capacitor 425 Preamplifier 426a, 426b Third switch 501 , 601 Amplified signal output section 502, 602 Detection section 503, 603 Control section 511a, 511b, 511n Amplifier 611a, 611b, 611n Transistor (first amplifier)
616 operational amplifier (second amplifier)
701, 801 Low noise amplifiers 702, 802a, 802b detection units 703, 803 control unit 708 sensor (group)
709, 809 A / D converter 791 Comparator 800 Analog front end array 808 Sensor array 810 Signal processing unit 832a, 832b Memory (register)

Claims (12)

An amplifier group composed of a plurality of amplifiers connected in parallel to the two input signal paths of the positive electrode and the negative electrode, and an input to a part or all of the amplifier group functions as either the positive side or the negative side Therefore, an amplification signal output unit including a switch group that selectively switches to connect, or a switch group that selectively switches connection or disconnection, and outputs positive and negative amplification signals by the amplifier group, respectively,
A detection unit for detecting an offset voltage output from the amplified signal output unit;
A reference voltage changeover switch for switching an input signal input to the amplified signal output unit to a reference voltage;
An enable signal for switching the reference voltage changeover switch, and a control unit for controlling the switching of the switch group, and a control unit for storing an offset voltage value detected by the detection unit,
The control unit selects a plurality of combinations having the same number of positive and negative sides from among a plurality of amplifiers constituting the amplifier group, and sequentially switches the switch group so as to correspond to each combination by the control signal. A differential amplifier that determines and maintains a combination of switch groups when the offset voltage detected by the detection unit is minimized. The amplified signal output unit includes an even number of paths formed by branching the input signal path,
Each amplifier constituting the amplifier group is individually provided for each of the even number of paths,
The switch group selectively switches the input / output before and after each amplifier constituting the amplifier group to either the positive side or the negative side,
The control signal for controlling switching of the switch group by the control unit is a signal for switching the switch group so that the even number of paths form two equal numbers of paths. The differential amplifier described. The amplifier group provided in the amplified signal output unit is divided into two sets of amplifier groups connected in advance to the same number of positive and negative sides,
The switch group supplies power to the two sets of amplifier groups, or switches between disconnecting,
2. The differential amplifier according to claim 1, wherein the control signal for controlling switching of the switch by the control unit is a signal for selecting the same number of amplifiers from the two sets of amplifier groups and connecting to a power source. . The amplified signal output unit includes an even number of paths formed by branching the input signal path, and the amplifier group includes a first-stage amplifier group provided individually for each of the even number of paths; The first stage amplifier group is divided into a second stage amplifier that cascades the first stage amplifier group via the switch group disposed on the output side of the first stage amplifier group,
The switch group selectively switches each input / output before and after the first-stage amplifier group to either the positive side or the negative side,
The control signal for controlling switching of the switch group by the control unit is a signal for switching the switch group so that the even number of paths form two equal numbers of paths. The differential amplifier described.   Each of the plurality of first amplifiers includes a transistor, each gate terminal of which is connected to an input terminal, each drain terminal is connected to an output terminal, each source terminal is connected to a tail current source, and the gate side and the drain side The differential amplifier according to claim 4, wherein the switch group is interposed in the differential amplifier. The amplified signal output unit includes an even number of paths formed by branching the input signal path, and the amplifier group includes a first-stage amplifier group provided individually for each even number of the paths; The first stage amplifier group is divided into a second stage amplifier that cascade-connects the first stage amplifier group via the switch group disposed on the output side of the first stage amplifier group, and further, the first stage amplifier group Is divided into two sets of first-stage amplifier groups in which the same number of amplifiers are connected in advance to the positive side and the negative side,
The switch group is for switching power supply to the two sets of first stage amplifier groups, or switching to disconnect,
2. The control signal for controlling switching of the switch group by the control unit is a signal for selecting the same number of amplifiers from the two sets of first-stage amplifier groups and connecting to a power source. The differential amplifier described.   The first-stage amplifier group includes transistors, each gate terminal of which is connected to an input terminal, each drain terminal is connected to an output terminal, each source terminal is connected to a tail current source, and only on the source side. The differential amplifier according to claim 6, wherein a switch group is interposed.   The detection unit includes at least one comparator, and the control unit changes a combination of the switch groups based on a value output from the comparator and determines a combination that minimizes the offset voltage. The differential amplifier according to claim 1, wherein the differential amplifier is one. The control unit includes a clock generator, and
The detection unit includes a sampling capacitor for accumulating a sampling capacity, a preamplifier connected in series with the sampling capacitor, a latched comparator connected in series with the preamplifier, and a signal from the amplified signal output unit. A first changeover switch for connecting or disconnecting a capacitor, a second changeover switch for connecting or disconnecting a reference voltage to the sampling capacitor, and a short circuit between the input and output of the preamplifier, or A third changeover switch for disconnecting,
9. The differential amplifier according to claim 1, wherein the first, second and third changeover switches are controlled by a clock signal output from the clock generator.   10. The control signal for controlling switching of the switch by the control unit includes a signal for repeating connection and disconnection inversion operations according to a chopping frequency together with the signal for the switch. The differential amplifier according to any one of the above. A signal amplifying apparatus using the differential amplifier according to any one of claims 1 to 10,
One or more signal output units for outputting an analog signal to the amplified signal output unit;
An analog-to-digital converter that has at least one comparator and converts a signal amplified by the amplified signal output unit into a digital signal;
The detection unit detects an offset voltage based on a signal output from the analog-digital converter while using a comparator of the analog-digital converter,
The control unit outputs a combination that minimizes an offset voltage to the amplified signal output unit based on a signal output from the detection unit. A signal amplifying apparatus that individually amplifies signals output from a plurality of devices using the differential amplifier according to claim 1,
A plurality of the amplified signal output units that individually input signals output from the plurality of devices, a plurality of the detection units that individually detect outputs of the respective amplified signal output units, and a plurality of the amplified signal output units And a single control unit that individually controls the amplified signal output unit while selecting the amplified signal output unit and the detection unit with respect to the detection unit.