JP6024742B2 - Information processing apparatus, information processing method, information processing program, and recording medium - Google Patents

Description

  The present invention relates to an information processing apparatus, an information processing method, an information processing program, and a recording medium.

  The computer system has firmware including a basic input output system (BIOS) that controls devices such as connected storage devices and input / output devices such as a keyboard and a display. Firmware is software that performs basic control of hardware resources that maximizes the functions of the hardware resources included in the computer system, for example, by retaining system configuration information. For example, when a new computer system is developed, a test for assuring quality (DVT: Design Verification Test) is performed. In a test to guarantee quality, when a hardware or firmware failure occurs in a new computer system, the firmware may be recreated.

  In the computer system, for example, system configuration information such as addition, change, or deletion of a device is changed for the purpose of improving performance. When the system configuration information is changed, it is necessary to update the firmware, for example, by upgrading the existing firmware to a firmware corresponding to the system having the changed configuration information. For this reason, the firmware is stored in a rewritable memory such as a flash memory.

  As an example of a technique for updating firmware, a technique for upgrading firmware with a plurality of memories is known. In this technique, when the current firmware is executed in one memory, the firmware to be updated is written in the other memory. Then, the computer system is restarted so that the firmware to be updated can be used. In addition, a technique for improving the reliability and maintainability of an information processing apparatus by notifying an error occurring in firmware to a maintenance center is known. Further, a technique is known that enables a test to be restarted without being stopped even when an error that cannot be recovered occurs during a firmware test.

  By the way, since it is necessary for the firmware to make the computer system exhibit its performance, the firmware to be updated needs to be finely adjusted, and the evaluation of the firmware to be updated is important. An example of firmware update and evaluation will be described. Firmware update is executed by turning on the computer system and rewriting the firmware in use with the firmware to be updated. After the firmware update, the computer system is restarted to validate the firmware update. After the restart, firmware evaluation is performed to check whether or not an error occurs using test data or the like for evaluating the firmware. Then, after the firmware to be updated is evaluated, the computer system is powered off. When evaluating a plurality of different firmwares, the above processing is repeatedly executed for each firmware.

JP 2006-260058 A Japanese Patent Laid-Open No. 7-262054 Japanese Patent Laid-Open No. 5-53852

  However, if the firmware is evaluated after updating the firmware, the time required for the process including the evaluation increases as the number of firmware to be evaluated increases.

  Further, for example, there are cases where a plurality of firmwares are created and a plurality of firmwares are evaluated at a time in order to cope with a function addition or a plurality of corrections. As an example, there is a case where a parameter for exerting the function of the hardware resource cannot be uniquely determined, and a plurality of firmwares are prepared and the parameter is determined based on an evaluation result. When evaluating a plurality of firmware at once, the time required for processing increases as the number of firmware increases.

  In one aspect, an object of the present invention is to shorten firmware evaluation time in an information processing apparatus.

  In the first proposal, the first information is stored as basic information in a first storage unit among a plurality of storage units that are provided in the processing unit and store basic information for causing the processing unit to execute processing. After storing the first information, the processing unit is caused to execute the first process by the first information. At the same time, the second information is stored as basic information different from the first information in the second storage unit among the plurality of processing units, and the second information is stored after the first processing is completed and after the second information is stored. Based on the information, the processing unit executes the second process. Then, when the first process or the second process is executed in the processing unit, the operating state of the processing unit by the first process or the second process at the time of execution is acquired, and the execution is performed based on the acquired operating state of the processing unit. The basic information corresponding to the first process or the second process is evaluated.

  According to the information processing apparatus according to one embodiment, the firmware evaluation time can be shortened.

It is a block diagram which shows schematic structure of the information processing apparatus which concerns on embodiment. It is a schematic block diagram of a computer that functions as an information processing apparatus. It is explanatory drawing about switching of the flash memory which has a some storage area. It is an image figure which shows an example of an evaluation plan table | surface. It is an image figure which shows an example of an evaluation plan table | surface. It is explanatory drawing which shows the relationship between each part contained in information processing apparatus and a to-be-evaluated part. It is a sequential flow which shows the flow of a process in information processing apparatus. It is explanatory drawing that time reduction is attained by firmware update and evaluation. It is a sequential flow showing the flow of processing in the information processing apparatus when an error occurs. It is a flowchart which shows the flow of a process in a data management part. It is a flowchart which shows the flow of a process in an error collection process. It is a flowchart which shows the flow of a process in an error analysis process. It is a flowchart which shows the flow of a process in an error analysis process. It is a flowchart which shows the flow of a process in an error analysis process. It is a flowchart which shows the flow of a process in a time management process. It is a flowchart which shows the flow of a process in a command operation process. It is an image figure which shows the evaluation table provided to a user. It is an image figure which shows the modification of an evaluation plan table | surface. It is a flowchart which shows the flow of a process in an error analysis process. It is a flowchart which shows the flow of a process in an error analysis process. It is a flowchart which shows the flow of a process in a time management process. It is an image figure which shows the modification of an evaluation plan table | surface. It is a flowchart which shows the flow of a process in a time management process.

  Hereinafter, an example of an embodiment of the disclosed technology will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 1 shows an information processing apparatus 10 according to the present embodiment. The information processing apparatus 10 includes a data management unit 12, an evaluation unit 14, and a command operation unit 22. The evaluation unit 14 includes a time management unit 16, an error collection unit 18, and an error analysis unit 20. The information processing apparatus 10 is connected to an evaluated unit 24 that is a computer system.

  The evaluated unit 24 performs various processes by each of a plurality of processing units as a computer system. The evaluated unit 24 includes a plurality of processing units 26 and a data control unit 28. Each of the plurality of processing units 26 is connected to the data control unit 28 via a bus 27 such as a PCI (Peripheral Component Interconnect) bus. Each of the plurality of processing units 26 includes a storage unit 30 including a first storage unit 32 and a second storage unit 34, a switching unit 36, a control unit 38, and a calculation unit 40. When a plurality of processing units 26 included in the evaluated unit 24 are targeted to individual processing units 26, symbols A to N are added after the reference symbols to distinguish the processing units 26 or elements from each other. May be handled.

  The information processing apparatus 10 is an example of an information processing apparatus in the disclosed technology, and any one of the plurality of processing units 26 is an example of a processing unit in the disclosed technology.

  The data management unit 12 manages data related to firmware update and evaluation. The data management unit 12 stores firmware data for updating firmware and test data for evaluating firmware. The data management unit 12 stores the number of firmware to be evaluated and parameters for each firmware evaluation, and can provide information on firmware data, test data, the number of firmware, and parameters for each firmware evaluation.

  The error collection unit 18 collects error information generated during firmware evaluation. The error collection unit 18 has a function of displaying the collected error information on a display device or the like.

  The command operation unit 22 outputs a command signal for operating the evaluated unit 24 to the evaluated unit 24. Examples of command signals include a signal indicating power-on to activate the device (Power_on signal), a signal indicating restart to enable firmware update (Reset signal), and a power-off to stop the operation of the device Signal (Shutdown signal). The command operation unit 22 outputs a command signal to the data control unit 28 of the evaluated unit 24.

  The time management unit 16 manages time related to firmware evaluation, and has an area for storing information on time to be managed. For example, information on the start time of firmware evaluation, elapsed time, and evaluation time (running time) is stored in an area for storing information on time to be managed. The time management unit 16 outputs the time and time information to the error analysis unit 20 and the data management unit 12.

  The error analysis unit 20 monitors errors that occur in the processing unit 26. For example, the error analysis unit 20 monitors the number and frequency of error occurrences based on information from the error collection unit 18 and the time management unit 16. Further, the error analysis unit 20 may request that the command operation unit 22 output a signal indicating a restart (Reset signal) or a power shutdown signal (Shutdown signal) depending on the result of error monitoring.

  The data control unit 28 of the evaluated unit 24 controls each of the plurality of processing units 26 based on data and instructions from the information processing apparatus 10. Each of the plurality of processing units 26 is configured so that the arithmetic unit 40 including a CPU or the like is basically used for hardware resources by firmware stored in the storage unit 30 including the first storage unit 32 and the second storage unit 34 such as a flash memory. Control. When the calculation unit 40 performs basic control in each of the plurality of processing units 26, the control unit 38 outputs various control signals and switches the switching unit 36. For example, the switching unit 36 receives the control signal from the control unit 38 and connects the first storage unit 32 and the calculation unit 40 in order to evaluate the firmware stored in the first storage unit 32. Further, the switching unit 36 performs switching so as to connect the second storage unit 34 and the control unit 38 in order to store the data from the control unit 38 in the second storage unit 34.

  The data management unit 12 of the information processing apparatus 10 outputs the first firmware data to the data control unit 28 in order to store the first firmware data of the firmware in the first storage unit 32. The data control unit 28 outputs a signal for switching the switching unit 36 in order to store the first firmware data in the first storage unit 32. Next, in order to validate the first firmware data, the data management unit 12 of the information processing apparatus 10 indicates a restart to the instruction operation unit 22 so that the plurality of processing units 26 are restarted. Request to output a signal. The command operation unit 22 receives a request from the data management unit 12 and outputs a signal indicating restart to the data control unit 28. The data control unit 28 receives the signal indicating the restart (Reset signal), resets the switching unit 36, and switches the connection. In the processing unit 26, processing by the firmware of the first firmware data is executed by the arithmetic unit 40. At the time of firmware evaluation, the data control unit 28 performs error detection. The error collection unit 18 of the information processing apparatus 10 collects errors detected by the data control unit 28 as information. Further, during the firmware evaluation by the first firmware data, the data management unit 12 of the information processing apparatus 10 stores the second firmware data in order to store the second firmware data of the firmware in the second storage unit 34. The data is output to the data control unit 28. The data control unit 28 stores the second firmware data in the second storage unit 34. In this way, by performing firmware update and evaluation in parallel, a plurality of firmware can be evaluated in a short time.

  The information processing apparatus 10 can be realized by, for example, the computer 42 illustrated in FIG. The computer 42 includes a CPU 44, a memory 46, a nonvolatile storage unit 48, an input / output port (I / O) 61, a display 62, a keyboard 63, a mouse 64, and a timer 65. The CPU 44, the memory 46, the nonvolatile storage unit 48, the input / output port (I / O) 61, the display 62, the keyboard 63, the mouse 64, and the timer 65 are connected to each other via the bus 60. The storage unit 48 can be realized by an HDD (Hard Disk Drive), a flash memory, or the like. The storage unit 48 serving as a recording medium stores a test program 50 for causing the computer 42 to function as the information processing apparatus 10. Further, the storage unit 48 stores a web browser (WebBrowser) program 56, a farm data DB 57, a test data DB 58, and an evaluation parameter DB 59, respectively. The CPU 44 reads out the web browser program 56 from the storage unit 48, expands it in the memory 46, and executes processing by the web browser program 56. Further, the CPU 44 reads the test program 50 from the storage unit 48 and develops it in the memory 46, and sequentially executes the processes included in the test program 50.

  The test program 50 includes a data management process 51, a time management process 52, an error collection process 53, an error analysis process 54, and an instruction operation process 55. The CPU 44 operates as the data management unit 12 illustrated in FIG. 1 by executing the data management process 51. That is, the information processing apparatus 10 is realized by the computer 42, and the computer 42 operates as the data management unit 12 illustrated in FIG. 1 by executing the data management process 51. The CPU 44 operates as the time management unit 16 illustrated in FIG. 1 by executing the time management process 52. When the CPU 44 operates as the time management unit 16, a partial area of the memory 46 is used as an area for storing time information obtained by processing of the time management unit 16.

  The CPU 44 operates as the error collection unit 18 illustrated in FIG. 1 by executing the error collection process 53. When the CPU 44 operates as the error collection unit 18, a partial area of the memory 46 is used as an area for storing error information obtained by the process of the error collection unit 18. The CPU 44 operates as the error analysis unit 20 shown in FIG. 1 by executing the error analysis process 54. When the CPU 44 operates as the error analysis unit 20, a partial area of the memory 46 is used as an area for storing information indicating an analysis result obtained by the process of the error analysis unit 20. The CPU 44 operates as the command operation unit 22 shown in FIG. 1 by executing the command operation process 55. When the CPU 44 executes the command operation process 55, the computer 42 that has executed the test program 50 functions as the information processing apparatus 10.

  As described above, the firmware data DB 57 is stored in the storage unit 48 of the computer 42. The firmware data DB 57 stores a plurality of firmware data corresponding to the firmware to be evaluated. A test data DB 58 is stored in the storage unit 48 of the computer 42. The test data DB 58 stores one or more test data used when evaluating the firmware to be evaluated.

  The storage unit 48 of the computer 42 stores an evaluation parameter DB 59. The evaluation parameter DB 59 stores, as one or more evaluation parameters, information that defines which firmware is to be evaluated with which test data when evaluating the firmware. For example, the evaluation parameter includes information that associates firmware data of firmware to be evaluated, test data for evaluating the firmware to be evaluated, and travel time. The travel time is the time for which the CPU is operated by test data for the firmware to be evaluated. In addition, the evaluation parameter can include the number of errors and the type of error that occur due to the CPU operation by the firmware. When the number of errors and the error type are included in the evaluation parameter, it is preferable that a process to be transferred next is determined by the evaluation parameter corresponding to the number of errors and the error type.

  In the present embodiment, an example in which an evaluation plan table based on information including a plurality of evaluation parameters is stored in the evaluation parameter DB 59 as a table in order to evaluate a plurality of firmware in a planned manner will be described. 4 and 5 show an example of the evaluation plan table. FIG. 4 shows a first table 97 that is a part of an evaluation plan table that stores, as information, evaluation parameters indicating evaluation contents for evaluating a plurality of firmware. FIG. 5 is a diagram of an evaluation plan table that stores, as information, criteria for determining the status transition of firmware evaluation based on errors depending on the type and frequency of errors occurring in the system when systematically evaluating a plurality of firmwares. The 2nd table 98 which is a part is shown.

  FIG. 4 shows an example when four types of firmware are evaluated in a planned manner. That is, a table in which the pattern name, firmware, travel time setting, test data, and LFWH (Local Firmware Hub) 0_BANK_sel items are associated with each other and are arranged in the order of the evaluation plan can be employed. The pattern name is a name for identifying an evaluation parameter group in which firmware, travel time setting, test data, and LFWH0_BANK_sel information are associated with each other. The information of the item LFWH0_BANK_sel stores the value of information for switching the bus switch included in the system board whose details will be described later. For example, when the pattern name is “pattern 1” in the first table 97 shown in FIG. Definition that the information LFWH0_BANK_sel is “1”, the firmware data “F1” is used for the firmware, the test data is “Data A”, and the running time is “2H (hours)”. become. In the example of FIG. 4, the firmware evaluation is executed in the order of the pattern 1.2.3.4.

  FIG. 5 shows an example of criteria for determining the status transition of firmware evaluation according to the type and frequency of errors that occur during firmware evaluation. FIG. 5 shows an example in which three types of information such as CE (Correctable Error), UE (Uncorrectable Error), and FE (Fetal Error), which are information indicating error contents, are used, with the error type as an item of error type. Show. The information CE indicating the error content is, for example, a 1-bit error indicated by the CPU or processor. Further, the information UE indicating the error content is, for example, a 2-bit error indicated by the CPU or the processor. The information FE indicating the error content is a fatal error such as an internal error or a bus error indicated by the CPU or processor. Information in which the frequency of error notification is associated with information CE, UE, and FE indicating error contents is assigned. For example, the information UE indicating the error content is “evaluation continuation” when the UE occurs once, “Shutdown” when the UE occurs twice in one minute, “firmware” when the UE occurs twice in 10 minutes, for example. Information indicating “switching” is given. That is, information indicating the criteria for determining the state transition of firmware evaluation that the firmware evaluation is continued when the UE occurs once during the running time is the content of the error that occurs during the firmware evaluation.

  In the above, an example in which three types of errors are used has been described, but the present invention is not limited to three types. Further, the information regarding the frequency of error notification is not limited to the information of FIG.

  The test program 50 is an example of an information processing program in the disclosed technology. That is, the test program 50 is an example of an information processing program for causing the computer 42 to function as the information processing apparatus 10.

  The evaluated unit 24 can be realized by, for example, the computer system 70 shown in FIG. The computer system 70 includes a plurality of system boards (hereinafter referred to as SB) 84 and a system control board 72. In the present embodiment, as exemplified by a well-known partition technique, the system can function as a system called a domain having a configuration in which a plurality of SBs 84 are regarded as a functional unit that performs processing combined by a plurality of SBs 84. In addition, when dealing individually with several SB84 contained in a domain, it attaches | subjects and describes with the code | symbol A-symbol N after a code | symbol, and demonstrates.

  Each of the plurality of SBs 84 included in the computer system 70 includes a system management controller (Baseboard Management Controller, hereinafter referred to as BMC) 86 and a CPU 90. Each of the plurality of SBs 84 includes a bus switch 92 and a local flash memory 94. In FIG. 2, the local flash memory 94 is expressed as LFWH0. The local flash memory 94 is a memory for storing firmware, and includes a first memory 95 and a second memory 96 in the present embodiment. In FIG. 2, the first memory 95 is expressed as LFWH0_A. In FIG. 2, the second memory 96 is denoted as LFWH0_B.

  The system control board 72 of the computer system 70 corresponds to the data control unit 28 shown in FIG. The SB 84 included in the computer system 70 corresponds to the processing unit 26 shown in FIG. Further, the BMC 86 of the SB 84 corresponds to the control unit 38 shown in FIG. The CPU 90 corresponds to the calculation unit 40 shown in FIG. The bus switch 92 corresponds to the switching unit 36 shown in FIG. The local flash memory 94 corresponds to the storage unit 30 shown in FIG. The first memory 95 corresponds to the first storage unit 32 shown in FIG. 1, and the second memory 96 corresponds to the second storage unit 34 shown in FIG.

  Moreover, although this embodiment demonstrates the case where SB84 is provided with one CPU90, the number of CPUs is not limited to one, Two or more may be sufficient. In the present embodiment, the local flash memory 94 will be described as a local flash memory 94 having two storage areas in which different firmware can be stored in the first memory 95 and the second memory 96. However, the storage area in which the firmware can be stored in the local flash memory 94 is not limited to two, and may be three or more.

  A CPU 90 is connected to the BMC 86 via a serial parallel interface bus (hereinafter referred to as SPI_BUS) 89. In addition, a bus switch 92 is connected to the BMC 86 via a serial parallel interface bus (hereinafter referred to as SPI bus) 88 and a serial bus 87. In the present embodiment, a so-called I2C bus (Inter-Integrated Circuit Bus) is used as an example of the serial bus 87. The bus switch 92 is connected to the local flash memory 94 and switches the connection between the BMC 86 and the CPU 90 and the first memory 95 and the second memory 96 of the local flash memory 94 by a control signal from the serial bus 87. That is, the bus switch 92 has a function of switching between the first switching state and the second switching state. The first switching state is a state in which the BMC 86 is connected to the first memory 95 via the SPI bus 88 and the CPU 90 and the second memory 96 are connected. The second switching state is a state in which the BMC 86 is connected to the second memory 96 via the SPI bus 88 and the CPU 90 and the first memory 95 are connected.

  Further, the BMC 86 includes a memory BMC_M such as an EEPROM (Electrically Erasable Programmable Read-Only Memory). The memory BMC_M stores a value of information indicating whether firmware can be updated (hereinafter referred to as information LFWH0_update) and a value of information for switching the bus switch 92 (hereinafter referred to as information LFWH0_BANK_sel). For example, as an example of the value of the information LFWH0_update, “1” is stored when the firmware is updated, and “0” is stored when the firmware update is prohibited. The information LFWH0_BANK_sel is information for setting the connection destination of the CPU 90 and the BMC 86 and the first memory 95 and the second memory 96. As shown in FIG. 3, as an example of the value of the information LFWH0_BANK_sel, “1” is stored when the BMC 86 and the first memory 95 are connected and the CPU 90 and the second memory 96 are connected. When the value of the information LFWH0_BANK_sel is “0” after resetting, the BMC 86 and the second memory 96 are connected, and the CPU 90 and the first memory 95 are connected.

  A system control board 72 included in the computer system 70 includes a CPU 78, a memory 79, a nonvolatile storage unit 74, an input / output port (I / O) 77, and a bus interface (I / F) 80 such as a PCI bus. The CPU 78, the memory 79, the nonvolatile storage unit 74, the input / output port (I / O) 77, and the bus interface (I / F) 80 are connected to each other via a bus 81. The storage unit 74 stores a control program 75 and a web user interface program 76. In FIG. 2, the web user interface program 76 is represented as WebUI_PG. The CPU 78 reads out the control program 75 and the web user interface program 76 from the storage unit 74, loads them into the memory 79, and executes processing by the control program 75 and the web user interface program 76. The bus interface 80 of the system control board 72 is connected to each of the BMCs 86 of the plurality of SBs 84 via the PCI bus 82. Further, the input / output port 77 is connected to the input / output port 61 via a LAN (Local Area Network) 68, whereby the computer 42 and the computer system 70 are connected so as to be able to exchange information. The system control board 72 operates as the data control unit 28 shown in FIG. 1 when the CPU 78 executes the control program 75 and the web user interface program 76.

Next, the operation of this embodiment will be described.
In the present embodiment, firmware update and evaluation are performed in parallel using the first memory 95 (LFWH0_A) and the second memory 96 (LFWH0_B) for storing the firmware of the SB84. For example, in the development of new products and the like, a test (DVT) for quality assurance is performed, but a hardware or firmware failure occurs, the firmware is recreated each time, and a long evaluation time is required. If the optimum parameter cannot be uniquely determined, a plurality of firmware may be prepared and the optimum firmware may be determined based on the evaluation result. However, when firmware update and firmware evaluation are executed alternately (serially), the time required for processing increases according to the number of firmware to be updated and evaluated. Therefore, in this embodiment, a plurality of storage areas for storing firmware are prepared, and firmware update and evaluation are performed in parallel, thereby reducing the time required for firmware evaluation.

  First, the operation of the information processing apparatus 10 will be described with reference to FIGS. FIG. 6 shows the relationship between the units included in the information processing apparatus 10 and the relationship between the units included in the evaluated unit 24. FIG. 7 shows a flow of processing related to each unit of the information processing apparatus 10 as a sequential flow. FIG. 8 is a diagram for explaining that the time can be shortened by updating and evaluating a plurality of firmwares. FIG. 9 shows a flow of processing related to each unit of the information processing apparatus 10 when an error occurs in the evaluated unit 24 as a sequential flow.

  Firmware data and test data of firmware to be evaluated are stored in the data management unit 12. The data management unit 12 transmits firmware data and test data of the firmware to be evaluated to the processing unit 26 installed in the evaluated unit 24 (see also FIG. 6). In addition, the data management unit 12 instructs the command operation unit 22 to perform a restart instruction for restart (Reset) for enabling the firmware, or power shutdown (Shutdown) for stopping the operation of the device when all the firmware evaluations are completed. A power-off instruction is output (see also FIG. 6).

  Specifically, the data management unit 12 instructs the command operation unit 22 to turn on the information processing apparatus 10 in order to cause the evaluated unit 24 (at least the processing unit 26) to turn on the power (see FIG. 7 step SF01). The command operating unit 22 commands the evaluated unit 24 to turn on the power in response to an instruction from the data management unit 12 (step SF02). The evaluated unit 24 receives the command from the command operating unit 22 and executes power-on (step SF03). In other words, the evaluated unit 24 executes a process in which the data control unit 28 of the evaluated unit 24 receives a command from the command operating unit 22 and powers on the entire apparatus including at least the processing unit 26. Along with the processing in step SF03, the data management unit 12 transmits information indicating whether the first firmware update is performed in the first storage unit 32 or the second storage unit 34. That is, the data management unit 12 transmits the LFWH0_BANK_sel signal (in this case, a signal of value “1”) based on the LFWH0_BANK_sel information in the first table 97 to the evaluated unit 24 based on the information in the evaluation plan table (Step 1). SF04). In the evaluated unit 24, the data control unit 28 of the evaluated unit 24 receives the LFWH0_BANK_sel signal transmitted from the data management unit 12, and switches the switching unit 36 of the processing unit 26 (step SF05). By the processing in step SF05, the processing unit 26 of the evaluated unit 24 executes processing up to the state for updating the firmware (step SF06). The process of step SF06 is a process of starting up until the operating system is activated.

  Next, the data management unit 12 transmits the value “1” of the information LFWH0_update to the evaluated unit 24 so that the processing unit 26 can update the firmware (step SF07). The to-be-evaluated part 24 performs the process which makes the firmware update possible in the process part 26 (step SF08). That is, in the evaluated unit 24, the data control unit 28 receives information LFWH0_update from the data management unit 12. Then, the data control unit 28 sets the value “1” of the information LFWH0_update in the control unit 38, so that the firmware data can be written into the first storage unit 32 of the processing unit 26. Along with the processing in step SF08, the data management unit 12 transmits the firmware data of the first firmware to the evaluated unit 24 (step SF09). After receiving firmware firmware data from the data management unit 12, the evaluated unit 24 updates the firmware (step SF10). In other words, in the evaluated unit 24, the data control unit 28 receives the firmware data of the first firmware and writes the firmware data to the first storage unit 32 via the control unit 38.

  When the first firmware update is completed in the processing unit 26 of the evaluated unit 24, the data control unit 28 notifies the data management unit 12 that the firmware update is completed (step SF11). The data management unit 12 sets the value “0” of the information LFWH0_update to be in a state in which the firmware cannot be updated after the first firmware update is completed in the processing unit 26 when the first firmware update is completed. It transmits to the to-be-evaluated part 24 (step SF12). The to-be-evaluated part 24 performs the process which makes the firmware update impossible in the process part 26 (step SF13). Further, the data management unit 12 instructs the instruction operation unit 22 to restart the processing unit 26 of the evaluated unit 24 in order to validate the updated first firmware (step SF14). The command operation unit 22 receives an instruction from the data management unit 12, and transmits a restart command to the evaluated unit 24 (step SF15). The evaluated unit 24 (data control unit 28) receives the restart command from the command operating unit 22, and restarts the processing unit 26 (step SF16). The state of the bus switch 92 is switched by restarting the processing unit 26 of the evaluated unit 24 (see also FIG. 3). In other words, it becomes possible for the computing unit 40 to operate with firmware based on the firmware data written in the first storage unit 32, that is, the computing unit 40 can execute the firmware data.

  In the to-be-evaluated unit 24, the processing unit 26 is restarted to execute processing up to the state for performing the firmware evaluation (OS_boot: processing to start up until the operating system is activated (step SF17)). . When the processing up to the state for evaluating the firmware after the restart of the processing unit 26 is completed, the data management unit 12 transmits the test data to the data control unit 28 of the evaluated unit 24 (step SF18). In the evaluated unit 24, the test data received by the data control unit 28 from the data management unit 12 is transmitted to the calculation unit 40 via the control unit 38. The calculation unit 40 performs firmware evaluation using the test data from the data management unit 12 (step SF19). When transmitting the test data, the data management unit 12 transmits information indicating that the firmware evaluation has started to the time management unit 16 (step SF20). The time management unit 16 receives the information from the data management unit 12 and records the evaluation start time (step SF21). The time management unit 16 transmits the recorded evaluation start time to the error analysis unit 20 (step SF22). The error analysis unit 20 acquires the evaluation start time (step SF23), and starts analysis for error analysis. For example, measurement of travel time is started.

  When the evaluation of the first firmware is started, the data management unit 12 determines whether there is unevaluated firmware (step SF24). When there is unevaluated firmware, the data management unit 12 proceeds to a process for updating the next firmware. That is, the data management unit 12 transmits the value “1” of the information LFWH0_update to the evaluated unit 24 so that the processing unit 26 can update the next firmware (step SF25). The evaluated unit 24 executes processing for making the next firmware updateable in the processing unit 26 (step SF26). Further, the data management unit 12 transmits the firmware data of the next firmware to the evaluated unit 24 (step SF27). The evaluated unit 24 receives the firmware data transmitted by the data management unit 12, and executes the next firmware update (step SF10). That is, in the evaluated unit 24, the data control unit 28 receives the firmware data of the next firmware, and writes the firmware data to the second storage unit 34 via the control unit 38.

  When the next firmware update is completed in the processing unit 26, the data control unit 28 notifies the data management unit 12 that the next firmware update is completed (step SF29). The data management unit 12 transmits the value “0” of the information LFWH0_update to the evaluated unit 24 so that the processing unit 26 cannot update the firmware when the next firmware update is completed ( Step SF30). The to-be-evaluated part 24 performs the process which makes the update of a firmware impossible in the process part 26 (step SF31).

  Next, the data management unit 12 transmits the travel time set in the first table 97 to the time management unit 16 for the first firmware evaluation (step SF32). The time management unit 16 receives the travel time from the data management unit 12 (step SF33), performs time management (monitoring) until the received travel time elapses, and passes the travel time to the data management unit 12 when the travel time elapses. Notification is made (step SF34). The data management unit 12 receives the notification of the elapsed travel time from the time management unit 16 and considers that the end of the evaluation has been notified (step SF37). In addition, the data management unit 12 transmits an evaluation parameter related to the firmware evaluation to the error analysis unit 20 (step SF35). The error analysis unit 20 acquires the evaluation parameter transmitted from the data management unit 12 (step SF36), and uses the evaluation parameter for error analysis.

  When there is no unevaluated firmware and all the evaluations are completed, the data management unit 12 instructs the command operation unit 22 to stop the operation of the processing unit 26 (step SF38). The command operation unit 22 receives an instruction from the data management unit 12, and transmits a power-off command to the evaluated unit 24 (step SF39). The evaluated unit 24 (data control unit 28) receives the power-off command from the command operating unit 22, and shuts off the power of the evaluated unit 24 (step SF40). When there is no unevaluated firmware (when a negative determination is made in step SF24), the data management unit 12 may wait for the evaluation to end.

  If there is unevaluated firmware after step SF37, the process returns to step SF14 and the above processing is repeated.

  With the above processing, the information processing apparatus 10 can update and evaluate a plurality of firmware in parallel, and can shorten the time for evaluating the plurality of firmware. That is, when the evaluation plan according to the first table 97 shown in FIG. 4 is executed, first, as shown in FIG. ) Is updated (step ST1). The firmware (F1) is updated to the first storage unit 32 of the processing unit 26. Next, the information processing apparatus 10 executes the evaluation of the firmware (F1) (step ST2), and executes the update of the firmware (F2) by the pattern 2 in parallel with the process of step ST2 (step ST3). The firmware (F2) is updated to the second storage unit 34 of the processing unit 26. Since the information processing apparatus 10 uses the first storage unit 32 and the second storage unit 34 included in the first storage unit 32 to update and evaluate the firmware, the firmware (F1) evaluation and the firmware ( Wait until both processes of F2) are completed.

  When the processing of both the firmware (F1) evaluation and the firmware (F2) update is completed, the information processing apparatus 10 executes the update of the firmware (F3) by the pattern 3 to the evaluated unit 24 (step ST4). ). The firmware (F3) is updated to the first storage unit 32 of the processing unit 26. In parallel with the process of step ST4, the information processing apparatus 10 executes the evaluation of the firmware (F2) (step ST5). In the evaluation of the firmware (F2), the second storage unit 34 of the processing unit 26 is used. The information processing apparatus 10 waits until both processing of firmware (F2) evaluation and firmware (F3) update is completed.

  When both the firmware (F2) evaluation and the firmware (F3) update processing are completed, the information processing apparatus 10 executes the firmware (F3) evaluation (step ST6). In parallel with the process of step ST6, the firmware (F4) is updated by the pattern 4 (step ST7). The firmware (F4) is updated to the second storage unit 34 of the processing unit 26. The information processing apparatus 10 waits until both processing of firmware (F3) evaluation and firmware (F4) update is completed.

  Upon completion of both the firmware (F3) evaluation and the firmware (F4) update processing, the information processing apparatus 10 executes the firmware (F4) evaluation (step ST8) and ends the evaluation of all the firmware.

  The process of evaluating the firmware (F1) (step ST2) and updating the firmware (F2) (step ST3) are performed in parallel. Therefore, both processes are completed in the longer time (time t2) of the time required for the evaluation of the firmware (F1) and the time required for updating the firmware (F2). Further, the processes of the firmware (F2) evaluation (step ST5) and the firmware (F3) update (step ST4) are performed in parallel. For this reason, both processes are completed in the longer time (time t4) of the time required for the firmware (F2) evaluation and the time required for the firmware (F3) update. Further, the processes of the firmware (F3) evaluation (step ST6) and the firmware (F4) update (step ST7) are performed in parallel. For this reason, both processes are completed in the longer time (time t6) of the time required for the evaluation of the firmware (F3) and the time required for the update of the firmware (F4).

  Therefore, the sum of the time required for the evaluation of the four different firmwares is the sum of the longer time in each parallel processing (t1 + t2 + t4 + t6 + t8 in the example of FIG. 8), and when the firmware update and evaluation processes are repeated alternately. It can be shortened in comparison.

  Next, a case where an error occurs in the evaluated unit 24 will be described. As shown in FIG. 9, when an error occurs in the evaluated unit 24, the evaluated unit 24 transmits error information to the error collecting unit 18 (step SF41). The error collecting unit 18 receives error information from the evaluated unit 24 (step SF43), and notifies the time management unit 16 of information indicating that an error has occurred in the evaluated unit 24 (step SF44). The time management unit 16 records the timing at which the notification of error occurrence from the error collection unit 18 is received (triggered) as the error occurrence time (step SF45). Next, the time management unit 16 transmits the recorded error occurrence time to the error analysis unit 20 (step SF46). The error analysis unit 20 acquires the error occurrence time transmitted from the time management unit 16 (step SF49).

  The error collection unit 18 transmits information indicating the content of the generated error to the error analysis unit 20 together with the notification of the occurrence of the error (step SF47). The error analysis unit 20 identifies information indicating the content of the error transmitted from the error collection unit 18 (step SF48). Next, the error analysis unit 20 performs analysis on the error using the identified error content and the acquired error occurrence time (step SF50). Analysis for errors is performed using the number of errors, the frequency of occurrence of errors, and evaluation parameters.

  When the analysis result for the error indicates restart (step SF51), the data management unit 12 sets the processing unit 26 of the evaluated unit 24 at the timing when the firmware update processing being executed in parallel ends. Restart (Reset). That is, the data management unit 12 instructs the command operation unit 22 to give a command to restart the processing unit 26 (step SF52). The command operation unit 22 receives an instruction from the data management unit 12, and transmits a restart command to the evaluated unit 24 (step SF53). The evaluated unit 24 (data control unit 28) receives the restart command from the command operating unit 22, and restarts the processing unit 26 (step SF54).

  On the other hand, when the analysis result for the error indicates that the power is shut down (step SF51), the data management unit 12 issues an instruction to immediately stop the operation of the processing unit 26 of the evaluated unit 24 (Shutdown). The operation unit 22 is instructed (step SF55). The command operation unit 22 receives an instruction from the data management unit 12, and transmits a power-off command to the evaluated unit 24 (step SF56). The evaluated unit 24 (data control unit 28) receives the power-off command from the command operation unit 22, and shuts off the power of the evaluated unit 24 to stop at least the operation of the processing unit 26 (step SF57).

  Next, the operation of each part of the information processing apparatus 10 realized by the computer 42 will be described in detail with reference to FIGS. 10 to 16 (see also FIG. 2).

  The system control board 72 and each of the plurality of SBs 84 are powered on, and firmware evaluation processing is executed by the CPU 90 of each SB 84 or at least one SB 84. Hereinafter, in order to simplify the description, a process for evaluating firmware for the SB 84A among the plurality of SBs 84 will be described as an example. In the following description, SB84A is denoted as SB84.

  First, the CPU 44 of the computer 42 executes each process included in the test program 50 stored in the storage unit 48. That is, the CPU 44 of the computer 42 expands the data management process 51, time management process 52, error collection process 53, error analysis process 54, and command operation process 55 stored in the test program 50 of the storage unit 48 in the memory 46. Run. Thereby, each processing routine shown in FIGS. 10 to 16 is executed.

  FIG. 10 is a flowchart showing the flow of processing in the data management unit 12. The information processing apparatus 10 is realized by the computer 42, and the computer 42 operates as the data management unit 12 (FIG. 1) by developing the data management process 51 in the memory 46 and executing it by the CPU 44. The firmware data of the firmware to be evaluated is stored in the firmware data DB 57, and the test data is stored in the test data DB 58.

  First, in step 100, in order to turn on the computer system 70, the command operation process 55 (command operation unit 22) is instructed to turn on the computer system 70. In the next step 102, based on the information in the evaluation plan table, the value based on the information of LFWH0_BANK_sel in the first table 97 (here, the value “1”) is transmitted to the computer system 70 as the LFWH0_BANK_sel signal. In the next step 104, the computer system 70 waits until the firmware can be updated, and the process proceeds to step 106. In the computer system 70, when the power is turned on, the system control board 72 receives the LFWH0_BANK_sel signal via the input / output port 77, and the bus switch 92 of the SB 84 is switched. When the bus switch 92 is switched, the SB 84 of the computer system 70 executes a process (OS_boot: process for starting up the operating system) up to a state where the firmware can be updated. In the second and subsequent firmware updates, the first memory 95 and the second memory 96 of the local flash memory 94 are alternately connected by setting and resetting the bus switch 92 as will be described later, so that information on LFWH0_BANK_sel There is no need to set the value by.

  In the next step 106, the value “1” of the information LFWH0_update is transmitted to the computer system 70 so that the firmware can be updated in SB 84. In the computer system 70, the system control board 72 receives the value of the information LFWH0_update and sets it in the BMC 86 of the SB84. When the value of the information LFWH0_update is set in the BMC 86, the first memory 95 of the SB 84 becomes ready to write firmware data. In the next step 108, the firmware data of the first firmware is transmitted to the computer system 70. When the firmware data of the first firmware is transmitted, the update of the first firmware is started in SB84. In the computer system 70, the system control board 72 receives the first firmware firmware data and writes the first firmware data to the first memory 95 via the BMC 86.

  Next, it continues until the transmission of the firmware data of the first firmware to the computer system 70 is completed (until affirmative determination is made at step 112) (step 110), and the firmware is updated. When the firmware update is completed, an affirmative determination is made at step 112, and the firmware update is released at step 114. That is, in step 114, the storage of data in the local flash memory 94 is prohibited (the firmware cannot be updated) with the completion of the first firmware update, so that the value “0” of the information LFWH0_update is set to the computer system 70. Send to. In the computer system 70, the system control board 72 receives the value of the information LFWH0_update and sets it in the BMC 86 of the SB84. As a result, the first memory 95 of the SB 84 becomes unable to write firmware data.

  In the next step 116, in order to validate the updated first firmware, an instruction to the instruction operation process 55 (instruction operation unit 22) is executed so that an instruction to restart (reset) the SB 84 of the computer system 70 is executed. . As will be described later, the command operation process 55 receives an instruction from the data management process 51 and transmits a restart command to the computer system 70. In the next step 118, the process waits until the computer system 70 can evaluate the firmware, that is, until the OS is in the operating state in SB 84, and proceeds to step 120.

  After the OS enters the operating state at SB84, test data is transmitted to the system control board 72 of the computer system 70 in the next step 120. When the test data is transmitted to the system control board 72, the firmware evaluation in the SB 84 is started. Here, the test data transmitted in step 120 is output via the BMC 86 to the CPU 90 operated by the first firmware stored in the first memory 95, and the firmware is evaluated.

  In the next step 122, it is determined whether there is unevaluated firmware. This determination can be made from the total number of firmware data registered in the data management process 51. If the determination in step 122 is affirmative, the process proceeds to step 124, and the value “1” of the information LFWH0_update is transmitted to the computer system 70 so that the next firmware can be updated. In the next step 126, update of the next firmware is started by transmitting the firmware data of the next firmware.

  Next, transmission of firmware data of the firmware is continued (until affirmative determination is made in step 130) until transmission to the computer system 70 is completed (step 128), and firmware update is executed. When the firmware update is completed, an affirmative determination is made in step 130 and the firmware update is released in step 132. That is, in step 132, the value “0” of the information LFWH0_update is transmitted to the computer system 70.

  In the next step 134, the negative determination is repeated until the evaluation of the firmware under evaluation is completed. If the determination in step 134 is affirmative, the process proceeds to step 136, and it is determined whether or not the evaluation of all the firmware set in the first table 97 has been completed. When all the firmware evaluations have been completed, an affirmative determination is made at step 136 and the process proceeds to step 138 to instruct the instruction operation process 55 (instruction operation unit 22) to issue an instruction to stop the operation of the computer system 70. As will be described later, the command operation process 55 transmits a power-off command to the computer system 70 to shut down the computer system 70. On the other hand, if the determination in step 136 is negative, there is firmware that has not been evaluated, so the process returns to step 116 and the above process is repeated.

  Next, processing in the error collection process 53 will be described. FIG. 11 is a flowchart showing the flow of processing in the error collection process 53. The information processing apparatus 10 is realized by the computer 42, and the error collection process 53 is expanded in the memory 46 and executed by the CPU 44, whereby the computer 42 operates as the error collection unit 18 (FIG. 1). The error collection process 53 acquires error information from the system control board 72 when an error occurs during the evaluation of the firmware, transmits the error content to the error analysis process 54 (error analysis unit 20), and that an error has occurred. Is transmitted to the time management process 52 (time management unit 16).

  First, in step 140, the process waits until a notification indicating that the evaluation of the firmware is started. When the evaluation of the firmware is started (when an affirmative determination is made in step 140), the process proceeds to step 141. In step 141, the presence / absence of an error in SB84 is detected, and in step 142, it is determined whether an error has occurred in SB84. That is, whether or not an error has occurred in the system control board 72 is detected by polling processing (polling) in step SB84, and if an error has been detected, an affirmative determination is made in step 142 and the processing proceeds to step 144.

  In step 144, information indicating the content of the detected error is transmitted to the error analysis process 54 (error analysis unit 20), and information indicating that an error has occurred is transmitted to the time management process 52 (time management unit 16). . In the next step 148, it is determined whether or not the firmware evaluation is completed. That is, when the data management process 51 (data management unit 12) notifies that the firmware evaluation has been completed (when an affirmative determination is made in step 148), the processing routine ends. On the other hand, if the determination in step 148 is negative, the process returns to step 141. Note that if a firmware evaluation end notification is made between step 141 and step 148, the processing routine can be ended assuming that an affirmative determination is made in step 148 as an interrupt process.

  Next, processing in the error analysis process 54 will be described. 12 to 14 are flowcharts showing the flow of processing in the error analysis process 54. The information processing apparatus 10 is realized by the computer 42, and the computer 42 operates as the error analysis unit 20 (FIG. 1) when the error analysis process 54 is expanded in the memory 46 and executed by the CPU 44. The error process 54 performs error analysis processing using the error information transmitted from the error collection process 53 (error collection unit 18). That is, the error analysis process 54 performs processing on error contents (CE, UE, FE) from the error information, the firmware evaluation start time acquired from the time management process 52 (time management unit 16), and the time when the error occurred. Do.

  First, in step 150, the process waits until a notification indicating that the evaluation of the firmware has been started. When the evaluation of the firmware is started (when an affirmative determination is made in step 150), the process proceeds to step 152. In step 152, the start time of firmware evaluation is acquired from the time management process 52 (time management unit 16). In the next step 154, negative determination is repeated until error information is received from the error collection process 53 (error collection unit 18). When error information is received from the error collection process 53 (error collection unit 18) (Yes in Step 154), in Step 156, it is identified whether the error content is CE, UE, or FE. In the next step 158, it is determined whether or not the content of the error is CE. If the determination in step 158 is affirmative, the process proceeds to step 168 after executing the process of step 160.

  On the other hand, when a negative determination is made at step 158, the routine proceeds to step 162, where it is determined whether or not the content of the error is UE. If the determination in step 162 is affirmative, the process proceeds to step 168 after executing the process of step 164. On the other hand, when a negative determination is made at step 162, it is assumed that the content of the error is FE, the process proceeds to step 166, and a power-off command is transmitted to the computer system 70 to the command operation process 55 (command operation unit 22). 70 is turned off. Note that in step 166, it may be instructed to transmit information requesting the power-off of the computer system 70 to the data management process 51 (data management unit 12). In this case, it is possible to instruct the power management command to be transmitted from the data management process 51 (data management unit 12) to the command operation process 55 (command operation unit 22).

  In step 168, it is determined whether the evaluation of the firmware has been completed. Step 168 is unconditionally affirmed when step 166 is passed. When the process passes through step 160, a determination is made on the result of the process described later in step 160. Similarly, when the process goes through step 164, a determination corresponding to the result of the process described later in step 164 is made. If an affirmative determination is made in step 168, this processing routine is terminated. If a negative determination is made, the process returns to step 154. If a firmware evaluation end notification is made between steps 152 to 166, this processing routine can be ended as an affirmative determination in step 168 as an interrupt process.

  In step 160 of FIG. 12 (when the error content is CE), the processing routine shown in FIG. 13 is executed. First, in step 170, the number of times an error has occurred is obtained (count_CE = count_CE + 1) and recorded. In the next step 172, the current time is acquired from the time management process 52 (time management unit 16), and the error occurrence time is acquired every time an error occurs. In the next step 174, the error occurrence time interval obtained in step 172 is obtained, and the error frequency obtained in step 170 and the error occurrence frequency according to the obtained error occurrence time interval are collated with the evaluation plan table. That is, it collates with each information of the error type “CE” in the second table 98.

  In step 176, it is determined whether or not the computer system 70 needs to be stopped using the collation result in step 174. If a negative determination is made in step 176, information indicating that the firmware evaluation is continued is set in step 178, and this routine is terminated. Information indicating that the firmware evaluation is continued is used for the determination in step 168 of FIG.

  On the other hand, when an affirmative determination is made in step 176, the process proceeds to step 180, and it is determined whether or not the collation result in step 174 is information indicating restart. When a negative determination is made at step 180, it is regarded as a collation result indicating that the operation of the computer system 70 is stopped. In step 182, an instruction to cut off the power supply of the computer system 70 is transmitted to the command operation process 55 (command operation unit 22), and the power supply of the computer system 70 is cut off. In step 166, information for requesting power-off of the computer system 70 may be transmitted to the data management process 51 (data management unit 12). In this case, a power-off instruction can be transmitted from the data management process 51 (data management unit 12) to the command operation process 55 (command operation unit 22).

  If the determination in step 180 is affirmative, the process waits until the next firmware update is completed (negative determination is repeated in step 184). When the update of the next firmware is completed (when an affirmative determination is made in step 184), the process proceeds to step 186, and an instruction to restart the SB 84 of the computer system 70 is transmitted to the instruction operation process 55 (instruction operation unit 22). Then, the SB 84 of the computer system 70 is restarted. In step 186, information for requesting restart of the SB 84 of the computer system 70 may be transmitted to the data management process 51 (data management unit 12). In this case, a restart instruction can be transmitted from the data management process 51 (data management unit 12) to the command operation process 55 (command operation unit 22).

  In step 164 of FIG. 12 (when the error content is UE), the processing routine shown in FIG. 14 is executed. The process in FIG. 14 is almost the same as the process in FIG. The difference between the process of FIG. 14 and the process of FIG. 13 is that the error content is “CE” or the error content is “UE”. In step 188 in FIG. 14, the error content can be realized by replacing “CE” with “UE”.

  Next, processing in the time management process 52 will be described. FIG. 15 is a flowchart showing the flow of processing in the time management process 52. When the information processing apparatus 10 is realized by the computer 42 and the time management process 52 is expanded to 46 and executed by the CPU 44, the computer 42 operates as the time management unit 16 (FIG. 1). The time management process 52 records the firmware evaluation start time and error occurrence time, acquires the firmware evaluation time from the data management process 51 (data management unit 12), and determines the error occurrence time as the error analysis process 54 ( To the error analyzer 20).

  First, in step 200, the process waits until a notification indicating that the evaluation of the firmware has been started. When the evaluation of the firmware is started (when an affirmative determination is made in step 200), the process proceeds to step 202. In step 202, the firmware evaluation start time is recorded. In step 202, the start time can be obtained by referring to the timer 65 and acquiring the current time.

  In the next step 204, the travel time corresponding to the firmware stored in the first table 97 is acquired from the data management process 51 (data management unit 12). In the next step 206, it is determined whether or not an error occurrence notification has been received from the error collection process 53 (error collection unit 18). On the other hand, when an affirmative determination is made at step 206, the routine proceeds to step 208 where the error occurrence time is recorded. In the next step 210, the recorded error occurrence time is transmitted to the error analysis process 54 (error analysis unit 20), and the process proceeds to step 212.

  In step 212, it is determined whether or not the travel time acquired in step 204 has elapsed. If a negative determination is made in step 212, the process returns to step 206. If an affirmative determination is made, the process proceeds to step 214. When the running time has elapsed, it is a time when the evaluation of the firmware has been completed, and therefore information indicating the end of the evaluation is transmitted to the data management process 51 (data management unit 12) in step 214.

  In step 216, it is determined whether the firmware evaluation has been completed. That is, when the data management process 51 (data management unit 12) notifies that the firmware evaluation has been completed (when an affirmative determination is made at step 216), the processing routine ends. On the other hand, if the determination in step 216 is negative, the process returns to step 206. If a firmware evaluation end notification is made between step 206 and step 216, it is possible to end this processing routine assuming that an affirmative determination is made in step 216 as an interrupt process.

  Next, processing in the command operation process 55 will be described. FIG. 16 is a flowchart showing the flow of processing in the command operation process 55. The information processing apparatus 10 is realized by the computer 42, and the instruction operation process 55 is expanded in the memory 46 and executed by the CPU 44, whereby the computer 42 operates as the instruction operation unit 22 (FIG. 1). The command operation process 55 can transmit a power-on command for the entire computer system 70 to the computer system 70. Further, in the command operation process 55, a restart command and a shutdown command instructed by the data management process 51 (data management unit 12), the error analysis process 54 (error analysis unit 20) are provided. To the computer system 70.

  First, in step 220, a power-on command for the entire computer system 70 that is instructed by the data management process 51 (data management unit 12) and the error analysis process 54 (error analysis unit 20) is output to the computer system 70. To do. The operation of the computer system 70 is started when the computer system 70 receives a power-on command. In the next step 222, it is determined whether or not a restart instruction has been issued from the data management process 51 (data management unit 12) or the error analysis process 54 (error analysis unit 20). If the result in step 222 is affirmative, a restart command signal is output to the computer system 70 in step 224, and the process returns to step 222. On the other hand, when the result in step 222 is negative, it is determined in step 226 whether or not a power shutdown instruction has been issued from the data management process 51 (data management unit 12) or the error analysis process 54 (error analysis unit 20). . If the determination in step 226 is negative, the process returns to step 222. If the determination is affirmative, in step 228, a power-off command signal is output to the computer system 70, and this routine is terminated.

  As described above, in the present embodiment, during firmware evaluation, firmware that is different from the firmware under evaluation can be updated. During firmware evaluation, firmware updates that are different from the firmware being evaluated are processed, thereby reducing the time required for firmware evaluation compared to alternating firmware updates and evaluations. Can do. For example, when evaluating four types of firmware, one example is a case where a processing time of 1 hour is required for firmware update and a processing time of 2 hours is required for firmware evaluation. In the technique of continuously processing each update and evaluation process for each of the four types of firmware, 12 hours are required for the entire evaluation. On the other hand, in this embodiment, since parallel processing is possible, all evaluations can be completed in a processing time of 9 hours.

  Further, in this embodiment, it is possible to shorten the firmware evaluation time due to the occurrence of an error. For example, if it can be determined that the significance of continuing the evaluation process has been lost due to the error type, error occurrence frequency, and error occurrence location, the evaluation is terminated before the set evaluation time (running time) elapses. When the evaluation ends before the set evaluation time elapses, it is possible to perform hardware maintenance by temporarily shutting down the next firmware evaluation or power supply, and the firmware evaluation time can be shortened. become.

  As described above, according to the information processing apparatus 10 of the present embodiment, the firmware evaluation time can be shortened. By the way, it is preferable to provide the user of the information processing apparatus 10 with the firmware evaluation result explicitly while shortening the firmware evaluation time by the information processing apparatus 10. Therefore, a specific example of explicitly providing the firmware evaluation result to the user who operates the information processing apparatus 10 will be described.

  FIG. 17 shows, as an example, an evaluation table 99 that explicitly provides firmware evaluation results to a user who operates the information processing apparatus 10. The evaluation table 99 is obtained by adding, to the first table 97, information in which the number of errors that have occurred, the evaluation start time, and the end time are associated with evaluation parameters. The evaluation table 99 can explicitly provide evaluation results of a plurality of firmware to a user who operates the information processing apparatus 10.

Second Embodiment
In the above embodiment, as the second table 98 which is a part of the evaluation plan table indicating the criteria for determining the state transition of firmware evaluation, the types and frequencies of errors are classified and set stepwise. In the present embodiment, a modified example of the second table 98 will be described as a second embodiment with reference to FIGS. In addition, since this embodiment is the structure substantially the same as the said embodiment, the same code | symbol is attached | subjected to the same part and detailed description is abbreviate | omitted.

  FIG. 18 shows the second table 98 (1). The second table 98 (1) is obtained by omitting a criterion relating to the frequency of error occurrence as a criterion for determining the state transition of firmware evaluation. More specifically, the second table 98 (1) is information only when there is an error notification, instead of the frequency of error occurrence in the second table 98, and information indicating error contents (CE, UE, FE) Information indicating the status transition of the firmware evaluation associated with the information).

Next, the operation of the second embodiment will be described.
The difference between the second embodiment and the first embodiment is the processing in the error analysis process 54 and the processing in the time management process 52. Specifically, the processing routine of FIG. 19 is executed instead of the processing routine of FIG. Further, the processing routine of FIG. 20 is executed instead of the processing routine of FIG. Further, the processing routine of FIG. 21 is executed instead of the processing routine of FIG. Hereinafter, differences will be described.

  First, processing in the error analysis process 54 will be described. The difference between FIG. 12 and FIG. 19 is that the processing of step 160 and step 164 of FIG. 12 is processed only by step 161 of FIG. That is, when the content of the error is CE or UE, step 161 is executed.

  Further, the difference between FIG. 13 and FIG. 20 is that the processing of FIG. 20 only processes the processing of step 184 and step 186 of FIG. That is, when the content of the error is CE or UE, the process waits until the next firmware update is completed (determination is negative in step 184). When the next firmware update is completed (when an affirmative determination is made in step 184), the process proceeds to step 186, and an instruction to restart the SB 84 of the computer system 70 is transmitted to the instruction operation process 55 (instruction operation unit 22). Then, the processing routine of FIG.

  Next, processing in the time management process 52 will be described. The difference between FIG. 15 and FIG. 21 is the timing at which step 212 in FIG. 15 is executed. That is, in the process of FIG. 21, when the determination process of step 206 is negative, the determination of the elapsed travel time at step 212 of FIG. If a negative determination is made in step 211, the process returns to step 206, and if an affirmative determination is made, the process proceeds to step 214. When the process of step 210 is completed, the process proceeds to step 214.

  In the second embodiment, when an error occurs even once, the evaluation process is terminated to switch to the next firmware evaluation. By terminating the evaluation process when an error occurs, firmware update and evaluation that do not cause an error can be realized. Further, if an error occurs even once, the evaluation is switched to the next firmware evaluation, so that the evaluation time can be further shortened.

<Third Embodiment>
In the second embodiment, the criterion for the case where there is an error notification is set as the second table 98 which is a part of the evaluation plan table indicating the criterion for determining the state transition of firmware evaluation. In the present embodiment, a modification of the second table 98 will be described as a third embodiment with reference to FIGS. 22 to 23. Since the third embodiment has substantially the same configuration as the first and second embodiments, the same parts are denoted by the same reference numerals and detailed description thereof is omitted.

  FIG. 22 shows an example of the second table 98 (2). The second table 98 (2) is obtained by adding a criterion when there is no error notification to the second table 98 of FIG. 5 as a criterion for determining the state transition of the firmware evaluation. Specifically, in the second table 98 (2), information indicating the status transition of firmware evaluation when there is no error notification is replaced with information (CE, UE, FE) indicating error contents, instead of the frequency of error occurrence. Associating and storing.

Next, the operation of the third embodiment will be described.
The difference between the third embodiment and the first embodiment is the processing in the time management process 52. Specifically, the processing routine of FIG. 23 is executed instead of the processing routine of FIG. Hereinafter, differences will be described.

  As processing in the time management process 52, the difference between FIG. 15 and FIG. 23 is that processing related to the occurrence of no error is added to the processing in FIG. That is, in the process of FIG. 23, when the process of step 204 is completed, the process proceeds to step 206 after counting the error-free time in step 230. Further, when a negative determination is made at step 206, it is determined whether or not the error-free state at step 232 has passed one hour. If a negative determination is made in step 232, the process proceeds to step 212, and if an affirmative determination is made, the process proceeds to step 214. When the process of step 210 is completed, the time count when an error has not occurred is reset (set to an initial value, for example, “0”), and then the process proceeds to step 214.

  As described above, in the present embodiment, when no error occurs for a predetermined time, the firmware to be evaluated is regarded as satisfying a predetermined constant evaluation criterion, and switching to the next firmware evaluation is performed. The evaluation process ends. By terminating the evaluation process when no error occurs for a certain period of time, firmware update and evaluation can be realized in a shorter time without evaluating the time to complete the running time.

  Note that an example in which the information processing apparatus 10 is realized by the computer 42 has been described above. However, the present invention is not limited to these configurations, and various improvements and modifications may be made without departing from the gist described above.

  Moreover, although the aspect by which the program was previously memorize | stored (installed) in the memory | storage part was demonstrated above, it is not limited to this. For example, the program in the disclosed technology can be provided in a form recorded on a recording medium such as a CD-ROM or a DVD-ROM.

  All documents, patent applications and technical standards mentioned in this specification are to the same extent as if each individual document, patent application and technical standard were specifically and individually stated to be incorporated by reference. Incorporated by reference in the book.

DESCRIPTION OF SYMBOLS 10 Information processing apparatus 12 Data management part 14 Evaluation part 16 Time management part 18 Error collection part 20 Error analysis part 22 Command operation part 24 Evaluated part 26 Processing part 28 Data control part 30 Storage part 32 First storage part 34 Second storage Unit 36 Switching unit 38 Control unit 40 Calculation unit 42 Computer 50 Test program 70 Computer system 72 System control board 84 System board (SB)
86 System Management Controller (BMC)
90 CPU
92 Bus switch 94 Local flash memory 95 ... 1st memory 96 ... 2nd memory

Claims (8)

The first information is stored as the information in a first storage unit among a plurality of storage units that are provided in the processing unit and store information used when the processing unit executes processing. after storing, the executing the first process in the processing unit by the first information, the second storage portion of the plurality of the storage unit in parallel with execution of the first process by the processor, the The second information different from the first information is stored as the information without setting the error detection related to the first process to be stored in the second storage unit , and after the end of the first process and A management unit that causes the processing unit to execute a second process according to the second information after storing the second information;
When the first process or the second process is performed by the processing unit, the operating state of the processing unit is acquired, and the first information or the second information is evaluated based on the acquired operating state of the processing unit. An evaluation section to
An information processing apparatus including: Information used when the processing unit executes processing is firmware for controlling hardware resources included in the processing unit.
The information processing apparatus according to claim 1. The processing unit includes a calculation unit that executes processing, a switching unit that switches the calculation unit to a state connected to the first storage unit or a state connected to the second storage unit, and a control that controls switching of the switching unit. Part
The management unit includes the control unit included in the processing unit,
Instructing storage of the first information, execution of the first process by the first information, storage of the second information, execution of the second process by the second information,
The information processing apparatus according to claim 1 or 2. The evaluation unit includes a time management unit that manages an execution time of the first process or the second process, and an error management unit that manages an error that occurs during the execution of the first process or the second process,
Based on the execution time of the first process or the second process managed by the time management unit and the error that occurs during the execution of the first process or the second process managed by the error management unit. The information processing apparatus according to any one of claims 1 to 3, wherein one information or the second information is evaluated. An instruction operation unit for instructing the processing unit to execute a canceling process for canceling the execution of the processing when the first processing or the second processing is performed by the processing unit;
The management unit, based on the evaluation result of the evaluation unit, stops the execution of the process with respect to the processing unit by the command operation unit when the processing unit executes the first process or the second process. The information processing apparatus according to any one of claims 1 to 4, wherein an instruction is given to stop processing that instructs execution of the stopping processing to be performed. The information processing apparatus according to claim 5, wherein the cancellation process includes a process of shutting down the processing unit. The first information is stored as the information in a first storage unit among a plurality of storage units that are provided in the processing unit and store information used when the processing unit executes processing. after storing, the executing the first process in the processing unit by the first information, the second storage portion of the plurality of the storage unit in parallel with execution of the first process by the processor, the The second information different from the first information is stored as the information without setting the error detection related to the first process to be stored in the second storage unit , and after the end of the first process and A management step of causing the processing unit to execute a second process according to the second information after storing the second information;
When the first process or the second process is performed by the processing unit, the operating state of the processing unit is acquired, and the first information or the second information is evaluated based on the acquired operating state of the processing unit. An evaluation step to
An information processing method including: On the computer,
The first information is stored as the information in a first storage unit among a plurality of storage units that are provided in the processing unit and store information used when the processing unit executes processing. After the first information is stored, the first process is executed by the processing unit based on the first information, and the second storage of the plurality of storage units is performed in parallel with the execution of the first process by the processing unit. The second information different from the first information is stored as the information without using the error detection related to the first processing as a condition for storing the second processing in the second storage unit . A management step of causing the processing unit to execute a second process according to the second information after completion and after storing the second information;
When the first process or the second process is performed by the processing unit, the operating state of the processing unit is acquired, and the first information or the second information is evaluated based on the acquired operating state of the processing unit. An evaluation step to
An information processing program for executing processing including:

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