JP6016510B2 - Wiring board and method of manufacturing wiring board - Google Patents

Description

  The present invention relates to a wiring board.

  Conventionally, a wiring board in which insulating layers containing ceramic and conductive wiring layers are alternately laminated is known. Such a wiring board is baked after the ceramic insulating layer and the wiring layer are laminated at the time of manufacture. When firing is performed, warping may occur due to a difference in shrinkage between the ceramic insulating layer and the wiring layer. For example, a technique disclosed in Patent Document 1 is known as a technique for suppressing warpage after firing.

Japanese Patent Laid-Open No. 5-110257 JP 2008-186919 A Japanese Patent Laid-Open No. 10-308582

  The warpage that occurs in the wiring board after firing includes a warp that protrudes upward in the vicinity of the center of the wiring board (hereinafter, positive warp) and a warp that protrudes downward in the vicinity of the center (hereinafter, negative warp). is there. When a positive warp occurs after firing, the amount of warpage is lowered because the vicinity of the center of the wiring board hangs down due to its own weight during firing. On the other hand, the amount of warping when negative warping occurs after firing is light because the peripheral part of the wiring board has few conductors, and the peripheral part of the wiring board hardly hangs down due to its own weight. For this reason, the total amount of warpage is unlikely to be small. Therefore, there has been a demand for suppressing the occurrence of negative warping after firing.

  The present invention has been made to solve at least a part of the above-described problems, and an object thereof is to provide a technique capable of suppressing the occurrence of negative warping in a wiring board.

In order to solve at least a part of the problems described above, the present invention can take the following forms or application examples. The first aspect of the present invention is formed in a plurality of ceramic insulating layers; a plurality of wiring layers disposed between the plurality of ceramic insulating layers; and a through-hole penetrating the ceramic insulating layer in the thickness direction; A plurality of through conductors that electrically connect the plurality of wiring layers; and the diameters of the through conductors included in the ceramic insulating layer of the same layer are all the same. The diameter of the through conductor included in at least one of the plurality of ceramic insulating layers is different from the diameter of the through conductor included in the ceramic insulating layer of the other layer; Is divided into two equal parts, the upper side is defined as the upper layer, the lower side is defined as the lower layer, and the total volume of the wiring layers included in the upper layer is Vc1 [mm ³ ]. Defined and included in the upper layer Wherein the total volume of through conductor is defined as Vp1 [mm ^3], the total volume of the wiring layer included in the lower layer is defined as Vc2 [mm ^3] that, said through conductors contained in the lower layer When the total volume of Vp2 [mm ³ ] is defined; the following relational expression (1):
Vc1 + Vp1 <Vc2 + Vp2 (1)
By satisfying the above, there is provided a wiring board characterized in that the lower layer is contracted more than the upper layer. The second embodiment of the present invention includes (a) a step of preparing a plurality of ceramic insulating layers; (b) a step of forming a through conductor in the ceramic insulating layer; and (c) a wiring layer on the ceramic insulating layer. A wiring board comprising: a step of forming; and (d) a step of laminating the ceramic insulating layer on which the wiring layer is formed to form a laminated body; and (e) a step of firing the laminated body to obtain a wiring substrate. The upper side is defined as the upper layer, the lower side is defined as the lower layer, and the wiring layer included in the upper layer The total volume is defined as Vc1 [mm ³ ], the total volume of the through conductors included in the upper layer is defined as Vp1 [mm ³ ], and the total volume of the wiring layers included in the lower layer is defined as Vp1 [mm ³ ]. Vc2 is defined as [mm ^3], contained in the lower layer If you define the total volume of serial through conductors and Vp2 [mm ^3], the step (b), the wiring substrate, the following relation (1):
Vc1 + Vp1 <Vc2 + Vp2 (1)
And a process for forming the through conductors having a plurality of types of diameters so that the lower layer is contracted more than the upper layer is provided as a manufacturing method. .

[Application Example 1]
A plurality of ceramic insulating layers;
A plurality of wiring layers disposed between the plurality of ceramic insulating layers;
A wiring board formed in a through-hole penetrating the ceramic insulating layer in the thickness direction, and having a plurality of through conductors electrically connecting the plurality of wiring layers,
The diameters of the through conductors included in the ceramic insulating layer of the same layer are all the same size,
The diameter of the through conductor included in at least one of the plurality of ceramic insulating layers is different from the diameter of the through conductor included in the ceramic insulating layer of the other layer,
When the thickness of the wiring board in the stacking direction is divided into two equal parts,
Define the upper side as the upper layer, the lower side as the lower layer,
The total volume of the wiring layer included in the upper layer is defined as Vc1 [mm ³ ],
The total volume of the through conductors included in the upper layer is defined as Vp1 [mm ³ ],
The total volume of the wiring layers included in the lower layer is defined as Vc2 [mm ³ ],
When the total volume of the through conductors included in the lower layer is defined as Vp2 [mm ³ ],
The following relational expression (1):
Vc1 + Vp1 ≦ Vc2 + Vp2 (1)
A wiring board characterized by satisfying
When firing is performed in the manufacturing process of the wiring board, the metal conductor and the ceramic insulating layer contract. Here, the shrinkage rate of the wiring layer and the metal conductor is larger than the shrinkage rate of the ceramic insulating layer. Therefore, if the above relational expression is satisfied, the lower layer shrinks more than the upper layer during firing, so that the occurrence of negative warping after firing of the wiring board can be suppressed.

[Application Example 2]
A wiring board according to Application Example 1,
Furthermore, the following relational expression (2):
(Vc2 + Vp2) − (Vc1 + Vp1) ≦ 100 (2)
A wiring board characterized by satisfying
In this way, since the difference between the shrinkage amount in the upper layer and the shrinkage amount in the lower layer is reduced, the amount of warpage after firing of the wiring board can be further reduced.

[Application Example 3]
The wiring board according to Application Example 1 or Application Example 2,
The diameter of the through conductor included in the ceramic insulating layer located on the uppermost side is 0.10 mm or more, and the wiring board is characterized in that:
In this way, it is possible to suppress the solder bumps formed on the exposed surface of the through conductor from becoming too small, and thus it is possible to suppress a decrease in mountability of the electronic component.

[Application Example 4]
(A) preparing a plurality of ceramic insulating layers;
(B) forming a through conductor in the ceramic insulating layer;
(C) forming a wiring layer on the ceramic insulating layer;
(D) laminating the ceramic insulating layer on which the wiring layer is formed to form a laminated body;
(E) a method of manufacturing a wiring board comprising: baking the laminate to form a wiring board,
When the thickness of the wiring board in the stacking direction is divided into two equal parts,
Define the upper side as the upper layer, the lower side as the lower layer,
The total volume of the wiring layer included in the upper layer is defined as Vc1 [mm ³ ],
The total volume of the through conductors included in the upper layer is defined as Vp1 [mm ³ ],
The total volume of the wiring layers included in the lower layer is defined as Vc2 [mm ³ ],
When the total volume of the through conductors included in the lower layer is defined as Vp2 [mm ³ ],
The step (b) includes the following relational expression (1):
Vc1 + Vp1 ≦ Vc2 + Vp2 (1)
The manufacturing method characterized by including the process of forming the said penetration conductor so that it may satisfy | fill.
According to such a manufacturing method, after firing, the lower layer shrinks more than the upper layer, and thus it is possible to suppress the occurrence of negative warping after firing.

[Application Example 5]
A method for manufacturing a wiring board according to Application Example 4,
In the step (b), the through conductors included in at least one of the plurality of ceramic insulating layers while the diameters of the through conductors included in the ceramic insulating layers of the same layer are all the same size. The manufacturing method characterized by including the process which makes a diameter different from the diameter of the said through conductor contained in the said ceramic insulating layer of another layer.
According to such a manufacturing method, generation | occurrence | production of a negative curvature can be suppressed, without making the process of forming a penetration conductor complicated.

[Application Example 6]
A method of manufacturing a wiring board according to Application Example 4 or Application Example 5,
The step (b) further includes the following relational expression (2):
(Vc2 + Vp2) − (Vc1 + Vp1) ≦ 100 (2)
The manufacturing method characterized by including the process of forming the said penetration conductor so that it may satisfy | fill.
According to such a manufacturing method, since the difference between the shrinkage amount in the upper layer and the shrinkage amount in the lower layer is reduced, the amount of warpage can be reduced.

  Note that the present invention can be realized in various modes. For example, the present invention can be realized in the form of a wiring board design method, a wiring board manufacturing apparatus, an integrated circuit for realizing the functions of the method or apparatus, a computer program, a recording medium storing the computer program, and the like.

It is sectional drawing which shows the structure of the wiring board as one Embodiment of this invention. It is process drawing which shows the manufacturing process of a wiring board. It is explanatory drawing which shows the mode of the manufacturing process of a wiring board. It is explanatory drawing which shows the mode of the manufacturing process of a wiring board. It is explanatory drawing which shows the mode of the manufacturing process of a wiring board. It is explanatory drawing which shows the mode of the manufacturing process of a wiring board. It is explanatory drawing which shows the mode of the manufacturing process of a wiring board. It is explanatory drawing which shows the relationship between the volume of the whole conductor contained in the upper layer and lower layer of a wiring board, the direction of the curvature after baking, and the amount of curvature in a table | surface form.

Next, embodiments of the present invention will be described in the following order based on examples.
A. Embodiment:
B. Experimental example:
C. Variations:

A. Embodiment:
FIG. 1 is a cross-sectional view showing a configuration of a wiring board 100 as an embodiment of the present invention. In the present embodiment, in the wiring board 100, a surface on which an electronic component is mounted is defined as a front surface AS, and a surface connected to a mother substrate (mother substrate) is defined as a back surface BS. The front surface AS side is defined as the upper side, and the rear surface BS side is defined as the lower side.

  Further, in FIG. 1, a center reference plane O that bisects the thickness of the wiring board 100 in the stacking direction is drawn. In the present embodiment, the upper side of the wiring substrate 100 from the center reference plane O is defined as the upper layer 10, and the lower side of the center reference plane O is defined as the lower layer 20. The layer located on the center reference plane O is defined as the upper layer 10.

  The wiring substrate 100 includes a plurality of ceramic insulating layers IL and a plurality of wiring layers CL disposed between the plurality of ceramic insulating layers IL and having a predetermined pattern. In other words, the wiring board 100 has a multilayer structure in which the ceramic insulating layers IL and the wiring layers CL are alternately stacked. In the present embodiment, the wiring board 100 includes first to sixth six ceramic insulating layers IL1 to IL6 and first to sixth six wiring layers CL1 to CL6.

The ceramic insulating layers IL1 to IL6 are formed with through conductors P1 to P6 that penetrate the ceramic insulating layers IL1 to IL6 in the thickness direction. In the present embodiment, the thickness of the wiring board 100 is 0.6 mm, and the areas of the front surface AS and the back surface BS of the wiring board 100 are 8800 mm ² .

  The ceramic insulating layers IL1 to IL6 are formed by firing ceramic green sheets, and function as insulating layers for insulating the wiring layers CL1 to CL6. Actually, after firing the ceramic green sheet, the ceramic insulating layers IL1 to IL6 are integrated, and the boundary line between the layers is almost disappeared.

  The wiring layers CL1 to CL6 are formed by screen-printing and baking a conductive paste on a ceramic green sheet. In this embodiment, the conductive paste contains at least one component such as Ag (silver), Cu (copper), W (tungsten), or Mo (molybdenum). The wiring layer CL is also called a metallized conductor. In addition, a nickel plating film 31 and a gold plating film 32 are formed on the first wiring layer CL1 formed on the back surface BS of the wiring substrate 100, and functions as a pad for connection to the mother substrate.

  The through conductors P1 to P6 electrically connect the wiring layers CL1 to CL6 of different layers. In this embodiment, the through conductors P1 to P6 are made of a conductive paste containing at least one component such as Ag (silver), Cu (copper), W (tungsten), Mo (molybdenum), etc. It is formed by filling the through-hole formed in and firing. Of the through conductor P6 formed in the sixth ceramic insulating layer IL6, a nickel plating film 35 and a gold plating film 36 are formed on a portion exposed to the surface AS. Then, solder bumps (not shown) are formed on the gold plating film 36, and electronic components are mounted.

In the wiring board 100 configured as described above, the volumes of the conductors (wiring layer CL and penetrating conductor P) included in the wiring board 100 are defined as follows.
Total volume of the wiring layer CL included in the upper layer 10: Vc1 [mm ³ ]
Total volume of the through conductors P included in the upper layer 10: Vp1 [mm ³ ]
Total volume of the wiring layer CL included in the lower layer 20: Vc2 [mm ³ ]
Total volume of through conductors P included in the lower layer 20: Vp2 [mm ³ ]
In this embodiment, the wiring layers CL4, CL5, CL6 and the through conductors P4, P5, P6 belong to the upper layer 10, and the wiring layers CL1, CL2, CL3 and the through conductors P1, P2, P3 are in the lower part. Belongs to layer 20.

In this case, the wiring board 100 of this embodiment satisfies the following relational expression (1).
(Vc1 + Vp1) ≦ (Vc2 + Vp2) (1)
In other words, in this embodiment, the total volume (Vc2 + Vp2) of the conductors (wiring layers CL1, CL2, CL3 and the through conductors P1, P2, P3) included in the lower layer 20 is the conductor ( The total volume (Vc1 + Vp1) of the wiring layers CL4, CL5, CL6 and the through conductors P4, P5, P6) is greater than or equal to. Therefore, according to this embodiment, generation | occurrence | production of the negative curvature after baking can be suppressed. The reason for this is as follows.

  Since the shrinkage ratio of the conductor due to firing is larger than the shrinkage ratio of the ceramic insulating layer IL, the conductor shrinks more than the ceramic insulating layer when fired. Accordingly, if the total volume of the conductors included in the lower layer 20 is equal to or greater than the total volume of the conductors included in the upper layer 10 as in the present embodiment, the lower layer 20 contracts more than the upper layer 10. Therefore, the direction of warping after firing becomes a positive direction, and the occurrence of negative warping can be suppressed.

Furthermore, the wiring board 100 of this embodiment satisfies the following relational expression (2).
(Vc2 + Vp2) − (Vc1 + Vp1) ≦ 100 (2)
In other words, in the present embodiment, the difference between the total volume of the conductors included in the upper layer 10 and the total volume of the conductors included in the lower layer 20 is 100 mm ³ or less. This is because if the difference between the total volume of the conductors contained in the upper layer 10 and the total volume of the conductors contained in the lower layer 20 is small, the shrinkage amount in the upper layer 10 and the shrinkage amount in the lower layer 20 This is because the amount of warpage can be reduced. The basis for defining the difference between the total volume of the conductors included in the upper layer 10 and the total volume of the conductors included in the lower layer 20 to be 100 mm ³ or less will be described later.

  In the present embodiment, the relational expressions (1) and (2) are satisfied by adjusting the diameter of the through conductor P. For this reason, in this embodiment, the diameter of the through conductor P included in at least one of the plurality of ceramic insulating layers IL is different from the diameter of the through conductor P included in the ceramic insulating layer IL of the other layers. It has become. Specifically, in this embodiment, the diameters of the through conductors P4 and P5 included in the fourth and fifth ceramic insulating layers IL4 and IL5 are all 0.08 mm, and the other ceramic insulating layers IL1 and IL2 The diameters of the through conductors P1, P2, P3, and P6 included in IL3 and IL6 are all 0.10 mm.

  In the present embodiment, the diameters of the through conductors P included in the same ceramic insulating layer IL are all the same. This is because if the diameters of the through conductors P included in the same ceramic insulating layer IL are different, the process of forming the through conductors P becomes complicated. Therefore, as in this embodiment, the diameters of the through conductors P included in the same ceramic insulating layer IL are all set to the same size, and the above relational expressions (1) and (2) are satisfied. If the diameters of the through conductors P are different for each layer, it is possible to suppress the occurrence of negative warping after firing while avoiding complicated manufacturing processes.

  FIG. 2 is a process diagram showing a manufacturing process of the wiring board 100. FIGS. 3 to 7 are explanatory views showing the manufacturing process of the wiring board 100. In step S100, a plurality of ceramic green sheets are created. Specifically, ceramic green sheets G1 to G6 are prepared by mixing alumina powder, an organic binder, a solvent, glass powder, and the like to form a ceramic slurry, and performing a doctor blade method on this ceramic slurry (see FIG. 3).

  In step S110, the ceramic green sheets G1 to G6 are punched to form through holes (through holes) H1 to H6 (FIG. 4). In step S120, conductive paste is printed and filled in the formed through holes H1 to H6 (FIG. 5). Thereby, unfired through conductors P1 to P6 are formed in the through holes H1 to H6. In addition, the electrically conductive paste of this embodiment contains at least any one component, such as Ag, Cu, W, Mo.

  In step S130, a conductive paste is screen-printed on the front and back surfaces of the ceramic green sheet to form an unfired wiring layer CL (FIG. 6). In step S140, a plurality of ceramic green sheets G1 to G6 are stacked in the thickness direction and pressed to form a stacked body 99 (FIG. 7).

  In step S150, the obtained laminate 99 is baked at a predetermined temperature to form the wiring board 100. In step S160, nickel plating and gold plating are performed on the conductor exposed on the front surface AS and the back surface BS of the wiring board 100 to form nickel plating films 31 and 35 and gold plating films 32 and 36 having a predetermined thickness. (FIG. 1).

  When an electronic component is mounted on the surface AS of the wiring substrate 100, a substantially hemispherical solder bump (not shown) is formed on the plated through conductor P6. Then, a flat surface is pressed against the formed solder bump and pressed to flatten the substantially hemispherical top of the solder bump. The reason for flattening the substantially hemispherical top is to make the heights of the plurality of solder bumps uniform and to prevent the electrodes of the electronic component from slipping out of the top of the solder bump.

  In the present embodiment, when designing the structure of the wiring board 100 prior to the above manufacturing process, after designing the circuit pattern of the wiring layer CL and the arrangement of the through conductors P, the wiring board 100 has the above relational expression ( The diameter of the through conductor P (equal to the diameter of the through hole H formed in the insulating layer) is determined so as to satisfy 1) and (2).

  Specifically, for example, the diameters of the through conductors P are all designed to be the same size, and the total volume of the conductors included in the upper layer 10 is larger than the total volume of the conductors included in the lower layer 20. In some cases, the diameter of the through conductor P included in the upper layer 10 is changed to be small so that the total volume of the conductors included in the lower layer 20 is equal to or greater than the total volume of the conductors included in the upper layer 10. To. In the example shown in FIG. 1, in order to reduce the volume of the conductor included in the upper layer 10, the diameters of the through conductors P4 and P5 in the fourth and fifth ceramic insulating layers IL4 and IL5 are from 0.10 mm to 0.08 mm. Has been changed.

  If the diameter of the through conductor P6 in the uppermost layer (sixth ceramic insulating layer IL6) is changed to a small diameter, the solder bumps formed on the surface AS are reduced, and the mountability of the electronic component is lowered. . Therefore, the diameter of the through conductor P6 in the uppermost layer is preferably not changed to a small diameter, and is preferably equal to or larger than a predetermined size. Specifically, the diameter of the through conductor P6 in the uppermost layer is preferably 0.10 mm or more.

Thus, in the present embodiment, the diameter of the through conductor P is determined so that the total volume of the conductors included in the lower layer 20 is equal to or greater than the total volume of the conductors included in the upper layer 10. Therefore, generation | occurrence | production of the negative curvature after baking can be suppressed. Furthermore, in this embodiment, the diameter of the through conductor P is large so that the difference between the total volume of the conductors included in the upper layer 10 and the total volume of the conductors included in the lower layer 20 is 100 mm ³ or less. Since the thickness is determined, the amount of warpage can be suppressed within an allowable range.

  Further, in this embodiment, the diameters of the through conductors P included in the same ceramic insulating layer IL are all the same, and the diameters of the through conductors P are different for each layer. The direction of warping and the amount of warping can be controlled without complicating the process of forming the conductor P.

  Furthermore, in this embodiment, after designing the circuit pattern of the wiring layer CL and the arrangement of the through conductors P, the diameter of the through conductors P is set so that the wiring board 100 satisfies the above relational expressions (1) and (2). Thus, the circuit pattern of the wiring layer CL and the arrangement of the through conductors P can be freely designed without being restricted.

B. Experimental example:
In this experimental example, a plurality of wiring board samples in which the diameters of the through conductors P are changed are prepared, the volume of the entire conductor included in the upper layer 10 and the lower layer 20 of the wiring board 100, the warping direction and warping after firing. The relationship with quantity was investigated.

  FIG. 8 is an explanatory diagram showing the relationship between the volume of the entire conductor included in the upper layer 10 and the lower layer 20 of the wiring board 100 and the direction and amount of warping after firing in a tabular form. In FIG. 8, the amount of warping in the case of positive warping is indicated by a positive number, and the amount of warping in the case of negative warping is indicated by a negative number. In the comprehensive evaluation, NG was evaluated when a negative warp occurred and when the amount of warp was 300 μm or more even if it was a positive warp. This is because if the amount of warpage is 300 μm or more, the mountability of the electronic component may be reduced, or an influence may occur when connecting to the mother board. Further, when the diameter of the through conductor P was changed, the diameter of the solder bump formed on the uppermost layer was reduced, and the case where there was a problem in the mounting property of the electronic component was evaluated as NG.

In addition, the diameter of the through conductor P of each sample is as follows.
Sample 1: Diameter of through conductors P1 to P6 = 0.10 mm
Sample 2: Through conductors P1 to P3, P5, and P6 diameter = 0.10 mm
Diameter of through conductor P4 = 0.08mm
Sample 3: Diameter of through conductors P1 to P3 and P6 = 0.10 mm
The diameter of the through conductors P4 and P5 = 0.08mm
Sample 4: Diameter of through conductors P1 to P5 = 0.10 mm
Diameter of through conductor P6 = 0.08mm
Sample 5: Diameter of the through conductors P1, P2, and P3 = 0.15 mm,
The diameter of the through conductors P4 and P5 = 0.08mm
The diameter of the through conductor P6 = 0.10 mm
Sample 6: Diameter of the through conductors P1 to P3, P5, and P6 = 0.10 mm
Diameter of through conductor P4 = 0.08mm
Sample 7: Diameter of the through conductors P1 to P3, P5, and P6 = 0.10 mm
Diameter of through conductor P4 = 0.08mm
Hereinafter, evaluation of each sample will be described with reference to FIG.

  In sample 1, since negative warping occurred, the overall evaluation was NG. This is because, in Sample 1, the value of (Vc2 + Vp2) − (Vc1 + Vp1) is a negative value. This is considered to be because the total volume of the conductor is smaller than (Vc1 + Vp1).

  On the other hand, in samples other than sample 1, the value of (Vc2 + Vp2) − (Vc1 + Vp1) is 0 or a positive value, that is, the total volume of conductors included in the lower layer 20 (Vc2 + Vp2) The total volume of the conductors contained in the layer 10 (Vc1 + Vp1) or more, and as a result, a positive warp occurred. Therefore, it can be understood that negative warping does not occur if the total volume of the conductors included in the lower layer 20 is equal to or greater than the total volume of the conductors included in the upper layer 10.

Further, in Sample 5 and Sample 7, warpage of 300 μm or more occurred, so the overall evaluation was NG. The reason for this is considered that the difference between the total volume of the conductors included in the upper layer 10 (Vc1 + Vp1) and the total volume of the conductors included in the lower layer 20 (Vc2 + Vp2) exceeds 100 mm ^3. .

On the other hand, in the samples 2 to 4 and the sample 6, the difference between the total volume of the conductors included in the upper layer 10 and the total volume of the conductors included in the lower layer 20 is 100 mm ³ or less. The amount was less than 300 μm. Therefore, if the difference between the total volume of the conductors included in the upper layer 10 and the total volume of the conductors included in the lower layer 20 is 100 mm ³ or less, the amount of warpage is less than 300 μm, and the amount of warpage is within an allowable range. I can understand that it fits.

  In sample 4, since the diameter of the through conductor P6 in the uppermost layer (sixth ceramic insulating layer IL6) was 0.08 mm, the diameter of the solder bump formed was reduced, and the overall evaluation was NG. Therefore, it can be understood that the diameter of the through conductor P6 in the uppermost layer is preferably larger than 0.08 mm, and more preferably 0.10 mm or more.

C. Variations:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

C1. Modification 1:
The wiring board 100 of the above embodiment satisfies both the relational expressions (1) and (2), but may satisfy only the relational expression (1). Moreover, in the manufacturing method of the wiring board 100 described above, the diameter of the through conductor P is determined so as to satisfy both the relational expressions (1) and (2). However, the relational expression ( The diameter of the through conductor P may be determined so as to satisfy only 1). Even if it does in this way, generation | occurrence | production of the negative curvature after baking can be suppressed.

C2. Modification 2:
In the above embodiment, the wiring substrate 100 having six ceramic insulating layers IL has been described. However, the present invention can also be applied to a wiring substrate having five or fewer ceramic insulating layers IL or seven or more ceramic insulating layers IL. it can.

C3. Modification 3:
In the above embodiment, when manufacturing the wiring substrate 100, the diameters of the through conductors P included in the ceramic insulating layer IL of the same layer are all the same size, and at least one of the plurality of ceramic insulating layers IL. Although the diameter of the through conductor P included in the layer is different from the diameter of the through conductor P included in the ceramic insulating layer IL of the other layer, the through conductor P included in the same ceramic insulating layer IL is used. The diameter may be different. In other words, if the wiring board 100 satisfies the relational expression (1) by forming through conductors having a plurality of types of diameters, the occurrence of negative warping after firing can be suppressed.

DESCRIPTION OF SYMBOLS 10 ... Upper layer 20 ... Lower layer 31 ... Nickel plating film 32 ... Gold plating film 35 ... Nickel plating film 36 ... Gold plating film 99 ... Laminated body 100 ... Wiring board O ... Center reference plane IL1-IL6 ... Ceramic insulating layer CL1- CL6 ... wiring layer P1 to P6 ... through conductor G1 to G6 ... ceramic green sheet H1 to H6 ... through hole AS ... front surface BS ... back surface

Claims (6)

A plurality of ceramic insulating layers;
A plurality of wiring layers disposed between the plurality of ceramic insulating layers;
A wiring board formed in a through-hole penetrating the ceramic insulating layer in the thickness direction, and having a plurality of through conductors electrically connecting the plurality of wiring layers,
The diameters of the through conductors included in the ceramic insulating layer of the same layer are all the same size,
The diameter of the through conductor included in at least one of the plurality of ceramic insulating layers is different from the diameter of the through conductor included in the ceramic insulating layer of the other layer,
When the thickness of the wiring board in the stacking direction is divided into two equal parts,
Define the upper side as the upper layer, the lower side as the lower layer,
The total volume of the wiring layers included in the upper layer is defined as Vc1 [mm ³ ],
The total volume of the through conductors included in the upper layer is defined as Vp1 [mm ³ ],
The total volume of the wiring layers included in the lower layer is defined as Vc2 [mm ³ ],
When the total volume of the through conductors included in the lower layer is defined as Vp2 [mm ³ ],
The following relational expression (1):
Vc1 + Vp1 < Vc2 + Vp2 (1)
The wiring board is characterized in that the lower layer is contracted more than the upper layer by satisfying the above . The wiring board according to claim 1,
Furthermore, the following relational expression (2):
(Vc2 + Vp2) − (Vc1 + Vp1) ≦ 100 (2)
A wiring board characterized by satisfying The wiring board according to claim 1 or 2,
The diameter of the through conductor included in the ceramic insulating layer located on the uppermost side is 0.10 mm or more, and the wiring board is characterized in that: (A) preparing a plurality of ceramic insulating layers;
(B) forming a through conductor in the ceramic insulating layer;
(C) forming a wiring layer on the ceramic insulating layer;
(D) laminating the ceramic insulating layer on which the wiring layer is formed to form a laminated body;
(E) a method of manufacturing a wiring board comprising: baking the laminate to form a wiring board,
When the thickness of the wiring board in the stacking direction is divided into two equal parts,
Define the upper side as the upper layer, the lower side as the lower layer,
The total volume of the wiring layers included in the upper layer is defined as Vc1 [mm ³ ],
The total volume of the through conductors included in the upper layer is defined as Vp1 [mm ³ ],
The total volume of the wiring layers included in the lower layer is defined as Vc2 [mm ³ ],
When the total volume of the through conductors included in the lower layer is defined as Vp2 [mm ³ ],
In the step (b), the wiring board has the following relational expression (1):
Vc1 + Vp1 < Vc2 + Vp2 (1)
Meets, the so than the upper layer in a state where it is contracted in the lower layer, characterized in comprising the step of forming the through conductor of the sizes of a plurality kinds of diameters, the manufacturing method. It is a manufacturing method of the wiring board according to claim 4,
In the step (b), the through conductors included in at least one of the plurality of ceramic insulating layers while the diameters of the through conductors included in the ceramic insulating layers of the same layer are all the same size. diameter of, and the sizes different from the diameter of the through conductors included in said ceramic insulating layer of the other layers, characterized in that it comprises a step of forming the through conductor method. It is a manufacturing method of the wiring board according to claim 4 or 5,
The step (b) further includes the following relational expression (2):
(Vc2 + Vp2) − (Vc1 + Vp1) ≦ 100 (2)
The manufacturing method characterized by including the process of forming the said penetration conductor so that it may satisfy | fill.

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