JP6009833B2 - Power converter - Google Patents

Description

  The present invention relates to a power conversion device having a PWM arm that performs PWM (pulse width modulation) switching of a semiconductor switch and a polarity reversing arm that switches when the polarity of an output voltage command is reversed.

  As a conventional technique, a single-phase inverter (power conversion device) that can reduce loss and cost by combining a PWM arm that performs constant PWM switching and a one-pulse arm that performs switching when the output voltage polarity is switched. ) Is disclosed. A circuit configuration in which the AC output sides of two or more single-phase inverters are connected in series is also generally known.

JP 2009-165222 A

  In a single-phase inverter having a PWM arm that PWMs a semiconductor switch and a polarity reversing arm that switches at the time of polarity reversal of an output voltage command, more surges are generated in the PWM arm than the polarity reversing arm, resulting in an increase in loss. An increase in the required breakdown voltage becomes a problem. In addition, when the polarity changes a plurality of times when the output voltage command value is near zero, the polarity reversing arm switches a plurality of times, which causes an increase in loss. For example, when the load is a train motor, when the wheel slips or the like occurs, the waveform of the output command is disturbed as if noise is mixed. At this time, if the output command value is near zero volts, the polarity reversing arm is switched a plurality of times, that is, the polarity is switched, and the increase in switching loss at this time becomes a problem.

  The embodiment aims at suppressing a surge and reducing a loss of a single-phase inverter and reducing a required breakdown voltage of an element in a power conversion device.

  A power conversion apparatus according to an embodiment includes a PWM arm having serially connected semiconductor switches that perform PWM switching, and a semiconductor switch that is switched in series when the polarity of the output voltage command value is inverted and connected in series. A polarity reversing arm; and a PWM capacitor and a DC capacitor connected in parallel to the polarity reversing arm. A wiring distance between the PWM arm and the DC capacitor is a wiring distance between the polarity reversing arm and the DC capacitor. Shorter.

The figure which shows the structure of the single phase inverter which has a PWM arm and a polarity inversion arm. The figure which shows the structure and operation | movement of a single phase inverter which made the PWM arm the multilevel structure with respect to the structure of FIG. The figure which shows the structure and operation | movement of a single phase inverter which made the polarity reversal arm multi-level structure with respect to the structure of FIG. The figure which shows the structure and operation | movement of a single phase inverter which connected the single phase inverter of FIG. 1 in two steps in series. The figure which shows other operation | movement of the said single phase inverter of FIG. The figure which shows the structure of the single phase inverter which connected in series the single phase inverter which has two PWM arms, and the single phase inverter which has a PWM arm and a polarity inversion arm.

  Hereinafter, an embodiment of a power converter will be described with reference to the drawings.

[Embodiment 1]
The first embodiment will be described with reference to FIG.
Figure 1 is a single-phase inverter comprising a DC capacitor _{C 1} and the polarity inversion arm 100 and PWM arm 101. Polarity inversion arm 100 is composed of a circuit which is connected in anti-parallel with the semiconductor switch Q _1, a diode D _1, a circuit which is connected in anti-parallel with the semiconductor switch Q ₂ and the diode D ₂ are connected in series. PWM arm 101 includes a circuit connected in parallel with the semiconductor switch Q ₃ and a diode D _3, a circuit connected in parallel with the semiconductor switch Q ₄ and the diode D ₄ are connected in series.

The control unit 10 based on the output voltage command _{V out} *, the polarity inversion arm 100 outputs a gate command for polarity inversion driving semiconductor switches _{Q 1} and _{Q 2,} gate command for PWM driving the PWM arm 101 and outputs to the semiconductor switches _{Q 3} and _{Q 4.} The PWM arm 101 is PWM driven and the polarity inversion arm 100 is polarity inversion driven by using the capacitor C ₁ to be charged as a DC power source, whereby an AC voltage is generated at the output terminals T1 and T2. The operation of the polarity inversion arm 100 is a so-called one-pulse operation.

Impedances Z ₁ and Z ₂ represent impedances of wirings or conductors connecting the DC capacitor C ₁ and the PWM arm 101, and impedances Z ₃ and Z ₄ represent impedances of wirings or conductors connecting the DC capacitor C 1 and the polarity inversion arm 100. Represents. For example, the semiconductor switches Q ₁ and Q ₂ constituting the polarity reversing arm 100 are IGBTs, and the semiconductor switches Q ₃ and Q ₄ constituting the PWM arm 101 are FETs. That is, the semiconductor switch of the PWM arm 101 uses a semiconductor element having switching performance faster than that of the polarity reversing arm 100. For the semiconductor switch of the PWM arm 101, a semiconductor element such as SiC (silicon carbide) or GaN (gallium nitride) can be suitably used.

Before describing suppression of surge according to the present embodiment, the principle of surge generation will be described. A surge is generally generated by a change in current and an inductance component (inductance component is one element constituting impedance). When _{Q 3} in Figure 1 is the on-state, _{Q 4} is off, current flows _{Q 3.} From that state, when Q ₃ changes to the OFF state and Q ₄ changes to the ON state, the current starts to flow through Q ₄ , the current of Q ₃ decreases, and the current of Q ₄ increases. At that time, a surge V represented by the following equation is applied to sw ₁ by the inductance components L ₁ and L ₂ of the impedances Z ₁ and Z ₂ between the PWM arm 101 and the DC capacitor and the change ΔI of the flowing current.

V = (L ₁ + L ₂ ) × ΔI / t
t represents time, and the above formula represents that a large surge occurs when a large current change occurs in a short time. Q ₄ are but located low resistance ON state, Q ₃ is for a located high resistance OFF state, a large surge in Q ₃ is applied. Since the PWM arm performs PWM switching, that is, high-speed switching with high frequency, a large current change occurs in a short time. As a result, many large surges occur in the PWM arm.

Therefore, in the mounting, the impedances Z ₁ and Z ₂ can be reduced by connecting the DC capacitor C ₁ and the PWM arm 101 with the shortest distance. That is, in the power conversion device according to the present embodiment, the wiring distance between the PWM arm and the DC capacitor is at least shorter than the wiring distance between the polarity reversing arm 100 and the DC capacitor.

Since most of the switching is performed by the PWM arm, the effect of reducing the surge by reducing the impedances Z ₁ and Z ₂ is greater than reducing Z ₃ and Z ₄ in the same manner. As a result, it is possible to suppress a surge as the entire single-phase inverter and to reduce switching loss.

[Embodiment 2]
A second embodiment will be described with reference to FIG.
FIG. 2A is a diagram showing a configuration of a single-phase inverter in which the PWM arm is a neutral point clamp type (NPC) multi-level circuit with respect to the configuration of FIG. The PWM arm is configured by connecting four parallel circuits of semiconductor switches and diodes in series. The number of stages (number of circuits) in which the parallel circuit of the semiconductor switch and the diode is connected in series is not limited to 4 as a multilevel circuit, and 2M (M is an integer of 2 or more) can be applied.

A series circuit of diodes is connected in parallel to both ends of the series circuit of the semiconductor switches Q ₄ and Q ₅ , and an interconnection point of these diodes is connected to a midpoint N. The polarity reversing arm is configured in the same manner as the circuit of FIG. A series circuit of capacitors C ₃ and C ₄ is connected in parallel to the PWM arm and the polarity inversion arm, and the interconnection point of these capacitors C ₃ and C ₄ is a neutral point N. Output terminals T1, T2 is connected to the connection point of the semiconductor switches _{Q 4} and the connection point and the semiconductor switch to _{Q 1 Q 5} and _{Q 2.}

Impedances Z _{1 to} Z ₅ indicate impedances of wiring for connecting the series circuit of the capacitors C ₃ and C ₄ , the PWM arm, and the polarity inversion arm in parallel with each other. Also in the present embodiment, each of the impedances Z ₁ , Z ₂ , and Z ₅ is smaller than any of the impedances Z ₃ and Z ₄ . That is, the wiring distance between the PWM arm and the capacitor is shorter than at least the wiring distance between the polarity reversing arm and the capacitor.

Figure 2 (b) is a diagram showing an output voltage _{V out} corresponding to the gate command semiconductor switches _Q 1 to Q _6. FIG. 2C shows waveforms showing a switching sequence, voltage V ₁ , voltage V ₂ , and output voltage V _out of the semiconductor switches Q _{1 to} Q ₆ . Based on the input output voltage command V _out *, the control unit 11 outputs a gate command shown in FIG. 2B to each of the semiconductor switches Q _{1 to} Q ₆ to control the power converter.

The voltages of the capacitors C ₃ and C ₄ are both set to Vdc. The voltage V ₁ is the output voltage of the PWM arm having the NPC configuration (the voltage between the neutral point N and the terminal T ₁ ), and the voltage V ₂ is the output voltage of the polarity inversion arm (the voltage between the neutral point N and the terminal T ₂ ). . Voltages _{V 1,} as shown in FIG. 2 (c), Vdc, 0 , it is possible to three-level output of the -Vdc. As shown in FIG. 2B, the output voltage _Vout becomes five levels of 2Vdc, Vdc, 0, −Vdc, and −2Vdc by the on / off control of the semiconductor switches Q _{1 to} Q ₆ . Further, as shown in FIG. 2B, there are two patterns of control methods for controlling the semiconductor switches Q _{1 to} Q ₆ only when the zero voltage of the voltage V _out is output. As shown in FIG. 2 (c), the command value _{V 1} * voltages _{V 1} has a waveform obtained by subtracting the output voltage of _{V 2} from the output command value _{V out} * of _{V out.} Also as shown in FIG. 2 (c), the output voltage _{V out} is the voltage _{V 1} and the voltage difference between the voltage of V2 _(V 1 -V _2).

  With the multi-level PWM arm, the output voltage of the PWM inverter becomes multi-stage, and the switching frequency of each semiconductor switch required to obtain the same switching frequency as before multi-stage is inversely proportional to the multi-stage number. As a result, loss of each semiconductor switch constituting the PWM arm can be reduced.

  Further, although FIG. 2 represents a neutral point clamp type multilevel circuit, it can also be configured by a flying capacitor system or a modular multilevel system.

[Embodiment 3]
A third embodiment will be described with reference to FIG.
FIG. 3A is a diagram showing a configuration of a single-phase inverter in which the polarity reversing arm is a neutral point clamp type multilevel circuit. The polarity inversion arm is configured by connecting an antiparallel circuit of a semiconductor switch and a diode in four circuits in series. Note that the number of stages (number of circuits) in which the antiparallel circuit of the semiconductor switch and the diode is connected in series is not limited to 4 as a multilevel circuit, and 2M (M is an integer of 2 or more) can be applied.

A series circuit of diodes is connected in parallel to both ends of the series circuit of the semiconductor switches Q ₁₂ and Q ₁₃ , and an interconnection point of these diodes is connected to a midpoint N. The PWM arm is configured similarly to the circuit of FIG. A series circuit of capacitors C ₃ and C ₄ is connected in parallel to the PWM arm and the polarity inversion arm, and the connection point of these capacitors C ₃ and C ₄ is a neutral point N. Output terminals T1, T2 is connected to the connection point of the semiconductor switches _{Q 15} and _{Q 16} at the connection point of the semiconductor switches _{Q 12} and _{Q 13.}

Impedances Z _{1 to} Z ₄ and Z ₆ indicate impedances of wirings for connecting the series circuit of the capacitors C ₃ and C ₄ , the PWM arm, and the polarity inversion arm in parallel with each other. Also in this embodiment, each of the impedances Z1, Z2, impedance _{Z 3,} Z 4, smaller than either of _{Z 6.} That is, the wiring distance between the PWM arm and the capacitor is shorter than at least the wiring distance between the polarity reversing arm and the capacitor.

3 (b) is a diagram showing an output voltage _{V out} corresponding to the gate command of the semiconductor switch _Q 11 _{to Q 16.} FIG. 3C shows waveforms showing the switching sequence, voltage V ₃ , voltage V ₄ , and output voltage V _out of the semiconductor switches Q _{11 to} Q ₁₆ . Based on the input output voltage command V _out *, the control unit 12 outputs a gate command shown in FIG. 3B to each of the semiconductor switches Q _{11 to} Q ₁₆ to control the power converter.

Voltage _{V 3} is the output voltage of the PWM arm and NPC configuration (voltage across neutral points N and the terminal T1), the voltage _{V 4} is the polarity inversion arm of the output voltage (voltage across neutral points N and the terminal T2). As shown in FIG. 3C, V ₃ can output three levels of Vdc, 0, and −Vdc. The output voltage _{V out,} as shown in FIG. 3 (b), the on-off control of the semiconductor switch _{Q 11 ~Q 16, 2Vdc, Vdc} , 0, -Vdc, the five-level -2Vdc. As also FIG. 3 (b), the time of zero voltage output of the voltage _{V out} only, there is a method of controlling the two patterns as a control method of the semiconductor switch _Q 11 _{to Q 16.} As shown in FIG. 3 (c), * command value _{V 3} of the voltage _{V 3} has a waveform obtained by subtracting the output voltage of _{V 4} from the output command value _{V out} * of _{V out.} Also as shown in FIG. 3 (c), the output voltage _{V out} is the difference voltage of the voltage _{V 3} and the voltage _{V 4 (V 3 -V 4)} .

  According to the present embodiment, by making the polarity reversing arm multi-level, it is possible to use a relatively low breakdown voltage semiconductor element for the polarity reversing arm, and it is possible to use a semiconductor element with lower loss. As a result, the loss of the polarity reversing arm can be reduced.

[Embodiment 4]
A fourth embodiment will be described with reference to FIGS.
4 (a) is a diagram showing a configuration of a power converter connected in series AC output terminals of the single-phase inverters 200,21 0 each having PWM arms and the polarity inversion arm.

The configuration of single-phase inverters 200 and 210 is the same as that of the single-phase inverter of FIG. The output terminal T3 is connected to a connection point of the semiconductor switches _{Q 25} and _{Q 26} (PWM arm 202 output), the output terminal T4 is connected to a connection point of the semiconductor switches _{Q 23} and _{Q 24} (inversion arm 211 output) The Connection point of the semiconductor switches _{Q 21} and _{Q 22} (inversion arm 201 output) is connected to a connection point of the semiconductor switches _{Q 27} and _{Q 28} (PWM arm 212 output).

4B shows the gate command of the semiconductor switches Q _{21 to} Q ₂₄ and the voltage V ₅ (the connection point E between the inverters 200 and 210 and the AC voltage command value V _inv * of the power converter shown in FIG. waveform of the voltage) between the output terminal T3, a diagram showing the waveform of voltage _{V 6} (connecting point E to the voltage between the output terminal T4 of the inverter 200, 210). Based on the input output voltage command value V _inv *, the control unit 13 outputs a gate command to each of the semiconductor switches Q _{21 to} Q ₂₈ to control the power converter.

Gate command of FIG. 4 (b) shows a case of delaying the switching of the polarity inversion arm ₂₁₁ of the single-phase inverter _{2 10 (Q 23, Q 24} ). The polarity reversing arm 211 composed of the semiconductor switches Q ₂₃ and Q ₂₄ switches the polarity at predetermined threshold points Vth and −Vth, not at the zero cross point of the command value V _inv *.

The output voltage V _inv of the power conversion device is a voltage obtained by adding the output voltage V ₅ of the inverter 200 and the output voltage V ₆ of the inverter 210. In polar state different periods P1, P2 of the polarity inversion arms 201, 211 of the inverter 200 and 210, the output voltage _{V 6} of the inverter 210 is a zero, the output voltage _{V inv} only by the output voltage _{V 5} of the inverter 200 is Generated.

When the command value V _inv of the power converter is near zero and the polarity changes a plurality of times due to the influence of disturbance, the command to switch the polarity reversing arm 211 is delayed and the command of the polarity reversing arm that has been switched once is latched. As a result, when the command value V _inv is near zero, the polarity reversing arm can be operated without switching a plurality of times.

  FIG. 5 shows an example in which the switching of the polarity reversing arm is accelerated as opposed to FIG. The effect similar to that of the configuration of FIG. 4B can also be obtained by switching the polarity inversion arm earlier.

  The time for delaying or speeding up the command of the polarity reversing arm of the single-phase inverter may be set individually for each single-phase inverter. For example, in the configuration of FIG. 4, the polarity inversion timing of the polarity inversion arm 201 of the inverter 200 may be advanced, and the polarity inversion timing of the polarity inversion arm 211 of the inverter 210 may be delayed.

  In addition, the polarity reversing arm that reverses the polarity after a predetermined time or before the predetermined time from the polarity reversal of the output voltage command value may be replaced at a constant cycle among the plurality of polarity reversing arms. Thereby, the loss of each single phase inverter 200, 210 can be equalized.

4 and 5, since two single-phase inverters are connected in series and one single-phase inverter that delays or speeds up the timing, 1/2 of the maximum amplitude of the voltage command V _inv of the power converter is polarity-inverted. Threshold. As another configuration, when n single-phase inverters are connected in series (n is an integer) and the number of single-phase inverters that delay or accelerate the timing is m (m is an integer less than n), the voltage command V _inv A threshold is set for each 1 / (m + 1) of the maximum amplitude, and the polarity inversion arm of one single-phase inverter is switched at each threshold. For example, when three single-phase inverters are connected in series, the polarity reversal threshold is set at an interval of 1/3 of the maximum amplitude of the voltage command _Vinv .

[Embodiment 5]
Next, Embodiment 5 will be described with reference to FIG.
FIG. 6 shows a power conversion device in which the AC terminal side of a single-phase inverter 300 having two PWM arm circuits and a single-phase inverter 310 having a PWM arm and a polarity inversion arm are connected in series.

Since the single-phase inverter 300 having two PWM arms does not have a polarity reversing arm, it differs from a single-phase inverter having a polarity reversing arm in the vicinity of zero of the output command value of the power converter. Does not occur. Therefore, even when the polarity of the output voltage command V _inv of the power conversion device changes near zero, the polarity reversing arm need not be switched multiple times, and the loss of the polarity reversing arm can be reduced.

  In FIG. 6, one inverter having two PWM arms and one inverter having a PWM arm and a polarity reversing arm are provided, but a plurality of inverters may be provided.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

_{Q 1 ~Q 6, Q 11 ~Q} 16, Q 21 ~Q 28 ... semiconductor _{switches, D} 1 ~D 4 _{... diodes, Z} 1 ~Z 6 _... impedance.

Claims (8)

A PWM arm comprising semiconductor switches connected in series each for PWM switching;
A polarity reversing arm comprising semiconductor switches connected in series, each switching at the time of polarity reversal of the output voltage command value,
A DC capacitor connected in parallel to the PWM arm and the polarity reversing arm;
The power converter according to claim 1, wherein a wiring distance between the PWM arm and the DC capacitor is shorter than a wiring distance between the polarity reversing arm and the DC capacitor. Examples semiconductor element used in the PWM arm, the power converter according to claim 1, characterized in that the polarity reversal arm capable of high-speed switching from the semiconductor element used in a semiconductor element is used. PWM arms each having 2M (M is an integer of 2 or more) semiconductor switches connected in series for PWM switching;
A polarity reversing arm comprising semiconductor switches connected in series, each switching at the time of polarity reversal of the output voltage command value,
A capacitor series circuit in which capacitors are connected in series;
The capacitor series circuit is connected in parallel to the PWM arm and the polarity inversion arm ;
The power converter according to claim 1, wherein a wiring distance between the PWM arm and the capacitor is shorter than a wiring distance between the polarity reversing arm and the capacitor . A PWM arm comprising semiconductor switches connected in series each for PWM switching;
A polarity reversing arm comprising 2M semiconductor switches (M is an integer of 2 or more) connected in series, and switching when the polarity of the output voltage command value is reversed;
A capacitor series circuit in which capacitors are connected in series;
The capacitor series circuit is connected in parallel to the PWM arm and the polarity inversion arm ;
The power converter according to claim 1, wherein a wiring distance between the PWM arm and the capacitor is shorter than a wiring distance between the polarity reversing arm and the capacitor . A power converter comprising a plurality of single-phase inverters whose output ends are connected in series, and a control unit that controls each single-phase inverter,
Each single-phase inverter
A PWM arm comprising semiconductor switches connected in series each for PWM switching;
Switching in synchronization with the polarity reversal of the output voltage command value, respectively, and a polarity reversing arm comprising semiconductor switches connected in series,
A DC capacitor connected in parallel to the PWM arm and the polarity reversing arm;
The control unit reverses the polarity of at least one of the polarity reversing arms after a predetermined time or a predetermined time since the polarity reversal of the output voltage command value. The control unit, the polarity inversion arms of two or more single-phase inverters, the timing of inverting the polarity, the power converter according to claim 5, wherein the set individually by the two or more single-phase inverter.   The control unit replaces the polarity inversion arm that reverses the polarity after a predetermined time or before the predetermined time from the polarity inversion of the output voltage command value in a plurality of polarity inversion arms at a constant period. The power conversion device according to claim 5. The power converter according to claim 5 , wherein a wiring distance between the PWM arm and the DC capacitor is shorter than a wiring distance between the polarity reversing arm and the DC capacitor.

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