JP6009525B2 - Game machine - Google Patents

Description

The present invention, Yu technique can perform a pachinko machine or a slot machine, relates to a gaming machine such as Parrott machine.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of game media are paid out to the player. There is something to be done. Also, when a game medium is inserted, a predetermined number of bets are set, multiple types of symbols are rotated by operating the operation lever, and a combination of stop symbols is specified when the symbols are stopped by operating the stop button There are cases where a predetermined number of premium game media are paid out to the player. Also, when a predetermined number of bets are set according to the number of game media taken in, a plurality of types of symbols are rotated by operating the operation lever, and the symbols are stopped when the symbols are stopped by operating the stop button. When the combination becomes a combination of specific symbols, a predetermined number of game media may be paid out to the player.

  Game progress in the gaming machine is controlled by game control means such as a microcomputer. If the payout control means for controlling the payout of game media is mounted on a payout control board different from the game control board (main board) on which the game control means is mounted, the progress of the game is mounted on the main board Therefore, the number of prize game media based on the winning is determined by the game control means, and a control command indicating the number of prize game media is transmitted to the payout control board. Then, the payout control means performs a process of paying out the prize game medium based on the winning based on the control command from the game control means.

  In addition, there is a game machine configured to execute an initialization process and a game state restoration process based on backup data when power supply to the game machine is started (for example, Patent Document 1). For example, Patent Document 1 discloses that when power supply to a gaming machine is started, the internal state is restored to the power-off state based on the backup data stored in the backup RAM area. It is described that it is possible to prevent the player from being disadvantaged and to improve the convenience of operating the gaming machine at the game store by executing the initialization process based on the clear switch being turned on. It is.

JP 2001-327727 A (paragraphs 0059-0063, paragraph 0241, FIG. 8)

  Generally, in a gaming machine, when an initialization process is executed, a random number circuit is also initialized. Therefore, immediately after the initialization process is executed, the update of the hardware random number is started from the initial value, so the random number value is relatively easy to predict and the big hit is likely to be targeted. In the gaming machine described in Patent Document 1, no measures are taken to prevent the act of resetting the power supply in a state where the clear switch is illegally turned on by inserting a device through the gap of the gaming machine during gaming. Therefore, the random number circuit is illegally initialized during the game, and there is a possibility that an illegal act aiming for a big hit is performed.

  In view of the above, an object of the present invention is to provide a gaming machine that can prevent an illegal act by preventing an initialization process from being executed illegally.

A gaming machine according to the present invention is a gaming machine capable of playing a game, a game control means for controlling the progress of the game, an electrical part control means for controlling electrical parts provided in the gaming machine, and a gaming machine An opening / closing door (for example, a game frame including a mechanism board) provided on the door is operable by opening it, and includes an initialization operation means (for example, a clear switch 921) that outputs an operation signal according to the operation. The game control means determines whether or not an operation signal is input from the initialization operation means when the power to the gaming machine is turned on (for example, a step in the game control microcomputer 560). S7 and the portions for performing), when the power to the game machine is turned on, determines the open state determining means for determining whether or not an open state (e.g., a microcomputer 5 for game control The step of executing step S7a at 0) and the operation signal determining means determine that the operation signal has been input and the open state determining means determines that the open state has been established. Initialization processing execution means to be executed (for example, a portion of the game control microcomputer 560 that proceeds to step S10 when step S7a is Y and executes steps S10 to S14), and when initialization processing is executed, An initialization command output means for outputting an initialization command for initializing the electrical component control means, and an initialization process executed by the initialization process execution means based on the determination that the release state determination means is not in the open state. Initialization limiting means for limiting execution (eg, in the game control microcomputer 560, the After executing step S7b when N in flop S7a, the process proceeds to loop processing as it is, with partial) to not perform the steps S10 to S14, upon detecting a predetermined abnormality and deactivation of the proceeding of the game, look including the deactivation means, deactivation due to deactivation means, by restoring the power to the gaming machine, it is determined that the operation signal by the operation signal determination means is input and an open state determining means It is canceled when the initialization process is executed by the initialization process execution unit based on the determination of the open state . With such a configuration, unauthorized actions can be prevented by preventing the initialization process from being executed illegally.

  The gaming machine has notification processing execution means (for example, a part for executing step S630 in the production control microcomputer 100) for executing a predetermined notification process based on the determination that the opening state determination means is not in the open state. It may be configured to include. According to such a configuration, it is possible to notify that there is a possibility that fraud is being performed, and it is possible to strengthen measures for preventing fraud.

  The gaming machine is a game control process executing means for executing a game control process for controlling the progress of the game (for example, a part for executing steps S21 to S39 (excluding steps S31 and S33) in the game control microcomputer 560). The disabling means for disabling the execution of the game control process by the game control process executing means based on the determination that the open state determining means is not in the open state (for example, in the game control microcomputer 560, step After executing step S7b when N in S7a, the process proceeds to the loop processing as it is, and the step S16 is not executed, so that the steps S21 to S39 are not executed). Also good. If it is detected that there is a possibility of cheating, continuation of the game can be disabled, and measures for preventing cheating can be strengthened.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a relay board | substrate, an effect control board, a lamp driver board | substrate, and an audio | voice output board | substrate. It is a block diagram which shows the structural example of a power supply board. It is a timing diagram which shows typically the state of a reset signal and a power-off signal. It is a block diagram which shows the structural example of the microcomputer for game control. It is a figure which shows an example of the address map in the microcomputer for game control. It is a figure which illustrates the main part of a program management area and a built-in register. It is a figure which shows an example of the setting content in a header and function setting. It is a figure which shows an example of the setting content in 1st random number initial setting, 2nd random number initial setting, and interruption initial setting. It is a figure which shows an example of the setting content in security time setting. It is a figure which shows the structural example etc. of an internal information register. It is a block diagram which shows the structural example of a random number circuit. It is a figure which shows the structural example etc. of a random number sequence change register. It is explanatory drawing which shows the change operation | movement of the random number update rule by a random number sequence change circuit. It is explanatory drawing which shows the change operation | movement of the random number update rule by a random number sequence change circuit. It is a figure which shows the structural example etc. of a random value acquisition register. It is a figure which shows the structural example etc. of a random number latch selection register. It is a figure which shows the structural example of a random value register. It is a figure which shows the structural example etc. of a random number latch flag register. It is a figure which shows the structural example etc. of a random number interrupt control register. It is a figure which shows the structural example in case a random number circuit is externally attached to the microcomputer for game control. It is a figure which shows the structural example etc. of an input port register. It is a block diagram which shows the structural example of the transmission part of a serial communication circuit. It is a block diagram which shows the structural example of the receiving part of a serial communication circuit. It is explanatory drawing which shows the example of the data format of the data which a serial communication circuit transmits / receives with the microcomputer mounted in each control board. It is explanatory drawing which shows the example of a baud rate register. It is explanatory drawing which shows the example of the control register A and communication format setting data. It is explanatory drawing which shows the example of the control register B and interrupt request setting data. It is a figure which shows the example of status register A and status confirmation data. It is a figure which shows the example of status register B and status confirmation data. It is explanatory drawing which shows the example of the control register C and error interrupt request setting data. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows the example of the table memory for jackpot determination. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a flowchart which shows the security check process which CPU in a main board | substrate performs. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows an example of a random number circuit setting process. It is a flowchart which shows an example of a random number circuit abnormality test | inspection process. It is a flowchart which shows a 4 ms timer interruption process. It is a flowchart which shows an example of a power-off process. It is a flowchart which shows an example of a power-off process. It is explanatory drawing which shows an example of the content of the control signal output with respect to the payout control means from a game control means. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is explanatory drawing which shows the example of the error information set to a connection OK command and a prize ball preparation command. It is a block diagram which shows the signal line etc. which are used for transmission / reception of a control signal and a control command. It is a sequence diagram showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer during normal operation. FIG. 6 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer during a prize ball operation. FIG. 6 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer during a prize ball operation. FIG. 10 is a sequence diagram showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a winning ball operation cannot be executed immediately. FIG. 5 is a timing chart showing signal transmission and reception between a game control microcomputer and a payout control microcomputer during normal operation. FIG. 10 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when an error occurs during a winning ball. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during connection confirmation. FIG. 5 is a timing chart showing signal transmission / reception between a game control microcomputer and a payout control microcomputer when a communication error occurs during award ball number notification. It is a flowchart which shows an example of a prize ball process. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball command output counter addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball transmission processing 1. It is a flowchart which shows a prize ball connection confirmation process. It is a flowchart which shows the prize ball transmission process 2. FIG. It is a flowchart which shows a prize ball receipt confirmation process. It is a flowchart which shows a prize ball completion | finish confirmation process. It is a flowchart which shows a prize ball counter subtraction process. It is a flowchart which shows an example of a frame state output process. It is explanatory drawing which shows the specific example of EXT data set to a frame state display command. It is a flowchart which shows an example of a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is a flowchart which shows an example of a special symbol normal process. It is explanatory drawing which shows each 2 byte buffer formed in RAM used by switch processing. It is a flowchart which shows the process example of a switch process. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a main control communication process. It is a flowchart which shows a main control command reception process. It is a flowchart which shows a main control connection confirmation process. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows the process during main control communication. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is a flowchart which shows a main control transmission command conversion process. It is a flowchart which shows payout control processing. It is a flowchart which shows the payout start waiting process. It is a flowchart which shows a payout motor stop waiting process. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is a flowchart which shows payout passage waiting processing. It is explanatory drawing which shows an example of the relationship between the kind of error, and the display of LED for an error display. It is a flowchart which shows an error process. It is a flowchart which shows an error process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows the main process which CPU for production control performs. It is a flowchart which shows the specific example of a command analysis process. It is a flowchart which shows production control process processing. It is a timing chart for demonstrating operation | movement in a random number circuit. 7 is a timing chart for explaining a read operation of a random value register, and the like. It is a timing chart for demonstrating the operation | movement etc. at the time of the fall of a power supply voltage. FIG. 11 is a front view of a slot machine as a modification of the gaming machine according to the present invention as viewed from the front. It is a block diagram which shows the circuit structural examples, such as a game control board (main board) and an effect control board, in a slot machine.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) that can be opened and closed with respect to the outer frame, and a mechanism plate to which mechanical parts and the like are attached is attached to the front frame. Various parts are also attached to the front frame.

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  In the vicinity of the center of the game area 7, there is provided an effect display device (decorative symbol display device) 9 including a plurality of variable display portions each variably displaying an effect decorative symbol (effect symbol). The effect display device 9 includes, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The effect display device 9 performs variable display of the effect symbol as a symbol for decoration (for effect) during the variable display period of the special symbol by the special symbol indicator 8. The effect display device 9 that performs variable display of effect symbols is controlled by an effect control microcomputer mounted on the effect control board.

  Below the effect display device 9, four special symbol hold memory indicators 18 are provided for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the number of hold memories (also referred to as start memory or start prize memory). ing. The special symbol reservation storage display 18 displays up to four reservation storage numbers in the order of winning. The special symbol hold storage display 18 increases the number of LEDs in the lit state by 1 each time there is a start winning in the start winning opening 14. Then, each time the special symbol display 8 starts variable display, the special symbol hold storage indicator 18 reduces the number of LEDs in the lit state by 1 (that is, turns off one LED). Specifically, the special symbol hold storage display 18 shifts the lighting state each time variable display is started on the special symbol display 8. In this example, the upper limit number (up to 4) is provided for the number of starting memories by winning to the start winning opening 14, but the upper limit number may be four or more.

  A special symbol display (special symbol display device) 8 that variably displays a special symbol as identification information is provided on the top of the effect display device 9. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display a larger number of numbers such as 0 to 99 in order to make it difficult for the player to grasp a specific stop symbol. Further, the effect display device 9 performs variable display of the effect symbol as a symbol for decoration (for effect) during the variable display period of the special symbol by the special symbol indicator 8.

  Below the effect display device 9, a variable winning ball device 15 that forms a start winning opening 14 is provided. The variable winning ball device 15 is configured to be able to open and close the wings, and when the wings are open, the game ball is likely to win a prize (open state), and when the wings are not open (closed). The game ball becomes difficult to win (closed state). The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. In this embodiment, as will be described later, on the basis of the detection of the game ball by the start port switch 14a, the special symbol variation display is started, and the prize ball payout is executed. The variable winning ball device 15 is opened by a solenoid 16. The first winning prize opening may be provided directly above the variable winning ball apparatus 15, and the variable winning ball apparatus 15 may be used as the second starting prize opening.

  Below the variable winning ball apparatus 15, a special variable winning ball apparatus 20 using an opening / closing plate that is controlled to be opened by a solenoid 21 in a specific gaming state (big hit state) is provided. The special variable winning ball apparatus 20 is a means for opening and closing the big winning opening. The winning ball that has won the special variable winning ball device 20 and led to the back of the game board 6 is detected by the count switch 23.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting left and right lamps (designs can be visually recognized when lit). For example, if the left lamp is lit at the end of variable display, it is a hit. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time the variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29 and 30, and winning of game balls to the winning holes 29 and 30 is detected by winning hole switches 29a and 30a, respectively. Each of the winning ports 29 and 30 constitutes a winning area provided on the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. In addition, it may be configured to detect with a detection switch that a game ball has passed a predetermined area (for example, a gate), instead of the configuration in which the game ball won in each winning opening 29, 30 is detected with a prize switch. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine. In this embodiment, the case where the light emitter provided in the gaming machine is configured by using a lamp or an LED is shown. However, the present invention is not limited to the mode shown in this embodiment. You may make it comprise all the provided light-emitting bodies using LED.

  Although not shown in FIGS. 1 and 2, a prize ball lamp that is turned on during the prize ball payout is provided in the vicinity of the left frame lamp 28b, and a supply ball is provided in the vicinity of the top frame lamp 28a. There is a ball-out lamp that illuminates when it runs out. Note that the award ball lamp and the out-of-ball lamp are controlled to be turned on by the effect control microcomputer mounted on the effect control board when the award ball is being paid out or when the out-of-ball is detected. Further, a prepaid card unit (hereinafter referred to as “card unit”) 50 that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1.

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, and a card unit. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock for releasing the card unit is provided.

  A game ball launched from the ball striking device by the player's operation enters the game area 7 through the hit ball rail, and then descends the game area 7. When the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, the special symbol on the special symbol display 8 starts variable display (variation) if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the number of reserved memories is increased by one.

  The variable display of the special symbol on the special symbol display device 8 stops when a certain time has elapsed. If the special symbol (stop symbol) at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the special variable winning ball apparatus 20 is released until a predetermined time elapses or a predetermined number (for example, 10) of gaming balls wins. The opening of the special variable winning ball apparatus 20 is allowed until the last round of the determined number of rounds (for example, up to 15 rounds).

  When the special symbol on the special symbol display 8 at the time of stoppage is a jackpot symbol (probability variation symbol) with a probability variation, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball passes through the gate 32, the normal symbol display unit 10 enters a state in which the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time.

  In addition, as shown in FIG. 2, above the game board, a door (in this example, a glass door frame 2) is in a closed state (covering the game area 7 or in a state where the game area 7 can be contacted from the outside). (Specifically, detecting whether or not the glass door frame 2 is opened with respect to the front frame to which the game board 6 having the game area 7 formed on the front surface is attached). A door opening sensor 155A is attached. In addition, the state of the mechanism plate (a closed state in which the inside of the gaming machine cannot be contacted from the outside or an open state in which the inside of the gaming machine can be contacted from the outside) is detected above the gaming board (specifically, the gaming area on the front side) A mechanism plate opening sensor 155B for detecting whether or not the mechanism plate has been opened is attached to the front frame to which the game board 6 on which the game board 6 is formed is attached. In addition, you may comprise so that the state of a door body (in this example, the glass door frame 2) and the state of a mechanism board may be detected using a common open sensor.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side. As shown in FIG. 3, on the back side of the pachinko gaming machine 1, a variable display control unit including an effect control board 80 on which an effect control microcomputer 100 for controlling the effect display device 9 is mounted, a game control microcomputer, and the like are provided. Various boards such as a mounted game control board (main board) 31, an audio output board 70, a lamp driver board 35, and a payout control board 37 mounted with a payout control microcomputer for performing ball payout control are installed. Yes. The game control board 31 is stored in the board storage case 200.

  Further, on the back side of the pachinko gaming machine 1, a power supply substrate 910 and a touch sensor substrate 91 on which power supply circuits for generating various power supply voltages such as DC30V, DC21V, DC12V, and DC5V are mounted. The power supply board 910 is supplied with the game control board 31 and each electrical component control board (the effect control board 80 and the payout control board 37) in the pachinko gaming machine 1 and each electrical component (power is supplied) provided in the pachinko gaming machine 1. A power switch as a power supply permission means for executing or shutting off the power supply to the component), and a clear switch for clearing the RAM 55 of the game control microcomputer 560 of the game control board 31 are provided. ing. Further, a replaceable fuse is provided inside the power switch (inside the substrate).

  In this embodiment, the main board 31 is provided on the game board side, and the payout control board 37 is provided on the game frame side. Even in such a configuration, as will be described later, the communication between the main board 31 and the payout control board 37 is performed by serial communication, thereby facilitating the routing of the wiring when replacing the game board. .

  Each control board is equipped with control means including a control microcomputer. The control means is an electrical component (game device: ball payout device 97, effect display device 9, light emission from a lamp, LED, etc.) provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like. Body, speaker 27, etc.). Hereinafter, the main board 31 may be included in the control board for explanation. In that case, the control means mounted on the control board refers to each of the game control means and the means for controlling the electrical components provided in the gaming machine in accordance with a command signal from the game control means or the like. A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate. The ball payout device 97 is a device for paying out a game ball guided by a passage for guiding the game ball and a sprocket driven by a stepping motor or the like to an upper plate or a lower plate. A payout number counting switch for counting prize balls and rental balls is also configured as part of the unit. In this embodiment, the payout detection means is realized by the payout number count switch 301 and has a function of detecting that a winning ball or a lending ball is actually paid out from the ball payout device 97. In this case, the payout number count switch 301 outputs a detection signal every time one payout of prize balls or rental balls is detected.

  On the back side of the pachinko gaming machine 1, a terminal board 160 having terminals for outputting various information to the outside of the pachinko gaming machine 1 is installed above. The terminal board 160 includes, for example, an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state (a start port signal shown in FIG. 60, one symbol determination signal, one jackpot signal, two jackpot signals, three jackpot signals, hour An information output terminal for externally outputting a short signal, security signal, prize ball signal 1, gaming machine error state signal) is provided.

  The game ball stored in the storage tank 38 passes through a guide rail (not shown), and reaches a ball payout device 97 covered with a payout case 40A through a curve rod. Above the ball payout device 97, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device 97 stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rail (in the storage tank 38). (Proximate part). When the ball break detection switch 167 detects a shortage of game balls, the game balls are replenished to the pachinko gaming machine 1 from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize or a game ball based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball guiding path. Further, when the game ball is paid out, a sensing lever (not shown) presses the full tank switch as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  FIG. 4 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 4 also shows a payout control board 37, an effect control board 80, and the like. On the main board 31, a game control microcomputer (corresponding to a game control means) 560 for controlling the pachinko gaming machine 1 according to a program, a control clock generation circuit 111, and a random number clock generation circuit 112 are mounted. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal. The I / O port unit 57 may be externally attached. The game control microcomputer 560 further includes a random number circuit 509 that generates hardware random numbers (random numbers generated by the hardware circuit).

  Here, the control clock generation circuit 111 generates a control clock CCLK that becomes an oscillation signal of a predetermined frequency outside the game control microcomputer 560. The control clock CCLK generated by the control clock generation circuit 111 is supplied to the clock circuit 502 via a control external clock terminal EXC of a game control microcomputer 560 as shown in FIG. The random number clock generation circuit 112 generates a random number clock RCLK that is an oscillation signal having a predetermined frequency different from the oscillation frequency of the control clock CCLK, outside the game control microcomputer 560. The random number clock RCLK generated by the random number clock generation circuit 112 is supplied to the random number circuit 509 via a random number external clock terminal ERC of a game control microcomputer 560 as shown in FIG. As an example, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 112 may be equal to or lower than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111. Alternatively, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 112 may be higher than the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  Further, the game control microcomputer 560 inputs / outputs (transmits / receives) signals to / from the payout control board 37 (the payout control microcomputer 370) and the effect control board 80 (the effect control microcomputer) by serial communication. Serial communication circuit 511 is incorporated. The payout control microcomputer 370 and the effect control microcomputer also incorporate a serial communication circuit for inputting / outputting signals to / from the game control microcomputer 560 through serial communication (the payout control microcomputer 370 includes (See FIG. 5 for the built-in serial communication circuit). The game control microcomputer 560 includes a two-channel serial communication circuit 511, and can perform serial communication with the payout control microcomputer 370 and also performs serial communication with the effect control microcomputer 100. It is possible. However, in this embodiment, for serial communication with the production control microcomputer 100, a signal is output only from the game control microcomputer 560 to the production control microcomputer, and the production control microcomputer 100 No signal is output to the game control microcomputer 560. Note that the communication between the game control microcomputer 560 and the effect control microcomputer is not limited to the serial communication configuration, and may be configured to perform parallel communication.

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power supply created on the power supply board. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data corresponding to the game state, that is, the control state of the game control means (such as the value of the special symbol process flag and the pending storage number counter) and data indicating the number of unpaid prize balls (specifically, prize balls described later) The value of the command output counter) is stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid prize balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board is input to the reset terminal of the game control microcomputer 560. A reset circuit for generating a reset signal supplied to the game control microcomputer 560 and the like is mounted on the power supply board. When the reset signal becomes high level, the game control microcomputer 560 and the like are in an operable state, and when the reset signal becomes low level, the game control microcomputer 560 and the like are in an operation stop state. Therefore, an allowable signal that allows the operation of the game control microcomputer 560 or the like is output during a period when the reset signal is at a high level, and a game control microcomputer is output when the reset signal is at a low level. An operation stop signal for stopping the operation of 560 or the like is output. Note that the reset circuit may be mounted on each electric component control board (a board on which a microcomputer for controlling the electric parts is mounted).

  Further, a power-off signal indicating that the power supply voltage from the power supply board has dropped below a predetermined value is input to the input port of the game control microcomputer 560. That is, the power supply board monitors the voltage value of a predetermined voltage (for example, DC30V or DC5V) used in the gaming machine, and when the voltage value decreases to a predetermined value (the power supply voltage is reduced). A power supply monitoring circuit that outputs a power-off signal indicating that). Instead of mounting the power monitoring circuit on the power supply board, it may be mounted on a board (for example, main board 31) backed up by a backup power supply. A clear signal (not shown) indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the game control microcomputer 560.

  Also, an input driver circuit 58 for supplying the basic circuit 53 with detection signals from the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a and 30a is also mounted on the main board 31, and the variable winning ball device 15 Are mounted on the main board 31 to reset the game control microcomputer 560 when the power is turned on. The solenoid 16 for opening and closing the solenoid and the solenoid 21 for opening and closing the special variable winning ball apparatus according to a command from the basic circuit 53 are also mounted. A system reset circuit (not shown) for output, and an information output circuit 64 for outputting information output signals such as jackpot information indicating the occurrence of a jackpot gaming state to an external device such as a hall computer via the terminal board 160 Is also mounted on the main board 31.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the relay board 77. The display control of the effect display device 9 that receives and displays the effect symbol variably is performed.

  FIG. 5 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 5, a payout control microcomputer 370 including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370. Note that, unlike the game control microcomputer 560, the RAM built in the payout control microcomputer 370 has not been backed up by a backup power source. Therefore, if the power supply to the gaming machine is stopped, the stored contents of the RAM built in the payout control microcomputer 370 are lost.

  The payout control microcomputer 370 performs control to pay out the game ball based on a predetermined payout condition being satisfied. Note that the predetermined payout condition is that a game ball has won a prize area (ordinary prize opening 29, 30, large prize opening, start prize opening 14) provided in the game area, or a rental ball request has been made. To establish. In addition, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also satisfied when a game ball or medal return request is made. Further, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also established when the symbol stop symbol becomes a predetermined winning symbol.

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. In this embodiment, the detection signal from the payout number count switch 301 is input to the payout control microcomputer 370 and then output to the main board 31 via the I / O port 372a and the output circuit 373B. .

  A detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . In the payout control microcomputer 370 mounted on the payout control board 37, the detection signal from the ball break switch 187 indicates that the ball is out of ball, or the detection signal from the full tank switch 48 indicates that the ball is full. Then, the ball payout process is stopped.

  Further, when the detection signal from the full tank switch 48 indicates a full state, the payout control microcomputer 370 has a low level with respect to the launch board 90 in order to stop the ball launch from the hitting ball launcher. A full tank signal is output. A launch motor signal output from the AND circuit 91 of the launch board 90 to the launch motor 94 is transmitted from the launch board 90 to the launch motor 94. A full tank signal from the payout control microcomputer 370 is input to one of the input sides of the AND circuit 91 mounted on the launch board 90, and a drive signal from the drive signal generation circuit 92 (for driving the launch motor 94). Is a signal that serves to supply power from the power supply board.) Is input to the other input side of the AND circuit 91. Then, the firing motor signal of the AND circuit 91 is input to the firing motor 94. That is, while the payout control microcomputer 370 is outputting the full tank signal, the output of the firing motor signal to the firing motor 94 is stopped. Even when the payout control microcomputer 370 is outputting a full tank signal, the output of the launch motor signal to the launch motor 94 is not stopped, and the ball launch from the hitting ball launcher is not stopped. May be.

  The payout control microcomputer 370 incorporates a serial communication circuit 380 for inputting / outputting (transmitting / receiving) signals with the game control microcomputer 560 through serial communication. In this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 are connected between the game control microcomputer 560 and the payout control microcomputer 370 via the serial communication circuits 511 and 380. In order to confirm, payout control commands (connection confirmation command, connection OK command) are exchanged (transmitted / received) at regular intervals (for example, 1 second). For example, the game control microcomputer 560 transmits a connection confirmation command for confirming the connection at regular intervals via the serial communication circuit 511, and the payout control microcomputer 370 receives the game control microcomputer 560 from the game control microcomputer 560. When the connection confirmation command is received, a connection OK command notifying that is transmitted to the game control microcomputer 560. Also, for example, when a winning occurs, the game control microcomputer 560 sets data indicating the number of winning balls to be paid out in the lower 4 bits of the winning ball number command, and the number of winning balls set in the setting. The command is transmitted to the payout control microcomputer 370. Then, the payout control microcomputer 370 transmits a prize ball number reception command indicating that the prize ball number has been received to the game control microcomputer 560. Furthermore, when the payout control microcomputer 370 finishes the prize ball payout operation, it transmits a prize ball end command indicating the completion of the prize ball to the game control microcomputer 560. The payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals until the prize ball payout operation is completed. In addition, when a predetermined error (an error such as ball lending, full tank, or out of ball) has occurred, the lower 4 bits of the connection OK command or the winning ball preparation command should be made different from the data indicating the error content. The connection OK command and the winning ball preparation command in which the setting is made are transmitted to the game control microcomputer 560. Note that specific signal exchange by serial communication between the game control microcomputer 560 and the payout control microcomputer 370 will be described in detail with reference to FIGS.

  Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. Although a driver circuit (motor drive circuit) is installed outside the output port 372a, the description is omitted in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are provided to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed when a payout command signal is received from the game control means.

  The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  Further, in this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  Further, a detection signal of a door opening sensor 155 </ b> A (see FIG. 2) that detects the state of the glass door frame 2 is input to the dispensing control board 37. In the payout control board 37, the detection signal of the door opening sensor 155 </ b> A is not input to the payout control microcomputer 370 but is branched onto the payout control board 37 and output to the main board 31. In addition, after branching on the payout control board 37, it may be output to the main board 31 via the output circuit 373B. Alternatively, the detection signal of the door opening sensor 155A may be input to the dispensing control microcomputer 370, and the door opening signal may be output to the main board 31 via the dispensing control microcomputer 370. Further, the detection signal of the door opening sensor 155A may be directly input to the main board 31 without being input to the payout control board 37.

  Further, a detection signal of a mechanism plate opening sensor 155B (see FIG. 2) that detects the state of the mechanism plate is input to the payout control board 37. In the payout control board 37, the detection signal of the mechanism plate opening sensor 155B is input to the payout control microcomputer 370 and branched on the payout control board 37 (the former part input to the payout control microcomputer 370). And then output to the main board 31. In addition, after branching on the payout control board 37, it may be output to the main board 31 via the output circuit 373B. Alternatively, the detection signal of the mechanism plate opening sensor 155B may be input to the payout control microcomputer 370, and the mechanism plate open signal may be output to the main board 31 via the payout control microcomputer 370. Further, the detection signal of the mechanism plate opening sensor 155B may be input to the payout control board 37 and also input directly to the main board 31. Further, the detection signal of the mechanism plate opening sensor 155B is not input to the payout control board 37, but is first input to the game control microcomputer 560, and the mechanism plate open signal is paid out via the game control microcomputer 560. You may make it output to the control board 37. FIG.

  FIG. 6 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 6, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 includes an effect control microcomputer 101 including an effect control CPU 101a and a RAM for storing information related to effects such as effect symbol process flags. The RAM may be externally attached. In this embodiment, the RAM in the production control microcomputer 100 is not backed up. In the effect control board 80, the effect control CPU 101a operates according to a program stored in a built-in or external ROM (not shown). The effect control microcomputer 100 has a built-in serial communication circuit 101b that inputs / outputs (transmits / receives) signals with the game control microcomputer 560 through serial communication. In addition, the effect control CPU 101a causes the VDP (video display processor) 109 to perform display control of the effect display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the effect display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100, and maps a VRAM therein. VRAM is a buffer memory for developing image data. Then, the VDP 109 outputs the image data in the VRAM to the effect display device 9 via the frame memory.

  The effect control CPU 101a outputs to the VDP 109 a command for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores character image data and moving image data displayed on the effect display device 9, specifically, a person, characters, figures, symbols (including effect symbols), and background image data in advance. ROM. The VDP 109 reads the image data from the CGROM in response to the instruction from the effect control CPU 101a. The VDP 109 executes display control based on the read image data.

  Further, the effect control CPU 101 a outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. In addition, the production control CPU 101 a outputs sound number data to the audio output board 70 via the output port 104.

  In the lamp driver board 35, a signal for driving the LED is input to the LED driver 352 via the input driver 351. The LED driver 352 supplies a current to a light emitter provided on the frame side such as the frame LED 28 based on a signal for driving the LED. Further, an electric current is supplied to the decoration LED 25 provided on the game board side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The voice synthesizing IC 703 generates voice or sound effect according to the sound number data, and outputs it to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data showing the output form of the sound effect or sound in a time series in a predetermined period (for example, the changing period of the effect design).

  Next, the configuration of the power supply substrate 910 will be described with reference to the block diagram of FIG. The power supply board 910 is provided with a power switch 914 for executing or shutting off power supply to each electrical component control board and mechanism component in the gaming machine. Note that the power switch 914 may be provided outside the power supply board 910 in the gaming machine. When the power switch 914 is in a closed state (on state), AC power (AC 24 V) is applied to the input side (primary side) of the transformer 911. The transformer 911 is for electrically insulating the AC power supply (AC24V) and the inside of the power supply substrate 910, and its output voltage is also AC24V. A varistor 918 as an overvoltage protection circuit is installed on the input side of the transformer 911.

  The power supply board 910 is installed independently of the electric component control board (the main board 31, the payout control board 37, the effect control board 80, etc.), and generates a voltage used by each board and the mechanical parts in the gaming machine. In this example, AC24V, VSL (DC + 30V), VLP (DC + 24V), VDD (DC + 12V) and VCC (DC + 5V) are generated. Further, a capacitor 916 serving as a storage holding means for holding the stored contents in the backup power supply (VBB), that is, the backup RAM, is charged from DC + 5V (VCC), that is, a power supply line that drives an IC or the like on each substrate. Further, a backflow prevention diode 917 is inserted between the + 5V line and the backup + 5V (VBB) line. Note that VSL is generated by rectifying and boosting AC 24 V with a rectifying element in the rectifying and smoothing circuit 915. VSL becomes a solenoid driving power source. VLP is a lamp lighting voltage, and is generated by rectifying AC24V with a rectifier element in the rectifier circuit 912.

  The DC-DC converter 913 serving as a power supply voltage generation unit has one or a plurality of switching regulators (two regulator ICs 924A and 924B are shown in FIG. 7), and generates VDD and VCC based on VSL. Relatively large capacitors 923A and 923B are connected to the input sides of the regulator ICs (switching regulators) 924A and 924B. Therefore, when the power supply to the gaming machine from the outside is stopped, the direct current voltages such as VSL, VDD, VCC, etc., decrease relatively slowly.

  As shown in FIG. 7, AC24V output from the transformer 911 is supplied to the connector 922B as it is. The VLP is supplied to the connector 922C. VCC, VDD and VSL are supplied to connectors 922A, 922B and 922C.

  The cable connected to the connector 922A is connected to the main board 31. VBB is also supplied to the connector 922A. The cable connected to the connector 922B is connected to the payout control board 37. Note that VBB may also be supplied to the connector 922B. That is, backup power may be supplied to the payout control board 37, and a power-off process described later may be executed. The cable connected to the connector 922C is connected to the lamp driver board 35. Each voltage is supplied to the effect control board 80 and the audio output board 70 via the lamp driver board 35.

  In addition, a clear switch 921 having a push button structure is mounted on the power supply board 910. Since the power supply board 910 is mounted, the power supply system extending from the power supply board 910 to the main board 31 can be integrated into one system, and the clear signal wiring from the clear switch 921 can be easily separated from the power supply system. it can. When the clear switch 921 is pressed, a low level (ON state) clear signal is output and output to the main board 31 via the connector 922A. If the clear switch 921 is not pressed, a high level (off state) signal is output. The clear switch 921 may have a configuration other than the push button structure. Further, the clear switch 921 may be provided other than the power supply board 910 in the gaming machine. The clear signal is sent to the payout control board 37 via the main board 31.

  Further, the power supply board 910 generates a reset signal for the microcomputer mounted on the electric component control board, amplifies the reset signal from the power supply monitor circuit 920 that outputs a power-off signal, and the power supply monitor circuit 920. In addition, an output driver circuit 925 that outputs to the main board 31 and the payout control board 37 via the connectors 922A and 922B, amplifies the power-off signal, starts the connector 922A, and outputs it to the main board 31 is mounted. The power-off signal is sent to the payout control board 31 and the effect control board 80 via the main board 31.

  The power supply monitoring circuit 920 is a circuit that realizes a power supply monitoring unit that outputs a power-off signal and a reset signal generation unit that generates a reset signal. Can do. The power supply monitoring circuit 920 has a predetermined period of time during which a predetermined voltage (for example, + 24V) used in the gaming machine is equal to or less than a predetermined value (for example, + 5V, but may be other values such as + 18V). For example, a power-off signal is output if it continues for 56 ms or longer. Specifically, the power-off signal is turned on (low level). If + 18V is set, as will be described later, it is possible to reliably prevent erroneous detection of the switch when the power supply is stopped.

  For example, the power supply monitoring circuit 920 sets the reset signal to a low level when VCC becomes +4.5 V or less. In this embodiment, the function of outputting the power-off signal and the function of outputting the reset signal are realized by one power supply monitoring circuit 920, but they may be realized by different circuits. In that case, a watchdog timer built-in IC can be used as a circuit for outputting a reset signal. In such an IC, in order to prevent the CPU from malfunctioning or running away due to a momentary power supply voltage interruption or instantaneous interruption, a period in which a clock signal is not input to the clock input terminal (CK terminal) ( (The period set according to the capacitance of a single capacitor connected to the capacitor connection terminal (TC terminal), and the timer monitoring time can be changed according to the resistance connected to the detection voltage variable terminal (VS terminal)) If the reset signal exceeds a predetermined time, the reset signal is changed from a high level to a low level (the level at which the CPU is stopped) for a certain period (the low level period is set according to the capacitance of the capacitor connected to the capacitor connection terminal). A watchdog function that repeats the setting of the This function can be stopped by setting the ground level to the same level as the input level of the GND terminal). For example, when VCC (operable voltage +0.8 V or more) is +5 V, VCC becomes +4.2 V or less. It has a hysteresis characteristic that changes the detection voltage value for inverting the level of the reset signal depending on whether the reset signal is low level and VCC is high or low, and the reset level is low level. In addition to a certain reset signal (output from the RESET terminal), a system reset IC that can output a reset signal (output from the RESET terminal) having a high reset level can be used. When the reset circuit is mounted on each electric component control board, the voltage value that causes the power-off signal to be low may be made different (for example, the case of the main board 31 is made highest). The power-off signal is input to the game control microcomputer 560 the earliest.)

  When the power supply to the gaming machine is stopped, the power supply monitoring circuit 920 sets the reset signal to a low level on condition that a predetermined period has elapsed since the power-off signal was output (set to a low level). The predetermined period is a time sufficient for the game control microcomputer 560 mounted on the main board 31 to execute a power-off process described later. That is, the power monitoring circuit 920 outputs an operation stop signal (low level of the reset signal) after the game control microcomputer 560 completes the power-off process after outputting the power-off signal as the voltage drop detection signal. To do. The power monitoring circuit 920 also serves as first power monitoring means for outputting a voltage drop detection signal and second power monitoring means for outputting an operation stop signal. In addition, when power supply to the gaming machine is started and VCC exceeds +4.5 V, for example, the reset signal is set to high level.

  In this embodiment, the power supply monitoring means monitors the output of the power supply of a predetermined potential, and the voltage from the outside of the gaming machine (this implementation) In this embodiment, it is used that the predetermined DC voltage created from AC24V) is equal to or lower than the predetermined value. However, the detection condition is not limited to this. Other conditions may be used. For example, the AC wave itself may be monitored and the AC wave may be detected as a detection condition, or the signal obtained by digitizing the AC wave may be monitored and the AC signal may be stopped when the digital signal becomes flat. May be used as a detection condition. Further, for example, a + 12V power supply voltage or a + 5V power supply voltage may be monitored, and it may be detected that the voltage has dropped to a predetermined value and a power-off signal is output. However, in order to prevent a malfunction of a switch operating at + 12V, it is preferable to monitor a voltage of + 12V or higher.

  In this embodiment, the power supply monitoring unit is mounted on the power supply board 910, but the power supply monitoring unit may be mounted on the payout control board 37. When mounted on the payout control board 37, the path of the power-off signal from the power monitoring means to the game control microcomputer 560 and the payout control microcomputer 370 is shortened, and noise may be applied to the power-off signal. Can be reduced.

  FIG. 8 is a timing chart schematically showing the states of the AC 24 V, VSL, VCC, reset signal, and power-off signal when power supply to the pachinko gaming machine 1 is started and when power supply is stopped. is there. As shown in FIG. 8, when the supply of power to the pachinko gaming machine 1 is started, VSL and VCC gradually reach specified values (DC + 30V and DC + 5V). At this time, when VCC exceeds the first predetermined value, the power supply monitoring circuit 303 stops outputting the reset signal (sets it to a high level) and turns it off. When VSL exceeds the second predetermined value, the power supply monitoring circuit 303 stops outputting the power-off signal (sets it to a high level) and turns it off. On the other hand, when the power supply to the pachinko gaming machine 1 is stopped, VSL and VCC gradually decrease. At this time, when VSL falls to the second predetermined value, the power supply monitoring circuit 303 outputs the power-off signal as an ON state (sets it to a low level). When VCC decreases to the first predetermined value, the power monitoring circuit 920 outputs the reset signal as an ON state (sets it to a low level).

  FIG. 9 shows a configuration example of the game control microcomputer 560 mounted on the main board 31. A game control microcomputer 560 shown in FIG. 9 is, for example, a one-chip microcomputer, and includes an external bus interface 501, a clock circuit 502, a specific information storage circuit 503, a reset / interrupt controller 504, a CPU (Central Processing Unit). ) 56, ROM (Read Only Memory) 54, RAM (Random Access Memory) 55, CTC (Counter / Timer Circuit) 508, random number circuit 509, PIP (Parallel Input Port) 510, and serial communication circuit 511. And an address decoding circuit 512.

  In this embodiment, the microcomputer on a board (for example, the payout control board 37 or the effect control board 80) different from the board (for example, the main board 31) on which the microcomputer incorporating the serial communication circuit 511 is mounted. Although the case where the serial communication circuit 511 is used for communication will be described, the serial communication circuit 511 may perform serial communication with another microcomputer included in the board on which the microcomputer including the serial communication circuit 511 is mounted. For example, when two microcomputers having the same configuration are mounted on the same substrate, serial communication circuits built in the microcomputers may perform serial communication with each other.

  FIG. 10 shows an example of an address map in the game control microcomputer 560. As shown in FIG. 10, the area from address 0000H to address 1FFFH is allocated to the ROM 54 and includes a user program area and a program management area. FIG. 11A shows an example of the usage and contents of the main part of the program management area in the ROM 54. The area from address 2000H to address 20FFH is a built-in register area assigned to the built-in register of the game control microcomputer 560. FIG. 11B shows an example of the usage and contents of the main part of the built-in register area. An area from address 7E00H to address 7FFFH is a work area assigned to the RAM 55, and can be assigned to an I / O map or a memory map. An area from address FDD0H to address FDFBH is an XCS decode area allocated to the address decode circuit 512.

  The program management area is a storage area for storing information necessary for the CPU 56 to execute the user program. As shown in FIG. 11A, the program management area includes a header KHDR, a function setting KFCS, a first random number initial setting KRS1, a second random number initial setting KRS2, an interrupt initial setting KIIS, a security time setting KSES, and the like. It is.

  A header KHDR stored in the program management area indicates a setting for reading internal data in the game control microcomputer 560. FIG. 12A illustrates the correspondence between setting data and operation in the header KHDR. Here, in the game control microcomputer 560, a ROM read prevention function and a bus output mask function can be set. The ROM read prevention function is a function for permitting or prohibiting the read operation of the data stored in the ROM 54 provided in the game control microcomputer 560. When the read prohibition is set, the data stored in the ROM 54 cannot be read. The bus output mask function is an address bus output, data bus output and control signal in the external bus interface 501 when an external device connected to the external bus interface 501 makes a read request for the internal data of the game control microcomputer 560. This function makes it impossible to read internal data from an external device by masking the output. As shown in FIG. 12A, the operation combination of the ROM read prevention function and the bus output mask function is set differently in accordance with the setting data of the header KHDR. Of the setting data shown in FIG. 12A, the setting data for which ROM reading is permitted and the bus output mask is valid is also referred to as bus output mask valid data. Further, the setting data (all “00H”) in which ROM reading is prohibited and the bus output mask is valid is also referred to as ROM reading prohibiting data. The setting data for which ROM reading is permitted and the bus output mask becomes invalid is also referred to as bus output mask invalid data.

  The function setting KFCS stored in the program management area indicates the operation setting of a watch dog timer (WDT) in the game control microcomputer 560 and the use setting of various function shared terminals. FIG. 12B shows an example of setting contents in the function setting KFCS.

  The bit number [7-5] of the function setting KFCS indicates, for example, the operation permission / prohibition of the watchdog timer that can be set as an interrupt factor in the reset / interrupt controller 504, and the cycle when it is permitted. The bit number [4] of the function setting KFCS indicates that the predetermined function shared terminal (first shared terminal) in the game control microcomputer 560 is the second channel transmission terminal TXB used by the serial communication circuit 511 or is address decoded. This is a TXB terminal setting that designates whether the circuit 512 uses the chip select output terminal XCS13. In the example shown in FIG. 12B, when the bit value in the bit number [4] of the function setting KFCS is “0”, the first shared terminal is used for the second channel transmission in the serial communication circuit 511. This is the setting for the 2-channel transmission terminal TXB. On the other hand, if the bit value is “1”, the first dual-purpose terminal is set to the chip select output terminal XCS13 used in the address decode circuit 512. In this embodiment, by setting the bit number [4] of the function setting KFCS to “0” and setting the first shared terminal to the second channel transmission terminal TXB, serial communication with the effect control board 80 is performed. to enable.

  The bit number [3] of the function setting KFCS indicates that a predetermined function shared terminal (second shared terminal) in the game control microcomputer 560 is the first channel transmission terminal TXA used by the serial communication circuit 511, or is address decoded. This is a TXA terminal setting that indicates whether the circuit 512 uses the chip select output terminal XCS12. In the example shown in FIG. 12B, if the bit value in the bit number [3] of the function setting KFCS is “0”, the second shared terminal is used for the first channel transmission in the serial communication circuit 511. 1 channel transmission terminal TXA is set. On the other hand, if the bit value is “1”, the second dual-purpose terminal is set to the chip select output terminal XCS12 used in the address decode circuit 512. In this embodiment, by setting the bit number [3] of the function setting KFCS to “0” and setting the second shared terminal to the first channel transmission terminal TXA, serial communication with the payout control board 37 is performed. to enable.

  The bit number [2] of the function setting KFCS indicates that the predetermined function shared terminal (third shared terminal) in the game control microcomputer 560 is the first channel reception terminal RXA used by the serial communication circuit 511, or the PIP 510 This is an RXA terminal setting indicating whether to use the input port P5. In the example shown in FIG. 12B, if the bit value in the bit number [2] of the function setting KFCS is “0”, the third shared terminal is used for the first channel reception in the serial communication circuit 511. 1 channel receiving terminal RXA is set. On the other hand, if the bit value is “1”, the third shared terminal is set to the input port P5 used in the PIP 510. In this embodiment, by setting the bit number [2] of the function setting KFCS to “0” and setting the third shared terminal to the first channel receiving terminal RXA, serial communication with the payout control board 37 is performed. to enable.

  The bit number [1] of the function setting KFCS is a predetermined function shared terminal (fourth shared terminal) in the game control microcomputer 560 is used as an external non-maskable interrupt terminal XNMI connected to the CPU 56 or the like, or is used by the PIP 510 This is an NMI connection setting indicating whether to set the input port P4. In the example shown in FIG. 12B, if the bit value in the bit number [1] of the function setting KFCS is “0”, the external non-maskable interrupt terminal XNMI connected to the CPU 56 or the like is set to the fourth shared terminal. (CPU connection). On the other hand, if the bit value is “1”, the fourth shared terminal is set for the input port P4 used in the PIP 510 (CPU disconnected).

  The bit number [0] of the function setting KFCS is a predetermined function shared terminal (fifth shared terminal) in the game control microcomputer 560 used as an external maskable interrupt terminal XINT connected to the CPU 56 or the like, or used by the PIP 510 The XINT connection setting indicates whether the input port is P3. In the example shown in FIG. 12B, if the bit value in the bit number [0] of the function setting KFCS is “0”, the external maskable interrupt terminal XINT whose fifth shared terminal is connected to the CPU 56 or the like is set. (CPU connection). On the other hand, if the bit value is “1”, the fifth shared terminal is set for the input port P3 used in the PIP 510 (CPU disconnected).

  The first random number initial setting KRS1 and the second random number initial setting KRS2 stored in the program management area indicate the initial setting of the random number circuit 509. FIG. 13A shows an example of setting contents in the first random number initial setting KRS1. FIG. 13B shows an example of setting contents in the second random number initial setting KRS2.

  The bit number [3] of the first random number initial setting KRS1 is a random number circuit use setting indicating whether to use the random number circuit 509 or not. In the example shown in FIG. 13A, if the bit value in the bit number [3] of the first random number initial setting KRS1 is “0”, the random number circuit 509 is not used (unused), but “1”. "Is set to use the random number circuit 509 (use). In this embodiment, the bit number [3] of the first random number initial setting KRS1 is set to “1”, and the random number circuit 509 is set to be usable.

  The bit number [2] of the first random number initial setting KRS1 is the random number update clock RGK (see FIG. 16) used for updating the numerical data that becomes the random number value in the random number circuit 509, or the internal system clock SCLK. This is a random number update clock setting indicating whether the clock RCLK is divided by two. In the example shown in FIG. 13A, if the bit value in the bit number [2] of the first random number initial setting KRS1 is “0”, the internal system clock SCLK is set to be used as the random number update clock RGK. If it is 1 ″, the random number clock RCLK is divided by two and used as the random number update clock RGK. In this embodiment, the bit number [2] of the first random number initial setting KRS1 is set to “1”, and the random number clock RCLK is divided by two to be used as the random number update clock RGK.

  The bit number [1-0] of the first random number initial setting KRS1 is a random number update rule setting indicating whether or not to change the random number update rule in the random number circuit 509 and the change method in the case of the change. In the example shown in FIG. 13A, if the bit value in the bit number [1-0] of the first random number initial setting KRS1 is “00”, the random number update rule is not changed, and if it is “01”. The setting for changing the random number update rule by software is made after the second round, and if it is “10”, the random number update rule is automatically changed after the second round.

  The bit number [3-2] of the second random number initial setting KRS2 is set to a fixed bit value “00”. Note that “B” of “00B” in FIG. 13B indicates binary display. The bit number [1-0] of the second random number initial setting KRS2 indicates the setting relating to the start value in the numerical data that becomes the random value in the random number circuit 509. In the example shown in FIG. 13B, if the bit value in the bit number [1] of the second random number initial setting KRS2 is “0”, the start value is set to a predetermined default value 0000H, while “1”. In this case, a value based on the ID number, which is unique identification information assigned to each game control microcomputer 560, is set as the start value. In the example shown in FIG. 13B, if the bit value in the bit number [0] of the second random number initial setting KRS2 is “0”, the start value is not changed every time the system is reset. When it is 1 ″, the start value is changed every time the system is reset. When the start value is set to a value based on the ID number, a part or all of the operations such as a predetermined scramble process for the ID number and the addition / subtraction / multiplication / division using the ID number are performed. It is only necessary to execute and use the calculated value as the start value. Further, when the bit value [0] of the second random number initial setting KRS2 is “1”, the count value in a predetermined free-run counter (for example, the free-run counter 554A shown in FIG. 16) every system reset. A value set based on the above may be used as the start value. Further, when the bit values [1] and [0] of the second random number initial setting KRS2 are both “1”, a value set based on the ID number and the count value in the free-run counter is set. It may be used as a start value.

  Note that when two systems (corresponding to the first and second channels) for generating numerical data to be random values in the random number circuit 509 are provided, the first shown in FIGS. 13A and 13B. The bit number [3-0] of the random number initial setting KRS1 and the bit number [3-0] of the second random number initial setting KRS2 are used to indicate the initial setting in the first channel. On the other hand, the bit number [7-4] of the first random number initial setting KRS1 and the bit number [7-4] of the second random number initial setting KRS2 (omitted in FIGS. 13A and 13B), the second It may be used as an indication of the initial setting in the channel.

  Interrupt initial settings KIIS stored in the program management area indicate initial settings related to handling of maskable interrupts generated in the game control microcomputer 560. FIG. 13C shows an example of setting contents in the interrupt initial setting KIIS.

  In the bit number [7-4] of the interrupt initial setting KIIS, the upper 4 bits of the interrupt vector are set. In the bit number [3-0] of the interrupt initial setting KIIS, a combination of maskable interrupt factor priorities is set. In the example shown in FIG. 13C, if any of “00H” to “02H” and “06H” is specified by the bit number [3-0] of the interrupt initial setting KIIS, the maskable interrupt factor from the CTC 508 is determined. A combination of priorities to be given the highest priority is set. On the other hand, if any one of “03H” and “07H” is specified, a combination of priorities that gives the highest priority to the maskable interrupt factor from the random number circuit 509 is set. If either “04H” or “05H” is designated, a combination of priorities with the highest priority given to the maskable interrupt factor from the serial communication circuit 511 is set. Note that even if the priority combination has the highest priority for maskable interrupt factors from the same circuit, if the specified value is different, the type of maskable interrupt factor that has the highest priority, the priority combination in the second or lower order, etc. will differ. ing.

  The security time setting KSES stored in the program management area is the frequency at which an abnormality is detected when monitoring the frequency of the random number clock RCLK, the time of the security mode in which the game control microcomputer 560 shifts to the start of operation, etc. Indicates settings related to (security time). Here, when the operation mode of the game control microcomputer 560 is the security mode, a predetermined security check process is executed to check whether or not the content stored in the ROM 54 has been changed. FIG. 14A shows an example of setting contents in the security time setting KSES.

  Bit number [7-6] of security time setting KSES is a random number clock abnormality detection setting indicating a frequency at which an abnormality is detected when the frequency of random number clock RCLK is monitored. FIG. 14B shows an example of setting contents in the bit number [7-6] of the security time setting KSES. The bit number [7-6] of the security time setting KSES designates a reference value (determination value) at which the frequency of the random number clock RCLK is detected as abnormal based on the frequency of the internal system clock SCLK. Whether or not an abnormality has occurred in the input state of the random number clock RCLK by comparing the input state of the random number clock RCLK with the internal system clock SCLK based on the setting in the bit number [7-6] of the security time setting KSES. It is possible to determine whether. The bit number “5” of the security time setting KSES is set to a fixed bit value “0”.

  The bit number [4-3] of the security time setting KSES indicates a time setting when the security time is extended by a random time every system reset. FIG. 14C shows an example of setting contents in the bit number [4-3] of the security time setting KSES. In the example shown in FIG. 14C, if the bit value in the bit number [4-3] of the security time setting KSES is “00”, the setting is such that random time extension is not performed. On the other hand, if the bit value is “01”, the short mode is set. If the bit value is “10”, the long mode is set. Here, when the short mode or the long mode is designated, for example, the count value of the free run counter built in the game control microcomputer 560 is set to a predetermined value provided in the game control microcomputer 560 when a system reset occurs. Store in the built-in register (variable security time register). Then, the security time can be reduced by using the stored value of the variable security time register as it is at the time of initial setting, or by using the value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function). What is necessary is just to determine the extension time at the time of extending at random. As an example, when the frequency of the internal system clock SCLK is 6.0 MHz, the extension time is randomly determined in the range of 0 to 680 μs (microseconds) in the short mode, and in the range of 0 to 348, 160 μs in the long mode. The extension time is determined at random. As another example, when the frequency of the internal system clock SCLK is 10.0 MHz, the extension time is randomly determined in the range of 0 to 408 μs in the short mode, and in the range of 0 to 208,896 μs in the long mode. The extension time is determined at random. The variable security time register only needs to be backed up using a backup power source common to the backup location on the main board 31, such as a backup area in the RAM 55 of the game control microcomputer 560. Alternatively, the variable security time register may be backed up by a power source provided separately from a backup power source used for a backup area in the RAM 55 or the like. In this way, the variable security time register is backed up by the backup power supply, so that the stored value of the variable security time register is saved for a predetermined period even when the power supply is stopped. The timing at which the count value in the free-run counter is read and stored in the variable security time register is not limited to when a system reset occurs, but may be any predetermined timing. Alternatively, the free run counter may be backed up by a backup power source, and the extension time for extending the security time using the stored value read from the free run counter at the initial setting may be determined at random.

  Further, the short mode or the long mode is set by the bit value in the bit number [4-3] of the security time setting KSES, and the bit value in the bit number [2-0] of the security time setting KSES is set to other than “000”. Thus, it is possible to set an extension time to be added to the fixed time. In this case, both the extension time corresponding to the bit value in the bit number [2-0] and the extension time randomly determined based on the bit value in the bit number [4-3] are fixed times. By adding, the security time during which the game control microcomputer 560 is in the security mode is determined.

  The external bus interface 501 provided in the game control microcomputer 560 shown in FIG. 9 includes an interface function between the external bus and the internal bus of the chip constituting the game control microcomputer 560, an address bus, a data bus, and each control signal. A bus interface having a direction control function and the like. For example, the external bus interface 501 is connected to an external memory or an external input / output device externally attached to the game control microcomputer 560, and an address signal, a data signal, various control signals, etc. are connected to these external devices. As long as it transmits and receives. In this embodiment, the external bus interface 501 includes an internal resource access control circuit 501A.

  The internal resource access control circuit 501A controls access to the internal data of the game control microcomputer 560 from an external device via the external bus interface 501, and for example, a game control program (game control processing program) stored in the ROM 54 And a circuit for limiting inappropriate external reading of internal data such as fixed data. Here, a circuit analysis device such as an in-circuit emulator (ICE; InCircuit Emulator) may be connected to the external bus interface 501 as an external device.

  As an example, switching between prohibiting or permitting reading of stored data in the ROM 54 can be switched according to the contents of the header KHDR stored in the program management area of the ROM 54. For example, when the header KHDR is bus output mask invalid data, the ROM 54 can be read by an external device, and external reading of internal data is permitted. On the other hand, when the header KHDR is the bus output mask valid data, the ROM 54 from the external device by masking the address bus output, data bus output, and control signal output in the external bus interface 501, for example. Is disabled, and external reading of internal data is prohibited. In this case, when reading of internal data is requested from an external device connected to the external bus interface 501, a predetermined fixed value is output so that the internal data cannot be read from the external device. . Further, when the header KHDR is ROM read prohibition data, the ROM 54 itself may not be read, and reading of stored data in the ROM 54 may be prevented. For example, in a ROM at the manufacturing stage, by making the header KHDR ROM read prohibition data, the ROM itself is made unreadable, and if it is a development ROM, bus output mask invalid data is written in the header KHDR, Allows verification of internal data by an external device. On the other hand, if the ROM for mass production is used, the bus output mask valid data is written in the header KHDR, so that the ROM 54 can be read in the game control microcomputer 560 by the CPU 56 or the like, while the external device It is only necessary to prevent the ROM 54 from being read.

  As another example, the internal resource access control circuit 501A is requested by an external device connected to the external bus interface 501 to read out internal data of the game control microcomputer 560 such as all or a part of data stored in the ROM 54. Detect that. When this read request is detected, the internal resource access control circuit 501A determines whether or not to permit reading of internal data of the game control microcomputer 560. For example, it is assumed that all or part of the stored data in the ROM 54 is encrypted. In this case, if the read request from the external device is a read request for an encryption processing program or key data stored in the ROM 54, the internal resource access control circuit 501A rejects the read request, and the game control micro Reading of internal data of the computer 560 is prohibited. In the external bus interface 501, a switch element is provided between the output port from which data stored in the ROM 54 is output and the internal bus. When the internal resource access control circuit 501 A prohibits reading of the internal data, the switch element May be controlled to be turned off. As described above, the internal resource access control circuit 501A reads the internal data depending on whether or not the read request from the external device requests reading of predetermined internal data (for example, a predetermined area of the ROM 54). You may make it determine whether it prohibits or permits.

  Alternatively, the internal resource access control circuit 501A may determine whether or not a predetermined authentication code has been input from an external device when detecting a read request for internal data. In this case, for example, a predetermined code pattern serving as an authentication code may be stored in advance in the internal resource access control circuit 501A or in a predetermined area of the ROM 54. When an authentication code is input from an external device, the authentication code is compared with an internally stored authentication code. If they match, a read request is accepted and the internal data of the game control microcomputer 560 is read. To give permission. On the other hand, if the authentication code input from the external device does not match the authentication code stored internally, the read request is rejected and reading of the internal data of the game control microcomputer 560 is prohibited. As described above, the internal resource access control circuit 501A determines whether to prohibit or permit reading of the internal data depending on whether or not the authentication code input from the external device matches the authentication code stored internally. You may make it do. As a result, it is possible to read out the internal data of the game control microcomputer 560 using a correct authentication code known in advance by an inspection organization or the like, and properly inspect the validity of the internal data. become.

  As yet another example, a read prohibition flag is provided in the internal resource access control circuit 501A, and reading of the ROM 54 by an external device is prohibited if the read prohibition flag is on. On the other hand, when the read prohibition flag is in the off state, reading of the ROM 54 by the external device is permitted. Here, the read prohibition flag is off in the initial state, but once the read prohibition flag is turned on, the read prohibition flag cannot be cleared and returned to the off state. That's fine. That is, the read prohibition flag can be irreversibly changed from the off state to the on state. For example, the internal resource access control circuit 501A does not have a function of clearing the read prohibition flag to turn it off, and is set so that the read prohibition flag cannot be cleared by any instruction. Just do it. Then, the internal resource access control circuit 501A determines whether or not the read prohibition flag is on when the external device requests to read the internal data of the game control microcomputer 560 such as the data stored in the ROM 54. At this time, if the read prohibition flag is on, the read request from the external device is rejected, and reading of the internal data of the game control microcomputer 560 is prohibited. On the other hand, if the reading prohibition flag is off, the reading request from the external device is accepted and reading of the internal data of the game control microcomputer 560 is permitted. With such a configuration, a provider who creates a game control processing program for game control and stores it in the ROM 54 can load a program that has been debugged from the ROM 54 with the read prohibition flag turned off from the external device. Can be read. Then, when shipping after the debugging work is completed, by setting the read prohibition flag to the on state, external reading of the ROM 54 can be restricted thereafter, and by the user of the pachinko gaming machine 1 or the like Reading of the ROM 54 can be prevented. As described above, the internal resource access control circuit 501A may determine whether to prohibit or permit reading of internal data depending on whether an internal flag such as a read prohibition flag is off or on. .

  Note that the read prohibition flag is not set irreversibly but can be changed from the on state to the off state, while the read prohibition flag is changed from the on state to the off state to permit reading of internal data. In this case, external reading of the ROM 54 may be restricted by erasing the data stored in the ROM 54 (for example, flash erasure).

  The clock circuit 502 included in the game control microcomputer 560 is a circuit that generates the internal system clock SCLK by, for example, dividing the oscillation signal input to the control external clock terminal EXC by two. In this embodiment, the control clock CCLK generated by the control clock generation circuit 111 is input to the control external clock terminal EXC. The internal system clock SCLK generated by the clock circuit 502 is supplied to various circuits such as the CPU 56 that control the progress of the game in the game control microcomputer 560. The internal system clock SCLK is also supplied to the random number circuit 509 and used to monitor the frequency of the random number clock RCLK supplied from the random number clock generation circuit 112. Further, the internal system clock SCLK may be output from the system clock output terminal CLKO connected to the clock circuit 502 to the outside of the game control microcomputer 560. It is desirable that the internal system clock SCLK is not output to the outside of the game control microcomputer 560. As described above, by limiting the external output of the internal system clock SCLK, it becomes difficult to specify the operation cycle of the internal circuit (such as the CPU 56) of the game control microcomputer 560 from the outside, and numerical data that becomes a random value Can be prevented from being specified from the outside when the software is updated by software.

  The unique information storage circuit 503 included in the game control microcomputer 560 is a circuit that stores a plurality of types of unique information that is internal information of the game control microcomputer 560, for example. As an example, the unique information storage circuit 503 stores three types of unique information such as a ROM code, a chip individual number, and an ID number. The ROM 54 code is a 4-byte numerical value generated from stored data in a predetermined area of the ROM 54, and four numerical values with different generation methods may be prepared. The chip individual number is a 4-byte number assigned when the game control microcomputer 560 is manufactured, and indicates a different value for each chip constituting the game control microcomputer 560. The ID number is an 8-byte number assigned when the game control microcomputer 560 is manufactured, and shows a different numerical value for each chip constituting the game control microcomputer 560. Here, the chip individual number may be read from the user program, while the ID number may be set so as not to be read from the user program. The unique information storage circuit 503 may be included in the ROM 54 by using a predetermined area of the ROM 54, for example. Alternatively, the unique information storage circuit 503 may be included in the CPU 56 by using a built-in register of the CPU 56, for example.

  A reset / interrupt controller 504 provided in the game control microcomputer 560 is for controlling various reset and interrupt requests generated inside and outside the game control microcomputer 560. Resets controlled by the reset / interrupt controller 504 include system resets and user resets. The system reset is a reset that occurs when a low level signal is input to the external system reset terminal XSRST for a certain period. The user reset is a reset that occurs due to a predetermined factor, such as a watchdog timer (WDT) time-out signal or a non-designated area travel prohibition (IAT).

  Interrupts controlled by the reset / interrupt controller 504 include a non-maskable interrupt NMI and a maskable interrupt INT. The non-maskable interrupt NMI is an interrupt that is unconditionally accepted even when the CPU 56 is in an interrupt disabled state, and is an interrupt that is generated when a low level signal is input to the external non-maskable interrupt terminal XNMI (also used as the input port P4) for a certain period. is there. The maskable interrupt INT is an interrupt that can permit / prohibit acceptance of an interrupt request by a setting instruction of the CPU 56, and multiple interrupts can be executed by setting priority. The cause of the maskable interrupt INT is that a low level signal has been input to the external maskable interrupt terminal XINT (also used as the input port P3) for a certain period of time, a time-out has occurred in the timer circuit included in the CTC 508, A plurality of types of interrupt factors are determined in advance, such as the occurrence of an interrupt factor due to data reception or data transmission in the serial communication circuit 511 and the occurrence of an interrupt factor due to fetching of numerical data as a random value in the random number circuit 509. It only has to be done.

  The reset / interrupt controller 504 includes an interrupt mask register IMR (address 2028H), an interrupt wait monitor register IRR (address 2029H), and interrupts among the built-in registers included in the game control microcomputer 560 as shown in FIG. The monitor register ISR (address 202AH), the internal information register CIF (address 208CH), etc. are used to control interrupts and manage resets. The interrupt mask register IMR is a register that sets what is used and what is not used among maskable interrupts INT caused by a plurality of different factors. The interrupt wait monitor register IRR is a register for confirming the generation state of a maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS. The in-interrupt monitor register ISR is a register for confirming the processing state of the maskable interrupt request signal for each maskable interrupt factor set by the interrupt initial setting KIIS. The internal information register CIF is a register for managing the reset factor generated immediately before and recording the frequency abnormality of the random number clock RCLK.

  FIG. 15A shows a configuration example of the internal information register CIF. FIG. 15B shows an example of setting contents in each bit of the internal information data stored in the internal information register CIF. The internal information data CIF4 stored in the bit number [4] of the internal information register CIF is a random number clock abnormality instruction indicating the presence or absence of a frequency abnormality in the random number clock RCLK. In the example shown in FIG. 15B, when the frequency abnormality of the random number clock RCLK is not detected, the bit value of the internal information data CIF4 is “0”, whereas when the frequency abnormality is detected, the bit value is “1”. The internal information data CIF2 stored in the bit number [2] of the internal information register CIF is a system reset instruction indicating whether or not the reset factor generated immediately before is a system reset. In the example shown in FIG. 15B, when the immediately preceding reset factor is not a system reset (system reset has not occurred), the bit value of the internal information data CIF2 is “0”, whereas when the system reset is a system reset (system reset) When the reset occurs), the bit value becomes “1”. As a first example of the operation using the internal information data CIF2, the CPU 56 of the game control microcomputer 560 checks the bit value of the internal information data CIF2 when the power is turned on, and the bit value is “1” (set). If not, it is determined that the power is not turned on normally. At this time, for example, by transmitting a predetermined effect control command to the effect control board 80, an illegal signal input action is performed aiming at a big hit gaming state immediately after power-on in the pachinko gaming machine 1. You may notify that there exists possibility with a production | presentation apparatus etc. Further, as a second example of the operation using the internal information data CIF2, when the pachinko gaming machine 1 notifies the probability variation state only when the power is turned on and does not inform the probability variation state normally, the game control microcomputer 560 when the power is turned on. The CPU 56 or the like may check the bit value of the internal information data CIF2, and if the bit value is not “1” (set), the gaming state may not be notified.

  The internal information data CIF1 stored in the bit number [1] of the internal information register CIF is a WDT timeout instruction indicating whether or not the reset factor generated immediately before is a user reset due to a watchdog timer (WDT) timeout. . In the example shown in FIG. 15B, when the previous reset factor is not a user reset due to a watchdog timer timeout (timeout has not occurred), the bit value of the internal information data CIF1 becomes “0”, while the watchdog When a user reset is caused by a timer timeout (timeout occurs), the bit value becomes “1”. The internal information data CIF0 stored in the bit number [0] of the internal information register CIF is an IAT generation instruction indicating whether or not the reset factor generated immediately before is a user reset due to prohibition of travel outside the designated area (IAT). . In the example shown in FIG. 15B, when the reset factor immediately before is not a user reset due to the occurrence of traveling outside the designated area (no IAT occurrence), the bit value of the internal information data CIF0 becomes “0”, while When the user reset is caused by the occurrence of out-of-area travel (the occurrence of IAT), the bit value becomes “1”.

  The CPU 56 included in the game control microcomputer 560 executes a user program (game control processing program for game control) based on the control code read from the ROM 54, thereby executing a game control in the pachinko gaming machine 1. CPU. When such game control is executed, the CPU 56 temporarily stores fixed data from the ROM 54, the CPU 56 temporarily stores various data in the RAM 55, and temporarily stores the data in the RAM 55. The CPU 56 temporarily stores the data in the RAM 55. The CPU 56 receives a variety of signals from the outside of the game control microcomputer 560 via the external bus interface 501, the PIP 510, the serial communication circuit 511, and the like. A transmission operation for outputting various signals to the outside of the game control microcomputer 560 via the external bus interface 501 and the serial communication circuit 511 is also performed.

  As described above, in the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54. Therefore, the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  The ROM 54 provided in the game control microcomputer 560 stores a control code indicating a user program (game control processing program for game control), fixed data, and the like. The ROM 54 stores a security check program 54A. The CPU 56 reads the security check program 54A stored in the ROM 54 when the game control microcomputer 560 shifts to the security mode in response to the power-on of the pachinko gaming machine 1 or the occurrence of a system reset. A security check process is executed to check whether or not the change has been made. The security check program 54A may be stored in a built-in memory different from the ROM 54. Further, the security check program 54A may correspond to a security check process for inspecting the storage content of an external memory externally attached to the game control microcomputer 560 via the external bus interface 501, for example.

  The RAM 55 provided in the game control microcomputer 560 provides a work area for game control. Here, at least a part of the RAM 55 may be a backup RAM that is backed up by a backup power source created in the power supply board 910. That is, even if the power supply to the pachinko gaming machine 1 is stopped, at least a part of the contents of the RAM 55 is stored for a predetermined period.

  The CTC 508 provided in the game control microcomputer 560 includes, for example, three channels (PTC0 to PTC2) of 8-bit programmable timers, and includes a timer circuit capable of generating a real-time interrupt and measuring time. Each programmable timer PTC0-PTC2 has a timer value that is updated in response to a change in the count clock signal generated based on the internal system clock SCLK (for example, a falling timing that changes from a high level to a low level). If it is. The CTC 508 may incorporate, for example, an 8-bit programmable counter with 4 channels (PCC0 to PCC3). Each of the programmable counters PCC0 to PCC3 only needs to have its count value updated in response to a signal change of the internal system clock SCLK or occurrence of a timeout in any of the programmable counters PCC0 to PCC3. The CTC 508 may include a free-run counter used to randomly determine an extension time (variable setting time) for extending the security time for each system reset. Alternatively, such a free-run counter may be included in an internal circuit of the game control microcomputer 560 different from the CTC 508, for example, a backup area of the RAM 55.

  A random number circuit 509 provided in the game control microcomputer 560 is a circuit that generates numerical data that is a random value having a predetermined update range, such as a 16-bit random number. In this embodiment, the hardware random number generated by the random number circuit 509 is used as a big hit determination random number (random R) for determining whether or not to make a big hit. Note that the CPU 56 uses the random counter different from the random number circuit 509 based on the numerical data extracted from the random number circuit 509 to process or update various numerical data by software so that all the random values used in the game can be obtained. Alternatively, numerical data indicating a part may be counted. Alternatively, the CPU 56 may count (update) a part of numerical data indicating a random value such as a big hit determination random number by software without using the random number circuit 509. As an example, numerical data extracted by the CPU 56 from the random number circuit 509 serving as hardware is processed by software to update the numerical data indicating the random number for jackpot determination (random R), and other random values (for example, The numerical data indicating the jackpot type determination random number, the variation pattern type determination random number, and the variation pattern determination random number) may be updated by software using the random counter or the like.

  FIG. 16 is a block diagram illustrating a configuration example of the random number circuit 509. As shown in FIG. 16, the random number circuit 509 includes a frequency monitoring circuit 551, a clock flip-flop 552, a random number generation circuit 553, a start value setting circuit 554, a free-run counter 554A, a random number sequence change circuit 555, and a random number sequence change setting circuit. 556, latch flip-flops 557A and 557B, random number latch selectors 558A and 558B, and random number value registers 559A and 559B. Note that the random value register 559A and the random value register 559B are a random value register R1D (address 2038H-2039H) and a random value register R2D included in the built-in registers of the game control microcomputer 560 as shown in FIG. (Addresses 203AH-203BH).

  The frequency monitoring circuit 551 is a circuit for monitoring the input state of the random number clock RCLK generated by the random number clock generation circuit 112 to the random number circuit 509 and detecting the occurrence of an abnormality. The frequency monitoring circuit 551 monitors, for example, an oscillation signal input to the random number external clock terminal ERC, and compares it with the internal system clock SCLK to set contents in the bit number [7-6] of the security time setting KSES (see FIG. 14 (B)), the bit number [4] of the internal information register CIF is set to “1”. In this embodiment, the random number clock RCLK generated by the random number clock generation circuit 112 is input to the random number external clock terminal ERC.

  The clock flip-flop 552 is configured using, for example, a D-type flip-flop, and the random number clock RCLK from the random number external clock terminal ERC is input to the clock terminal CK. Further, in the clock flip-flop 552, the negative phase output terminal (inverted output terminal) Q bar is connected to the D input terminal. The random number update clock RGK is output from the positive phase output terminal (non-inverted output terminal) Q, while the latch clock RC0 is output from the negative phase output terminal (inverted output terminal) Q bar. In this case, when the signal state of the random number clock RCLK input to the clock terminal CK changes a predetermined state, the clock flip-flop 552 has a positive phase output terminal (non-inverted output terminal) Q and a negative phase output terminal ( Inverted output terminal) Changes the signal state in the output signal from the Q bar. For example, the clock flip-flop 552 rises when the signal state of the random number clock RCLK changes from a low level to a high level, or rises when the signal state of the random number clock RCLK changes from a high level to a low level. The input signal at the D input terminal is captured at any one of the falling timings. At this time, from the positive phase output terminal (non-inverted output terminal) Q, the input signal captured at the D input terminal is output without being inverted, while the negative phase output terminal (inverted output terminal) Q bar is output. From the input signal captured by the D input terminal is inverted and output. Thus, the random number update clock RGK having an oscillation frequency (for example, 10 MHz) that is ½ of the oscillation frequency (for example, 20 MHz) of the random number clock RCLK from the positive phase output terminal (non-inverted output terminal) Q of the clock flip-flop 552. Is output from the negative phase output terminal (inverted output terminal) Q bar, that is, the reverse phase signal (inverted signal) of the random number update clock RGK, that is, the same frequency as the random number update clock RGK and the phase of the random number update clock RGK is π. A different latch clock RC0 is output by (= 180 °).

  The random number update clock RGK output from the clock flip-flop 552 is input to the clock terminal of the random number generation circuit 553 and used for incrementing the count value in the random number generation circuit 553. The latch clock RC0 output from the clock flip-flop 552 is branched into the latch clock RC1 and the latch clock RC2 at the branch point BR1. Therefore, the latch clock RC1 and the latch clock RC2 have the same oscillation frequency, and the signal state changes with a common cycle. Here, examples of changes in the signal state in the latch clock RC1 and the latch clock RC2 include a rising edge that changes from a low level to a high level and a falling edge that changes from a high level to a low level. The latch clock RC1 is input to the clock terminal CK of the latch flip-flop 557A, and becomes a random number acquisition clock used to generate the start winning latch signal SL1. The latch clock RC2 is input to the clock terminal CK of the latch flip-flop 557B and becomes a random number acquisition clock used to generate the start winning latch signal SL2.

  Here, the oscillation frequency of the random number clock RCLK and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111 are different from each other, and one of the oscillation frequencies is the other. It is never an integral multiple of the oscillation frequency. As an example, while the oscillation frequency of the control clock CCLK is 11.0 MHz, the oscillation frequency of the random number clock RCLK may be 9.7 MHz. Therefore, both the random number update clock RGK and the latch clocks RC1 and RC2 are oscillation signals whose signal states change at a different period from the control clock CCLK supplied to the CPU 56. In other words, the clock flip-flop 552 is based on the random number clock RCLK generated by the random number clock generation circuit 112, and the random number update clock RGK for updating the count value and the latch clock that is used as a plurality of random number acquisition clocks. As RC1 and RC2, oscillation signals whose signal states change with a period different from the control clock CCLK and the internal system clock SCLK (the control clock CCLK divided by two) are generated.

  The random number generation circuit 553 is composed of, for example, a 16-bit counter and the like, based on an input such as a random number update clock RGK output from the clock flip-flop 552, from a predetermined initial value within a predetermined range in which numerical data can be updated. It is a circuit that cyclically updates to a predetermined final value. For example, the random number generation circuit 553 responds to the falling edge of the random number update clock RGK, which is an input signal to a predetermined clock terminal, from the initial value set within the range from “0” to “65535” to “65535”. The numerical data is counted up so that “1” is added to “1”. Then, after counting up to “65535”, the numerical data is updated cyclically by counting up from “0” to a numerical value that becomes a final value that is 1 smaller than the initial value.

  The start value setting circuit 554 sets the start value in the count value generated by the random number generation circuit 553 in accordance with the bit value (see FIG. 13B) in the bit number [1-0] of the second random number initial setting KRS2. Set. For example, the start value setting circuit 554 sets the start value to the default value “0000H” if the bit number [1-0] of the second random number initial setting KRS2 is “00”, and if it is “10”. A value based on the ID number is set. If “01”, the value is set based on the count value in the free-run counter 554A which is changed every time the system is reset. Set to a value based on the count value. In the configuration example shown in FIG. 16, a free-run counter 554A is built in the random number circuit 509. When the start value is changed at every system reset, the count value of the free-run counter 554A is used as it is at the initial setting, or the count value is substituted into a predetermined arithmetic function (for example, a hash function). The start value may be determined at random by using the obtained value. The free-run counter 554A only needs to be backed up using a backup power source common to the backup location on the main board 31, such as a backup area in the RAM 55 of the game control microcomputer 560. Alternatively, the free-run counter 554A may be backed up by a power source provided separately from a backup power source used for a backup area in the RAM 55 or the like. In this way, the free-run counter 554A is backed up by the backup power source, so that the count value in the free-run counter 554A is stored for a predetermined period even when the power supply is stopped.

  The free-run counter 554A is not limited to the one backed up by the backup power source. For example, when a system reset occurs, the count value of the free-run counter 554A is stored in a predetermined built-in register (for example, a random number start value register). May be backed up by a backup power source. Then, the initial value is randomly determined by using the stored value of the random number start value register as it is or by using the value obtained by substituting the stored value into a predetermined arithmetic function. Also good. In this case, the timing at which the count value in the free-run counter 554A is read and stored in the random number start value register is not limited to when a system reset occurs, but may be any predetermined timing. The free-run counter 554A may be a dedicated free-run counter built in the random number circuit 509 and used to randomly determine the start value of numerical data. That is, the free-run counter 554A may be provided as a separate configuration from the free-run counter used for random determination of the extension time when extending the security time. Alternatively, as a free-run counter 554A, a free-run counter incorporated in the game control microcomputer 560 but provided outside the random number circuit 509 and used for random determination of the extension time when extending the security time. A common one may be used. In this case, in the process of determining the start value of the numerical data and the process of randomly determining the extension time in the security time, for example, the calculation function for substituting the count value is different from each other, or one of the determinations is made In the process, the count value is used as it is, while in the other determination process, the value obtained by substituting the count value into a predetermined arithmetic function is used. It may be different.

  Thus, the free-run counter 554A is not limited to the one built in the random number circuit 509, and may be included in the CTC 508, for example. Alternatively, it may be included in an internal circuit of the game control microcomputer 560 different from the CTC 508, for example, a backup area of the RAM 55. In addition, the free-run counter 554A may be the same counter as the free-run counter used for randomly determining the extension time for extending the security time for each system reset, or provided separately. It may be a counter.

  The random number sequence change circuit 555 is a circuit that allows the permutation of numerical data generated by the random number generation circuit 553 to be changed to a permutation according to a predetermined random number update rule. For example, the random number sequence change circuit 555 executes bit scramble processing such as bit replacement or transposition in numerical data output from the random number generation circuit 553. Further, the random number sequence change circuit 555 can change the permutation of numerical data, for example, by changing a bit scramble key or a bit scramble table used for bit scramble processing.

  The random number sequence change setting circuit 556 changes the random number update rule in the random number sequence change circuit 555 according to the bit value (see FIG. 13A) in the bit number [1-0] of the first random number initial setting KRS1. It is a circuit for setting. For example, if the bit number [1-0] of the first random number initial setting KRS1 is “00”, the random number sequence change setting circuit 556 sets the random number update rule not to change after the second round, while “01” If so, the random number update rule is changed in response to a change request by software after the second round, and if it is “10”, the random number update rule is automatically changed.

  When the random number update circuit 556 changes the random number update rule by software in response to the bit number [1-0] of the first random number initial setting KRS1 being “01”, FIG. Among the built-in registers included in the game control microcomputer 560 as shown, the random number update rule RDSC (address 2034H) is used to control the change of the random number update rule. FIG. 17A shows a configuration example of the random number sequence change register RDSC. FIG. 17B shows an example of setting contents in each bit of random number sequence change request data stored in the random number sequence change register RDSC. The random number sequence change request data RDSC0 stored in the bit number [0] of the random number sequence change register RDSC indicates the presence / absence of a random number sequence change request when the random number update rule is changed by software. In the example shown in FIG. 17B, when the random number sequence change request is not received by software, the bit value of the random number sequence change request data RDSC0 is “0”. The bit value is “1”.

  FIG. 18 shows an operation example when the random number update rule is changed by software. In this case, when the count value permutation RCN output from the random number generation circuit 553 is cyclically updated from a predetermined initial value to a predetermined final value, the response is that the random number sequence change request data RDSC0 is “1”. Then, change the random number update rule. In the operation example shown in FIG. 18, the random number sequence RSN output from the random number sequence change circuit 555 first is “0 → 1 →... → 65535”. Thereafter, it is assumed that “1” is written to the bit number [0] of the random number sequence change register RDSC at a predetermined timing by the CPU 56 executing the user program stored in the ROM 54.

  In response to the bit number [1-0] of the first random number initial setting KRS1 being “01”, the random number sequence change setting circuit 556 reads the random number sequence change request data RDSC0 and the bit value is “1”. In response to "," a setting for changing the random number update rule is made. At this time, the random number sequence change setting circuit 556, according to the count value permutation RCN output from the random number generation circuit 553 reaching a predetermined final value, for example, any one of a plurality of types of random number update rules prepared in advance. The random number update rule is changed by selecting. In the operation example shown in FIG. 18, the random number sequence change circuit 555 outputs numerical data “65535” corresponding to the final value in the count value permutation RCN output from the random number generation circuit 553, and then responds to the random number sequence change request data RDSC0. Change the random number update rule. Thereafter, the random number sequence change circuit 555 outputs “65535 → 65534 →... → 0” as the random number sequence RSN according to the changed random number update rule. The random number sequence change register RDSC is initialized when the random number sequence change setting circuit 556 reads the random number sequence change request data RDSC0. Therefore, until the bit value “1” is written to the bit number [0] of the random number sequence change register RDSC again, the random number sequence RSN output from the random number sequence change circuit 555 is “65535 → 65534 →... → 0”. Become.

  When the CPU 56 executes the user program stored in the ROM 54 and the bit value “1” is written again to the bit number [0] of the random number sequence change register RDSC, the random number update rule is changed again. In the operation example shown in FIG. 18, when the random number sequence change circuit 555 outputs the numerical data “0” corresponding to the final value in the random number sequence RSN, the bit value “1” is written as the random number sequence change request data RDSC0. Change the random number update rule accordingly. Thereafter, the random number sequence changing circuit 555 outputs “0 → 2 →... → 65534 → 1 →... → 65535” as the random number sequence RSN according to the changed random number update rule.

  FIG. 19 shows an operation example when the random number update rule is automatically changed. In this case, in response to the count value permutation RCN output from the random number generation circuit 553 being cyclically updated from a predetermined initial value to a predetermined final value, the random number sequence change setting circuit 556 automatically changes the random number update rule. To change. In the operation example shown in FIG. 19, the random number sequence RSN output from the random number sequence change circuit 555 is “0 → 1 →... → 65535”.

  When the random number sequence RSN output from the random number change circuit 555 reaches a predetermined final value, the random number sequence change setting circuit 556 follows a predetermined order from among a plurality of types of update rules prepared in advance. The update rule may be changed by selecting the update rule. Alternatively, the random number sequence change setting circuit 556 may change the update rule by selecting an arbitrary update rule from among a plurality of types of update rules. In the operation example shown in FIG. 19, the random number sequence RSN output from the random number sequence change circuit 555 becomes “65535 → 65534 →. Thereafter, due to the second change in the random number update rule, the random number sequence RSN output from the random number sequence change circuit 555 becomes “0 → 2 →... → 65534 → 1 →. In the operation example illustrated in FIG. 19, the random number sequence RSN output from the random number sequence change circuit 555 is “65534 → 0 →... → 32768” due to the third change in the random number update rule. When the fourth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 555 becomes “16383 → 49151 →... → 49150”. When the fifth random number update rule change is performed, the random number sequence RSN output from the random number sequence change circuit 555 becomes “4 → 3 →... → 465553”.

  Thus, the random number sequence change circuit 555 changes the count value permutation RCN output from the random number generation circuit 553 based on the random number update rule determined in advance by the setting of the random number sequence change setting circuit 556, so that the numerical value A random number sequence RSN in which data is updated by a predetermined procedure can be output.

  Each of the latch flip-flops 557A and 557B is configured using, for example, a D-type flip-flop. In the latch flip-flop 557A, a wiring from the input port P0 included in the PIP 510 is connected to the D input terminal, and a wiring for transmitting the latch clock RC1 is connected to the clock terminal CK. In this embodiment, the start winning signal SS from the start port switch 14a is input to the input port P0. The latch flip-flop 557A takes in the start winning signal SS in response to the falling edge of the latch clock RC1, and outputs it as the start winning latch signal SL1. Thus, in the latch flip-flop 557A, the start winning signal SS is output as the start winning latch signal SL1 in synchronization with the falling edge of the latch clock RC1. In the latch flip-flop 557B, a wiring from the input port P1 included in the PIP 510 is connected to the D input terminal, and a wiring for transmitting the latch clock RC2 is connected to the clock terminal CK. In this embodiment, the start winning signal SS from the start port switch 14a is also input to the input port P1. The latch flip-flop 557B takes in the start winning signal SS in response to the falling edge of the latch clock RC2, and outputs it as the start winning latch signal SL2. Thus, in the latch flip-flop 557B, the start winning signal SS is output as the start winning latch signal SL2 in synchronization with the falling edge of the latch clock RC2. For example, when the gaming machine has two start winning ports, a start winning signal from one start port switch is output as a start winning latch signal SL1, and a start winning signal from the other start port switch is output. It may be output as the start winning latch signal SL2.

  The start winning signal SS is not limited to the signal directly transmitted from the start port switch 14a. As an example, a timer circuit that measures the time during which the output signal from the start port switch 14a is on and outputs a start winning signal SS when the measured time reaches a predetermined time (for example, 3 ms). It may be provided.

  The random number latch selector 558A is a circuit that takes in the start winning latch signal SL1 transmitted from the latch flip-flop 557A and the random number latch request signal by software, and selectively outputs one as the random number latch signal LL1. The random number latch selector 558B is a circuit that takes in the start winning latch signal SL2 transmitted from the latch flip-flop 557B and the random number latch request signal by software, and selectively outputs one as the random number latch signal LL1. The random number latch selector 558A and the random number latch selector 558B are a random value fetch register RDLT (address 2032H) and a random number latch selection register RDLS among the built-in registers included in the game control microcomputer 560 as shown in FIG. (Address 2030H) is used to control the output of the random number latch signal LL1 and the random number latch signal LL2. The random value acquisition register RDLT is a register used for acquiring numerical data in the random number sequence RSN output from the random number sequence change circuit 555 into the random value register 559A or the random value register 559B by software. The random number latch selection register RDLS receives the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 into the random number value register 559A or the random number value register 559B by software, or by signal input to the input ports P0 and P1. It is a register indicating a fetching method of fetching.

  FIG. 20A shows a configuration example of the random value fetch register RDLT. FIG. 20B shows an example of the setting contents in each bit of the random value fetch specification data stored in the random value fetch register RDLT. The random value acquisition specification data RDLT1 stored in the bit number [1] of the random value acquisition register RDLT indicates whether or not the random value acquisition specification for the random value register 559B serving as the random value register R2D is present. In the example shown in FIG. 20 (B), when the random number value acquisition specification for the random value register R2D is not specified by software, the bit value of the random value acquisition specification data RDLT1 is “0”, while the random value acquisition is not performed. The bit value is “1” when an instruction is included. The random value acquisition specification data RDLT0 stored in the bit number [0] of the random value acquisition register RDLT indicates whether or not a random value acquisition specification is given to the random value register 559A serving as the random value register R1D. In the example shown in FIG. 20 (B), when the random number value acquisition specification for the random value register R1D is not specified by software, the bit value of the random value acquisition specification data RDLT0 is “0”, while the random value acquisition is not performed. The bit value is “1” when an instruction is included.

  FIG. 21A shows a configuration example of the random number latch selection register RDLS. FIG. 21B shows an example of setting contents in each bit of random number latch selection data stored in the random number latch selection register RDLS. The random number latch selection data RDLS1 stored in the bit number [1] of the random number latch selection register RDLS indicates a method of taking in the random number value register 559B serving as the random number value register R2D. In the example shown in FIG. 21B, when the numerical value data that becomes the random number value is loaded into the random number value register R2D in response to the writing of the random number value loading designation data RDLT1 by the software, the bit value of the random number latch selection data RDLS1 is set to “ 0 ”. On the other hand, when the numerical value data to be a random number value is taken into the random value register R2D in response to the signal input to the input port P1, the bit value of the random number latch selection data RDLS1 is set to “1”. The random number latch selection data RDLS0 stored in the bit number [0] of the random number latch selection register RDLS indicates a method of taking in the random number value register 559A serving as the random number value register R1D. In the example shown in FIG. 21B, when the numerical value data that becomes the random number value is loaded into the random number value register R1D in response to the writing of the random number value loading designation data RDLT0 by software, the bit value of the random number latch selection data RDLS0 is set to “ 0 ”. On the other hand, when the numerical value data to be a random number value is taken into the random value register R1D in response to the signal input to the input port P0, the bit value of the random number latch selection data RDLS0 is set to “1”.

  The random value registers 559A and 559B are registers for storing numerical data in the random number sequence RSN output from the random number sequence changing circuit 555 as random number values. 22A and 22B show a configuration example of a random value register 559A serving as the random value register R1D. 22A shows the lower byte R1D (L) of the random value register R1D, and FIG. 22B shows the upper byte R1D (H) of the random value register R1D. 22C and 22D show a configuration example of a random value register 559B serving as the random value register R2D. Note that FIG. 22C shows the lower byte R2D (L) of the random value register R2D, and FIG. 22D shows the upper byte R2D (H) of the random value register R2D. Each of the random value registers 559A and 559B is a 16-bit (2-byte) register and can store a 16-bit random value.

  The random value register 559A takes in the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 as a random value in response to the random number latch signal LL1 supplied from the random number latch selector 558A being turned on. Store with. When the register read signal RRS1 supplied from the CPU 56 is turned on, the random value register 559A is in a readable (enable) state and outputs the stored numerical data to an internal bus or the like. On the other hand, when the register read signal RRS1 is in the off state, the same value (for example, “65535H” or the like) is always output, and the reading is disabled (disabled). Further, the random value register 559A may be in a state in which the register read signal RRS1 cannot be received when the random number latch signal LL1 is in the ON state. Further, the random number register 559A may be configured to be in a state in which the random number latch signal LL1 cannot be received when the register read signal RRS1 is in the on state before the random number latch signal LL1 is in the on state. Good.

  The random value register 559B takes in the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 as a random value in response to the random number latch signal LL2 supplied from the random number latch selector 558B being turned on. Store with. When the register read signal RRS2 supplied from the CPU 56 is turned on, the random value register 559B is in a readable (enable) state and outputs stored numerical data to an internal bus or the like. On the other hand, when the register read signal RRS2 is in the OFF state, the same value (for example, “65535H” or the like) is always output, and the reading is disabled (disabled). Further, the random value register 559B may be in a state in which the register read signal RRS2 cannot be received when the random number latch signal LL2 is in the ON state. Further, the random value register 559B may be configured to be in a state in which the random number latch signal LL2 cannot be received when the register read signal RRS2 is in the on state before the random number latch signal LL2 is in the on state. Good.

  The random value register 559A and the random value register 559B are a random number latch flag register RDFM (address 2033H) and a random number interrupt control register RDIC (of the built-in registers included in the game control microcomputer 560 as shown in FIG. 11B). Address 2031H) and enable operation management and interrupt control at the time of random number latching. The random number latch flag register RDFM is a register for storing a random number latch flag indicating whether or not numerical data to be a random number value is latched corresponding to each of the random number value register 559A and the random number value register 559B. For example, in the random number latch flag register RDFM, data indicating the state (ON or OFF) of the random number latch flag corresponding to each of the random number value register 559A and the random number value register 559B is stored, and numerical values are stored in the random number value register 559A and the random number value register 559B. When the data is fetched and stored, the corresponding random number latch flag is turned on and storage of new numerical data is restricted, while the numerical data stored in the random value register 559A or the random value register 559B is read. The corresponding random number latch flag is turned off, and storage of new numerical data is permitted. The random number interrupt control register RDIC is a register that sets permission / prohibition of an interrupt that occurs when numerical data that becomes a random value is latched in the random value register 559A or the random value register 559B.

  FIG. 23A shows a configuration example of the random number latch flag register RDFM. FIG. 23B shows an example of setting contents in each bit of the random number latch flag data stored in the random number latch flag register RDFM. The random number latch flag data RDFM1 stored in the bit number [1] of the random number latch flag register RDFM becomes a random number latch flag indicating whether or not numerical data has been taken into the random number value register 559B serving as the random number value register R2D. In the example shown in FIG. 23B, when the numerical value data is not taken into the random value register R2D (no random value is taken), the bit value of the random number latch flag data RDFM1 becomes “0” and the random number latch flag is set. On the other hand, when the numerical data is fetched (with random number fetching), the bit value becomes “1” and the random number latch flag is set to the on state while clearing to the off state. The random number latch flag data RDFM0 stored in the bit number [0] of the random number latch flag register RDFM is a random number latch flag indicating whether or not numerical data has been taken into the random number value register 559A serving as the random number value register R1D. In the example shown in FIG. 23B, when the numerical data is not taken into the random value register R1D (no random value is taken), the bit value of the random number latch flag data RDFM0 becomes “0” and the random number latch flag is set. On the other hand, when the numerical data is fetched (with random number fetching), the bit value becomes “1” and the random number latch flag is set to the on state while clearing to the off state.

  When each random number latch flag is on, storage of new numerical data in the random number value register R1D or the random number value register R2D associated with each random number latch flag is restricted (prohibited). That is, when the bit value of the random number latch flag data RDFM0 indicating whether or not the numerical value data is taken into the random number value register R1D is “1” and the random number latch flag is in the ON state, the numerical value stored in the random number value register R1D Data cannot be changed, and storage (import) of new numerical data is restricted (prohibited). Further, when the bit value of the random number latch flag data RDFM1 indicating whether or not the random number value data is taken into the random number value register R2D is “1” and the random number latch flag is in the ON state, the random number value register R2D is stored in the random number value register R2D. Numerical data cannot be changed, and storage (import) of new numerical data is restricted (prohibited). On the other hand, when each random number latch flag is off, storage of new numerical data in the random number value register R1D or the random number value register R2D associated with each random number latch flag is permitted. That is, when the bit value of the random number latch flag data RDFM0 is “0” and the random number latch flag is in the OFF state, the numerical data stored in the random value register R1D can be changed, and new numerical data is stored ( Import) is allowed. Further, when the bit value of the random number latch flag data RDFM1 is “0” and the random number latch flag is in the OFF state, the numerical data stored in the random value register R2D can be changed, and new numerical data can be stored ( Import) is allowed.

  Note that the bit values of the random number latch flag data RDFM0 and the random number latch flag data RDFM1 are set to “0” when the corresponding random number latch flag is cleared to “off”, while being set to “1”. It is not limited to a positive logic type, and it may be a negative logic type that turns on when a corresponding random number latch flag is turned off when it is “1”. That is, each random number latch flag is turned on when numerical data is stored in the corresponding random value register R1D or random value register R2D, and the storage of new numerical data is restricted (prohibited), while the corresponding random value Any register may be used as long as it is turned off when reading of the register R1D or the random number register R2D is performed and storage of new numerical data is permitted.

  FIG. 24A shows a configuration example of the random number interrupt control register RDIC. FIG. 24B shows an example of setting contents in each bit of random number interrupt control data stored in the random number interrupt control register RDIC. The random number interrupt control data RDIC1 stored in the bit number [1] of the random number interrupt control register RDIC permits or prohibits an interrupt that occurs when numerical data is taken into the random number value register 559B serving as the random number value register R2D. Indicates the interrupt control setting for In the example shown in FIG. 24B, when interrupting at the time of fetching into the random value register R2D is prohibited (interrupt disabled), the bit value of the random number interrupt control data RDIC1 is set to “0”, while this interrupt is When enabling (interrupt enabled), the bit value is set to “1”. The random number interrupt control data RDIC0 stored in the bit number [0] of the random number interrupt control register RDIC allows or prohibits an interrupt that occurs when numerical data is taken into the random value register 559A that becomes the random value register R1D. Indicates the interrupt control setting for In the example shown in FIG. 24 (B), when interrupting at the time of fetching into the random value register R1D is prohibited (interrupt disabled), the bit value of the random number interrupt control data RDIC0 is set to “0”, while this interrupt is When enabling (interrupt enabled), the bit value is set to “1”.

  In the configuration example shown in FIG. 9, a random number circuit 509 is built in the game control microcomputer 560. On the other hand, for example, as shown in FIG. 25, the random number circuit 509 may be externally attached to the game control microcomputer 560 as a random number circuit chip different from the game control microcomputer 560. In this case, the start winning signal SS from the start port switch 14a is branched inside the switch circuit 114, one is input to the input port P0 of the PIP 510 provided in the game control microcomputer 560, and the other is the random number circuit 509. May be input to the D input terminal of the latch flip-flops 557A and 557B. Between the game control microcomputer 560, for example, the frequency monitor circuit 551 provided in the random number circuit 509 includes the internal system clock SCLK output from the clock circuit 502 provided in the game control microcomputer 560 via the system clock output terminal CLKO. The random number value register R1D and the random number value register R2D are input to the clock flip-flop 552 or via an address bus, data bus, control signal line, etc. connected to the external bus interface 501 provided in the game control microcomputer 560. The numerical data stored in the data may be read out.

  Also, as shown in FIG. 25, when the random number circuit 509 is externally attached to the game control microcomputer 560, the random number value register R1D and the random number value register R2D depending on the state (ON / OFF) of each random number latch flag. It is only necessary to limit (prohibit) or permit storage of new numerical data in the. Among the built-in registers shown in FIG. 11B, for example, the random number latch selection register RDLS, the random number interrupt control register RDIC, the random value fetch register RDLT, the random number latch flag register RDFM, the random number sequence change register RDSC, the random number value register R1D, random Various registers used by the random number circuit 509, such as the numerical register R2D, may not be built in the game control microcomputer 560 but may be built in the random number circuit 509 externally attached to the game control microcomputer 560. . In this case, the CPU 56 of the game control microcomputer 560 may write and read various registers built in the random number circuit 509 via, for example, the external bus interface 501 or the like.

  The PIP 510 provided in the game control microcomputer 560 shown in FIG. 9 is, for example, a 6-bit input dedicated port. P5 is included. The input port P3 is also used as an external maskable interrupt terminal XINT connected to the CPU 56 or the like. The input port P4 is also used as an external non-maskable interrupt terminal XNMI connected to the CPU 56 and the like. The input port P5 is also used as the first channel reception terminal RXA used by the serial communication circuit 511. The use setting of the input port P3 to the input port P5 is instructed by the function setting KFCS stored in the program management area.

  The PIP 510 uses the input port register PI (address 2090H) among the built-in registers included in the game control microcomputer 560 as shown in FIG. 11 (B) to manage the status of the input port P0 to the input port P5. Do. The input port register PI is a register that stores a bit value indicating the input state of the external signal corresponding to each of the input port P0 to the input port P5.

  FIG. 26A shows a configuration example of the input port register PI. FIG. 26B shows an example of the setting contents in each bit of the input port data stored in the input port register PI. The input port data PI5 stored in the bit number [5] of the input port register PI indicates the terminal state (ON / OFF) at the input port P5 that is also used as the first channel receiving terminal RXA. The input port data PI4 stored in the bit number [4] of the input port register PI indicates the terminal state (ON / OFF) at the input port P4 that is also used as the external non-maskable interrupt terminal XNMI. The input port data PI3 stored in the bit number [3] of the input port register PI indicates the terminal state (ON / OFF) at the input port P3 that is also used as the external maskable interrupt terminal XINT. The input port data PI2 stored in the bit number [2] of the input port register PI indicates the terminal state (ON / OFF) at the input port P2. The input port data PI1 stored in the bit number [1] of the input port register PI indicates the terminal state (ON / OFF) at the input port P1. The input port data PI0 stored in the bit number [0] of the input port register PI indicates the terminal state (ON / OFF) at the input port P0.

  Next, the configuration of the serial communication circuit 511 will be described. The serial communication circuit 511 is a data format using a full-duplex method, an asynchronous method, and standard NRZ (non-return zero) encoding, and a microcomputer on each control board (for example, the payout control board 37 and the effect control board 80). Perform serial communication. The serial communication circuit 511 transmits a variety of data (for example, prize ball number command and effect control command) to the microcomputer of each control board, and various data (for example, prize ball ACK) from the microcomputer of each control board. Command).

  FIG. 27 is a block diagram illustrating a configuration example of the transmission unit of the serial communication circuit 511. FIG. 28 is a block diagram illustrating a configuration example of the receiving unit of the serial communication circuit 511. The serial communication circuit 511 includes a baud rate register 702, a baud rate generation circuit 703, two status registers 705 and 706, three control registers 707, 708, and 709, a transmission data register 710, a reception data register 711, a transmission shift register 712, and a reception Shift register 713, interrupt control circuit 714, transmission format / parity generation circuit 715, and reception format / parity check circuit 716. As shown in FIG. 27, the transmission unit of the serial communication circuit 511 includes a baud rate register 702, a baud rate generation circuit 703, a status register A 705, control registers 707, 708, and 709, a transmission data register 710, among these components. , A transmission shift register 712, an interrupt control circuit 714, and a transmission format / parity generation circuit 715. As shown in FIG. 28, the receiving unit of the serial communication circuit 511 includes a baud rate register 702, a baud rate generation circuit 703, status registers 705 and 706, control registers 707, 708, and 709, received data, among these components. The register 711, the reception shift register 713, the interrupt control circuit 714, and the reception format / parity check circuit 716 are configured.

  In the serial communication circuit 511, the transmission unit and the reception unit are actually configured by using a common circuit. As described above, the serial communication circuit 511 functions as a transmission circuit or a reception circuit by properly using each component of the serial communication circuit 511.

  First, the data format of data transmitted and received by the serial communication circuit 511 with the microcomputer mounted on each control board will be described. FIG. 29 is an explanatory diagram showing an example of a data format of data transmitted / received by the serial communication circuit 511 to / from a microcomputer mounted on each control board. As shown in FIG. 29, the data format of data transmitted and received by the serial communication circuit 511 is configured with a start bit, data, and stop bits as one frame. Further, the data length of data transmitted and received by the serial communication circuit 511 can be set to either 8 bits or 9 bits by performing initial setting in a serial communication circuit setting process described later. FIG. 29A shows an example of a data format when the data length is set to 8 bits. FIG. 29B shows an example of the data format when the data length is set to 9 bits.

  As shown in FIG. 29, the data format of data transmitted / received by the serial communication circuit 511 is a start bit (logic “0”) indicating the start of one frame after an idle line of high level (logic “1”). ")including. The data format includes 8-bit or 9-bit transmission / reception data after the start bit. The data format includes a stop bit (logic “1”) indicating the end of one frame after transmission / reception data.

  The serial communication circuit 511 transmits / receives data first from the least significant bit (bit 0) of the transmission / reception data according to the data format shown in FIG. Further, if initial setting is performed in a serial communication circuit setting process described later, it is possible to set so that a parity bit is added to transmission / reception data. When a setting is made to add a parity bit, the most significant bit of the transmission / reception data is used as a parity bit (odd parity or even parity). For example, when the data length is set to 8 bits, bit 7 of transmission / reception data is used as a parity bit. For example, when the data length is set to 9 bits, bit 8 of transmission / reception data is used as a parity bit.

  The baud rate generation circuit 703 generates a baud rate used by the serial communication circuit 511 based on a clock signal output from the clock circuit 501 and a setting value (also referred to as a baud rate setting value) set in the baud rate register 702. In this case, the baud rate generation circuit 703 obtains the baud rate using a predetermined calculation formula based on the clock signal and the baud rate setting value. For example, the baud rate generation circuit 703 obtains the baud rate used by the serial communication circuit 511 using Expression (1).

Baud rate = clock frequency / (baud rate set value x 16) Equation (1)

  FIG. 30 is an explanatory diagram showing an example of the baud rate register 702. The baud rate register 702 is a register that sets a predetermined setting value for designating a baud rate value generated by the baud rate generation circuit 703. For example, it is assumed that the baud rate register 702 obtains the baud rate using the equation (1) and the clock frequency is 3 MHz. In this case, if the desired target baud rate is 1200 bps, the setting value “156” is set in the baud rate register 702. Then, the baud rate generation circuit 703 generates the baud rate “1201.92 bps” using the equation (1) based on the clock frequency “3 MHz” and the baud rate set value “156”. The baud rate register 702 is a 16-bit register, and an initial value is set to “0 (= 00h)”. The baud rate register 702 is configured such that bits 0 to 12 can be written and read. Further, the baud rate register 702 is configured such that bits 13 to 15 cannot be written or read. Therefore, even if a control for writing a value to bits 13 to 15 of the baud rate register 702 is performed, it is invalid, and all the values read from the bits 13 to 15 are “0 (= 000b)”.

  FIG. 31A is an explanatory diagram illustrating an example of the control register A707. The control register A 707 is a register for setting the communication format of the serial communication circuit 511. In this embodiment, the communication format of the serial communication circuit 511 is set by setting the value of each bit of the control register A707. In the control register A707, communication format setting data for setting a communication format such as a data format of transmission / reception data and various communication methods is set. As shown in FIG. 31A, the control register A707 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register A 707 is configured such that bits 0 to 4 can be written and read. Control register A 707 is configured such that bits 5 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 5 to 7 of the control register A707, it is invalid, and all the values read from bits 5 to 7 are “0 (= 000b)”.

  FIG. 31B is an explanatory diagram of an example of communication format setting data set in the control register A707. As shown in FIG. 31B, setting data for setting the data length of data to be transmitted and received is set in bit 4 (bit name “M”) of the control register A707. As shown in FIG. 31B, by setting bit 4 to “0”, the data length of the transmission / reception data is set to 8 bits. Further, by setting bit 4 to “1”, the data length of the transmission / reception data is set to 9 bits.

  In bit 3 (bit name “WAKE”) of the control register A707, setting data for setting a wake-up method for waking up the receiver circuit (the receiving unit of the serial communication circuit 511) in the standby state (making it online). Is set. As shown in FIG. 31 (B), by setting bit 3 to “0”, an idle line wakeup method for wakeup when an idle line is recognized is set. In addition, by setting bit 3 to “1”, an address mark wakeup method for wakeup by recognizing a predetermined address mark is set.

  In bit 2 (bit name “ILT”) of the control register A707, setting data for selecting an idle line detection method of received data is set. As shown in FIG. 31B, by setting bit 2 to “0”, a detection method for detecting the idle line after the start bit included in the received data is set. In addition, by setting bit 2 to “1”, a detection method for detecting an idle line after a stop bit included in received data is set.

  Setting data for setting whether to use the parity function is set in bit 1 (bit name “PE”) of the control register A707. As shown in FIG. 31B, by setting bit 1 to “0”, the parity function is set not to be used. Further, by setting bit 1 to “1”, the parity function is set to be used.

  Setting data for setting the type of parity when the parity function is used is set in bit 0 (bit name “PT”) of the control register A707. As shown in FIG. 31B, by setting bit 0 to “0”, even parity is set as the parity type. Also, by setting bit 0 to “1”, odd parity is set as the parity type.

  FIG. 32A is an explanatory diagram illustrating an example of the control register B708. The control register B 708 is a register for setting whether to permit an interrupt request from the serial communication circuit 511. In this embodiment, whether or not an interrupt request from the serial communication circuit 511 is permitted is set by setting the value of each bit of the control register B708. In the control register B708, interrupt request setting data indicating whether or not various interrupt requests are permitted is mainly set. In addition to the interrupt request setting data, setting data for performing various settings of the serial communication circuit 511 is also set in the control register B708. As shown in FIG. 32A, the control register B 708 is an 8-bit register, and its initial value is set to “0 (= 00h)”. Control register B 708 is configured such that bits 0 to 7 can be written and read.

  FIG. 32B is an explanatory diagram showing an example of interrupt request setting data set in the control register B708. As shown in FIG. 32B, setting data indicating whether or not a transmission interrupt request, which is an interrupt request to be performed at the time of data transmission, is permitted is set in bit 7 (bit name “TIE”) of the control register B708. Is done. As shown in FIG. 32B, by setting bit 7 to “0”, the transmission interrupt request is set to be prohibited. Also, by setting bit 7 to “1”, the transmission interrupt request is set to be permitted.

  Bit 6 (bit name “TCIE”) of the control register B708 is set with setting data indicating whether or not to permit a transmission completion interrupt request, which is an interrupt request to be made when data transmission is completed. As shown in FIG. 32B, by setting bit 6 to “0”, the transmission completion interrupt request is set to be prohibited. Also, by setting bit 6 to “1”, the transmission completion interrupt request is set to be permitted.

  Bit 5 (bit name “RIE”) of the control register B 708 is set with setting data indicating whether or not a reception interrupt request, which is an interrupt request performed when data is received, is permitted. As shown in FIG. 32B, by setting bit 5 to “0”, the reception interrupt request is set to be prohibited. Further, by setting bit 5 to “1”, the reception interrupt request is set to be permitted.

  Bit 4 (bit name “ILIE”) of the control register B 708 is set with setting data indicating whether or not to allow an idle line interrupt request, which is an interrupt request when an idle line of received data is detected. As shown in FIG. 32B, by setting bit 4 to “0”, an idle line interrupt request is set to be prohibited. Further, by setting bit 4 to “1”, it is set to permit an idle line interrupt request.

  In bit 3 (bit name “TE”) of the control register B708, setting data indicating whether or not to use the transmission circuit (the transmission unit of the serial communication circuit 511) is set. As shown in FIG. 32B, by setting bit 3 to “0”, the transmission circuit is set not to be used. Further, by setting bit 3 to “1”, the transmission circuit is set to be used. In this embodiment, setting to use the transmission circuit is performed by setting bit 3 to “1”. Such setting is performed in the initial setting of the main process (for example, step S15a).

  In bit 2 (bit name “RE”) of the control register B708, setting data indicating whether or not to use the receiving circuit is set. As shown in FIG. 32B, by setting bit 2 to “0”, the receiving circuit is set not to be used. Further, by setting bit 2 to “1”, the receiving circuit is set to be used. In this embodiment, setting to use the receiving circuit is performed by setting bit 2 to “1”. Such setting is performed in the initial setting of the main process (for example, step S15a).

  Setting data indicating whether or not to use the wakeup function of the receiving circuit is set in bit 1 (bit name “RWU”) of the control register B708. As shown in FIG. 32B, by setting bit 1 to “0”, the wakeup function is set not to be used. Further, by setting bit 1 to “1”, the wakeup function is set to be used.

  Setting data indicating whether or not to use a predetermined break code transmission function is set in bit 0 (bit name “SBK”) of the control register B708. As shown in FIG. 32B, by setting bit 1 to “0”, the break code transmission function is set not to be used. Further, by setting bit 1 to “1”, the break code transmission function is set to be used. When bit 1 is set to “1”, the serial communication circuit 511 causes the microcomputer on which the control board (the payout control board 37 and the effect control board 80) is mounted with a break code (for example, a signal including “0” continuously). Send to.

  FIG. 33A is an explanatory diagram showing an example of the status register A705. The status register A705 is a register for confirming various statuses of the serial communication circuit 511. In this embodiment, the CPU 56 can confirm various statuses of the serial communication circuit 511 by confirming the value of each bit of the status register A705. As shown in FIG. 33A, the status register A705 is an 8-bit register, and the initial value is set to “0 (= 00h)”. In addition, the status register A705 is configured so that bits 0 to 7 can only be read. Therefore, even if control is performed to write a value to bits 0 to 7 of the status register A705, it is invalid.

  In this embodiment, as will be described later, when transmission data is not stored in the transmission data register 710 (transmission data empty) or transmission of transmission data stored in the transmission shift register 712 is completed, interrupt control is performed. Circuit 714 sets the corresponding bit in status register A705. Then, the CPU 56 reads the value of each bit set in the status register A705.

  FIG. 33B is a diagram showing an example of status confirmation data stored in the status register A705. As shown in FIG. 33B, transmission data indicating that transmission data is not stored in transmission data register 710 in bit 7 (bit name “TDRE”) of status register A705 (transmission data empty). Stores an empty flag. As shown in FIG. 33B, when “0” is stored in bit 7, the transmission data is not yet transferred from the transmission data register 710 to the transmission shift register 712, and transmitted to the transmission data register 710. Indicates that the data is still stored. In addition, when “0” is stored in bit 7, data is not written to the transmission data register. For example, in steps S5211, S52305, transmission data is set on condition that “0” is not stored in bit 7. When “1” is stored in bit 7, the transmission data is transferred from the transmission data register 710 to the transmission shift register 712, and there is no transmission data in the transmission data register 710 (transmission data empty). ).

  Bit 6 (bit name “TC”) of the status register A 705 stores a transmission completion flag indicating that transmission of transmission data from the serial communication circuit 511 has been completed. As shown in FIG. 33B, when “0” is stored in bit 6, the transmission data stored in the transmission shift register 712 is being transmitted, and the transmission data from the serial communication circuit 511 is transmitted. Indicates that transmission has not been completed. When “1” is stored in bit 6, the transmission data stored in the transmission shift register 712 has been transferred, and the transmission of transmission data from the serial communication circuit 511 has been completed. It shows that. When the command storage area is in the ring buffer format, if “1” is stored in bit 6, the command read pointer is updated.

  Note that the transmission of the transmission data is completed, and the game control microcomputer 560 waits for a reception confirmation signal from the transmission destination microcomputer. In this embodiment, when a transmission interrupt is set, which will be described later, the serial communication circuit 511 sets the bit 6 of the status register A 705 to “1” and confirms reception when detecting the completion of transmission of transmission data. An interrupt request (referred to as an interrupt request during transmission) is made to the CPU 56 as a signal waiting state.

  Bit 5 (bit name “RDRF”) of status register A 705 stores a reception data full flag indicating that reception data is stored in reception data register 711 (reception data full). As shown in FIG. 33B, when “0” is stored in bit 5, it indicates that the reception data register 711 contains no reception data. When “1” is stored in bit 5, the value of the reception shift register 713 is transferred to the reception data register 711, and reception data is stored in the reception data register 711 (reception data Full). Whether or not the command from the payout control microcomputer 370 has been received is confirmed by whether or not “1” is stored in bit 5. For example, in steps S5221, S52401, and S52501, it is determined that the command is received on condition that “0” is not stored in bit 5. In this embodiment, bit 5 (RDRF) of status register A 705 is cleared when reception data is read from reception data register 711 by game control microcomputer 560. If the bit 5 (RDRF) of the status register A 705 is not automatically cleared when the received data is read, the game control microcomputer 560 reads the received data from the received data register 711. Every time reception data is read, it is necessary to perform processing for clearing bit 5 (RDRF) of the status register A705.

  When the reception data is stored in the reception data register 711, the CPU 56 is ready to perform reception processing by reading the reception data from the reception data register 711. In this embodiment, when the reception interrupt is set, the serial communication circuit 511 sets the bit 5 of the status register A 705 to “1” when reception data full is detected and enables reception processing. As an example, an interrupt request is made to the CPU 56 (referred to as an interrupt request upon reception).

  Bit 4 (bit name “IDLE”) of status register A705 stores an idle line detection flag indicating that the receiving circuit has detected an idle line. As shown in FIG. 33B, when “0” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 511 has not detected an idle line. When “1” is stored in bit 4, it indicates that the receiving unit of the serial communication circuit 511 has detected an idle line.

  In bit 3 (bit name “OR”) of the status register A 705, the reception shift register 713 has received the next data before the CPU 56 reads the reception data stored in the reception data register 711 (overload). An overrun flag indicating (run) is stored. As shown in FIG. 33B, when “0” is stored in bit 3, it indicates that the receiving circuit has not detected an overrun. If “1” is stored in bit 3, it indicates that the receiving circuit has detected an overrun.

  If an overrun occurs, the next received data is stored in the receiving shift register 713 before the received data in the received data register 711 is read, so that the received data is overwritten and the CPU 56 receives the received data. It cannot be read correctly. For this reason, communication with the microcomputer mounted on each control board cannot be performed correctly, causing the CPU 56 to malfunction. In this embodiment, when detecting an overrun, the serial communication circuit 511 sets bit 3 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 2 (bit name “NF”) of status register A 705 stores a noise error flag indicating that noise has been detected in the received data. As shown in FIG. 33B, when “0” is stored in bit 2, it indicates that the receiving circuit is not detecting noise in the received data. Further, when “1” is stored in bit 2, it indicates that the receiving circuit has detected noise in the received data.

  For example, when detecting each bit of the received data, the serial communication circuit 511 detects “1” or “0” having a predetermined bit length using the baud rate generated by the baud rate generation circuit 703. In this case, when the detected length of “1” or “0” is less than the predetermined bit length, the serial communication circuit 511 detects a noise error as noise has occurred in the received data. When a noise error occurs, there is a high possibility that correct received data cannot be received due to the noise, which causes the CPU 56 to malfunction. In this embodiment, when detecting a noise error, the serial communication circuit 511 sets bit 2 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 1 (bit name “FE”) of the status register A 705 indicates that it is detected that the position of the stop bit of the received data is “0” (originally, the stop bit is “1”) (framing error). A framing error flag is stored. As shown in FIG. 33B, when “0” is stored in bit 1, it indicates that the receiving circuit has not detected a framing error in the received data. When “1” is stored in bit 1, it indicates that the receiving circuit has detected a framing error.

  When a framing error occurs, it is in a state where the stop bit of the received data has not been correctly received, and therefore there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when detecting a framing error, the serial communication circuit 511 sets bit 1 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 as an error has occurred during communication.

  Bit 0 (bit name “PF”) of the status register A 705 has a parity error flag indicating that the parity value obtained from the received data does not match the parity value included in the received data (parity error). Is stored. As shown in FIG. 33B, when “0” is stored in bit 0, it indicates that the receiving circuit has not detected a parity error in the received data. Further, when “1” is stored in bit 0, it indicates that the receiving circuit has detected a parity error.

  When a parity error occurs, it is in a state where each data bit or parity bit of the received data has not been correctly received, so there is a high possibility that correct received data cannot be received, causing the CPU 56 to malfunction. In this embodiment, when the serial communication circuit 511 detects a parity error, the serial communication circuit 511 sets bit 0 of the status register A 705 to “1” and issues an interrupt request to the CPU 56 on the assumption that an error has occurred during communication.

  FIG. 34A is an explanatory diagram showing an example of the status register B706. The status register B 706 is a register for confirming the reception state (reception status) of the serial communication circuit 511. In this embodiment, the CPU 56 can confirm the reception status of the serial communication circuit 511 by confirming the value of the bit of the status register B 706. As shown in FIG. 34B, the status register B 706 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Further, the status register B 706 is configured so that bit 0 can only be read. Therefore, even if control is performed to write a value to bit 0 of status register A 705, it is invalid. Status register B 706 is configured such that bits 1 to 7 cannot be written or read. Therefore, even if control is performed to write a value to bits 1 to 7 of the status register A 705, the value is invalid and all the values read from bits 1 to 7 are “0 (= 0000b)”.

  FIG. 34B is a diagram showing an example of status confirmation data stored in the status register B706. As shown in FIG. 34B, a reception active flag indicating that the reception circuit is receiving reception data (reception active) is stored in bit 0 (bit name “RAF”) of the status register B706. . As shown in FIG. 34B, when “0” is stored in bit 0, it indicates that the reception circuit is not receiving reception data. Further, when “1” is stored in bit 0, it indicates that the reception circuit is receiving reception data. Even when “1” is stored in bit 0, command data is not written or command data cannot be written. When the serial communication circuit 511 detects the start bit, it sets the bit 0 of the status register B 706 to “1” on the assumption that reception of received data has started.

  FIG. 35A is an explanatory diagram illustrating an example of the control register C709. The control register C709 is a register that sets whether to permit an interrupt request when a communication error occurs in the serial communication circuit 511. In this embodiment, by setting the value of each bit of the control register C709, it is set whether the interrupt request at the time of communication from the serial communication circuit 511 is permitted or prohibited. In the control register C709, error interrupt request setting data indicating whether or not various interrupt requests at the time of a communication error are permitted is mainly set. In addition to the error interrupt request setting data, the control register C709 stores 9th bit data when the data length is set to 9 bits. Various settings of the serial communication circuit 511 are also set. As shown in FIG. 35A, the control register C709 is an 8-bit register, and the initial value is set to “0 (= 00h)”. Control register C709 is configured such that bits 0 to 3 and bits 6 and 7 can be written and read. Further, the control register C709 is configured such that bits 4 and 5 cannot be written or read. Therefore, even if a control for writing a value to bits 4 and 5 of the control register C709 is performed, it is invalid, and all the values read from the bits 4 and 5 are “0 (= 0000b)”.

  FIG. 35B is an explanatory diagram showing an example of error interrupt request setting data set in the control register C709. As shown in FIG. 35 (B), the bit 7 (bit name “R8”) of the control register C709 stores the 9th bit data of the received data when the data length is set to 9 bits. Further, bit 6 (bit name “T8”) of the control register C709 stores the 9th bit data of the transmission data when the data length is set to 9 bits.

  In bit 3 (bit name “ORIE”) of the control register C709, setting data indicating whether or not to permit an overrun flag interrupt request, which is an interrupt request to be performed when an overrun is detected, is set. As shown in FIG. 35B, by setting bit 3 to “0”, the overrun flag interrupt request is set to be prohibited. Further, by setting bit 3 to “1”, the overrun flag interrupt request is set to be permitted.

  Bit 2 (bit name “NEIE”) of the control register C709 is set with setting data indicating whether or not to permit a noise error flag interrupt request, which is an interrupt request to be performed when a noise error is detected. As shown in FIG. 35B, by setting bit 2 to “0”, the noise error flag interrupt request is set to be prohibited. Also, by setting bit 2 to “1”, the noise error flag interrupt request is set to be permitted.

  Bit 1 (bit name “FEIE”) of the control register C709 is set with setting data indicating whether or not to permit a framing error flag interrupt request, which is an interrupt request to be performed when a framing error is detected. As shown in FIG. 35B, by setting bit 1 to “0”, the framing error flag interrupt request is set to be prohibited. Further, by setting bit 1 to “1”, the framing error flag interrupt request is set to be permitted.

  Bit 0 (bit name “PEIE”) of the control register C709 is set with setting data indicating whether or not to permit a parity error flag interrupt request which is an interrupt request to be performed when a parity error is detected. As shown in FIG. 35B, by setting bit 0 to “0”, the parity error flag interrupt request is set to be prohibited. Further, by setting bit 0 to “1”, the parity error flag interrupt request is set to be permitted.

  FIG. 36 is an explanatory diagram illustrating an example of a data register included in the serial communication circuit 511. The data register 701 is a register that stores data transmitted and received by the serial communication circuit 511. As shown in FIG. 36, the data register is an 8-bit register, and the initial value is set to “0 (= 00h)”. Data register 701 is configured such that bits 0 to 7 can be written and read.

  In this embodiment, when the serial communication circuit 511 transmits transmission data, the data register is used as the transmission data register 710. When the data length is set to 9 bits, bit 6 of the data register and control register C709 is used as the transmission data register 710. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the transmission data register 710, and bit 6 of the control register C709 is used as bit 8 of the transmission data register 710.

  When the serial communication circuit 511 receives received data, the data register is used as the received data register 711. When the data length is set to 9 bits, bit 7 of the data register and control register C709 is used as the reception data register 711. In this case, bits 0 to 7 of the data register are used as bits 0 to 7 of the reception data register 711, and bit 7 of the control register C709 is used as bit 8 of the reception data register 711.

  The interrupt control circuit 714 makes various interrupt requests to the CPU 56. In this embodiment, when the bit 6 (TCIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 notifies the CPU 56 when transmission of transmission data to the transmission data register 710 is completed. In addition to outputting an interrupt signal, an interrupt request is made by setting bit 6 (TC) of status register A705 to “1”. The interrupt control circuit 714 may output a different interrupt signal to the CPU 56 for each interrupt factor, instead of making the interrupt factor identifiable by the set value of the bit of the status register A705.

  In addition, when bit 5 (RIE) of the control register B 708 is set to “1”, the interrupt control circuit 714 enters a state where reception data is stored in the reception data register 711 (when reception data full is detected). ), An interrupt signal is output to the CPU 56, and an interrupt request is made by setting bit 5 (RDRF) of the status register A705 to “1”.

  Further, when any of the bits 0 to 3 of the control register C709 is set to “1”, the interrupt control circuit 714 outputs an interrupt signal to the CPU 56 and also indicates the type of communication error. In response to this, an interrupt request is made by setting "1" to bits 0 to 3 of the status register A705. For example, if bit 3 (ORIE) of the control register C709 is set to “1”, “1” is set to bit 3 (OR) of the status register A705 when an overrun is detected and an interrupt request is made. To do. For example, when bit 2 (NEIE) of the control register C709 is set to “1”, when a noise error is detected and an interrupt request is made, “1” is set to bit 2 (NF) of the status register A705. Set. For example, when bit 1 (FEIE) of the control register C709 is set to “1”, when a framing error is detected and an interrupt request is made, “1” is set to bit 1 (FE) of the status register A705. Set. For example, when bit 0 (PEIE) of the control register C709 is set to “1”, when a parity error is detected and an interrupt request is made, “1” is set to bit 0 (PF) of the status register A705. Set. When a plurality of communication errors are detected, the interrupt control circuit 714 makes an interrupt request based on the plurality of communication errors and sets the corresponding bits of the status register A 705 to “1”.

  The transmission format / parity generation circuit 715 generates a data format of transmission data. In this embodiment, the transmission format / parity generation circuit 715 generates a data format by adding a start bit and a stop bit to the transmission data stored in the transmission data register 710 and transfers the data format to the transmission shift register 712. If bit 1 (PE) of control register A707 is set to “1” and the parity function is set to be used, the transmission format / parity generation circuit 715 adds a parity bit to the transmission data. Generate a data format.

  The reception format / parity check circuit 716 detects the data format of the reception data. In this embodiment, the reception format / parity check circuit 716 detects the start bit and the stop bit from the reception data stored in the reception shift register 713, detects the data portion included in the reception data, and receives the reception data register. Forward to 711. When bit 1 (PE) of the control register A707 is set to “1” and the parity function is set to be used, the reception format / parity check circuit 716 obtains the parity of the reception data and receives the reception data. It is detected whether or not it matches the parity included in. If the obtained value does not match the parity included in the received data, the reception format / parity check circuit 716 detects a parity error. If it is set in the serial communication circuit setting process to be described later that an interrupt request at the time of communication error is permitted, the interrupt control circuit 714 interrupts the CPU 56 with the occurrence of the communication error as a cause of interruption when detecting a parity error. Make a request.

  The jackpot determination table memory 571 stores a plurality of jackpot determination tables used by the CPU 56 to determine whether or not the display result of the special symbol display 8 is a jackpot symbol. Specifically, as shown in FIG. 37A, the big hit determination table memory 571 stores a normal time big hit determination table 571a used in a gaming state (referred to as a normal state) other than the probability variation state. Also, the jackpot determination table memory 571 stores a probability change jackpot determination table 571b used in the probability change state, as shown in FIG. Note that, when the big hit determination is performed using the determination table shown in FIG. 37, the probability of determining a big hit depends on the random number maximum value set in the random number maximum value setting register 535. In this case, for example, if the set random number maximum value is too small, the difference in the probability of determining a big hit between the case where the normal big hit determination table 571a is used and the case where the probability variation big hit determination table 571b is used is small. As a result, the player's interest in the game is diminished. Therefore, a plurality of determination tables (a plurality of normal big hit determination tables 571a and a plurality of probability variation big hit determination tables 571b) are stored in the big hit determination table memory 571 in association with the random number circuit 509 and the random number maximum value. Also good. Then, the CPU 56 uses the random number circuit 509 to be used and the determination tables 571a and 571b corresponding to the maximum random number among the determination tables stored in the jackpot determination table memory 571, and displays a special symbol according to the display result determination program 552. It may be determined whether or not the display result of the device 8 is a jackpot symbol. By doing so, even if the type of random number circuit 509 to be used and the maximum random number are different, it is possible to control so that the probability of determining a big hit is somewhat the same.

  In the example shown in FIG. 37, for example, in the case of the normal big hit determination table shown in FIG. 37A, determination values are assigned to four ranges of 1020 to 1059, 13360 to 13399, 34400 to 34439, and 57700 to 577739. In the case of the probability change jackpot determination table shown in FIG. 37 (B), the determination values are assigned to four ranges of 1020 to 1219, 13360 to 13559, 34400 to 34599, and 57700 to 57899. In each jackpot determination table, a determination value may be assigned to a series of one range.

  FIG. 38 is an explanatory diagram showing an example of output port assignment in the game control means. As shown in FIG. 38, the output port 0 outputs a payout control signal (in this example, a connection signal) transmitted to the payout control board 37. Further, a solenoid (large winning port door solenoid) 21 for opening and closing a variable winning ball device 20 for opening and closing the big winning port, and a solenoid (ordinary electric accessory solenoid) 16 for opening and closing the variable winning ball device 15 are driven. The signal is also output from output port 0.

  Note that the logic (for example, 0 is on) opposite to the “logic” (for example, 1 is on) shown in FIG. 38 may be used. In particular, for the connection signal, the main board 31 and the payout control board. The “logic” is determined so that the payout control microcomputer 370 always detects the off state when the signal line to the terminal 37 is disconnected or when the cable is disconnected (including no cable connection). . Specifically, generally, when disconnection or cable disconnection occurs, a high level is detected on the signal receiving side, so the high level on the signal line between the main board 31 and the payout control board 37 is the game control means. The “logic” is determined to be in the off state at the output port at. Therefore, if necessary, an output buffer circuit for logically inverting the signal is provided outside the output port on the main board 31.

  Then, from the output port 1 to the external device (for example, hall computer) via the terminal board 160, a seed information output signal, that is, information related to the control (for example, start port signal, symbol determination number 1 signal, jackpot 1 signal, 2 jackpots, 3 jackpots, short time signal, security signal) are output. In this embodiment, a prize ball signal 1 (a signal that is output every time one prize ball payout is detected) or a gaming machine error status signal (a gaming machine is in an error status (in this example, a ball is out of ball). An error state or a full tank error state) is also output to the external device via the terminal board 160. In this case, on the payout control board 37 side, a prize ball payout or an error state of the gaming machine is detected, and a prize ball signal 1 or a gaming machine error state signal is input to the main board 31. The prize ball signal 1 and the gaming machine error status signal input to the main board 31 are output via the terminal board 160 via the main board 31 as they are without passing through the game control microcomputer 560. Is done. The prize ball signal 1 and the gaming machine error state signal input to the main board 31 may be output to the outside via the terminal board 160 after temporarily passing through the gaming control microcomputer 560.

  Note that signals output to the outside via the terminal board 160 are not limited to those shown in this embodiment. For example, a door opening signal indicating that the glass door frame 2 is in an open state, a mechanism plate opening signal indicating that the mechanism plate is in an open state, and a prize ball that is output every time ten award balls are detected. Information may also be output to an external device via the terminal board 160. In this case, it is detected on the payout control board 37 side that the glass door frame 2 is in the open state, the mechanism plate is in the open state, and the payout of the prize ball is detected. Information is input to the main board 31. Then, the door opening signal, mechanism plate opening signal, and prize ball information input to the main board 31 do not pass through the game control microcomputer 560 but pass through the main board 31 as they are through the terminal board 160. Output externally. However, it is assumed that the door opening signal, the mechanism plate opening signal, and the prize ball information are branched on the main board 31 and input to the game control microcomputer 560. Also in this case, the door opening signal, the mechanism plate opening signal, and the prize ball information input to the main board 31 are output to the outside via the terminal board 160 after passing through the game control microcomputer 560 once. You may do it.

  In addition, for example, the gaming machine has two start winning ports, a first start winning port and a second starting winning port, and is configured to be capable of variably displaying two special symbols, a first special symbol and a second special symbol. In this case, the symbol determination frequency signal 2 may be externally output via the terminal board 160 in addition to the symbol determination frequency signal 1 as a symbol determination frequency signal for notifying the number of times of variation of the special symbol. . In this case, for example, in order to notify the number of fluctuations of both the first special symbol and the second special symbol by externally outputting the symbol determination number 2 signal as a signal for notifying only the number of fluctuations of the first special symbol. The signal may be configured to be externally output as a signal of the number of symbol determinations. With such a configuration, on the external device side such as a hall computer, in addition to the number of fluctuations of only the first special symbol, the number of fluctuations of the first special symbol and the second special symbol, or the fluctuation of only the second special symbol The number of times can also be grasped.

  FIG. 39 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 39, the count switch 23, the gate switch 32a, the winning opening switches 29a and 30a, the magnet sensor signal 1, the magnet sensor signal 2, and the prize ball information are input to the bits 0 to 7 of the input port 0, respectively. Is done. In this embodiment, two magnet sensors (not shown) for detecting fraud using a magnet are provided, and detection signals from the respective magnet sensors are also input from the input port 0. . Further, the detection signal of the start port switch 14a is input to bit 0 of the input port 1. In addition, the power-off signal and the clear switch detection signal from the power supply board 910 are input to the bits 3 and 4 of the input port 1, respectively. Further, the mechanism plate opening signal and the door opening signal are input to the bits 6 and 7 of the input port 1 via the payout control board 37, respectively.

  Next, the operation of the gaming machine will be described. When power is supplied to the gaming machine and power supply is started, the input level of the reset terminal to which the reset signal is input becomes high level, and the gaming control microcomputer 560 (specifically, the CPU 56) Based on the security check program 54A read from the ROM 54, a security check process, which is a process for confirming whether the contents of the program are valid, is executed. At this time, the game control microcomputer 560 is in the security mode, and the game control user program stored in the ROM 54 is not yet executed.

  FIG. 40 is a flowchart showing a security check process executed by the game control microcomputer 560 on the main board 31. When the security check process is started, the CPU 56 first executes a process for determining a time (security time) when the game control microcomputer 560 is in the security mode by executing the security check process. At this time, the CPU 56 reads the bit value in the bit number [2-0] of the security time setting KSES stored in the program management area of the ROM 54 (step S1001). Then, it is determined whether or not the read value is “000” (step S1002).

  If it is determined in step S1002 that the read value is “000” (Y in step S1002), the steady set time is set to a predetermined fixed time (step S1003). Here, the regular setting time is constant regardless of the number of times security check processing is executed based on the occurrence of a system reset or the like in the pachinko gaming machine 1 (the number of times that the game control microcomputer 560 is in the security mode). Is a time component. The fixed time is an invariant time component determined in advance based on the specifications of the game control microcomputer 560 in the security time, and may be any minimum value that can be set as the security time, for example.

  If it is determined in step S1002 that the read value is other than “000” (N in step S1002), the read value is selected according to the set content shown in FIG. 14D in addition to the fixed time. The extended time is set to the steady set time (step S1004). Thus, when the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, the security time that is the execution time of the security check process can be selected in advance in addition to the fixed time. It can be set to any one of a plurality of extension times.

  After executing any of the processes in steps S1003 and S1004, the bit value in the bit number [4-3] of the security time setting KSES is read (step S1005). Then, it is determined whether or not the read value is “00” (step S1006).

  If it is determined in step S1006 that the read value is “00” (Y in step S1006), the steady setting time is set as the security time (step S1007). On the other hand, if it is determined that the read value is other than “00” (N in step S1006), the variable setting time determined in accordance with the read value is added to the steady setting time to obtain the security time. (Step S1008). Here, the variable setting time is a time component that changes every time the security check process is executed, and the bit value in the bit number [4-3] of the security time setting KSES is “01” (short). Mode) or “10” (long mode), and changes in different predetermined time ranges. For example, when the count value in a predetermined free-run counter is stored in the variable security time register built in the game control microcomputer 560 at the occurrence of a system reset, in the process of step S1008, for the variable security time By using the stored value of the register as it is, or by using the value obtained by substituting the stored value for a predetermined arithmetic function (for example, a hash function), the variable setting time is within a predetermined time range for each system reset. It may be determined so as to change randomly. Thus, when the bit value in the bit number [4-3] of the security time setting KSES is a value other than “00”, the security time that is the execution time of the security check process is set as the security based on the occurrence of a system reset or the like. Each time the check process is executed, it can be changed within a predetermined time range.

  Here, the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000”, and the bit value in the bit number [4-3] of the security time setting KSES is other than “00”. In this case, both the extension time set in step S1004 and the variable setting time set in step S1008 are added to the fixed time to determine the security time. .

  After executing one of the processes in steps S1007 and S1008, the security code stored in the predetermined area of the ROM 54 is read (step S1009). Here, in a predetermined area of the ROM 54, a security code as a calculation result obtained by calculating the data of the stored content by a predetermined arithmetic expression is stored in advance. As a method for generating a security code, for example, a hash value is generated using a hash function, an error detection code (CRC code) is used, or an error correction code (ECC code) is used. A generation method may be used. In a predetermined area different from the security code storage area of the ROM 54, an arithmetic expression for specifying the security code by calculation is encrypted and stored in advance.

  Following the processing in step S1009, the encrypted arithmetic expression is decrypted and restored (step S1010). Thereafter, the storage code in the predetermined area of the ROM 54 is calculated by the arithmetic expression decrypted in step S1010 to specify the security code (step S1011). At this time, the storage data used for the calculation for specifying the security code is, for example, program data corresponding to all or part of the user program different from the security check program 54A in the storage data of the ROM 54, or predetermined table data May be all or a part of the fixed data constituting the. Then, the security code read in step S1009 is compared with the security code specified in step S1011 (step S1012). At this time, it is determined whether or not the security codes match in the comparison result (step S1013).

  If the security codes do not match in step S1013 (N in step S1013), it is determined that an unauthorized change has been made to the ROM 54, and the operation of the CPU 56 is shifted to a halt state (HALT). On the other hand, if the security codes match in step S1013 (Y in step S1013), it is determined whether the security time set in the processing in step S1007 or step S1008 has elapsed (step S1014). . If the security time has not elapsed (N in step S1014), the processing in step S1014 is repeatedly executed, and the process waits until the security time elapses. On the other hand, if it is determined in step S1014 that the security time has elapsed (Y in step S1014), for example, the value of the program counter built in the CPU 56 is set to the start address (address 0000H) of the user program in the ROM 54. The execution of the game control main process is started by setting or the like. At this time, the execution of the game control is started from the head of the control code constituting the user program stored in the ROM 54, so that the operation state of the game control microcomputer 560 shifts from the security mode to the user mode. Execution of the control main process is started.

  41 and 42 show main processing executed by the CPU 56 of the game control microcomputer 560 in response to the start of power supply to the game machine and the reset signal to the game control microcomputer 560 becoming high level. It is a flowchart which shows. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 of the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid. The main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode indicating the interrupt address. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the CPU 56 starts outputting a connection signal to the payout control microcomputer 370 (step S4). When the CPU 56 starts outputting the connection signal in step S4, the CPU 56 sends a connection signal to the payout control microcomputer 370 unless the power supply of the gaming machine is stopped or output is impossible due to some communication error. Output continuously.

  Next, the built-in device register is set (initialized) (step S5). By the processing in step S5, the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized).

  The game control microcomputer 560 used in this embodiment also incorporates an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, the CPU 56 sets the RAM 55 in an accessible state (step S6), and proceeds to a clear signal check process.

  Note that a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software may be executed. By such software delay processing, the start timing of the game control processing can be delayed as compared with the case where the software delay processing is not executed. When the delay process is executed, a situation occurs in which the microcomputer of the other control board cannot receive the command transmitted from the game control board (main board 31) to the other control board (for example, the payout control board 37). Can be prevented.

  Next, the CPU 56 checks whether or not the clear switch is turned on (step S7). Note that the CPU 56 may confirm the state of the clear signal only once via the input port 0, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed that the state of the clear signal is an off state, after a delay time of a predetermined time (for example, 0.1 seconds), the state of the clear signal is reconfirmed. If it is confirmed that the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. Further, at this time, if it is confirmed that the state of the clear signal is the off state, after a delay time of a predetermined time, the state of the clear signal may be confirmed again. Here, the number of reconfirmations is not limited to once or twice, but may be three or more times. It is also possible to check twice and check again when the check results do not match.

  If the clear switch is on and an operation signal is input from the clear switch in step S7, the CPU 56 checks whether or not the mechanism plate opening signal from the mechanism plate opening sensor 155B is on ( Step S7a). If the mechanism plate open signal is in the on state (that is, if the mechanism plate is in the open state), the process proceeds to an initialization process after step S10. If the mechanism plate open signal is not in the on state (that is, if the mechanism plate is in the closed state), the CPU 56 designates initialization for notifying the possibility that the initialization process is improperly performed. Control to transmit the fraud notification command to the production control microcomputer 100 is performed (step S7b), and the process proceeds to loop processing.

  Generally, when turning on the power to the gaming machine when the game shop is opened, the clear switch 921 is mounted on the power supply board 910 inside the gaming machine. Therefore, the game clerk or the like must open the mechanism board. The game machine cannot be turned on while the clear switch 921 is pressed, and the game machine cannot be activated in the initialized state. Therefore, when starting the gaming machine according to a regular procedure, if the clear switch 921 is in an on state at the start of power supply to the gaming machine, the mechanism plate opening signal should be in an on state at the same time. The fact that the ON state of the mechanism plate opening signal is not detected in step S7a even though the ON state of the clear switch is detected in step S7 means that the clear switch 921 is pressed while the mechanism plate remains closed. This means that the power was turned on. For this reason, there is a high possibility that an action of resetting the power supply in a state where the clear switch 921 is turned on illegally by inserting an instrument from the gap of the gaming machine during the game is performed. Therefore, in this embodiment, if the ON state of the mechanism plate opening signal is not detected in step S7a even though the ON state of the clear switch is detected in step S7, the initialization process is illegally performed. It is determined that there is a high possibility that it is going to be performed, and an initialization fraud notification command is transmitted to perform notification, and control is performed so as to shift to the loop processing and not shift to the game control processing of FIG. That is, the progress of the game is disabled so that the game cannot be performed. By controlling in such a manner, in this embodiment, it is possible to prevent the initialization process from being executed illegally and to prevent illegal acts.

  In addition, when the progress of the game is disabled due to the transition to the loop process, in order to cancel the disabled state, the clear switch is set after the mechanism plate is opened according to a normal procedure. The power to the gaming machine must be turned on again while pressing 921. Even if the power is not turned on again, for example, in the loop processing after the initialization fraud notification command transmission processing in step S7b, the clear switch is on and the mechanism plate open signal is turned on. If it is in an on state, the game control process may be started by proceeding to an initialization process after step S10.

  If the clear switch is not turned on in step S7, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of power supply stop is stored. . When it is confirmed that the power supply stop process is not performed, the CPU 56 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ) Is confirmed by whether or not. Note that such a confirmation method is an example. For example, a flag indicating that the power supply stop process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check (parity check in this example) in the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S14) executed when the power is turned on, not when the power supply is stopped is stopped. Run.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and proceeds to step S14a. In addition, after setting in step S93, a backup command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Also, the initial address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  By the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a special symbol process flag, a winning ball flag, a ball-out flag, and the like are selectively processed according to the control state. An initial value is set in a flag for performing the above.

  Further, the CPU 56 sets the start address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the effect display device 9, an initialization command to the payout control board 37, or the like can be used. After setting in step S13, an initialization command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  After the processing of steps S91 to S93 is executed to restore the gaming state before the power interruption, or after the initialization processing of steps S10 to S14, the game control is performed based on the stored data in the program management area of the ROM 54. Operation settings of various circuits built in the microcomputer 560 are performed (step S14a). As an example, in the process of step S14a, the first random number initial setting KRS1 and the second random number initial setting KRS2 stored in the program management area are read and the random number circuit setting process is executed.

  FIG. 43 is a flowchart illustrating an example of random number circuit setting processing. In the random number circuit setting process, the CPU 56 first performs setting for using the random number circuit 509 based on the bit value in the bit number [3] of the first random number initial setting KRS1 (step S5001). In this embodiment, the bit value in the bit number [3] of the first random number initial setting KRS1 is set to “1” in advance, and setting to use the random number circuit 509 is performed corresponding to this bit value. Subsequently, the random number update clock RGK is set in the random number circuit 509 based on the bit value in the bit number [2] of the first random number initial setting KRS1 (step S5002). For example, in response to the bit value [2] of the first random number initial setting KRS1 being set to “1” in advance, the random number clock RCLK generated by the random number clock generation circuit 112 is divided by two. As a result, the random number update clock RGK is set.

  After the setting in step S5002, the random number update rule is set in the random number circuit 509 based on the bit value in the bit number [1-0] of the first random number initial setting KRS1 (step S5003). For example, when the bit value in the bit number [1-0] of the first random number initial setting KRS1 is set to “00” in advance, the random number update designating the update order of the numerical data that becomes the random value in the random number sequence RSN The rule is set so as not to change after the second round. Further, when the bit value [1-0] of the first random number initial setting KRS1 is set to “01” in advance, the random number update rule in the random number sequence RSN is set to be changed by software after the second round. Is made. Further, when the bit value in the bit number [1-0] of the first random number initial setting KRS1 is set to “10” in advance, the random number update rule in the random number sequence RSN is automatically changed after the second round. Is made.

  Subsequently, based on the bit value in the bit number [1] of the second random number initial setting KRS2, a start value at start-up in numerical data to be a random value is determined (step S5004S). For example, when the bit value [1] of the second random number initial setting KRS2 is set to “0” in advance, the random value start value is set to the default value “0000H”. When the bit value [1] of the second random number initial setting KRS2 is set to “1” in advance, the random number start value is set to a value based on the ID number.

  Further, based on the bit value in the bit number [0] of the second random number initial setting KRS2, it is set whether or not to change the start value of the numerical data serving as the random value every time the system is reset (step S5005). For example, when the bit value in the bit number [0] of the second random number initial setting KRS2 is set to “0” in advance, the pachinko gaming machine 1 is activated when the power is initially turned on (activation after backup is disabled). The start value setting circuit 554 may be used as the start value in the random number circuit 509 using the start value at the start set in step S5004 as it is, regardless of whether the system is restarted by a system reset. Further, when the bit value [0] of the second random number initial setting KRS2 is set to “1” in advance, a setting for changing the start value of the random number at every system reset is made. For example, when a count value in a predetermined free run counter such as the free run counter 554A is stored in a random number start value register built in the game control microcomputer 560 at a predetermined timing such as when a system reset occurs. In the process of step S5005, a random number can be obtained by using the stored value of the random number start value register as it is or by using a value obtained by substituting the stored value into a predetermined arithmetic function (for example, a hash function). Is determined so as to randomly change in a predetermined numerical range (for example, a range including all or part of the numerical data included in the count value permutation RCN generated by the random number generation circuit 553) at each system reset. Just do it.

  After the processing of step S5005 is executed, the bit number [1] or bit number [0] of the random number latch flag register RDFM is read by reading the numerical data stored in the random value register R1D or the random value register R2D, for example. The bit values of the random number latch flag data RDFM1 and the random number latch flag data RDFM0 stored in are set to “0”, and each random number latch flag is cleared to an off state (step S5006). As an example, for the random number latch flag data RDFM1 and the random number latch flag data RDFM0, it is determined whether each value is “1” or “0”, and if the value is “1”, the corresponding random value The random number latch flag may be turned off by reading the register. Alternatively, each random number latch flag may be turned off by reading the random number value register R1D and the random number value register R2D regardless of the values of the random number latch flag data RDFM1 and the random number latch flag data RDFM0. Note that the numerical data read from the random value register R1D or the random value register R2D in the process of step S5006 is used for determining whether to control the big hit gaming state with the special figure display result as “big hit”. It can be discarded (erased) as it is. When the setting by the processing in step S5006 is completed, the random number circuit 509 may start the random value generation operation.

  Note that part or all of the setting by the random number circuit setting process may be performed autonomously by the random number circuit 509 based on the data stored in the program management area without the processing of the CPU 56 being involved. In this case, the random number circuit 509 may be configured not to perform the initial setting when the game control microcomputer 560 is in the security mode and to prevent the random number value generation operation from being performed. Then, when the CPU 56 reads out the user program stored in the ROM 54 in the game control microcomputer 560 and the execution of the game control main process is started, the CPU 56 instructs the random number circuit 509 to make an initial setting, for example. In response to the signal being transmitted, the random number circuit 509 may perform the initial setting and then start the random value generation operation. Alternatively, particularly when the random number circuit 509 is externally attached to the game control microcomputer 560, the random number circuit 509 is independent of the processing in the CPU 56 even when the game control microcomputer 560 is in the security mode. Thus, the random number generation operation may be started after initial setting based on the stored data in the program management area. Further, the process of step S14a shown in FIG. 41 includes a process of reading the interrupt initial setting KIIS stored in the program management area and setting the priority control of the maskable interrupt factor in the reset / interrupt controller 504. May be. When setting the priority order of the maskable interrupt factor, the highest priority interrupt is set according to the bit value in the bit number [3-0] of the interrupt initial setting KIIS. For example, by setting the bit value [3-0] of the interrupt initial setting KIIS to either “04H” or “05H” in advance, the interrupt processing due to the interrupt factor generated in the serial communication circuit 511 has the highest priority. Can be executed. Thus, by performing priority control of maskable interrupt factors according to the bit value in bit number [3-0] of interrupt initial setting KIIS, the priority order of interrupt processing can be arbitrarily set, and the degree of freedom of design is increased. be able to.

  After the setting in step S14a, random number circuit abnormality inspection processing for inspecting the presence or absence of operation abnormality in the random number circuit 509 is executed (step S14b). FIG. 44 is a flowchart showing an example of the random number circuit abnormality inspection process executed in step S14b.

  In the random number circuit abnormality inspection process shown in FIG. 44, the CPU 56 first clears a random number clock abnormality determination counter provided in, for example, the RAM 55 and sets the random number clock abnormality determination count value, which is the count value, to “0”. (Step S561). Subsequently, the internal information data CIF4 stored in the bit number [4] of the internal information register CIF is read (step S562). Then, it is determined whether or not the read value in step S562 is “1” (step S563). The frequency monitoring circuit 551 provided in the random number circuit 509 compares the input state of the random number clock RCLK at the random number external clock terminal ERC with the internal system clock SCLK. Then, when a frequency abnormality corresponding to the setting content as shown in FIG. 14B is detected in the input state of the random number clock RCLK, the bit value “1” is written as the internal information data CIF4.

  Therefore, when it is determined in step S563 that the read value is “1” (Y in step S563), the random number clock abnormality determination count value is updated to be incremented by 1 (step S564). At this time, it is determined whether or not the count value after the update in step S564 has reached a predetermined clock abnormality determination value (step S565). Here, the clock abnormality determination value may be a numerical value determined in advance to determine that the clock abnormality is detected when the frequency monitoring circuit 551 continuously detects the frequency abnormality of the random number clock RCLK. If the clock abnormality determination value has not been reached in step S565, the process returns to step S562, and determination based on the bit value of the internal information data CIF4 is performed again.

  If the clock abnormality determination value is reached in step S565 (Y in step S565), a predetermined random number clock error process is executed (step S566), and the random number circuit abnormality inspection process is terminated. In the random number clock error process, for example, a setting for transmitting a predetermined effect control command to the effect control board 80 is performed, and notification that the effect device has detected a frequency abnormality of the random number clock RCLK is notified. In addition, the processing may not be continued until a predetermined error canceling procedure (for example, system reset, error canceling switch operation, etc.) is taken, or at the end of random number clock error processing After the random number circuit abnormality inspection process is finished, the game control or the like that is almost the same as the normal time when the random number clock error process is not executed may be executed. Here, when the game control or the like is executed after executing the random number clock error process in step S566, the error occurrence state corresponding to the execution of the random number clock error process is stored, for example, When a customer waiting demonstration designation command is transmitted, a customer waiting demonstration designation command for notifying the occurrence state of the error may be transmitted. Further, the operation of the CPU 56 may be shifted to the halt state (HALT) without executing the random number clock error process.

  If it is determined in step S563 that the read value is “0” (N in step S563), for example, the random value abnormality determination counter provided in the RAM 55 or the like is cleared, and the random value abnormality determination that is the count value is performed. The count value is initialized to “0” (step S567). In the process of step S563, the read value is “0” when the bit value of the internal information data CIF4 read in step S562 continuously becomes “0” a plurality of times (for example, twice). May be determined.

  Following the processing in step S567, a check value used for checking whether there is an abnormality in the random number value is set to an initial value “0000H” (step S568). Then, the stored numeric data as the random value is read from the random value register 559A serving as the random value register R1D and the random value register 559B serving as the random value register R2D included in the random number circuit 509 (step S569). For example, in the process of step S569, the bit values of the random number latch selection data RDLS1 and the random number latch selection data RDLS0 stored in the bit number [1] and the bit number [0] of the random number latch selection register RDLS are set to “0”. Specifies fetching random values by. Subsequently, the bit values of the random number acquisition specification data RDLT1 and the random value acquisition specification data RDLT0 stored in the bit number [1] and the bit number [0] of the random value acquisition specification register RDLT are set to “1”. Specifying loading into the random value register R2D or the random value register R1D. Note that setting the bit value in the bit number [1] or bit number [0] of the random value fetch specification register RDLT to “1” instructs the CPU 56 to fetch (latch) numerical data to the random number circuit 509. This corresponds to outputting a latch signal. After that, by turning on the register read signal RRS2 supplied to the random value register R2D or turning on the register read signal RRS1 supplied to the random value register R1D, the numerical data that becomes the stored random value May be read out. Note that the numerical data stored in each of the random value register R2D and the random value register R1D may be read simultaneously to check whether there is an abnormality in the random number value, or after checking whether there is an abnormality in one of the registers. The other register may be checked for abnormality.

  After the numerical data is read in step S569, the read value is set as a random number inspection reference value (step S570). Subsequently, numerical data that becomes a random value is read from the random value register 559A and the random value register 559B (step S571). Note that the reading operation in step S571 may be performed in the same procedure as the reading operation in step S569. In addition, a sufficient delay time may be provided between the read operation in step S569 and the read operation in step S571 so that the numerical data in the random number sequence RSN generated by the random number circuit 509 changes. After the numerical data is read in step S571, an exclusive OR operation is performed between the random number inspection reference value and the read value in step S571 (step S572). Further, a logical sum operation between the calculation result in step S572 and the check value is executed, and the calculation result is updated so as to be a new check value (step S573). For example, the check value may be stored in a predetermined area of the RAM 55, and each time the process of step S573 is executed, the calculation result obtained by the process may be saved as a new check value. As a result, changes in all the bits in the numerical data read from the random value register 559A and the random value register 559B are recorded, and if the bit has changed at least once during a plurality of times of reading, it corresponds in the check value. The bit value is “1”.

  Therefore, it is determined whether or not the check value is “FFFFH” (step S574), and if it is (Y in step S574), a change in the bit value is recognized for all bits, so that the random number value is normal. The random number circuit abnormality inspection process is terminated by determining that the number has been updated. When it is confirmed that the random number value has been updated normally, the random number latch selection data RDLS1 and the random number latch selection stored in the bit number [1] and the bit number [0] of the random number latch selection register RDLS are selected. The bit value of the data RDLS0 is set to “1”, the random value is taken into the random value register R2D according to the signal input to the input port P1, and the random value register R1D according to the signal input to the input port P0 You may make it instruct | indicate numerical value acquisition. In this embodiment, a wiring for transmitting the start winning signal SS from the start port switch 14a is connected to the input port P0, and a wiring for transmitting the start winning signal SS from the start port switch 14a is also connected to the input port P1. The Thereby, when the start winning signal SS is turned on, the random number value can be taken into the random value register R1D, and when the start winning signal SS is turned on, the random number value register R2D is loaded. Random value acquisition can be performed.

  If it is determined in step S574 that the check value is other than “FFFFH” (N in step S574), the random number abnormality determination count value is updated to be incremented by 1 (step S575). At this time, it is determined whether or not the count value after the update in step S575 has reached a predetermined random value abnormality determination value (step S576). Here, the random value abnormality determination value is determined so that all bits of the numerical data read from the random value register 559A and the random value register 559B change at least once if the random number circuit 509 is operating normally. It may be a predetermined numerical value so as to be the number of times. If the random number abnormality determination value has not been reached in step S576, the process returns to step S571, and numerical data that becomes a random number value is read again from the random number circuit 509, and determination for checking the presence or absence of abnormality is performed.

  If the random value abnormality determination value is reached in step S576 (Y in step S576), a predetermined random value error process is executed (step S577), and the random circuit abnormality inspection process is terminated. In the random value error processing, for example, a setting for transmitting a predetermined effect control command to the effect control board 80 is performed to notify that an abnormality in the random number value is detected by the effect device, Until the error release procedure (for example, system reset, error release switch operation, etc.) is taken, the subsequent processing may not proceed, or the random number circuit error check processing will be performed at the end of the random number error processing. After that, game control or the like that is almost the same as the normal time when the random number error process is not executed may be executed. Here, when the game control or the like is executed after executing the random value error process in step S577, the error occurrence state corresponding to the execution of the random value error process is stored. When transmitting a waiting demonstration designation command, a customer waiting demonstration designation command for notifying the occurrence state of the error may be transmitted. Further, the operation of the CPU 56 may be shifted to the stop state (HALT) without executing the process at the time of the random value error.

  As described above, in the random number circuit abnormality inspection process, for example, the numerical data stored in the random value register R1D (559A) or the random value register R2D (559B) of the random number circuit 509 is obtained by repeatedly executing the process of step S571. Read multiple times. Then, all the bits of the numerical data read out by executing the processing of step S572 to step S574 are monitored, and an abnormality occurs in the operation state of the random number circuit 509 in step S576 based on the presence or absence of bit data that does not change. Determine whether or not. As a result, it is possible to reliably and easily detect that an abnormality has occurred in the operating state of the random number circuit 509 and prevent fraud.

  Note that the random number circuit abnormality inspection process in step S14b is not limited to that executed by the CPU 56, and the random number circuit abnormality inspection process may be executed by a built-in circuit in the game control microcomputer 560 other than the CPU 56. As an example, the random number circuit 509 has a function of executing a random number circuit abnormality inspection process. When a frequency abnormality of the random number clock RCLK is detected, or when an abnormality of a random number value is detected, the CPU 56 detects the occurrence of an error. May be notified. Further, the random number circuit abnormality inspection process is not limited to that executed only in step S14b. For example, every time a timer interrupt occurs in the game control microcomputer 560, a game control timer interrupt process (see FIG. 45), part or all of the random number circuit abnormality inspection process may be executed. That is, the random number circuit abnormality inspection process in step S14b may be executed after the process in step S16 shown in FIG. 41 is executed. As an example, when the random number circuit abnormality inspection process is executed in the game control timer interrupt process, for example, the processes of steps S561 to S566 shown in FIG. 44 are executed, while the processes of steps S567 to S577 are executed. It may not be executed. The processing from step S567 to step S577 may take a long processing time, for example, to repeatedly execute the processing of step S569 to repeatedly read numerical data from the random number circuit 509. May occur. Therefore, in this case, by executing only the processing from step S561 to step S566, the processing amount in the game control timer interrupt processing can be reduced, and the occurrence of processing failure can be prevented.

  Further, the CPU 56 executes a serial communication circuit setting process for initial setting of the serial communication circuit 511 (step S15a). In this case, the CPU 56 sets the data stored in the predetermined area of the ROM 54 in the serial communication circuit 511 in accordance with the serial communication circuit setting program, so that the serial communication circuit 511 performs serial communication with the payout control microcomputer. I do.

  When the serial communication circuit 511 is initialized, the CPU 56 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 511 (step S15b). In this case, the CPU 56 initializes the priority of interrupt processing by executing processing according to the interrupt priority setting program.

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. In this embodiment, the CPU 56 performs initialization according to the interrupt processing priority table so as to preferentially execute an interrupt process that causes an interrupt to occur in the serial communication circuit 511. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 511 occur at the same time, the CPU 56 preferentially performs an interrupt process by the timer interrupt.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition to steps S15a to S15b, a part of the setting process of the serial communication circuit 511 is also executed in the process of step S5. For example, in step S5, processing for setting initial values in the baud rate register, communication setting register, interrupt control register, and status register of the serial communication circuit 511 is executed as the built-in device register.

  For example, in setting the internal device register, the CPU 56 sets the baud rate of the serial communication circuit 511. In this case, the CPU 56 writes a setting value corresponding to the baud rate to be set in the baud rate register 702 of the serial communication circuit 511. For example, the game control microcomputer 560 stores specification information for specifying a set value set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 writes the setting value in the baud rate register 702 according to the designation information stored in a predetermined storage area of the ROM 54. For example, when the baud rate set value “156” is set by the CPU 56, the baud rate “1201.92 bps” is generated by the baud rate generation circuit 703 using the equation (1) and the clock frequency “3 MHz”.

  For example, the CPU 56 sets the data format of data transmitted and received by the serial communication circuit 511. In this case, the CPU 56 sets the data length (8 bits or 9 bits) of the transmission / reception data and the use / nonuse of the parity function by setting the value of each bit of the control register A707. For example, the game control microcomputer 560 stores specification information for specifying the value of each bit of the control register A707 set by the user (for example, the manufacturer of the game machine) in a predetermined storage area of the ROM 54 in advance. Yes. Then, the CPU 56 sets the value of each bit of the control register A707 according to the designation information stored in a predetermined storage area of the ROM 54.

  Further, for example, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 511. In this case, the CPU 56 sets the value of bits 5, 6, and 7 of the control register B708 to thereby send an interrupt request at the time of transmission (a transmission interrupt request that is an interrupt request when transmitting data, or a transmission completion interrupt that is performed when transmission is completed). Request) and whether or not to accept interrupt request at reception. The CPU 56 can also be set to allow both a transmission interrupt request and a reception interrupt request, and allows only one of a transmission interrupt request and a reception interrupt request. It is also possible to set. Further, the CPU 56 sets whether or not to permit an interrupt request at the time of each communication error by setting the values of the bits 0 to 3 of the control register C709. For example, the game control microcomputer 560 stores in advance a designation information for designating values of each bit of the control register B 708 and the control register C 709 set by a user (for example, a manufacturer of the gaming machine) in a predetermined storage area of the ROM 54. I remember it. Then, the CPU 56 sets the value of each bit of the control register B 708 and the control register C 709 according to the designation information stored in a predetermined storage area of the ROM 54.

  In the initialization process of the main process, a process of setting “250” as an initial value to a prize ball number counter used for detecting a prize ball shortage error or a prize ball excess error, which will be described later, is also executed. The process for setting the initial value in the prize ball number counter may be executed, for example, in the process for sequentially setting each initial value in the work area in steps S92 and S12 until the process proceeds to steps S17 to S19. It only has to be executed during

  Then, the CPU 56 executes a timer interrupt setting process for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 4 ms) ( Step S16). That is, a value corresponding to, for example, 4 ms is set as an initial value in a predetermined register (time constant register). In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the timer interrupt setting is completed, the CPU 56 first disables the interrupt (step S17), executes the initial value random number update process (step S18a) and the display random number update process (step S18b), The interrupt is permitted again (step S19). That is, the CPU 56 sets the interrupt disabled state when the initial value random number update process and the display random number update process are executed, and interrupts enable state when the initial value random number update process and the display random number update process are finished. To.

  The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining the type of jackpot (for example, a jackpot symbol determining random number for determining a special symbol for generating a jackpot or whether to shift the gaming state to a probable state) Initial value of the count value such as a counter (determination random number generation counter) for generating a probability variation determining random number for generating, a normal random number for determining whether or not to generate a hit based on a normal symbol It is a random number for determining the value. A game control process described later (a process in which a game control microcomputer controls itself a game device such as an effect display device 9, a variable winning ball device 15, a ball payout device 97 provided in the gaming machine, or When the count value of the determination random number generation counter makes one round in a process of transmitting a command signal to cause another microcomputer to control, or a gaming apparatus control process), an initial value is set in the counter.

  The display random number is a random number for determining the display of the special symbol display 8. In this embodiment, as a display random number, a random number for determining a variation pattern for determining a variation pattern of a special symbol, or a random number for determining a reach for determining whether or not to reach when a big hit is not generated, is used. Used. The display random number update process is a process for updating the count value of the counter for generating the display random number.

  In addition, when the display random number update process is executed, the interrupt disabled state is executed by the display random number update process and the initial value random number update process also in the timer interrupt process described later (that is, the timer This is because the same process is executed in steps S26 and S27 of the interrupt process), so as to avoid conflict with the process in the timer interrupt process. That is, if a timer interrupt is generated during the processing of steps S18a and S18b and the count value of the counter for generating the initial value random number and the display random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt is prohibited during the processing of steps S18a and S18b.

  When the interrupt enabled state is set in step S19, the timer interrupt or the interrupt request from the serial communication circuit 511 is permitted until the processing in step S17 is executed and the interrupt disabled state is set next time. . When a timer interrupt occurs while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process to be described later. When an interrupt request is generated from the serial communication circuit 511 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process and reception Execute time interruption processing and transmission completion interruption processing). In this embodiment, priority is given to the interrupt process before the timer interrupt or the interrupt request is set to be permitted by executing step S15b before the loop process from step S17 to step S19. Processing for setting or changing the order is performed.

  Next, the timer interrupt process will be described. FIG. 45 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, in a period during which interruption is permitted during execution of the loop process of steps S17 to S19, the CPU 56 of the game control microcomputer 560 A timer interrupt process that is activated in response to the occurrence of a timer interrupt is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not a power-off signal is output (whether the power-on signal is turned on) (step S20). Then, the CPU 56 inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a and 30a via the switch circuit 58, and detects the input of each switch (switches) Process: Step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 executes display control processing for performing display control of the special symbol display 8, the normal symbol display 10, the special symbol hold storage display 18, and the normal symbol hold storage display 41 (step S22). For the special symbol display 8 and the normal symbol display 10, control for outputting a drive signal to each display is executed according to the contents of the output buffer set in steps S36 and S37.

  Next, the CPU 56 executes magnet sensor error notification processing for performing magnet sensor error notification based on the detection signal input from the magnet sensor (step S24).

  Next, the CPU 56 performs a process of updating the count value of each counter for generating a random number for determination such as a random number for determination per ordinary symbol used for game control (determination random number update process: step S25). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S26). Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S27).

  Next, the CPU 56 performs special symbol process processing (step S28). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S29). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting the effect control command related to the effect symbol synchronized with the change of the special symbol in the transmission data register of the serial communication circuit 511 and sending the effect control command (effect symbol command control process: step S30). . It should be noted that the fact that the variation of the effect symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Next, the CPU 56 performs information output processing for outputting data such as a start port signal supplied to the hall management computer, a symbol determination number of times 1 signal, a jackpot 1 to 3 signal, a time reduction signal, a security signal, and the like (step S31). ).

  Next, the CPU 56 executes processing for transmitting / receiving (input / output) signals to / from the payout control microcomputer 370 via the serial communication circuit 511, and when a winning occurs, detection of the winning opening switches 29a, 30a, etc. Prize ball processing is performed for setting the number of prize balls based on the signal (step S32). In this embodiment, data indicating the number of winning balls is obtained by changing the lower 4 bits of the winning ball number command in response to detection of winning based on the winning opening switch 29a, 30a being turned on. The command is set to a command, and the set prize ball number command is output to the payout control microcomputer 370 via the serial communication circuit 511. The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number command in which data indicating the number of prize balls is set.

  In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S33). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 relates to the connection signal and the contents related to the solenoid in the RAM area of the output port 0. Is output to the output port (step S34: output processing). And CPU56 performs the memory | storage process which checks the increase / decrease in a pending | holding memory | storage number (step S35).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S36). Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in an output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S37).

  Next, the CPU 56 performs a status display lamp display process for setting status display control data for displaying each status display lamp in an output buffer for setting the status display control data (step S38). In this case, when the gaming state is the short time state, the state display control data for displaying the state indicator lamp indicating the short time state is set in the output buffer. When the gaming state is also controlled to a high probability state (for example, a probability variation state), state display control data for displaying a state indicator lamp indicating the high probability state is set in the output buffer. You may do it.

  Next, the CPU 56 performs frame state output processing for transmitting a frame state display command in which information indicating the error state of the gaming machine is set to display the error state of the gaming machine to the production control microcomputer 100. Execute (Step S39).

  Thereafter, the interrupt permission state is set (step S40), and the process ends.

  With the above control, in this embodiment, the game control process is started every 4 ms. The game control process corresponds to the processes of steps S21 to S39 (except for steps S31 and S33) in the timer interrupt process. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  46 and 47 are flowcharts illustrating an example of the power-off process in step S20. In the power-off process, the game control microcomputer 560 first checks whether or not a power-off signal is output (whether or not it is turned on) (step S450). If not on, the value of the backup monitoring timer formed in the RAM 55 is cleared to 0 (step S451). If it is on, the value of the backup monitoring timer is incremented by 1 (step S452). If the value of the backup monitoring timer matches the determination value (for example, 2) (step S453), the power supply stop processing after step S454, that is, the preparation processing for power supply stop is executed. That is, the state shifts from the state in which the progress of the game is controlled to the state in which the power supply stop process (the power-off control process) for saving the game state is executed. Note that “formed in the RAM” means an area in the RAM.

  By using the backup monitoring timer and the determination value, if the power-off signal is kept on for a time corresponding to the determination value, the power supply stop process is started. That is, even when the power-off signal is turned on for a moment due to noise or the like, the power supply stop process is not erroneously started. Note that the value of the backup monitoring timer is stored by the backup power source for a predetermined period even when power supply to the gaming machine is stopped. Therefore, in step S8 in the main process, it can be confirmed that the process result of the power supply stop process is stored because the value of the backup monitoring timer is the same as the determination value.

  In the power supply stop process, the game control microcomputer 560 creates parity data (steps S454 to S463). That is, first, clear data (00) is set in the checksum data area (step S454), and the checksum calculation start address corresponding to the start address of the RAM area in which the contents are to be stored even when power supply is stopped is set in the pointer. (Step S455). Further, the number of checksum calculations corresponding to the final address of the RAM area where the contents are to be stored even when the power supply is stopped is set (step S456).

  Next, an exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated (step S457). The calculation result is stored in the checksum data area (step S458), the pointer value is incremented by 1 (step S459), and the checksum calculation count value is decremented by 1 (step S460). Then, the processes in steps S457 to S460 are repeated until the value of the checksum calculation count becomes 0 (step S461).

  When the value of the checksum calculation count becomes 0, the game control microcomputer 560 inverts the value of each bit of the contents of the checksum data area (step S462). Then, the inverted data is stored in the checksum data area (step S463). This data becomes parity data to be checked when the power is turned on. Next, an access prohibition value is set in the RAM access register (step S471). Thereafter, the built-in RAM 55 cannot be accessed.

  Further, the game control microcomputer 560 sets the head address of the port clear setting table stored in the ROM 54 as a pointer (step S472). In the port clear setting table, the number of processes (the number of output ports to be cleared) is set to the first address, and then the output port address and output value data (clear data: the value of the off state of each bit of the output port) However, the output ports for the number of processes are sequentially set.

  The game control microcomputer 560 loads data at the address pointed to by the pointer (that is, the number of processes) (step S473). Further, the value of the pointer is incremented by 1 (step S474), and the data of the address pointed to by the pointer (that is, the address of the output port) is loaded (step S475). Further, the value of the pointer is incremented by 1 (step S476), and the data of the address pointed to by the pointer (that is, output value data) is loaded (step S477). Then, the output value data is output to the output port (step S478). Thereafter, the number of processes is reduced by 1 (step S479), and if the number of processes is not 0, the process returns to step S474. If the number of processes is 0, that is, if all the output ports to be cleared are cleared, the timer interrupt is stopped (step S481) and the loop process is started. Note that the process of clearing the output port may be executed before the process of creating checksum data. For example, the CPU 56 may execute the output port clear processing in steps S472 to S480 immediately after determining Y in step S453.

  In the loop processing, it is monitored whether or not the power-off signal is turned off (step S482). Then, while the power-off signal is in the ON state (Y in step S482), the process in step S482 is repeatedly executed to stand by. In contrast, when the power-off signal is turned off in step S482 (Y in step S482), processing for clearing the random number latch flag is executed.

  That is, the random number latch flag corresponding to the random value register R1D is turned on according to whether or not the bit value of the random number latch flag data RDFM0 stored in the bit number [0] of the random number latch flag register RDFM is “1”. It is determined whether or not there is (step S483). If this random number latch flag is on (Y in step S483), the random value register R1D is read to clear the bit value of the random number latch flag data RDFM0 to “0”, and the corresponding random number latch flag is set. An off state is set (step S484). If the random number latch flag specified by the random number latch flag data RDFM0 is OFF in step S483 (N in step S483) or after executing the processing in step S484, the bit number [1 of the random number latch flag register RDFM is set. ], It is determined whether or not the random number latch flag corresponding to the random number register R2D is on (step S485). At this time, if the random number latch flag is ON (Y in step S485), the random value register R2D is read to clear the bit value of the random number latch flag data RDFM1 to “0”, and the corresponding random number latch flag is set. An off state is set (step S486). Through the processing in step S484 and step S486, the random number latch flag is turned off, and the random number value register R1D and the random number value register R2D can be set in a state where storage of new numerical data is permitted. Note that the numerical data read from the random value register R1D or the random value register R2D by the processing in step S484 or step S486 is a process for determining whether or not to control the big hit gaming state with the special figure display result as “big hit”. It can be discarded (erased) as it is. Further, instead of the processing of step S483 to step S486, the random number latch flag is set by reading the random number value register R1D and the random number value register R2D regardless of the values of the random number latch flag data RDFM0 and the random number latch flag data RDFM1. Processing to turn off may be performed. In this embodiment, since there is one start winning opening, only one of the random number registers R1D and R2D may be used, and only one of the random number registers may be read. . Further, for example, the gaming machine may be configured to include three or more start winning ports, and when there are three start winning ports, three random number value registers may be read. As such, it is only necessary to read all the random value registers that are used and clear the random number latch flags.

  When the random number latch flag specified by the random number latch flag data RDFM1 is OFF in step S485 (N in step S485) or after performing the process in step S486, after setting for a predetermined power failure recovery is performed. (Step S487), the process returns to the top of the main process shown in FIG. As an example, in the process of step S487, the storage address of the power-off recovery vector table is stored in the stack pointer built in the CPU 56, and the game control timer interrupt process is returned (returned). Here, the power-off recovery vector table may be any table that specifies the head address of the control code (game control program) stored in the ROM 54. When returning from an interrupt process such as the timer interrupt process shown in FIG. 45, the stored data at the address specified by the stack pointer is read as the return address. Thus, after executing the processing of step S487, the CPU 56 can start (restart) the execution of the game control from the head of the control code stored in the ROM 54.

  When the power supply is stopped by the above processing, the power supply stop processing in steps S454 to S481 is executed, and data indicating that the power supply stop processing has been executed (backup monitoring having a determination value). Timer and checksum) are stored in the backup RAM, RAM access is disabled, the output port is cleared, and timer interrupt for executing the game control process is set to disabled.

  In this embodiment, the RAM 55 is backed up by a backup power source (the contents of the RAM 55 are preserved for a predetermined period even when the power supply to the gaming machine is stopped). In this example, the checksum based on the content of the RAM 55 when the power-off signal is output is stored in the backup area of the RAM 55 together with the value of the backup monitoring timer by the processing of steps S452 to S479. After the power supply to the gaming machine is stopped, when the power supply is restored within a predetermined period, the game control means performs the data stored in the RAM 55 (immediately before the power supply is stopped) by the processing of steps S41 to S44 described above. In accordance with the data indicating the game state that is the control state by the game control means (for example, including the process flag state, the big hit flag state, the probability change flag state, the output port output state, etc.) It is possible to return to the state immediately before the supply is stopped. If the power supply stop period exceeds the predetermined period, the value of the backup monitoring timer and the checksum should be different from the regular values. In this case, the initialization process of steps S10 to S13 is executed. The

  As described above, the power supply stop process (preparation process for stopping the power supply) ensures that the data for returning the gaming state to the state immediately before the power supply stopped is the fluctuation data storage means (in this example) Stored in a part of the RAM 55). Therefore, even if the power is cut off due to a power failure or the like, if the power is restored within a predetermined period, the gaming state can be returned to the state immediately before the power supply is stopped.

  If the power-off signal is turned off, the process returns to step S1. In this case, since data indicating that the power supply stop process has been executed is set, the recovery process of steps S91 to S93 is executed. Therefore, when the power-off signal from the payout control board 37 is turned off after executing the power supply stop process, the process returns to the state of controlling the progress of the game. Therefore, even if a power interruption or the like occurs, the game control process does not stop, and the game control process is automatically continued.

  Next, the prize ball process (step S32) in the main process will be described. First, payout control signals (connection signals, prize ball information) and payout control commands transmitted and received between the main board 31 and the payout control board 37 will be described.

  FIG. 48 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means. In this embodiment, a connection signal and prize ball information are transmitted and received as control signals between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like. As shown in FIG. 48, the connection signal is output when the main board 31 rises (when the game control means starts the game control process), and notifies the payout control board 37 that the main board 31 has risen. This is a signal (connection signal for the main board 31). The connection signal indicates that the prize ball can be paid out. The connection signal is output via the I / O port 57 and the output circuit 67A of the game control microcomputer 560, and is used for payout control via the input circuit 373A and the I / O port 372e of the payout control microcomputer 370. It is input to the microcomputer 370. The connection signal is 1-bit data and is transmitted through one signal line. Note that the connection signal is ready to be output by setting an initial value to the bit corresponding to the connection signal of the output port 0 by the process of step S4 executed when the power is turned on (specifically, in step S34). Although it is output by processing, it may be output at the timing of step S4). The prize ball information is information for notifying the main board 31 that ten prize balls have been detected each time one prize ball has been detected on the payout control board 37 side. . The prize ball information is output via the I / O port 372a and the output circuit 373B of the payout control microcomputer 370, and the game control is performed via the input circuit 67B and the I / O port 57 of the game control microcomputer 560. To the microcomputer 560. The prize ball information is 1-bit data and is transmitted through one signal line.

  Similarly to the game control microcomputer 560, the payout control microcomputer 370 includes a serial communication circuit 380. Various payout control commands are transmitted and received between the serial communication circuit 511 built in the game control microcomputer 560 and the serial communication circuit 380 built in the payout control microcomputer 370. The configuration and function of the serial communication circuit 380 built in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 511 built in the game control microcomputer 560.

  FIG. 49 is an explanatory diagram showing an example of the contents of control commands transmitted and received between the game control means and the payout control means. In this embodiment, various payout control commands are transmitted and received between the microcomputers of the main board 31 and the payout control board 37 in order to perform various controls related to payout control and the like.

  As described above, the payout control command is composed of 8-bit data (binary 8-digit data), and is output as a control command indicating predetermined contents depending on the contents of the set 8-bit data.

  The connection confirmation command is sent from the game control microcomputer 560 at regular intervals (1 s) in order to confirm whether or not the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal. Control command to be sent. The data content of the connection confirmation command is “A0 (H)”, that is, “10100000”.

  The connection OK command is a control command for notifying that the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal, and the payout control microcomputer 370 issues a connection confirmation command. Is a control command that is transmitted as a response signal in response to the reception of. The data content of the connection OK command is “8x (H)”, that is, “1000xxxx”. Here, with regard to “xxxx” in the second byte of the connection OK command, as shown in FIG. 50, a winning ball error (a winning ball paying operation based on winning or a ball lending paying operation based on a ball lending request cannot be normally performed. 96: When the main control unconnected error shown in FIG. 96, payout switch abnormality detection error 1, payout switch abnormality detection error 2, payout case error, main control communication error) occur. In this case, “1” is set to “x” of the first bit (bit 0). When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, during the confirmation of the connection between the game control microcomputer 560 and the payout control microcomputer 370, the occurrence of a predetermined error in the payout control microcomputer 370 is detected. 560 can be notified. In the example shown in FIG. 50, a case has been shown in which a value indicating a payout error (award ball error, full tank error, out of ball error, payout number error error) is set as a control state in the connection OK command. A control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that a prize ball payout operation or a lending ball payout operation is in a control state to the connection OK command, and transmits it to the game control microcomputer 560. You may make it do.

  The award ball number command is a control command for notifying the number (0 to 15) of game balls for which a payout request is made, and is a control command transmitted by the game control microcomputer 560 based on the occurrence of a win. . The content of the prize ball number command data is “5x (H)”, that is, “0101xxx”. In this embodiment, three game balls are paid out when a game ball is detected by the start port switch 14a, and 10 game balls are paid out when a game ball is detected by any of the game port switches 29a and 30a. When a game ball is detected by the count switch 23, 15 prize balls are paid out. Therefore, when a game ball is detected by the start port switch 14a, a prize ball number command “01010011” for notifying the number of prize balls of 3 is transmitted, and the game ball is detected by one of the winning port switches 29a and 30a. If a prize ball number command “01011010” for notifying 10 prize balls is transmitted and a game ball is detected by the count switch 23, the number of prize balls for notifying 15 prize balls is sent. The command “0101111” is transmitted.

  The prize ball number acceptance command is a control command for notifying that the prize ball number specified by the prize ball quantity command has been accepted, and the payout control microcomputer 370 responds upon receipt of the prize ball quantity command. It is a control command transmitted as a signal. The content of the prize ball number reception command data is “70 (H)”, that is, “01110000”.

  The award ball end command is a control command indicating that the award ball operation (award ball payout operation) has ended, and is a control command that the payout control microcomputer 370 transmits based on the end of the award ball operation. The data content of the winning ball end command is “50 (H)”, that is, “01010000”.

  The command for preparing a prize ball is a control command for notifying that a prize ball movement has not been completed due to a long time for a prize ball movement, a rental ball movement or a predetermined error. is there. The contents of the data of the winning ball preparation command are “4x (H)”, that is, “0100xxxx”. Here, with regard to “xxxx” of the second byte of the command for preparing a prize ball, as shown in FIG. 50, when a prize ball error occurs, “1” is set to “x” of the first bit (bit 0). Is set. When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout number abnormality error occurs when the cumulative value of the number of payouts of prize balls and rental balls, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit 3) “1” is set to “x” of In this way, the payout control microcomputer 370 receives a prize ball when the prize ball operation takes a long time, or during a lending ball operation or when a predetermined error occurs during the execution of the prize ball operation. It is possible to notify the game control microcomputer 560 that the operation has not ended, and to notify the game control microcomputer 560 of the content of the error. As in the case of the connection OK command, the award ball preparation command notifies that a predetermined error has occurred by changing the contents of the lower 4 bits in accordance with the error state (by changing the predetermined bits). Note that the command for preparing a prize ball is not only in a state where an error occurs and the prize ball operation cannot be executed, but also in a state where the prize ball payout operation cannot be started immediately because the ball rental operation is in progress, This command (signal) is output even in the running state (the state in which the payout operation for the number of prize balls specified by the prize ball number command has not been completed). In the example shown in FIG. 50, a case in which a value indicating a payout error (award ball error, full tank error, out of ball error, payout number error error) is set as a control state in the command for preparing a prize ball is shown. However, a control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that the prize ball payout operation or the lending ball payout operation is in the control state in the award ball preparation command, and the game control microcomputer 560. You may make it transmit to.

  In this embodiment, the connection confirmation signal is realized by a connection confirmation command of the payout control command, the response signal is realized by a connection OK command, the payout number signal is realized by a prize ball number command, and the acceptance signal is It is realized by a prize ball number acceptance command, a payout end signal is realized by a prize ball end command, and a payout signal is realized by a prize ball preparation command.

  51 is a block diagram showing signal lines and the like used for transmission / reception of the control signal shown in FIG. 48 and the control command shown in FIG. As shown in FIG. 51, the connection signal is output by the game control microcomputer 560 via the output circuit 67A, and is input to the payout control microcomputer 370 via the input circuit 373A. The prize ball information is output by the payout control microcomputer 370 via the output circuit 373B, and input to the game control microcomputer 560 via the input circuit 67B. A prize ball signal 1 and a gaming machine error state signal, which will be described later, are also output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B. May be. The door opening signal and the mechanism plate opening signal may also be output by the payout control microcomputer 370 via the output circuit 373B and input to the game control microcomputer 560 via the input circuit 67B.

  Of the control commands, the connection confirmation command and the prize ball number command are output from the serial communication circuit 511 built in the game control microcomputer 560 and input to the serial communication circuit 380 built in the payout control microcomputer 370. The Of the control commands, the connection OK command, the winning ball number acceptance command, the winning ball end command, and the winning ball preparation command are output from the serial communication circuit 380 built in the payout control microcomputer 370, and the gaming control microcomputer 560. Is input to the serial communication circuit 511 incorporated therein. In FIG. 51, two signal lines (signal lines for sending commands from the game control microcomputer 560 to the payout control microcomputer 370 side and payout control microcomputers) are used as signal lines for serial communication. 370 shows a signal line for transmitting a command from 370 to the game control microcomputer 560 side. A signal line for transmitting a command from the game control microcomputer 560 to the payout control microcomputer 370 side, and a signal line for transmitting a command from the payout control microcomputer 370 to the game control microcomputer 560 side. May be configured as separate signal lines.

  Next, transmission / reception of a payout control command between the game control microcomputer and the payout control microcomputer during normal operation will be described. In this embodiment, a connection confirmation command and a prize ball number command are transmitted from the game control microcomputer 560 to the payout control microcomputer 370, and the payout control microcomputer 370 is connected to the game control microcomputer 560. An OK command, a prize ball number reception command, a prize ball end command, and a prize ball preparation command are transmitted.

  FIG. 52 is a sequence diagram showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 52, the game control microcomputer 560 is connected to the payout control microcomputer 370 via the serial communication circuit 511 to confirm whether or not the signal line is disconnected. A confirmation command is transmitted to the payout control microcomputer 370. When the payout control microcomputer 370 receives the connection confirmation command via the serial communication circuit 380, the payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560. When the game control microcomputer 560 receives the connection OK command, the game control microcomputer 560 transmits a connection confirmation command after 1 s (1 second) has elapsed since the reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  53 and 54 are sequence diagrams showing transmission and reception of signals between the game control microcomputer and the payout control microcomputer during the prize ball movement. As shown in FIGS. 53 and 54, when a winning occurs and a winning ball payout operation is executed, the game control microcomputer 560 is set with data indicating the number of winning balls via the serial communication circuit 511. The prize ball number command is transmitted to the payout control microcomputer 370. In this case, the game control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the received connection OK command with respect to the previously transmitted connection confirmation command (see FIG. 50), and A winning ball number command is transmitted to the payout control microcomputer 370 on the condition that the winning prize is received after the connection OK signal is received until 1 second elapses.

  Next, when the payout control microcomputer 370 receives the award ball number command, if the award ball operation can be executed immediately (that is, if the lending ball is not being dispensed and no error has occurred), the award A prize ball number reception command indicating that the number of balls has been received is transmitted to the game control microcomputer 560 via the serial communication circuit 380. If the prize ball payout is not completed within 1 s (1 second) from the time when the prize ball number acceptance command is transmitted, the prize ball is being prepared after 1 s (1 second) has elapsed since the prize ball number acceptance command is transmitted. Send a command. Thereafter, until the completion of the payout of the winning ball, the winning ball preparation command is repeatedly transmitted every 1 s (1 second) from the time when the winning ball preparation command is transmitted. Also, a payout operation for the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, a prize ball end command indicating the end of the prize ball payout operation is played via the serial communication circuit 380. It transmits to the control microcomputer 560.

  Next, when the game control microcomputer 560 receives the prize ball end command, as shown in FIG. 53, if the number of prize balls to be paid out is not yet stored, the game control microcomputer 560 issues a prize ball end command. Transmission of a new connection confirmation command is resumed after 1 s (1 second) has elapsed from the time of reception. On the other hand, as shown in FIG. 54, when the number of winning balls to be paid out is already stored, a winning ball number command for designating the next winning ball number is immediately issued without waiting for 1 s (1 second). This is sent to the payout control microcomputer 370. Also in this case, the gaming control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the previously received connection OK command or the winning ball preparation command (see FIG. 50), and The award ball number command is transmitted to the payout control microcomputer 370 on the condition that the winning prize is received from the reception of the ball end command until 1 second elapses. Thereafter, transmission and reception of control commands are repeated according to the same sequence.

  FIG. 55 is a sequence diagram showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when the winning ball operation cannot be executed immediately. Even if the payout control microcomputer 370 receives the award ball number command, if the lending ball is being paid out or is in an error state, the award ball number specified by the received award ball number command. Unable to start the prize ball payout operation. In such a case, as shown in FIG. 55, even when the payout control microcomputer 370 receives the prize ball number command, it does not immediately send the prize ball number acceptance command, and the prize ball payout operation is completed. A command for preparing a prize ball for notifying that the game has not been sent is transmitted to the game control microcomputer 560. In this case, the payout control microcomputer 370 is in a state of preparing a prize ball at regular intervals (every 1 s) unless the payout operation of the lending ball is completed and the award ball action can be started or the error is not canceled. The command is transmitted to the game control microcomputer 560.

  Next, the payout control microcomputer 370 finishes the lending ball payout operation and becomes ready to start the next prize ball operation, or when the error is canceled, the prize indicating that the number of prize balls has been received is received. The ball number acceptance command is transmitted to the game control microcomputer 560 via the serial communication circuit 380. If the prize ball payout is not completed within 1 s (1 second) from the time when the prize ball number acceptance command is transmitted, the prize ball is being prepared after 1 s (1 second) has elapsed since the prize ball number acceptance command is transmitted. Send a command. Thereafter, until the completion of the payout of the winning ball, the winning ball preparation command is repeatedly transmitted every 1 s (1 second) from the time when the winning ball preparation command is transmitted. Also, a payout operation for the number of prize balls specified by the prize ball number command is executed, and when the prize ball payout operation is completed, a prize ball end command indicating the end of the prize ball payout operation is played via the serial communication circuit 380. It transmits to the control microcomputer 560.

  FIG. 56 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer during normal operation. As shown in FIG. 56, when the game control microcomputer 560 transmits the connection confirmation command to the payout control microcomputer 370, the game control microcomputer 560 receives the connection OK command transmitted from the payout control microcomputer 370. When the game control microcomputer 560 receives the connection OK command, the game control microcomputer 560 transmits the connection confirmation command again after 1 s (1 second) has elapsed since the reception. As long as the connection state is normal, the game control microcomputer 560 and the payout control microcomputer 370 repeatedly execute the connection confirmation communication process as described above.

  If there is a prize when the connection confirmation communication process is not executed (between receiving the connection OK command and transmitting the next connection confirmation command), the game control microcomputer 560 The control for repeatedly transmitting the confirmation command is interrupted, data indicating the number of winning balls is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. In this case, the game control microcomputer 560 performs a process of subtracting the prize ball number storage based on the reception of the prize ball number reception command (specifically, 1 is subtracted from a prize ball command output counter described later). (See step S52404). Then, the payout control microcomputer 370 pays out the number of prize balls specified by the prize ball number command, and when the prize ball payout (prize ball payout operation) is completed, the prize ball end command is sent to the game control microcomputer. Send to computer 560. As described above, when the winning ball payout operation takes a long time, the payout control microcomputer 370 waits for 1 s (1 second) until the winning ball payout operation is completed. Is sent repeatedly. When the game control microcomputer 560 receives the prize ball end command, if the number of prize balls to be paid out is not yet stored, the game control microcomputer 560 transmits a connection confirmation command after 1 s (1 second) has elapsed since the reception. To do.

  If there is a prize during the execution of the connection confirmation communication process (between sending the connection confirmation command and receiving the connection OK command), the game control microcomputer 560 and the payout control microcomputer 370 Since the connection state is not confirmed, the award ball number command is not immediately transmitted, but the process waits until the connection OK command can be confirmed. When the connection OK command is received from the payout control microcomputer 370, the game control microcomputer 560 sets data indicating the number of winning balls in the lower 4 bits of the winning ball number command, and sets the set number of winning balls. The command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. Then, the payout control microcomputer 370 performs the same processing, pays out the number of prize balls designated by the prize ball number command, and when the prize ball is paid out (prize ball payout operation), The ball end command is transmitted to the game control microcomputer 560.

  After receiving the winning ball end command, the game control microcomputer 560 does not set a value indicating an error in the lower 4 bits of the previously received connection OK command or winning ball preparation command (see FIG. 50). In addition, even when the start winning prize is received from the reception of the winning ball end command until 1 second elapses, the winning ball number command is transmitted to the payout control microcomputer 370. In other words, in this embodiment, the game control microcomputer 560 receives a prize ball end command from when a connection OK signal in which a value indicating an error is not set until one second elapses. The award ball number command can be transmitted until 1 second has elapsed.

  FIG. 57 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when an error occurs in the winning ball. As shown in FIG. 57, when the game control microcomputer 560 transmits the connection confirmation command to the payout control microcomputer 370, the game control microcomputer 560 receives the connection OK command transmitted from the payout control microcomputer 370. If there is a win when the communication process for confirming the connection is not executed, the game control microcomputer 560 sets the data indicating the number of winning balls in the lower 4 bits of the winning ball number command, and the set winning prize is set. The ball number command is transmitted to the payout control microcomputer 370. Upon receiving the prize ball number command, the payout control microcomputer 370 transmits a prize ball number reception command to the game control microcomputer 560. Then, the payout control microcomputer 370 pays out the number of prize balls specified by the prize ball number command. When executing the payout operation for the number of prize balls specified by the prize ball number command, a predetermined error (for example, an abnormal payout number error, a ball lending, a full tank, or an out of ball error) occurs. When the ball payout operation cannot be performed (abnormal state, error state), the payout control microcomputer 370 issues a prize ball preparing command for notifying that an error has occurred and the prize ball payout operation has not ended. It transmits to the game control microcomputer 560. In this case, the payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals (every 1 s) unless the generated error is canceled. When the predetermined error state is canceled (resolved) and the winning ball payout operation ends, the payout control microcomputer 370 transmits a winning ball end command to the game control microcomputer 560. The award ball preparation command is transmitted from the payout control microcomputer 370 to the game control microcomputer 560 every 1 s after the award ball number acceptance command is transmitted. Further, while the game control microcomputer 560 is receiving a command for preparing a prize ball, the game control microcomputer 560 is controlled not to transmit a connection confirmation command. Specifically, the payout control microcomputer 370 outputs a prize ball end command based on the completion of the prize ball payout operation, and the game control microcomputer 560 receives the prize ball end command. Based on this, control is performed so as to return to a state in which a connection confirmation command is output every predetermined period (1S).

  FIG. 58 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer when a communication error occurs during connection confirmation. As shown in FIG. 58, the game control microcomputer 560 has transmitted the connection confirmation command to the payout control microcomputer 370, but has not received the connection OK command from the payout control microcomputer 370, that is, When a connection state abnormality (communication error) occurs, the connection confirmation command is transmitted again after 10 s (10 seconds) have elapsed since the connection confirmation command was transmitted. In other words, if the process of transmitting the connection confirmation command every 1 s (1 second) when the connection OK command cannot be received is continued, the number of connection confirmation command transmissions is increased even though the communication state is unstable. Since it increases in vain, the transmission interval of the connection confirmation command is extended to 10 s (10 seconds), and the control is switched to transmitting the connection confirmation command with the minimum necessary number of transmissions until the communication state is recovered. If a winning occurs when a communication error has occurred, the game control microcomputer 560 will receive a connection OK command from the payout controlling microcomputer 370, even if a new winning occurs. Without transmitting the award ball number command, the connection confirmation command is continuously transmitted at regular intervals (10 s). When the communication error is canceled (resolved) and a connection OK command is transmitted from the payout control microcomputer 370, the game control microcomputer 560 transmits a prize ball number command.

  FIG. 59 is a timing chart showing signal transmission / reception between the game control microcomputer and the payout control microcomputer at the time of a communication error during prize ball number notification. As shown in FIG. 59, the game control microcomputer 560 has transmitted a prize ball number command based on the occurrence of a win, but has not received a prize ball number acceptance command from the payout control microcomputer 370. In this case, that is, when a connection state abnormality (communication error) occurs, a connection confirmation command is transmitted to the payout control microcomputer 370 after 10 seconds (10 seconds) have elapsed since the prize ball number command was transmitted. Then, the connection confirmation command is repeatedly transmitted every 10 s (10 seconds) until the communication state is recovered. Thereafter, when the communication error is canceled (resolved) and the connection OK command is received from the payout control microcomputer 370, the award game control microcomputer 560 returns to the normal (normal) operation, and the number of winning balls The command is retransmitted (retryed) to the payout control microcomputer 370. Specifically, the game control microcomputer 560 does not subtract the prize ball number storage if it does not receive the prize ball number acceptance command even after sending the prize ball number command (described later). If N in step S52403, the value of the prize ball command output counter in step S52404 is not subtracted by 1), and the value of the prize ball command output counter is maintained as it is when the prize ball number command is transmitted next time. The prize ball number command is retransmitted based on that (see steps S52301 to S52035 described later).

  Next, the prize ball process (step S32) will be described. FIG. 60 is a flowchart showing an example of the prize ball processing in step S32. In the prize ball process, the game control microcomputer 560 (specifically, the CPU 56), the prize ball command output counter addition process (step S501), the prize ball control process (step S502), and the prize ball counter subtraction process (step S503). ).

  In the prize ball command output counter addition process, a prize ball number table shown in FIG. 61 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “4”) is set to the start address of the prize ball number table, and then the lower address of the switch-on buffer, the prize ball command output counter, and the prize ball designation for designating the number of prize balls Data is set sequentially. The prize ball command output counter is a counter that counts the number of prizes received in the prize opening, and is set in the ROM 54, for example. The game control microcomputer 560 includes a corresponding prize ball command output counter for each number of prize balls (0 to 15). In this embodiment, the game control microcomputer 560 includes a prize ball command output counter 1 corresponding to the prize ball number “15” and prize ball command output counters 2, 3 (2) corresponding to the prize ball number “10”. Corresponding to the normal winning ports 29 and 30) and a prize ball command output counter 4 corresponding to the number of prize balls “3”. Each prize ball command output counter is counted up by prize ball command output counter addition processing, as will be described later. If the prize ball command output counter 1 set in the prize ball number table is not 0, the CPU 56 indicates the number of prize balls (15) based on the prize ball designation data for designating the number of prize balls (15). The data is set in the lower 4 bits of the prize ball number command, and the set prize ball number command is transmitted to the payout control microcomputer 370. The CPU 56 determines the number of prize balls (10) if the value of the prize ball command output counter 1 set in the prize ball number table is 0 and the value of the prize ball command output counters 2 and 3 is not 0. Is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. To do. Further, the CPU 56 determines that the values of the prize ball command output counter 1 and the prize ball command output counters 2 and 3 set in the prize ball number table are 0 and the value of the prize ball command output counter 4 is not 0. Based on the prize ball designation data for designating the number of prize balls (3), data indicating the number of prize balls (3) is set in the lower 4 bits of the prize ball number command, and the set prize ball number command is issued. It transmits to the control microcomputer 370. In FIG. 61, the switch-on buffer 1 corresponds to the input port 0, and the switch-on buffer 2 corresponds to the input port 2.

  FIG. 62 is a flowchart showing the prize ball command output counter addition processing in step S501. In the prize ball command output counter addition process, the game control microcomputer 560 (specifically, the CPU 56) sets the start address of the prize ball number table as a pointer (step S5101). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S5102).

  Next, the CPU 56 increments the pointer value by 1 (step S5103), loads the lower address of the switch-on buffer pointed to by the pointer into the lower byte of the pointer buffer (step S5104), and loads the switch-on buffer pointed by the pointer buffer into the register. (Step S5105). Next, the CPU 56 increments the value of the pointer by 1 (step S5106), and loads the lower address of the prize ball command output counter pointed to by the pointer into the lower byte of the pointer buffer (step S5107). Next, the CPU 56 increments the value of the pointer by 1 (step S5108), and calculates the logical product of the contents of the switch-on buffer loaded in the register and the prize ball designation data pointed to by the pointer (step S5109).

  If the calculation result in step S5109 is 0 (Y in step S5110), that is, if the detection signal of the switch to be inspected is not on, the number of processes is reduced by 1 (step S5114), and if the number of processes is 0 The process ends, and if the number of processes is not 0, the process returns to step S5103 (step S5115).

  If the calculation result in step S5109 is not 0 (N in step S5110), that is, if the detection signal of the switch to be inspected is on, the CPU 56 adds 1 to the value of the prize ball command output counter pointed to by the pointer. (Step S5111). However, when a carry occurs in the value of the prize ball command output counter as a result of the addition, the CPU 56 subtracts 1 from the value of the prize ball command output counter and restores the original value (steps S5112, S5113). Then, the process proceeds to step S5114.

  FIG. 63 is a flowchart showing the prize ball control processing in step S502. In the prize ball control process, the game control microcomputer 560 (specifically, the CPU 56) executes any one of steps S521 to S525 in accordance with the value of the prize ball process code.

  FIG. 64 is a flowchart showing the prize ball transmission process 1 (step S521) executed when the value of the prize ball process code is zero. In the prize ball transmission process 1, the CPU 56 performs control to transmit a connection confirmation command to the payout control microcomputer (step S5211). Specifically, the CPU 56 performs processing for outputting a connection confirmation command to the transmission data register of the serial communication circuit 511. Then, the CPU 56 sets a value “1” indicating a prize ball connection confirmation process in the prize ball process code (step S5212), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S5213). . If a connection OK command is not received even after 10 seconds have elapsed after transmitting the connection confirmation command based on the connection confirmation time 2 set in step S5213, the connection confirmation command is transmitted thereafter. It is controlled so as to extend the interval to 10 seconds. Specifically, the prize ball process timer set in step S5213 is measured in the process of step S5229, which will be described later, 10 seconds elapses without receiving a connection OK command, and the determination is Y in step S5227. Then, it returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S5228 and S5211).

  The prize ball process timer is set to a value (for example, an integer multiple of the interrupt period) in consideration of the interrupt period in the timer interrupt process executed by the game control microcomputer 560. This is because other timers used in the game control microcomputer 560, the payout control microcomputer 370, and the effect control microcomputer 100 (for example, main control communication control timer, payout control timer, re-payout waiting timer, The same applies to the prize ball information output timer and prize ball signal 1 output timer.

  FIG. 65 is a flowchart showing a prize ball connection confirmation process (step S522) executed when the value of the prize ball process code is 1. In the winning ball connection confirmation process, the CPU 56 first confirms whether there is data in the reception data register of the serial communication circuit 511 (step S5221). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 511 (see FIG. 33). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S5227.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether or not an error has occurred in the serial communication circuit 511 (step S5222). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 511 is set (see FIG. 33). If an error has occurred, the process proceeds to step S5227.

  If no error has occurred in the serial communication circuit 511, the CPU 56 reads the command from the reception data register of the serial communication circuit 511, and checks whether the received command is a connection OK command (step S5223). If it is not a connection OK command, the process proceeds to step S5227.

  If the connection OK command has been received, the CPU 56 stores the error information (see FIG. 50) set in the lower 4 bits of the connection OK command in the frame state display buffer (step S5224).

  Next, the CPU 56 sets a value “2” indicating the prize ball transmission process 2 in the prize ball process code (step S5225), and sets a connection confirmation time 1 (for example, 1 second) in the prize ball process timer (step S5226). . Note that, based on the connection confirmation time 1 set in step S5226, control is performed to repeatedly transmit the next connection confirmation command every time one second elapses after reception of the connection OK command. Specifically, the prize ball process timer set in step S5226 is measured in the process of step S52315 described later, and a timeout occurs after 1 second has passed without sending a prize ball number command, and it is determined as Y in step S52313. Then, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  In step S5227, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if the connection OK command has not been received even after 10 seconds have passed after sending the connection confirmation command), the CPU 56 sends a winning ball to the winning ball process code. A value “0” indicating the process 1 is set (step S5228), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S5229).

  FIG. 66 is a flowchart showing the prize ball transmission process 2 (step S523) executed when the value of the prize ball process code is 2. In the prize ball transmission process 2, the CPU 56 checks whether or not any prize ball command output counters 1 to 4 have a count value other than 0 (step S52301). If there is no count value other than 0, the process proceeds to step S52313.

  If any of the prize ball command output counters 1 to 4 has a count value other than 0 (that is, if the count value is 1 or more), the CPU 56 loads the contents of the frame state display buffer. Then, it is confirmed whether or not the content of the frame state display buffer is 0 (step S5232). If the content of the frame state display buffer is not 0, the processing is terminated as it is. By performing such control, when the connection OK command in which the error information is set is received and the payout control microcomputer 370 is controlled to be in the payout stop state, the process does not proceed to step S52303 and subsequent steps. Then, control is made so that transmission of the prize ball number command is suspended.

  If the contents of the frame state display buffer are 0 (that is, if no error relating to payout has occurred), the payout control CPU 371 determines the number of prize balls corresponding to the prize ball command output counter whose count value is not 0. It is set in the buffer (step S52303). Specifically, in step S52301, the CPU 56 first checks whether or not the count value of the prize ball command output counter 1 is zero. If the count value of the prize ball command output counter 1 is 1 or more, in step S52303, the CPU 56 sets 15 prize balls in the number buffer. In step S52301, if the count value of the prize ball command output counter 1 is 0, the CPU 56 checks whether the count values of the prize ball command output counters 2 and 3 are 0 or not. If the count value of the prize ball command output counters 2 and 3 is 1 or more, the CPU 56 sets the number of prize balls in the number buffer in step S52303. In step S52301, if the count value of the prize ball command output counters 2 and 3 is also 0, the CPU 56 checks whether the count value of the prize ball command output counter 4 is 0 or not. If the count value of the prize ball command output counter 4 is 1 or more, in step S52303, the CPU 56 sets the number of prize balls to 3 in the number buffer.

  In addition, the CPU 56 sets the number of prize balls corresponding to the prize ball command output counter whose count value is not 0 in the prize ball number command (step S52304), and uses the prize ball number command in which the number of prize balls is set for payout control. Control to transmit to the microcomputer 370 is performed (step S52305). Specifically, the CPU 56 performs a process of outputting a prize ball number command in which the prize ball number is set in the transmission data register of the serial communication circuit 511.

  By executing the processing of steps S52301 and S52305, in this embodiment, if there is a prize ball command output counter whose count value is not 0 regardless of the connection confirmation command transmission timing (ie, If there is a prize ball number storage and a predetermined payout condition is established), a prize ball number command is transmitted to the payout control microcomputer 370.

  Then, the CPU 56 sets a value “3” indicating the prize ball reception confirmation process in the prize ball process code (step S52306), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52307). . It should be noted that, based on the connection confirmation time 2 set in step S52307, after transmitting the prize ball number command, it is confirmed whether a prize ball number acceptance command or a prize ball preparation command is received within 10 seconds. . Specifically, the prize ball process timer set in step S52307 is measured in the process of step S52411 to be described later, and 10 seconds elapses without receiving a prize ball number acceptance command or a prize ball preparation command. If it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  If the prize ball number command is transmitted in step S52305 by executing the process of step S52306, the process proceeds to the prize ball reception confirmation process without returning to the prize ball transmission process 1 including the connection confirmation command transmission process. Is done. Therefore, in this embodiment, the process of repeatedly transmitting the connection confirmation command is executed every predetermined time (for example, 1 second) until the prize ball number command is transmitted, but the prize ball number command is transmitted. In particular, the control for transmitting the connection confirmation command is stopped (more specifically, after the prize ball number command is transmitted, the process proceeds to the prize ball end confirmation process by receiving the prize ball number acceptance command described later. Connection (without returning to the prize ball transmission process 1) by repeating the prize ball receipt confirmation process (see steps S52403 to S52405) or by receiving the prize ball preparation command (see steps S52406 to S52408). In this case, the control for sending the confirmation command is stopped. Unless an abnormal state occurs in which no payout control command is returned, after the prize ball number command is transmitted, the game control microcomputer 560 is connected until the prize ball payout operation is finished and the prize ball end command is received. A confirmation command is never sent.

  Next, the CPU 56 adds the value of the number buffer set in step S52303 to the prize ball number counter (step S52308), and whether or not the added count value is equal to or greater than a predetermined prize ball shortage determination value (eg, 501). Is confirmed (step S52309). In this embodiment, the prize ball number counter is a counter used for grasping the number of prize balls that have not been paid out on the game control microcomputer 560 side, and when the prize ball number command is transmitted, The number of prize balls designated in (1) is added, and every time ten prize balls are paid out, 10 is subtracted based on the prize ball information output from the payout control microcomputer 370. Further, as described above, the prize ball number counter is set to “250” as an initial value in the initial setting process of the main process. When the count value of the prize ball counter reaches a predetermined prize ball shortage determination value (for example, 501) or more, the number of prize balls that have not been paid out is excessively large. Can be determined. Further, when the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), an abnormally large number of game balls are paid out in excess of the number to be paid out originally. Therefore, it can be determined that an excessive number of prize balls has occurred.

  In this embodiment, the prize ball number counter is added (see step S52308) immediately after the prize ball number command is transmitted (see step S52305). However, the prize ball number command is transmitted. For example, a prize ball number command may be transmitted immediately after the addition process of the prize ball number counter is executed.

  When it is determined that there is a shortage of prize balls, the signal line for outputting the prize ball information is disconnected in addition to the case where some trouble occurs on the payout control microcomputer 370 side and the payout operation cannot be performed normally. Cases are also conceivable. On the other hand, when it is determined that the number of prize balls is excessive, a prize ball number command is transmitted in addition to the case where some kind of trouble occurs on the payout control microcomputer 370 side and the payout operation is performed more than necessary. It is also conceivable that some injustice is applied to the command line and the award ball number command is illegally input to the payout control microcomputer 370.

  When the count value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (for example, 501), the CPU 56 displays a prize ball error flag indicating that a prize ball shortage or a prize ball excess has occurred. It is confirmed whether it has already been set (step S52310). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets a prize ball error flag (step S52311) and controls to send a prize ball shortage error command to the effect control microcomputer 100 (step S52312). Specifically, the CPU 56 performs a process of setting the address of the winning ball shortage error command transmission table as a pointer. Then, based on the fact that the address of the winning ball shortage error command transmission table is set in the pointer in step S52312, the serial communication circuit of the transmission / reception channel with the effect control board 80 in the effect symbol command control processing in step S30. The prize ball shortage error command is output to the transmission data register 511, and the prize ball shortage error command is transmitted to the production control microcomputer 100. Note that once the prize ball error flag is set, it is maintained without being cleared until the power supply to the gaming machine is turned on again after the power supply to the gaming machine is stopped. In this embodiment, regarding the communication between the game control microcomputer 560 and the effect control microcomputer 100, a command is transmitted from the game control microcomputer 560 to the effect control microcomputer 100. Only, not the other way around. Therefore, the game control microcomputer 560 may be equipped with a transmission-only serial communication circuit for communication with the effect control microcomputer 100.

  In this embodiment, based on the reception of a prize ball shortage error command or a prize ball excess error command described later, the effect control microcomputer 100 performs an error notification of prize ball shortage or prize ball excess. (Refer to Steps S625 to S628) However, the error notification of insufficient prize balls or excessive prize balls may be recovered when a predetermined period has elapsed from the start of notification. Further, for example, when the value of the prize ball number counter returns to a range of a predetermined prize ball shortage determination value (for example, 501) or a predetermined prize ball excess determination value (for example, 0), the prize ball shortage or the prize ball is excessive. It is also possible to recover from the error notification.

  In this embodiment, the case where the prize ball number is added to the prize ball number counter at the timing at which the prize ball number command is transmitted in step S52308 is shown. For example, the number of prize balls may be subtracted instead of the one shown in the embodiment. In this case, for example, in the process of step S5311 to be described later, on the contrary, 10 may be added to the value of the winning ball counter based on the input of winning ball information. In the process of step S52309, if the value of the prize ball number counter is less than 0, it is determined that there is a prize ball shortage error. What is necessary is just to determine with an excess error.

  In step S52313, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if no winning ball has been stored and no new winning has occurred by the time one second has elapsed after receiving the connection OK command), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52314), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52315).

  FIG. 67 is a flowchart showing the winning ball reception confirmation process (step S524) executed when the value of the winning ball process code is 3. In the winning ball receipt confirmation process, the CPU 56 first confirms whether there is data in the reception data register of the serial communication circuit 511 (step S52401). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 511 (see FIG. 33). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52409.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether or not an error has occurred in the serial communication circuit 511 (step S52402). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 511 is set (see FIG. 33). If an error has occurred, the process proceeds to step S52409.

  If no error has occurred in the serial communication circuit 511, the CPU 56 reads the command from the reception data register of the serial communication circuit 511, and confirms whether or not the received command is a prize ball number acceptance command (step S52403). . If the winning ball number reception command has been received, the CPU 56 subtracts 1 from the value of the winning ball command output counter corresponding to the winning ball number set by the transmitted winning ball number command (step S52404). In addition, the CPU 56 sets a value “4” indicating a prize ball end confirmation process in the prize ball process code (step S52405), and proceeds to step S52408.

  If the received command is not a prize ball number acceptance command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52406). If it is not a prize ball preparation command, the process advances to step S52409.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 50) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52407). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52408). In addition, after receiving the prize ball preparation command based on the connection confirmation time 2 set in step S52408, neither the prize ball number acceptance command nor the next prize ball preparation command can be received after 10 seconds. If it is, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52408 is measured in the processing of steps S52409 and S52411 described later, and 10 seconds are received without receiving a prize ball number acceptance command or a next prize ball preparation command. If time elapses and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  In step S52409, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, if no prize ball number acceptance command or prize ball preparation command is received after 10 seconds have passed since the prize ball number command was transmitted), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52410), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52411).

  FIG. 68 is a flowchart showing the winning ball end confirmation process (step S525) executed when the value of the winning ball process code is 4. In the winning ball end confirmation process, the CPU 56 first confirms whether or not there is data in the reception data register of the serial communication circuit 511 (step S52501). Specifically, the CPU 56 may confirm the value of bit 5 of the status register A of the serial communication circuit 511 (see FIG. 33). If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52509.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether or not an error has occurred in the serial communication circuit 511 (step S52502). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register A of the serial communication circuit 511 is set (see FIG. 33). If an error has occurred, the process proceeds to step S52509.

  If no error has occurred in the serial communication circuit 511, the CPU 56 reads a command from the reception data register of the serial communication circuit 511, and checks whether the received command is a prize ball end command (step S52503). If the winning ball end command has been received, the CPU 56 sets a value “2” indicating the winning ball transmission process 2 in the winning ball process code (step S52504), and the connection check time 1 (for example, 1) is set in the winning ball process timer. Second) is set (step S52505). It should be noted that, based on the connection confirmation time 1 set in step S52505, the control for transmitting the connection confirmation command when the start winning prize does not occur even after one second has elapsed after receiving the winning ball end command. Return to. Specifically, the prize ball process timer set in step S52505 is measured by the processing in steps S52313 and S52315, and one second has elapsed without sending a prize ball number command without generating a new start prize. If time-out occurs and it is determined as Y in step S52313, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  Since the process of step S52504 is executed, when a prize ball end command is received, the process first proceeds to prize ball transmission process 2. Therefore, when the number of prize balls is stored, the next is immediately performed. Control is performed so that a winning ball number command is transmitted. On the other hand, after the transition to the prize ball transmission process 2, there is no memorization of the number of prize balls, and a new prize is generated until the connection confirmation time 1 (for example, 1 second) set in step S52505 has elapsed. If not, the process further proceeds to a prize ball transmission process 1, and the process of repeatedly transmitting the connection confirmation command is resumed.

  If the received command is not a prize ball end command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52506). If it is not a prize ball preparation command, the process advances to step S52509.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 50) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52507). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52508). In addition, after receiving the winning ball preparation command based on the connection confirmation time 2 set in step S52508, neither the winning ball end command nor the next winning ball preparation command could be received after 10 seconds. In this case, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52508 is measured in the process of step S52511 described later, and 10 seconds have elapsed without receiving a prize ball end command or a next prize ball preparation command. If time-out occurs and it is determined as Y in step S52509, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52510 and S5211).

  In step S52509, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, the prize ball end command or the prize ball preparation command cannot be received even after 10 seconds have passed since the prize ball number acceptance command or prize ball preparation command is received) In this case, the CPU 56 sets a value “0” indicating the prize ball transmission process 1 in the prize ball process code (step S52510), and ends the process. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52511).

  FIG. 69 is a flowchart showing the prize ball counter subtraction process in step S503. In the prize ball counter subtraction process, the CPU 56 first checks whether or not the prize ball information input invalid timer has timed out (step S5301). The prize ball information input invalid timer is a timer that is measured in order to provide an interval period after confirming the input of prize ball information until confirming the input of the next prize ball information. If not timed out, the CPU 56 subtracts 1 from the value of the prize ball information input invalid timer (step S5302) and ends the process.

  If the prize ball information input invalid timer has timed out, the CPU 56 inputs the contents of the input port 0 (step S5303), and checks whether or not the bit of the prize ball information is on (step S5304). If the bit of the prize ball information is on, the process proceeds to step S5305.

  In step S5305, the CPU 56 sets a predetermined prize ball information confirmation count (for example, 8) as the number of processes (step S5305). Then, the CPU 56 confirms whether or not the prize ball information is input, and if the input of the prize ball information can be confirmed, the CPU 56 adds the value of the prize ball information on counter to 1 and the number of processes (8 in this example). The process is repeated until the process is completed (steps S5306 to S5308).

  Next, the CPU 56 checks whether or not the value of the prize ball information on counter is 6 or more (step S5309). If the value of the prize ball information on counter is 6 or more, the CPU 56 sets a predetermined time (for example, 0.8 seconds) in the prize ball information input invalid timer (step S5310) and sets the value of the prize ball number counter to 10 Subtraction is performed (step S5311).

  By executing the above processing, in this embodiment, it is determined that the prize ball information has been inputted on the condition that the prize ball information has been inputted 6 times or more out of the 8 confirmation processes, and 10 pieces of prize ball information are entered. The value of the prize ball number counter is decremented by 10 assuming that the prize ball has been paid out. By such processing, in this embodiment, the situation where it is determined that the prize ball information is erroneously input is reduced, and the game control microcomputer 560 side cannot properly grasp the number of prize balls that have not been paid out. It is preventing.

  Next, the CPU 56 checks whether or not the count value after subtraction is less than a predetermined prize ball excess determination value (for example, 0) (step S5312). When the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), the CPU 56 checks whether or not the prize ball error flag is already set (step S5313). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets the prize ball error flag (step S5314) and controls to send a prize ball excess error command to the effect control microcomputer 100 (step S5315). Specifically, the CPU 56 performs a process of setting the address of the winning ball excessive error command transmission table as a pointer. Then, based on the fact that the address of the winning ball excess error command transmission table is set in the pointer in step S5315, in the effect symbol command control process in step S30, the serial communication circuit of the transmission / reception channel with the effect control board 80 is performed. A prize ball excess error command is output to the transmission data register 511, and the prize ball excess error command is transmitted to the production control microcomputer 100.

  Next, the frame state output process (step S39) will be described. FIG. 70 is a flowchart illustrating an example of the frame state output process in step S39. In the frame state output process, the CPU 56 first loads the contents of the frame state display buffer (step S391). Next, the CPU 56 inputs the contents of the input port 1 (step S392) and logically ANDs the input contents of the input port 1 with a predetermined door opening signal confirmation mask value (specifically, 10000000). (Step S393). Further, the CPU 56 calculates the logical product of the operation result obtained by the logical product and the contents of the frame state display buffer loaded in step S391 (step S394). By executing the above processing, a calculation result is obtained in which the door opening signal input state is further added to the contents of the frame state display buffer.

  Next, the CPU 56 compares the calculation result with the contents of the previous frame state display buffer (step S395). The previous frame state display buffer stores the calculation result of step S394 calculated when the frame state output processing is executed by the previous timer interrupt. When the calculation result is different from the content of the previous frame state display buffer (Y in step S396), the CPU 56 stores the calculation result calculated in step S394 in the previous frame state display buffer and updates the previous frame state display buffer. Along with (Step S397), the calculation result calculated in Step S394 is set as it is as EXT data of the frame state display command, and control is performed to transmit the frame state display command to the effect control microcomputer 100 (Step S398). Specifically, the CPU 56 performs processing for setting the address of the frame state display command transmission table in the pointer. Then, based on the fact that the address of the frame state display command transmission table is set in the pointer in step S398, in the effect symbol command control processing in step S30, the serial communication circuit 511 of the channel for transmission and reception with the effect control board 80 is performed. The frame state display command is output to the transmission data register, and the frame state display command is transmitted to the production control microcomputer 100.

  FIG. 71 is an explanatory diagram of a specific example of EXT data set in the frame state display command. As shown in FIG. 71, a prize ball error (abnormal state in which a prize ball payout operation based on a winning or a ball lending payout operation based on a ball lending request cannot be normally performed: If a control unconnected error, payout switch error detection error 1, payout switch error detection error 2, payout case error, main control communication error) is detected, the first bit (bit 0) winning ball error bit Is set to “1”. When a full tank error is detected, “1” is set in the second tank (bit 1) full tank error bit. When a ball break error is detected, “1” is set to the third bit (bit 2) ball break error bit. If a payout quantity abnormality error is detected when the cumulative value of the number of prize balls or rental balls to be paid, which will be described later, reaches a predetermined value (for example, 2000), the fourth bit (bit) “1” is set in the payout number error error bit of 3). When it is detected that the glass door frame 2 is in the open state, “1” is set in the door opening abnormality error bit of the eighth bit (bit 7).

  Note that information indicating that the mechanism plate is detected to be in the open state may also be set in the frame state display command and transmitted. In this case, for example, when it is detected in FIG. 71 that the mechanism plate is in the open state, “1” is set to the mechanism plate open error error bit of the seventh bit (bit 6). May be.

  By executing the above processing, the error information set by the connection OK command or the winning ball preparation command from the payout control microcomputer 560 (the payout number error error, the ball running out error, the full tank error, the winning ball error) And the door open signal input state are set in the frame state display command and transmitted to the effect control microcomputer 100.

  Next, the special symbol process (step S28) in the main process will be described. FIG. 72 is a flowchart showing an example of a special symbol process processing program executed by the CPU 56 of the game control microcomputer 560. The CPU 56 of the game control microcomputer 560 has the start opening switch 14a for detecting that the game ball has won the start winning opening 14 provided in the game board 6 being turned on, that is, the game ball is starting start winning. If a winning is received at the opening 14 and the winning detection signal SS is input from the start opening switch 14a (step S311), after the start opening switch passing process (step S312) is performed, the processing of steps S300 to S306 is performed according to the internal state. Do one of these processes.

  Special symbol normal processing (step S300): A state where variable symbol special display can be started (for example, the symbol variation has not been made in the special symbol display 8, and the previous symbol variation in the special symbol display 8 has ended) Waits for a predetermined period of time to elapse, and not a big hit game). When the special symbol variable display can be started, the start winning memory number for the special symbol is confirmed. If the number of start winning prizes is not 0, it is determined whether or not the result of variable symbol special display is a big hit based on the random R generated by the random number circuit 509 stored in the special figure holding memory. Further, when it is determined to be a big hit, control for transmitting a display result designation command capable of specifying the determined display result to the microcomputer 100 for effect control is further determined, such as whether or not to make a probable big hit. I do. Then, the internal state (special symbol process flag) is updated so as to shift to step S301.

  Fluctuation time setting process (step S301): A variation pattern is determined, and the variation time in the variation pattern (variable display time: time from the start of variable display until the display result is derived and displayed (stop display)) is a special symbol. It is determined to be a variable display variable time. In addition, control is performed to transmit a variation pattern command specifying the determined variation pattern to the effect control microcomputer 100, and a variation time timer for measuring the variation time of the determined special symbol is started. Then, the internal state (special symbol process flag) is updated so as to shift to step S302.

  Special symbol variation processing (step S302): When a predetermined time (the time indicated by the variation time timer in step S301) elapses, the internal state (special symbol process flag) is updated to shift to step S303.

  Special symbol stop process (step S303): An effect symbol stop command for instructing stop of the effect symbol is transmitted to the effect control board 80. Moreover, the special symbol in the special symbol display 8 is stopped. If the stop symbol of the special symbol is a jackpot symbol, the internal state (special symbol process flag) is updated to shift to step S304. If not, the internal state is updated to shift to step S300. In addition, it is good also as a structure which does not transmit an effect design stop command. In this case, the effect control board 80 sets the change time to the change time timer based on the change pattern command received from the main board 31 and updates the change time timer to uniquely change the change time of the effect symbol. Monitoring, and when it is determined that the fluctuation time has elapsed, a process of stopping the effect design may be performed.

  Preliminary winning opening opening process (step S304): Control for opening the large winning opening is started. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the grand prize opening) and a flag (a flag used when detecting winning in the prize opening) are initialized, and the solenoid 21 is driven. Open the big prize opening. Also, the process timer sets the execution time of the big prize opening opening process and sets the big hit flag. Then, the internal state (special symbol process flag) is updated so as to shift to step S305.

  Processing for opening a special prize opening (step S305): Control for sending a presentation control command for round display of the special prize opening to the production control board 80 and closing conditions for the special prize opening (for example, a predetermined number (for example, ten) for the special prize opening ) To confirm that the game ball has won a prize). When the closing condition for the big prize opening is satisfied, if there are still rounds, the internal state is updated to shift to step S304. When all the rounds have been completed, the internal state is updated to shift to step S306.

  Big hit end processing (step S306): Control for causing the effect control means to perform display control for notifying the player that the big hit gaming state has ended. Then, the internal state is updated so as to shift to step S300.

  FIG. 73 is a flowchart showing the start port switch passing process (step S312). In the start-port switch passing process, the CPU 56 of the game control microcomputer 560 sets the start-winning memory number indicated by the start-winning memory counter (or the start-winning memory number stored in the special figure holding memory) to 4 which is the maximum value. It is confirmed whether it has reached (step S321). If the start winning memorized number has not reached 4, the CPU 56 specifies a random value register from which numerical data to be a big hit determination random number (random R) is read (step S322A). In this embodiment, the CPU 56 specifies the random number value register R1D as a numerical data reading source.

  For example, in the case where the gaming machine has two start winning openings, when the game ball passes (enters) one start winning opening, the random value register R1D is specified as the reading source of the numerical data. When the game ball passes (enters) the other start winning opening, the random value register R2D may be specified as the reading source of the numerical data.

  Next, the CPU 56 extracts numerical data from the specified random number value register of the random number circuit 509 and also extracts values from a counter for generating software random numbers (step S322B), and sets them to the value of the start winning memory number. The data is stored in the corresponding storage area (special symbol determination buffer (special symbol holding memory)) (step S323).

  In step S322B, numerical data is read and extracted from the random value register 559A as the random value register R1D included in the random number circuit 509 based on the fact that the random value register R1D has been identified as the read source in the process of step S322A. In this case, the random number latch flag corresponding to the random number value register R1D from which the numerical data has been read is turned off. That is, when the random value register R1D is specified as the reading source in the process of step S322A, the bit value of the random number latch flag data RDFM0 is updated from “1” to “0” by reading the numerical data by the process of step S322B. The random number latch flag associated with the random value register R1D is turned off.

  The numerical data read from the random value register R1D may be stored as it is in the special figure reservation memory as a big hit determination random number (random R), or may be stored after a predetermined processing. May be. As an example, the numerical data extracted from the random number circuit 509 is temporarily stored in a 16-bit general-purpose register included in the CPU 56. Subsequently, a refresh register value that is a stored value of a refresh register built in the CPU 56 is read as numerical data that becomes a random number value for processing. In this case, the refresh register value may be added to the upper byte in the general-purpose register, while the lower byte may be left as it is. Here, instead of adding the refresh register value, predetermined arithmetic processing such as subtraction, logical sum, and logical product may be executed. Alternatively, the refresh register value may be added to the lower byte in the general-purpose register. Also, the upper byte and lower byte of the numerical data extracted from the random number circuit 509 may be exchanged and stored as the upper byte or lower byte in the general-purpose register. Furthermore, after the refresh register value is added to the high-order byte or low-order byte in the general-purpose register, or without performing arithmetic processing such as addition to the high-order byte or low-order byte in the general-purpose register, the high-order byte and the low-order byte are switched. It may be. Of the upper byte and lower byte of the numerical data extracted from the random number circuit 509, the data of a specific bit may be replaced with the data of other bits. In this case, for example, in the bus connecting the random number value register R1D in the random number circuit 509 and the upper byte or lower byte of the general-purpose register, the wiring is crossed so that the data of a specific bit is replaced with the data of another bit. You can do it. Thereafter, the CPU 56 performs an AND operation on the stored value of the general-purpose register and a predetermined logical value (for example, “FFFFH”), or outputs the stored value of the general-purpose register as it is and stores it in a predetermined area of the RAM 55. Thus, numerical data indicating the 16-bit random value MR1 may be set. For example, when setting numerical data indicating a 14-bit random number value, a 14-bit value can be acquired by performing an AND operation on the stored value of the general-purpose register and “7F7FH”. . Further, a logical sum operation may be executed instead of the logical product operation.

  Further, numerical data indicating a random value for determining the addition value may be set based on the stored value of the general-purpose register. As an example, when the numerical data indicating the random value for determining the addition value takes a value in the range of “0” to “7”, the stored value of the general-purpose register and “C0C0H” or the like are ANDed. Numerical data indicating a 4-bit random value may be set by storing it in a predetermined area of the RAM 55 or the like.

  In this embodiment, a case is shown in which numerical data is read from the random value register R1D among the random value registers provided in the random number circuit 509 and used as a big hit determination random number (random R). For example, numerical data may be read from the random value register R2D and used as a jackpot determination random number (random R). Further, for example, numerical data may be read alternately from the random value register R1D and the random value register R2D and used as a big hit determination random number (random R).

  Next, the CPU 56 sets the value of the random R stored in the predetermined buffer area to the head of the empty entry in the special figure reservation memory (step S324), and adds 1 to the count number of the start prize counter so that the start prize storage number is increased. Is increased by 1 (step S325).

  Note that if the start prize is stored in step S321 but the maximum value of 4 is reached, the CPU 56 clears the random number latch flag by reading the random value register (step S326), and then performs the start port switch passing process. finish. In the process of step S326, the numerical data stored in the random value register R1D is read in correspondence with the case where the game ball has passed (entered) the start winning opening 14.

  Next, the special symbol normal process (step S300) in the special symbol process will be described. FIG. 74 is a flowchart showing special symbol normal processing. In the special symbol normal process, the CPU 56 of the game control microcomputer 560 can start the variation of the special symbol (for example, when the value of the special symbol process flag is a value indicating step S300). (Step S380), the random R value stored in correspondence with the hold number “1” is read from the special figure hold memory (step S381). In this case, the CPU 56 subtracts 1 from the count number of the start winning counter, thereby reducing the number of reserved memories by 1 and assigns to the second to fourth entries (holding numbers “2” to “4”) of the special figure reservation memory. The stored random R value is shifted up by one entry (step S382).

  Further, the CPU 56 checks whether or not the probability variation flag is set (step S383). That is, the CPU 56 confirms whether or not the gaming state is controlled to the certain change state. When the probability variation flag is not set, the CPU 56 determines that the gaming state is a normal state other than the probability variation state, and is a table used to determine whether or not the display result of the special symbol display 8 is a jackpot symbol. The normal big hit determination table 571a (see FIG. 37A) is set (step S384). Further, when the probability change flag is set, the CPU 56 determines that the gaming state is a probability change state, and as a table used to determine whether or not the display result of the special symbol display 8 is a jackpot symbol. A probability change big hit determination table 571b (see FIG. 37B) is set (step S385).

  The CPU 56 determines whether or not the display result of the special symbol display 8 is a big hit symbol based on the random R value stored in the predetermined buffer area in the start port switch passing process (step S386). In this case, the CPU 56 uses the normal-time big hit determination table 571a set in step S384 or the probability change big hit determination table 571b set in step S385 to determine whether or not to win.

  If it is determined that the display result of the special symbol display 8 is a jackpot symbol, the CPU 56 turns on a jackpot flag indicating that it is a jackpot state (step S387). If it is determined that the display result of the special symbol display 8 is not a big hit symbol, the CPU 56 turns off the big hit flag (step S388). Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the variation time setting process (step S389).

  Although omitted in FIG. 74, in the special symbol normal process, if it is determined that the display result of the special symbol display 8 is to be a big hit symbol (to make a big hit), the CPU 56 Based on the type determination random number, a big hit type (for example, a probable big hit, a normal big hit, or a sudden probable big hit) is also determined. Then, the CPU 56 sets a value corresponding to the result of the jackpot determination or the determination result of the jackpot type in the jackpot symbol determination buffer formed in the RAM 55. For example, “1” is set for a normal big hit, “2” is set for a probable big hit, and “3” is set for a sudden probable big hit. Further, the CPU 56 performs control to transmit a display result designation command capable of specifying the determined display result to the effect control microcomputer 100.

  Next, the switch process (step S21) in the timer interrupt process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch is surely turned on, and processing corresponding to the switch on is started. FIG. 75 is an explanatory diagram showing each 2-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer for storing the contents of the ports 0 and 1 input this time. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected. The previous port buffer, port buffer, and switch-on buffer shown in FIG. 75 are prepared for each of the input ports 0 and 1. For example, in this embodiment, two switch-on buffers 1 and 2 are prepared, the switch state of the input port 0 is set to the switch-on buffer 1, and the switch state of the input port 1 is the switch-on buffer 2. Set to

  FIG. 76 is a flowchart showing a processing example of the switch processing in step S21 in the game control processing. In the switch process, the game control microcomputer 560 first inputs data input to the input ports 0 and 1 (see FIG. 39) (step S101), and sets the input data in the port buffer (step S102). ).

  Next, the initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the wait counter reaches 0, the data of the input ports 0 and 1 are input again (step S106), and a logical product is obtained for each bit between the input data and the data set in the port buffer. (Step S107). Then, the logical product operation result is set in the port buffer (step S108). Of the two input data input from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time of steps S104, S105)] by the processing of steps S103 to S108, both “ Only the bits that are “1” will be “1” in the port buffer. In other words, if the ON state of the switch detection signal continues for a predetermined period [initial value of wait counter × (processing time of steps S104 and S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the game control microcomputer 560 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”. The game control microcomputer 560 further performs a logical product for each bit between the exclusive OR operation result and the data set in the port buffer (step S110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  Then, the game control microcomputer 560 sets the logical product calculation result in step S110 in the switch-on buffer (step S111), and sets the contents of the port buffer in which the calculation result in step S108 is set in the previous port buffer. (Step S112).

  By the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer.

  Next, the operation of the payout control means (the payout control microcomputer 370) will be described. FIG. 77 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 77, each phase signal supplied to the payout motor 289 by the stepping motor is output from the output port 0. In addition, a PRDY signal or an EXS signal is output from the output port 0 to the card unit 50, and a game indicating that the gaming machine is in an error state (in this example, a ball-out error state or a full tank error state). A machine error state signal and a prize ball signal 1 indicating that a prize ball payout has been detected are also output. Further, from the output port 1, each segment output signal of the error display LED 374 by 7 segment LED is output. The output port 1 also outputs prize ball information indicating that ten prize ball payouts have been detected.

  FIG. 78 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 78, the VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 0 to 2 of the input port 0, respectively. A connection signal from the main board 31 is input to bit 4 of the input port 0. In addition, the detection signal of the full switch 48, the detection signal of the ball break switch 187, and the detection signal of the payout motor position sensor 295 are input to the bits 5 to 7 of the input port 0, respectively. In addition, the operation signal from the error release switch 375 and the detection signal of the payout number count switch 301 are input to the bits 0 and 1 of the input port 1, respectively. Further, the mechanism plate opening signal from the mechanism plate opening sensor 155B is input to the bit 7 of the input port 1.

  Next, the operation of the payout control means will be described. FIG. 79 is a flowchart showing a main process executed by the payout control means. In the main process, the payout control CPU 371 of the payout control microcomputer 370 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703).

  Next, the payout control CPU 371 sets a built-in device register (step S704). In the process of setting the internal device register in step S704, the payout control CPU 371 sets the CTC. In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore, the payout control CPU 371 performs register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and register setting for setting an interrupt vector. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 1 ms, a value corresponding to 1 ms is set as an initial value in a predetermined register (time constant register).

  In step S704, the payout control CPU 371 initializes the priority of interrupt processing to be executed in response to the interrupt request from the serial communication circuit 380. In this case, in this case, the payout control CPU 371 initializes the priority order of the interrupt process according to the same process as the priority order initial setting process (see step S15b) performed by the CPU 56 of the game control microcomputer 560.

  In step S <b> 704, the payout control CPU 371 sets the serial communication circuit 380. In this case, the payout control CPU 371 sets the baud rate of the receiving circuit, sets the receiving mode (either 8-bit or 9-bit data format), and sets the parity (the presence or absence of parity, even parity or odd parity). Set). In addition, the control registers of the receiving circuit are initialized and the status registers are initialized. Also, the payout control CPU 371 sets the baud rate of the transmission circuit, sets the transmission mode (either 8-bit or 9-bit data format), and sets the parity (the presence / absence of parity, even parity or odd parity) )I do. Also, each control register of the transmission circuit is initialized.

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. The timer interruption process includes a payout control process for controlling the payout means (including a process for driving the ball payout device 97 at least in response to a command signal relating to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control microcomputer 370. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC. The interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. .

  Next, the payout control CPU 371 sets the RAM in an accessible state (step S705), and performs a RAM clear process (step S706). In addition, initial values are set in the flags and counters of the RAM area (step S707). Note that the processing in step S707 includes processing for setting the unpaid-off number counter initial value in the unpaid-out number counter. In the process of step S707, the payout control CPU 371 also performs a process of clearing an error flag indicating a detection state of a payout number abnormality error, a full tank error, and a ball breakage error. In this embodiment, when it is determined that there is a payout number error and the payout number error error specification bit is set in the error flag, the payout number error error specification bit is not cleared until the power is reset. Although it does not recover from the number abnormality error, specifically, when the process of step S707 is executed when the power is turned on, the payout number abnormality error designation bit in the error flag is cleared and the payout number abnormality error is recovered.

  The payout control CPU 371 executes serial communication circuit setting processing for initial setting of the serial communication circuit 380 (step S708). In this case, the payout control CPU 371 causes the serial communication circuit 380 to serially communicate with the game control microcomputer 560 according to the same process as the serial communication circuit setting process (see step S15a) performed by the CPU 56 of the game control microcomputer 560. Make settings for Further, as described above, a part of the initial setting of the serial communication circuit 380 is executed in the built-in device register setting process in step S704. Note that all the setting processing of the serial communication circuit 380 may be performed by the serial communication circuit setting processing in step S708.

  Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S709). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control microcomputer 370 is set so as to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 of the payout control microcomputer 370 executes a timer interrupt process.

  FIG. 80 is a flowchart showing an example of timer interrupt processing executed by the payout control means. In the timer interrupt process, the payout control CPU 371 of the payout control microcomputer 370 executes the following process. First, the payout control CPU 371 performs a switch check process (step S751). In the switch check process, the payout control CPU 371 performs a process of confirming the on / off state of the payout number count switch 301 and the error release switch 375 based on the input of the input port 1. Next, the payout control CPU 371 performs an input determination process (step S752). The input determination process is a process for detecting the state of bits 0 to 7 (see FIG. 78) of the input port 0 and reflecting the detection result in a predetermined 1 byte of the RAM (referred to as a sensor input state flag). The payout control CPU 371 checks the state of the sensor input state flag instead of directly checking the state of the input port when performing control based on the state of bits 0 to 7 of the input port 0.

  Next, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S753). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S754). Next, the payout control CPU 371 performs control for paying out the lent balls in response to a ball lending request from the card unit 50, and performs control for paying out the number of prize balls indicated by the prize ball number command from the main board 31. A payout control process to be executed is executed (step S755).

  Next, the payout control CPU 371 executes a payout motor control process (step S756). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Next, the payout control CPU 371 executes error processing for detecting various errors (step S757). Next, the payout control CPU 371 executes a prepaid card unit error control process for performing error control of the card unit 50 (step S758). Next, the payout control CPU 371 executes information output processing for outputting prize ball information to the main board 31 and outputting the prize ball signal 1 and the gaming machine error state signal to the outside (step S759). Further, display control processing for performing a predetermined display on the error display LED 374 according to the result of the error processing is executed (step S760).

  In the present embodiment, when various errors (for example, a payout number error error, a full tank error, a ball shortage error, a prepaid card unit unconnected error) are detected in error processing to be described later, an error corresponding to the detected error is detected. Bit is set. Then, in the display control process of step S760, the payout control CPU 371 performs a predetermined display on the error display LED 374 based on the fact that the error bit is set.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer) corresponding to the output state of the output port is provided. However, the payout control CPU 371 includes an output port 0 buffer and an output port. The contents of the port 1 buffer are output to the output port (step S761: output processing). The output port 0 buffer and the output port 1 buffer include a payout motor control process (step S756), a prepaid card control process (step S753), a main control communication process (step S754), an information output process (step S759), and a display control process ( It is updated in step S760).

  FIG. 81 is a flowchart showing the main control communication process in step S754. In the main control communication process, the payout control microcomputer 370 (specifically, the payout control CPU 371) executes a main control command reception process (step S740). Then, the payout control CPU 371 executes one of steps S741 to S744 according to the value of the main control communication control code.

  FIG. 82 is a flowchart showing the main control command reception process of step S740 in the main control communication process. In the main control command receiving process, the payout control CPU 371 first checks whether or not a connection signal is input (step S74001). If no connection signal is input, the payout control CPU 101 initializes the transmission circuit and the reception circuit of the serial communication circuit 380 (step S74002). As described above, when the connection signal cannot be received, the transmission circuit and the reception circuit of the serial communication circuit 380 are initialized, so that the command is transmitted even though the connection state with the main board 31 is abnormal. It is possible to prevent a situation in which data is stored in the register or the reception data register. Next, the payout control CPU 371 loads the value of the main control communication control code (step S74003), and checks whether the value of the main control communication control code is a value “0” indicating the main control connection confirmation processing. (Step S74004).

  In this embodiment, in the main control communication process, input of a connection signal from the game control microcomputer 560 is started after power supply to the gaming machine is started, and reception of the first connection confirmation command can be confirmed. The main control connection confirmation process in step S741 is executed. Then, when the reception of the connection confirmation command can be confirmed, the process proceeds to step S742 and subsequent steps, and transmission / reception processing of various payout control commands is executed. Thereafter, if the communication state with the game control microcomputer 560 is maintained normally, one of the processes of steps S742 to S744 is executed, and the main control connection confirmation process of step S741 is basically a game. It will be executed only when the machine is powered on. In step S74004, the fact that the value of the main control communication control code indicates a value other than the main control connection confirmation processing means that after shifting to the processing after step S742, some communication error occurs and the connection signal cannot be input. This is the case. Therefore, if the value of the main control communication control code indicates a value other than the main control connection confirmation process in step S74004, the payout control CPU 371 determines the main control communication error designation bit (game control microcomputer) of the error flag. A bit indicating that an abnormality has occurred in the communication state with 560) is set (step S74005). The error flag is a flag in which various prize ball errors are set, and is formed in a RAM provided in the payout control microcomputer 370. The payout control CPU 371 sets a value “0” indicating main control connection confirmation processing in the main control communication control code (step S74006). If the value of the main control communication control code is “0” indicating the main control connection confirmation process in step S74004, the process proceeds to step S74006).

  Note that the main control confirmation process in step S741 may be executed exceptionally even after the power is turned on to the gaming machine. Specifically, as described above, after determining that the connection signal is not input in step S74001, if the main control connection confirmation process is not being executed in step S74004, the connection signal is not displayed after the game machine is turned on. It is determined that there is a possibility of being disconnected, and the process returns to the main control connection confirmation process (see step S74006), and again confirms the connection state with the game control microcomputer 560 (specifically, a connection confirmation command is issued). Confirm that it can be received (see step S7412). Further, in the main control communication normal processing described later, even if a predetermined period (1050 ms in this example) has elapsed since the connection OK command was transmitted, the connection confirmation command and the prize ball number command are received from the game control microcomputer 560. If not, it is determined that some communication abnormality has occurred, and the process returns to the main control connection confirmation process (see steps S74202 and S74203), and the connection state with the game control microcomputer 560 is confirmed again (specifically, Confirm that the connection confirmation command can be received (see step S7412).

  If the connection signal is input, the payout control CPU 371 checks whether or not the reception error flag is set in the status register of the serial communication circuit 380 (step S74007). For example, if a flag indicating a parity error, a framing error, a noise error, an overrun error, or an idle line error is set in the status register of the serial communication circuit 380, the payout control CPU 371 receives a reception error of the serial communication circuit 380. It is determined that it is in a state.

  If the reception error flag is set, the payout control CPU 371 initializes the reception circuit of the serial communication circuit 380 (step S74008). In this way, by initializing the receiving circuit of the serial communication circuit 380 in the case of a reception error state, it is possible to prevent a situation in which a reception command is stored in the reception data register even though some reception abnormality has occurred. can do. Then, the payout control CPU 371 sets the main control communication error designation bit of the error flag (step S74009).

  If the reception error flag is not set, the payout control CPU 371 loads the contents of the reception buffer (step S74010) and checks whether or not a connection confirmation command is received (step S74011). Specifically, the payout control CPU 371 checks whether or not the content of the loaded reception buffer is “A0 (H)” (see FIG. 49). If the connection confirmation command has been received, the payout control CPU 371 proceeds to step S74014.

  If a connection confirmation command has not been received, the payout control CPU 371 checks whether or not a prize ball number command has been received. In this embodiment, as shown in FIG. 49, the contents of the connection number command should be at least “51 (H)” and less than “60 (H)”. Accordingly, the payout control CPU 371 first checks whether or not the content of the loaded reception buffer is equal to or greater than the minimum prize ball number command value “51 (H)” (step S74012). Next, if the prize ball number command minimum judgment value is “51 (H)” or more, the payout control CPU 371 determines whether the content of the loaded reception buffer is less than the prize ball number command maximum judgment value “60 (H)”. It is confirmed whether or not (step S74013). If it is less than the winning ball number command maximum determination value “60 (H)”, the payout control CPU 371 determines that a winning ball number command has been received, and proceeds to step S74014.

  In step S74014, the payout control CPU 371 stores the contents of the reception buffer (connection confirmation command, prize ball number command) in the main control communication reception buffer. The main control communication reception buffer is composed of 1 byte and can store only one reception command at a time. Even with this configuration, in this embodiment, the timer interrupt period (1 ms in this example) in the payout control microcomputer 370 is equal to the timer interrupt period (in this example, the game control microcomputer 560). 4 ms), a situation in which a plurality of payout control commands are received within one timer interrupt does not occur, and there is no inconvenience. In addition, even if the award ball number command is received before receiving the first connection confirmation command due to erroneous processing after turning on the power to the gaming machine, the connection confirmation command is subsequently issued. If it is received, it is overwritten and stored in the main control communication reception buffer. Therefore, there is a situation in which the connection confirmation command cannot be confirmed at all in the main control connection confirmation process (step S741) described later, and it becomes impossible to shift to the main control communication normal process. Can be prevented.

  FIG. 83 is a flowchart showing main control connection confirmation processing (step S741) executed when the value of the main control communication control code is zero. In the main control connection confirmation process, the payout control CPU 371 loads the contents of the main control communication reception buffer (step S7411), and confirms whether or not a connection confirmation command is received (step S7412). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S7413) and executes main control transmission command conversion processing (step S7414). In the main control transmission command conversion process in step S7414, a process of setting a control state (an error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S7415). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when transmitting the connection OK command in step S7415. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S7416). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S7417).

  84 and 85 are flowcharts showing main control communication normal processing (step S742) executed when the value of the main control communication control code is 1. In the main control communication normal process, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74201), and checks whether the main control communication control timer has timed out (step S74202).

  In this embodiment, as described above, every time one second elapses after the connection OK command is received from the payout control microcomputer 370, the next connection confirmation command is transmitted from the game control microcomputer 560. Therefore, if the main control communication control timer has timed out in step S74202, it means that the next connection confirmation command is issued even if 1050 ms (see steps S7417 and S74209) elapses more than 1 second after the transmission of the connection OK command. This is a case where reception was not possible. Therefore, the payout control CPU 371 sets a value “0” indicating the main control connection confirmation process in the main control communication control code (step S74203), returns to the main control connection confirmation process, and waits for the recovery of the communication state. To do.

  If the main control communication control timer has timed out in step S74202, the payout control CPU 371 clears the main control communication reception buffer. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not a reception command is stored in the main control communication reception buffer (step S74204). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74205). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74206) and executes main control transmission command conversion processing (step S74207). In the main control transmission command conversion process in step S74207, a process for setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74208). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when the connection OK command is transmitted in step S74208. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74209).

  If the command received in step S74205 is not a connection confirmation command, it means that a prize ball number command has been received. In this case, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74210). If the value of the error flag is not 0 (that is, if it is an error state and any error bit is set), the process proceeds to step S74219. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74211). If the BRDY signal is input, the process proceeds to step S74219.

  If no BRDY signal is input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74212), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74213). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is being performed, the process proceeds to step S74219. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74213, it is not determined that the prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, the winning ball payout operation based on the received winning ball number command can be started immediately. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication reception buffer (that is, the number of winning balls set in the winning ball number command) in the unpaid-out number counter (step S74214). The unpaid-out number counter is a counter for counting the number of unpaid out prize balls and rental balls.

  Next, the payout control CPU 371 performs control to transmit a prize ball number acceptance command to the game control microcomputer 560 (step S74215). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits a prize ball number acceptance command in step S74215. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74216). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74218). It should be noted that if a prize ball payout operation is not completed after one second has elapsed after the prize ball number acceptance command is transmitted based on the value set in step S74218, a prize ball preparation command is transmitted.

  In step S74219, the payout control CPU 371 stores the lower 4 bits of the main control communication reception buffer (that is, the number of prize balls set with the prize ball number command) in the main control communication prize ball number buffer. That is, in this case, an error state has occurred, or during the winning ball payout operation, the ball lending payout operation, or during the ball lending preparation, the winning ball payout operation based on the received winning ball number command is immediately performed. Can't start. Therefore, the payout control CPU 371 suspends the reply of the prize ball number acceptance command and temporarily saves the prize ball number set in the prize ball number command in the main control communication prize ball number buffer.

  Next, the payout control CPU 371 sets a prize ball preparing command (step S74220) and executes main control transmission command conversion processing (step S74221). In the main control transmission command conversion process in step S74221, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74222). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Note that the payout control CPU 371 clears the main control communication reception buffer when the award ball preparing command is transmitted in step S74222. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “2” indicating the main control communication process to the main control communication control code (step S74223). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) to the main control communication control timer (step S74224). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74224, the command for preparing the next prize ball is transmitted if it is not ready to start the prize ball payout operation after one second has elapsed. Will be.

  86 and 87 are flowcharts showing main control communication in-process (step S743) executed when the value of the main control communication control code is 2. In the main control communication process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74301). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S 74302). If it is not a connection confirmation command, the process proceeds to step S74306. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74303) and executes main control transmission command conversion processing (step S74304). In the main control transmission command conversion process in step S74304, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error, etc.) in the lower 4 bits of the connection OK command. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74305). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, the process proceeds to step S74306.

  In step S74306, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication process is a process that is executed after receiving the prize ball number command until the prize ball payout operation can be started based on the received prize ball number command. Since the response of the command is suspended, the game control microcomputer 560 is in a waiting state for receiving the award ball number reception command. During this time, a new payout control command is received from the game control microcomputer 560. There is no trap. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74306. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74307). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74308).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74309), and checks whether the main control communication control timer has timed out (step S74309). S74310).

  If the main control communication control timer has timed out (Y in step S74310), it means that one second or more has elapsed since the previous prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a winning ball preparing command in order to transmit the next winning ball preparing command (step S74311), and executes main control transmission command conversion processing (step S74312). In the main control transmission command conversion process of step S74312, the control state (error status such as a payout number error error, a ball outage error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74313). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74314). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74314, a command for preparing the next prize ball is issued if it is not yet ready to start a prize ball payout operation after one second has passed. Will be sent.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74315). If the value of the error flag is not 0 (that is, if it is in an error state and one of the error bits is set), the winning ball payout operation cannot be started yet, so the processing is ended as it is. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74316). If the BRDY signal is input, the winning ball payout operation cannot be started yet, and the process is terminated as it is.

  If the BRDY signal is not input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74317), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74318). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is in progress, the winning ball payout operation cannot be started yet, so the processing is ended as it is. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74318, it is not determined that a prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command can be started. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication prize ball number buffer (that is, the temporarily saved prize ball number) in the unpaid number counter (step S74319).

  In this embodiment, as described above, when the winning ball payout operation cannot be started immediately when the winning ball number command is received, the winning ball number specified by the winning ball number command is immediately set to the unpaid number. Instead of being set in the counter, it is temporarily saved in the main control communication award ball number buffer, but this control is performed, for example, by adding the award ball number to the unpaid number counter during the lending ball payout operation. This is to prevent inconvenience in processing related to payout control, such as preventing a situation where the number of winning balls cannot be accurately managed.

  Next, the payout control CPU 371 performs control to transmit a prize ball number reception command to the game control microcomputer 560 (step S74320). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74321). Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74322). It should be noted that if a prize ball payout operation is not completed after a lapse of one second after the prize ball number acceptance command is transmitted based on the value set in step S74322, a prize ball preparing command is transmitted.

  FIG. 88 is a flowchart showing main control communication end processing (step S744) executed when the value of the main control communication control code is 3. In the main control communication end process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74401). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74402). If it is not a connection confirmation command, the process proceeds to step S74406. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74403) and executes main control transmission command conversion processing (step S74404). In the main control transmission command conversion process of step S74404, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74405). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, control goes to a step S74406.

  In step S74406, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication end process is a process executed after receiving the prize ball number command and starting the prize ball payout operation until the prize ball payout operation based on the received prize ball number command is ended. Since the microcomputer for use 560 is in a waiting state for receiving the winning ball end command, it is unlikely that a new payout control command will be received from the game control microcomputer 560 during this period. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74406. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74407). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74408).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74409), and checks whether the main control communication control timer has timed out (step S74409). S74410).

  If the main control communication control timer has timed out (Y in step S74410), it means that one second or more has elapsed since the last time a prize ball acceptance command or a prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a prize ball preparing command in order to transmit the next prize ball preparing command (step S74411), and executes main control transmission command conversion processing (step S74412). In the main control transmission command conversion process in step S74412, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74413). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this example) in the main control communication control timer (step S74414). It should be noted that, based on the value set in step S74414, after the command for preparing a prize ball is transmitted, if the prize ball payout operation is not yet completed after another one second, the next command for preparing a prize ball is transmitted. It will be.

  If the main control communication control timer has not timed out, the payout control CPU 371 loads a payout control state flag (step S74415), and checks whether or not a prize ball payout operation is in progress (step S74416). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit is set in the payout control state flag. If the winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has not been finished yet, and the payout control CPU 371 ends the process as it is. If no winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has ended. Therefore, the payout control CPU 371 performs control to transmit a prize ball end command to the game control microcomputer 560 (step S74417). Specifically, the payout control CPU 371 performs a process of outputting a prize ball end command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits the winning ball end command in step S74417. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74418). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this example) in the main control communication control timer (step S74419).

  FIG. 89 is a flowchart showing main control transmission command conversion processing executed in steps S7414, S74207, S74221, S74304, S74312, S74404, and S74412. In the main control transmission command conversion process, the payout control CPU 371 first loads an error flag and checks whether or not the payout number abnormality error designation bit is set (step S731). If the payout number abnormality error designation bit is set, the payout control CPU 371 sets a main control communication payout number error error output bit (specifically, bit 3) in the conversion buffer (step S732).

  Next, the payout control CPU 371 checks whether or not the ball break error designation bit is set (step S733). If the ball-out error designation bit is set, the payout control CPU 371 sets the main control communication ball-out output bit (specifically bit 2) in the conversion buffer (step S734).

  Next, the payout control CPU 371 checks whether or not the full error designation bit is set (step S735). If the full error specification bit is set, the payout control CPU 371 sets the full output bit for main control communication (specifically bit 1) of the conversion buffer (step S736).

  Next, the payout control CPU 371 checks whether or not other prize ball error designation bits are set (step S737). Specifically, the payout control CPU 371 includes a main control communication error designation bit, a main control unconnected error designation bit, a withdrawal switch abnormality detection error 1 designation bit, a withdrawal switch abnormality detection error 2 designation bit, a withdrawal in the error flag. Check if the case error specification bit is set. If any other prize ball error designation bit is set, the payout control CPU 371 sets a main control communication ball out output bit (specifically bit 0) in the conversion buffer (step S738).

  Then, the payout control CPU 371 sets the contents of the conversion buffer in the payout control command (connection OK command or prize ball preparing command) set for transmission (step S739).

  FIG. 90 is a flowchart showing the payout control process in step S755. In the payout control process, the payout control CPU 371 confirms that the detection signal of the payout number count switch 301 is turned on (step S7501), and checks whether the value of the unpaid number counter is 0. (Step S7502). If the value of the unpaid number counter is 0, the payout control CPU 371 adds 1 to the value of the payout number abnormality counter for counting the cumulative number of abnormal payouts (step S7503). In other words, Y in step S7502 means that the unpaid number to be paid out is not set in the unpaid-out number counter, so that the payout operation is performed even though the game ball should not be paid out. And the payout count switch 301 detects the payout of the game ball. For this reason, there is a possibility that the payout operation has been performed by some kind of fraud, so the payout control CPU 101 cumulatively adds 1 to the value of the payout number abnormality counter.

  The payout number abnormality counter indicates the number of payouts exceeding the number of unpaid game balls to be paid out and the number of payout shortages that did not meet the number of unpaid game balls to be paid out. This is a counter for cumulatively counting. As will be described later, in this embodiment, when the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), it is determined that a payout number error has occurred and the payout is stopped. Processing to control the state is performed. Note that the process of step S7503 corresponds to a process of cumulatively counting the excess payout in the payout number abnormality counter.

  In this embodiment, without distinguishing whether the ball is a winning ball or a lending ball, the payout excess number and the payout shortage number are cumulatively counted in the payout number abnormality counter. For only one of the rented balls, the excessive payout and the shortage payout may be cumulatively counted in the payout number abnormality counter. Further, for example, with respect to prize balls and lending balls, it is possible to cumulatively count the excess payout and the shortage payout using separate counters. In this case, it may be determined that a payout number error occurs when the value of one of the counters reaches a predetermined threshold value, or a payout number error error when the total value of both counters reaches a predetermined threshold value. May be determined.

  Further, in this embodiment, the case where the value of the payout number abnormality counter is incremented by 1 when an excessive payout is detected in step S7503 has been shown, but the method of counting up the value of the payout number abnormality counter is described in this embodiment. It is not limited to what is shown in the form. For example, conversely, the excessive payout number may be subtracted from the value of the payout number abnormality counter, and the insufficient payout number may be added to the value of the payout number abnormality counter. In this case, for example, the payout control CPU 371 sets “2000” as the initial value in the payout number abnormality counter in the initial setting process when the power is turned on, and subtracts 1 from the value of the payout number abnormality counter in step S7503. In steps S75320, S75325, and S75335, which will be described later, a value corresponding to the insufficient payout number may be added to the value of the payout number abnormality counter. For example, in the processing of steps S7504, S75321, and S7725 described later, it may be determined that a payout number error has occurred based on the value of the payout number error counter being 2000 or less.

  Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7504). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error error has occurred, and indicates a payout number error error indicating that a payout number error error has occurred. A flag is set (step S7505). That is, in this embodiment, the number of abnormal payouts detected is cumulatively managed on the payout control microcomputer 370 side, and if the accumulated value is equal to or greater than a predetermined payout number abnormal error determination value (for example, 2000), It is determined that there is an extremely high possibility that a payout operation is being performed due to some sort of fraud, and it is determined that a payout number abnormality error (an error indicating that the number of game balls paid out is abnormal) has occurred. In addition, there are not a few cases where game balls are paid out excessively or insufficient due to malfunctions, etc. The frequency determined to be a payout number abnormality error becomes higher than necessary, and the game is hindered. Therefore, in this embodiment, the number of abnormal payouts detected is cumulatively managed, and the payout number abnormality error is determined on the condition that the accumulated value is equal to or greater than a predetermined payout number abnormality error determination value (for example, 2000). By determining, it is prevented that it is determined that the payout number abnormality error is more than necessary.

  In this embodiment, if it is determined that there is a payout number error and the payout number error error flag is set once, the payout number error error flag is not cleared until the power is reset, and the payout number error error is not recovered. When the payout number abnormality error flag is set, the processes in steps S7504 and S7505 and the processes in S75321, S75322, S7725, and S7726 described later may not be executed. By doing so, it is possible to prevent useless processing after it is once determined that the payout number abnormality error has occurred, and to reduce the processing burden.

  Further, in this embodiment, “2000” corresponding to the number of game balls that can be stored in a game ball storage box (so-called dollar box) generally used in a game store is set as a predetermined payout number abnormality error determination value. Although the case where it uses is shown, other values (for example, 1000 or 3000) may be used as the predetermined payout number abnormality error determination value.

  In this embodiment, the payout control process shown in FIG. 90 is a process that is commonly executed when the prize ball payout operation is executed and when the lending ball payout operation is executed. This counter is used in common when counting the number of game balls that have not been paid out with prize balls and when counting the number of game balls that have not been paid out with lending balls. When an abnormality in the number of payouts is detected, the value of the payout number abnormality counter is incremented without distinguishing between payout with a prize ball and payout with a lending ball, and whether or not a payout number abnormality error has occurred. A determination is made.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 subtracts 1 from the value of the unpaid-out number counter (step S7506), and a payout ball detection designation bit (game ball payout) is added to the flag of the payout control state. A bit indicating detection) is set (step S7507). The payout ball detection designation bit is a bit that is set when the payout number count switch 301 is turned on, and indicates that the payout number count switch 301 has detected at least one game ball during the payout operation. is there.

  Thereafter, the payout control CPU 371 executes any one of steps S7511 to S7513 according to the value of the payout control code.

  FIG. 91 is a flowchart showing a payout start waiting process (step S7511) executed when the payout control code is 0. In the payout start waiting process, the payout control CPU 371 first checks whether or not the value of the error flag is 0 (step S75101). If an error bit (one or more of all error bits in the error flag) is set, the payout control CPU 371 controls not to execute the subsequent processing. In this embodiment, by executing the process of step S75101, it is determined that there is a payout number abnormal error, and the payout number abnormal error designation bit of the error bit is set, so that the steps after step S75102 are set. Control is performed so as not to shift to processing, and the payout is stopped.

  If the value of the error flag is 0, the payout control CPU 371 checks whether or not the BRDY signal is input (step S75102). If the BRDY signal is input, the payout control CPU 371 loads a payout control state flag (step S75103), and checks whether or not a ball lending request is being made (step S75104). Specifically, the payout control CPU 371 checks whether or not a ball lending request specifying bit (a bit indicating that a ball lending request is being made) is set in the payout control state flag. The payout control CPU 371 may determine whether or not a ball lending request is being made by confirming whether or not a BRQ signal is input. If a ball lending request is being made (that is, when a ball lending payout operation is started), the payout control CPU 371 resets the ball lending request specifying bit of the payout control state flag (step S75105) and at the same time a payout control state flag. The designated bit during the ball lending / dispensing operation is set (step S75106). Next, the payout control CPU 371 sets a predetermined ball lending number (25 in this example) in the unpaid number counter (step S75107) and a predetermined ball lending number (25 in this example) in the payout motor rotation number buffer. Is set (step S75108). Then, control goes to a step S75113.

  The payout motor rotation frequency buffer is referred to in the payout motor control process (step S756). That is, in the payout motor control process, control is performed to rotate the payout motor 289 by the number of rotations corresponding to the value set in the payout motor rotation frequency buffer.

  If the BRDY signal is not input, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 0 (step S75109). If the value of the unpaid number counter is not 0 (that is, when the prize ball payout operation is started), the payout control CPU 371 sets the value of the unpaid number counter in the payout motor rotation number buffer (step S75110). That is, in this case, since the number of prize balls designated by the received prize ball number command should be set in the unpaid quantity counter (see steps S74214 and S74319), the prize ball dispensing operation is started. Then, a process of setting the number of prize balls in the payout motor rotation frequency buffer is performed. Next, the payout control CPU 371 loads a payout control state flag (step S75111), and sets a prize ball paying-out operation designation bit in the payout control state flag (step S75112). Then, control goes to a step S75113.

  In step S75113, the payout control CPU 371 sets a value in the payout motor control code for selecting a process to be executed in the payout motor control process according to the payout motor activation process. Thereby, in the payout motor control process in step S756, a payout motor starting process for starting the payout motor 289 is executed, and a lending ball payout operation or a prize ball payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75114), and ends the process.

  FIG. 92 is a flowchart showing the payout motor stop waiting process (step S7512) executed when the payout control code is 1. In the payout motor stop waiting process, the payout control CPU 371 first loads a payout control state flag (step S7521), and checks whether or not the payout operation is completed (step S7522). Specifically, the payout control CPU 371 checks whether or not a payout operation end designation bit (a bit indicating that the payout operation has ended) is set in the payout control state flag. The payout operation end designation bit is set in the payout motor brake process and the payout motor ball biting release process in the payout motor control process in step S756 shown in FIG.

  In the payout motor control processing, the payout control CPU 371 performs payout motor normal processing (processing such as setting the pointer at the head address of the table stored in the ROM), payout, according to the value of the payout motor control code. Motor start-up processing (processing such as setting the initial value of the excitation pattern in bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), payout motor slow-up processing (starting the rotation of the payout motor 289 smoothly) Therefore, the output state of the output port 0 is read out by reading the contents of the payout motor excitation pattern table at intervals longer than those in the case of constant speed processing and gradually approaching the time intervals in the case of constant speed processing. , Processing of setting bits 4 to 7 in the port 0 buffer corresponding to), payout motor constant speed processing (periodic payout motor excitation pattern) The process of reading the contents of the table and setting the bits 4 to 7 of the port 0 buffer corresponding to the output state of the output port 0), the dispensing motor brake process (the constant speed process to smoothly stop the dispensing motor 289) Port 0 buffer corresponding to the output state of the output port 0 by reading out the contents of the payout motor excitation pattern table at intervals longer than those in the case of, and gradually away from the time interval in the case of constant speed processing Processing of setting the bits 4 to 7), the payout motor ball biting process (when the ball biting state is detected, in order to release the ball biting, the contents of the payout motor excitation pattern table are read and the output port 0 is set. Processing to set bits 4 to 7 of the port 0 buffer corresponding to the output state) Either processing shifts to the payout motor normal processing process returns to the normal motor control state) execution.

  If the payout operation has been completed, the payout control CPU 371 resets the payout operation end designation bit of the payout control state flag (step S7523) and stops the payout motor used to set a payout passage monitoring time to be described later. The waiting process setting table 2 is set (step S7524).

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S7525). The designated number of paid-out balls inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). If the payout ball number inspected designation bit is set, the process proceeds to step S7527. If the payout ball number inspected designation bit is not set, the payout control CPU 371 sets a payout motor stop waiting process setting table (step S7526). That is, the payout control CPU 371 replaces the table set in step S7524 with a payout motor stop waiting process setting table. Then, control goes to a step S7527.

  In step S7527, the payout control CPU 371 sets a value “2” indicating payout passing waiting processing in the payout control code. The payout control CPU 371 sets the payout passing monitoring time in the payout control timer based on the table set in steps S7524 and S7526 (step S7528). The payout passing monitoring time is a time that has a margin in the time from when the last payout ball is paid out by the payout motor 289 until it passes through the payout number count switch 301. In this embodiment, when the payout ball number inspected bit is set in step S7525, 1 second is set as the payout passing monitoring time based on the payout motor stop waiting process setting table 2 set in step S7524. To do. If the paid ball number inspected bit is not set in step S7525, 0.6 seconds is set as the payout passing monitoring time based on the payout motor stop waiting process setting table replaced in step S7526.

  93 to 95 are flowcharts showing a payout passing waiting process (step S7513) executed when the value of the payout control code is 2. In the payout passing waiting process, the payout control CPU 371 first checks the value of the payout control timer (step S75301). If the value is 0, the process proceeds to step S75304. If the value of the payout control timer is not 0, the value of the payout control timer is decremented by 1 (step S75302). If the value of the payout control timer is not 0 (step S75303), that is, if the payout control timer has not timed out, the process is terminated.

  If the payout control timer has timed out, the payout control CPU 371 loads the error flag, and sets the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit. It is confirmed whether or not (step S75304). If any one of the payout number abnormality error designation bit, the dispensing switch abnormality detection error 1 designation bit, or the dispensing switch abnormality detection error 2 designation bit is set, it is determined that the dispensing operation cannot be continued any more, and the process proceeds to step S75306. Transition. If none of the payout number error error specification bit, the payout switch error detection error 1 specification bit, and the payout switch error detection error 2 specification bit is set, the payout control CPU 371 sets the value of the unpaid number counter to 0. It is confirmed whether or not (step S75305). If the value of the unpaid-out counter is 0, the payout control CPU 371 assumes that the payout operation has ended normally, loads a payout control state flag (step S75306), and is requesting a ballot for the payout control state flag. Bits other than the designated bit and the payout operation end designation bit are reset (step S75307). Then, the payout control CPU 371 sets a value “0” indicating the payout start waiting process in the payout control code (step S75308), and ends the process.

  If the value of the unpaid-out number counter is not 0, the payout control CPU 371 loads an error flag and confirms whether or not the ball breakage error designation bit or the full tank error designation bit is set (step S75309). . If the ball breakage error designation bit or the full tank error designation bit is set, the processing is terminated as it is. If neither the ball breakage error designation bit nor the full tank error designation bit is set, the payout control CPU 371 checks whether or not the payout case error designation bit is set in the error flag (step S75310). If the payout case error designation bit is set, the payout control CPU 371 loads the payout control status flag (step S75311), and sets the payout ball number checked designation bit in the payout control status flag (step S75312). . The payout control CPU 371 also includes a 1 designation bit during re-payout operation (bit indicating execution of the first re-payout operation) and a 2 designation bit during re-payout operation (execution of the second re-payout operation). Is reset (step S75313), and the process is terminated.

  Note that the designated number of paid-out balls has been inspected is a bit indicating that the detection of the number-of-payout count switch 301 has been determined at the end of the payout operation by the payout motor 289 (at the end of normal operation). Note that, when the value of the unpaid-out number counter remains two or more despite the end of the payout operation, the remaining number is added to the payout number abnormality counter. Further, the detection determination by the payout number count switch 301 at the end of the payout operation is executed only once every time the payout operation is executed, and the payout motor ball biting process or the payout motor ball bite releasing process is executed. It is not executed when the biting operation is finished (specifically, since the payout case error designation bit is set in the ball biting state, the ball biting operation is performed by setting the payout ball number checked designation bit in advance in step S75312. (The detection determination by the payout number count switch 301 is not performed even if the operation is finished). It should be noted that the payout ball number inspected designation bit is also set when the payout motor constant speed process in the payout motor control process becomes full.

  If the payout case error designation bit is not set in step S75310, the payout control CPU 371 loads a payout control state flag (step S75314) and performs processing for executing re-payout processing after step S75315.

  In order to execute the re-payout process, the pay-out control CPU 371 first checks whether or not the 2 designation bit during re-payout operation of the payout control state flag is set (step S75315). If it is not set, the payout control CPU 371 checks whether or not the 1 designation bit during re-payout operation of the payout control state flag is set (step S75316). If the 1 designation bit during re-payout operation is not set, the payout control CPU 371 sets the 1 designation bit during re-payout operation in the payout control state flag in order to execute the first re-payout operation (step S75317). .

  Next, the payout control CPU 371 checks whether or not the payout ball number inspected designation bit is set in the payout control state flag (step S75318). If the specified number of paid-out balls is inspected, the process proceeds to step S75326. If the specified number of paid-out balls has been inspected, the payout control CPU 371 checks whether or not the value of the unpaid-out number counter is 2 or more (step S75319). If the value of the unpaid-out number counter is not 2 or more, the process proceeds to step S75326. If the value of the unpaid number counter is 2 or more, the payout control CPU 371 adds the value of the unpaid number counter to the payout number abnormality counter (step S75320). Note that the process of step S75320 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Next, the payout control CPU 371 checks whether or not the value of the added payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S75321). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error error has occurred, and indicates a payout number error error indicating that a payout number error error has occurred. A flag is set (step S75322).

  In this embodiment, the payout is performed on condition that the value of the unpaid-out number counter remains at a predetermined reference number (2 in this example) even though the payout operation is finished by the process of step S75319. The value of the unpaid number counter is added to the number abnormality counter. That is, since the payout operation is terminated due to a malfunction or the like, the value of the unpaid-out number counter remains in a small number (1 in this example). If even one unsettled number counter value remains, if it is immediately counted as a cumulative count in the paid number abnormality counter, the frequency judged as a paid number abnormality error will be higher than necessary, causing problems to the game. End up. Therefore, in this embodiment, on the condition that the value of the unpaid-out number counter remains 2 or more with a little allowance, the accumulated number is counted in the payout number abnormality counter, and it is determined that there is an unnecessarily large number of payout errors. Is prevented. The process of step S75319 shows a case where the payout number abnormality counter is cumulatively counted up on condition that the payout shortage number is equal to or greater than a predetermined reference number (2 in this example). Alternatively, the payout number abnormality counter may be counted up cumulatively on condition that the number is a predetermined reference number (2 in this example) or more. In this case, for example, on the condition that the number of times determined to be Y in step S7502 shown in FIG. 90 has accumulated and has reached two or more, a count value corresponding to an excessive number of payouts is cumulatively set in step S7503. Count up. In the processing of steps S75319 and S75320, the value of the unpaid number counter is always used as it is in the payout number abnormality counter regardless of whether or not the value of the unpaid number counter remains at a predetermined reference number (2 in this example). You may make it add.

  If the 1 designation bit during re-payout operation is set in step S75316, the payout control CPU 371 checks whether or not the dispensed ball detection designation bit is set in the payout control state flag (step S75323). If the payout ball detection designation bit is set, the payout control CPU 371 proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 sets the 2 designation bit during re-payout operation in the payout control state flag to execute the second re-payout operation (step S75324). Then, 1 is added to the value of the payout number abnormality counter (step S75325). Note that the process of step S75325 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Then, control goes to a step S75326. Note that by executing the processing of step S75325, the value of the payout number abnormality counter is incremented by 1 when the re-payout operation is not performed normally despite the execution of the first re-payout operation. The Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75323, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  In step S75326, the payout control CPU 371 sets 1 as the number of repaid operations in order to execute the first repaid operation. Next, the payout control CPU 371 sets the number of re-payout operations (1 in this example) in the payout motor rotation frequency buffer (step S75327). Next, the payout control CPU 371 loads the payout control state flag (step S75328), and resets the payout ball detection designation bit of the payout control state flag (step 75329).

  Next, the payout control CPU 371 sets a value in the payout motor control code for selecting a process executed in the payout motor control process in accordance with the payout motor activation process (step S75330). Thereby, in the payout motor control process of step S756, the payout motor starting process for starting the payout motor 289 is executed, and the re-payout operation is started. Then, the payout control CPU 371 sets a value “1” indicating the payout motor stop waiting process in the payout control code (step S75331), and ends the process.

  If the 2 designation bit during re-payout operation is set in step S75315, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75332). Next, the payout control CPU 371 checks whether or not the payout ball detection designation bit of the payout control state flag is set (step S75333). If the payout ball detection designation bit is set, the process proceeds to step S75326. If the payout ball detection designation bit is not set, the payout control CPU 371 resets the 2 designation bit during re-payout operation of the payout control state flag (step S75334) and adds 1 to the value of the payout number abnormality counter (step S75334). Step S75335). Note that the process of step S75335 corresponds to a process of cumulatively counting the number of shortage payouts in the payout number abnormality counter. Also, by executing the process of step S75335, even if the second re-payout operation is executed, if the re-payout operation is not performed normally, the value of the payout number abnormality counter is incremented by one. Even when the payout is completed normally, the value of the unpaid-out number counter may not be 0 due to an erroneous count or the like. Therefore, if the payout ball detection designation bit is set by executing the process of step S75333, that is, if the payout number count switch 301 detects the payout of at least one game ball during the payout operation. Since there is a possibility that the payout has been completed normally, the process proceeds to step S75326 without performing the cumulative count of the payout number abnormality counter.

  Next, the payout control CPU 371 loads an error flag, and sets a payout case error designation bit in the error flag (step S75336). Then, the payout control CPU 371 sets a predetermined time (for example, 2 minutes) in the re-payout waiting timer (step S75337) and ends the process. The re-payout waiting timer set in step S57337 is measured by error processing described later (see step S7710), and the payout case error designation bit in the error flag is reset based on the time-out of the re-payout timer. (See steps S7711 and S7712). By executing such processing, in this embodiment, after the payout case error is detected, the error state is automatically recovered based on the fact that two minutes have passed.

  Next, error processing will be described. FIG. 96 is an explanatory diagram showing the relationship between the type of error and the display of the LED 374 for error display. As shown in FIG. 96, when no error has occurred, “−” is displayed on the error display LED 374. When the cumulative count value of the payout number abnormality counter is 2000 or more and a payout number error is detected, the payout control CPU 371 of the payout control microcomputer 370 detects an error display LED 374 as a payout number error. Control to display “A” on the screen. If a payout number abnormality error occurs, the error state is continued until the power supply of the gaming machine is reset.

  When the connection signal from the main board 31 is turned off, the payout control CPU 371 of the payout control microcomputer 370 performs control to display “1” on the error display LED 374 as a main board non-connection error. Do.

  When the disconnection of the payout count switch 301 or a ball clogging occurs at the payout count switch 301, the error display LED 374 is controlled to display “2” as the payout switch abnormality detection error 1. The disconnection of the payout number count switch 301 or the occurrence of ball clogging in the payout number count switch 301 is determined by the detection signal of the payout number count switch 301 not being turned off.

  When the detection signal of the payout number count switch 301 is turned on even though the game ball is not paying out, a control for displaying “3” on the error display LED 374 as a payout switch abnormality detection error 2 is performed. Do. If the detection signal of the payout count switch 301 does not turn on despite the rotation abnormality of the payout motor 289 or the game ball being paid out, “4” is displayed on the error display LED 374 as a payout case error. Control. The specific method for detecting that the detection signal of the payout number count switch 301 is not turned on is as described above.

  When a serial communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, control is performed to display “5” on the error display LED 374 as a main control communication error. .

  In addition, when the lower pan is full, that is, when the full switch 48 is turned on, control is performed to display “6” on the error display LED 374 as a full error. When the supply ball is insufficient, that is, when the ball break switch 187 is turned on, control is performed to display “7” on the error display LED 374 as a ball break error.

  Further, when the VL signal from the card unit 50 is turned off, control is performed to display “8” on the error display LED 374 as a prepaid card unit non-connection error. When communication with the card unit 50 is performed at an improper timing, control is performed to display “9” on the error display LED 374 as a prepaid card unit communication error. The prepaid card unit communication error is detected in the prepaid card unit control process (step S758).

  Among the above errors, after a payout switch abnormality detection error 2, a payout case error, or a main control communication error occurs, the error release switch 375 is operated and an operation signal is output from the error release switch 375 (becomes ON state). The payout control means returns to the state before the error occurred.

  As already described, the payout control CPU 371 specifically displays an error on the error display LED 374 according to the relationship shown in FIG. 96 in the display control process of the timer interrupt process (see step S760). For example, the payout control CPU 371 generates a prepaid card unit unconnected error in the display control process based on the setting of the prepaid card unit unconnected state designation bit in the error process described later (see step S7729). An error display “8” indicating that is displayed on the error display LED 374 is controlled. Further, for example, based on the fact that the full error specification bit is set in the error processing (see step S7714), an error display “6” indicating that a full error has occurred in the display control processing is displayed on the error display LED 374. Control the display.

  97 and 98 are flowcharts showing the error processing in step S757. In the error processing, the payout control CPU 371 first loads an error flag, and the error flag payout switch abnormality detection error 2 designation bit, a payout case error designation bit, a main control communication error designation bit, and a payout number abnormality error designation bit. The other error bits are reset (step S7701). Next, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S7702). If the value of the error flag is 0, the process proceeds to step S7710. If the value of the error flag is not 0 (that is, if the payout switch abnormality detection error 2 designation bit, the withdrawal case error designation bit, the main control communication error designation bit, or the withdrawal number abnormality error designation bit is set) The control CPU 371 checks whether or not the operation signal is turned on from the error release switch 375 (step S7703). When the operation signal is turned on, the payout control CPU 371 checks whether or not the mechanism plate opening signal from the mechanism plate opening sensor 155B is turned on (step S7703a). If the mechanism plate release signal is on (that is, if the mechanism plate is in the open state), the payout control CPU 371 sets the error return time in the pre-error return timer (step S7709). The error recovery time is the time from when the error release switch 375 is operated until the actual return from the error state to the normal state. If the mechanism plate open signal is not in the on state (that is, if the mechanism plate is in the closed state), the payout control CPU 371 proceeds to step S7710 without executing the process of step S7709.

  In general, since the error release switch 375 is mounted on the payout control board 37 inside the gaming machine, a game clerk or the like can release the error state by pressing the error release switch 375 unless the mechanism board is opened. I can't. Therefore, when the error state is released according to the normal procedure, if the error release switch 375 is in the on state, the mechanism plate open signal should be in the on state at the same time. Although the ON state of the mechanism release signal is not detected in step S7703a even though the ON state of the error release switch 375 is detected in step S7703, the error release switch 375 remains in the closed state. Is pressed. For this reason, there is a high possibility that an act of illegally turning on the error release switch 375 by inserting a device from the gap of the gaming machine during the game is performed. Therefore, in this embodiment, if the ON state of the mechanism plate release signal is not detected in step S7703a even though the ON state of the error release switch 375 is detected in step S7703, the error state is illegally detected. Therefore, it is determined that there is a high possibility that the error state is going to be canceled, and control is performed so that the error state is not released by not setting the pre-error recovery timer in step S7709. By controlling in such a manner, in this embodiment, it is possible to detect the possibility that fraud is being performed even with respect to cancellation of the error state, and it is possible to strengthen measures for preventing fraud. .

  If the operation signal from the error release switch 375 is not on, the value of the timer before error recovery is confirmed (step S7704). If the value of the timer before error recovery is 0, that is, if the timer before error recovery is not set, the process proceeds to step S7710. If the pre-error recovery timer is set, the value of the pre-error recovery timer is decremented by -1 (step S7705). If the pre-error recovery timer value becomes 0 (step S7706), the payout switch of the error flags is set. The abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset (step S7707), and if set, the re-payout waiting timer is reset (step S7708). Then, control goes to a step S7710. If the pre-error recovery timer has not timed out, the process proceeds to step S7713.

  When the processing of step S7707 is executed, there may be an error bit that is not in the set state among the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit. There is no problem even if the error bit that is not in the set state is reset. As described above, in this embodiment, when an error (see FIG. 96) that causes the setting of the payout switch abnormality detection error 2, the payout case error, and the main control communication error bit occurs, an error occurs. The error is released when the release switch 375 is pressed.

  In step S7710, if set, the payout control CPU 371 subtracts 1 from the value of the re-payout waiting timer, and checks whether the re-payout wait timer after the subtraction has timed out (step S7711). If the re-payout waiting timer has timed out, the payout control CPU 371 resets the payout case error designation bit of the error flag (step S7712). Then, control goes to a step S7713.

  As described above, in this embodiment, when the payout case error is detected and the payout detection error designation bit is set by executing the processes of steps S7707 and S7712, the error release switch 375 is pressed. On the condition that the error has been canceled (more precisely, the time before error recovery has passed) and on the condition that a predetermined time (2 minutes in this example) has passed after detection of the payout case error The error may be automatically canceled. In this embodiment, regarding the payout number abnormality error, once detected, it is not canceled unless the power supply to the gaming machine is reset.

  When the processing of steps S7707 and S7712 is executed and the payout case error designation bit is reset, the payout control code is “2” (corresponding to the execution of the payout passing waiting process shown in FIGS. 93 to 95). Then, the game ball payout retry operation is started. That is, when the payout control process in step S755 is executed next, if the payout passing waiting process in step S7513 is executed, the repayout process is performed again. For example, if a prize ball payout process has been performed and the value of the unpaid-out number counter is not 0, the process proceeds from step S75305 to steps S75309 and S75310, and the payout case error designation bit is in the reset state in step S75310. Therefore, the process for starting the re-payout process after step S75314 is executed again, and the re-payout process is executed.

  As described above, the payout control means is used to pay out a game ball when the payout number count switch 301 detects no game ball even though the ball payout device 97 pays out a game ball. After performing the correct payout control for causing the ball payout device 97 to execute the retry operation for a predetermined number of times (for example, twice) as a limit, the payout number count switch 301 has detected no game balls. When it is detected (see step S75314 and subsequent steps in FIGS. 93 to 95), the control state related to payout is shifted to an error state, and an error release signal is output from the error release switch 375 in the error state, or a payout case Corrected payout that makes correction payout control again on condition that a predetermined time (2 minutes in this example) has passed since the error was detected To run the control restart processing.

  Further, even during re-payout processing in an error state (specifically, during re-payout processing before setting a payout case error and during re-payout processing after the error release switch 375 is pressed), step S7501 shown in FIG. S7502 and S7506 are executed. That is, even when an error relating to payout occurs, if the game ball passes the payout number count switch 301, the value of the unpaid-off number counter is subtracted. Accordingly, the value of the unpaid-out number counter when returning from the error state is a value reflecting the number of game balls actually paid out. That is, even if an error related to payout occurs, the number of game balls actually paid out can be accurately managed.

  Also, in the payout passing waiting process shown in FIGS. 93 to 95, even when it is confirmed that the game ball has been paid out as a result of the re-payout process, the payout case error bit is not reset. The bit of the payout case error is reset only when the error release switch 375 is operated (specifically, when an error return time after operation has elapsed) or when a payout case error is detected for a predetermined time. (2 minutes in this example) has elapsed (steps S7707, S7712). That is, until a predetermined time (in this example, 2 minutes) has passed since the detection of the payout case error, the payout case error (insufficient payout) is automatically determined based on the fact that the game ball has passed through the payout number count switch 301. The error) state is not canceled, and the payout case error is not canceled without an artificial operation. Therefore, the game store clerk and the like can surely recognize that a shortage of payout has occurred. However, in this embodiment, at least a long time (2 minutes in this example) after the occurrence of the payout case error is configured to automatically cancel the payout case error so that the payout case error is generated. Prevents continued for longer than necessary.

  In some cases, a gaming machine may be configured such that a hardware reset (reset for the payout control CPU 371) is performed by operating the error release switch 375. When the error release switch 375 is operated, for example, the value of the unpaid number counter is also cleared. However, in this embodiment, since the payout control means is configured to perform the re-payout operation again by operating the error release switch 375, the payout process is executed reliably, which is disadvantageous to the player. Can not be given.

  In step S7713, the payout control CPU 371 checks the detection signal of the full switch 48. If the detection signal of the full tank switch 48 is output (if it is in the ON state), the full tank error designation bit in the error flag is set (step S7714).

  Further, the payout control CPU 371 checks the detection signal of the ball break switch 187 (step S7715). If the detection signal of the ball break switch 187 is output (if it is on), the ball break error designation bit in the error flag is set (step S7716).

  Furthermore, the payout control CPU 371 checks the state of the connection signal from the main board 31 (step S7717), and if the connection signal is not output (if it is in the off state), sets the main board unconnected error designation bit. (Step S7718).

  Further, the payout control CPU 371 checks the value of the switch timer corresponding to the payout number count switch 301 among the switch timers in which the state of the detection signal of each switch is set, and the value is the switch on maximum time (for example, “ 250 ") (step S7719), the bit of the payout switch abnormality detection error 1 is set in the error flag (step S7720). It should be noted that the value of each switch timer is incremented by 1 when the state of the input port to which the detection signal of each switch is input is switched on in the input determination process of step S752, and cleared by 0 when it is off. Accordingly, the fact that the value of the switch timer corresponding to the payout number count switch 301 exceeds the switch on maximum time means that the payout number count switch 301 is in the on state exceeding the switch on maximum time. Then, it is determined that the game ball is clogged at the disconnection of the payout number count switch 301 or at the portion of the payout number count switch 301.

  Further, the payout control CPU 371 loads the payout control state flag when the value of the switch timer corresponding to the payout number count switch 301 becomes a switch-on determination value (for example, “4”) (step S7721). In step S7722), it is confirmed whether the winning ball payout operation or the ball lending payout operation is in progress (step S7723). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit or a ball lending payout operation specifying bit is set in the payout control state flag. If the designated bit during the winning ball payout operation and the designated bit during the ball lending payout operation are both in the reset state, the payout control CPU 371 determines that the game ball has passed through the payout number count switch 301 even though the payout operation is not in progress, an error flag. Among these, the bit of the payout switch abnormality detection error 2 is set (step S7724).

  Further, the payout control CPU 371 checks whether or not the value of the payout number abnormality counter is equal to or greater than a predetermined payout number error error determination value (for example, 2000) (step S7725). If it is equal to or greater than a predetermined payout number error error determination value (for example, 2000), the payout control CPU 371 determines that a payout number error has occurred and sets a payout number error error flag (step S7726).

  Next, the payout control CPU 371 resets the prepaid card unit error flag for setting the error state of the prepaid card unit 50 (step S7727). Further, the payout control CPU 371 checks the input state of the VL signal from the card unit 50 (step S7728), and if the VL signal is not input (if it is in the OFF state) The prepaid card unit unconnected error designation bit is set (step S7729).

  In the display control process of step S760, the error display LED 374 performs notification by display (numerical display) according to the error flag and the error bit in the prepaid card unit error flag. Therefore, a communication error can be notified by the error display LED 374. Further, since the communication error is detected on the payout control means side, the communication error can be detected without increasing the burden on the game control means.

  In this embodiment, the main board unconnected error is automatically canceled when the connection signal is turned on (see steps S7701, S7717, and S7718), but the condition that the error cancel switch 375 is further operated is set. In addition, the error state may be eliminated.

  In this embodiment, a communication error is reported so as to be distinguishable from a communication error with the card unit 50 (prepaid card unit non-connection error and prepaid card unit communication error) and other errors (see FIG. 96). ). Therefore, a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is easily identified.

  In this embodiment, in error processing, first of the error flags, other than the payout switch abnormality detection error 2 designation bit, the payout case error designation bit, the main control communication error designation bit, and the withdrawal number abnormality error designation bit. After the bit is reset once (see step S7701), it is checked every time error processing is executed whether a full error, a ball break error, or a main control unconnected error has occurred. The payout switch abnormality detection error 2 designation bit, the payout case error designation bit, and the main control communication error designation bit are reset on the condition that the error release switch 375 has been operated. However, the payout number abnormality error is not canceled once it is set. Therefore, in this embodiment, when a payout number error occurs, the payout number error is canceled as a condition that the power supply is reset.

  99 and 100 are flowcharts showing the information output processing in step S759. In the information output process, the payout control CPU 371 first loads a payout control state flag (step S7901), and checks whether or not a ball lending payout operation is in progress (step S7902). Specifically, the payout control CPU 371 checks whether or not the designated bit during the ball lending payout operation of the payout control state flag is set. If the ball lending / dispensing operation is in progress, the process proceeds to step S7909. If the ball lending payout operation is not in progress, the payout control CPU 371 checks whether or not the payout number count switch 301 is in the on state (step S7903). If the payout number count switch 301 is in the ON state (in this case, the payout by the winning ball is detected), the payout control CPU 371 adds 1 to the value of the winning ball signal 1 output number counter (step S7904). At the same time, the value of the prize ball payout number counter is incremented by 1 (step S7905). The prize ball signal 1 output number counter is a counter for counting the number of times the condition for outputting the prize ball signal 1 is satisfied. The prize ball payout number counter is a counter for counting the number of game balls paid out by the prize ball payout.

  Next, the payout control CPU 371 checks whether or not the value of the added prize ball payout counter is equal to or greater than a predetermined prize ball information output determination value (10 in this example) (step S7906). If it is equal to or greater than a predetermined prize ball information output determination value (10 in this example), the payout control CPU 371 resets the prize ball payout number counter (step S7907) and sets the value of the prize ball information output number counter. 1 is added (step S7908). The prize ball information output count counter is a counter for counting the number of times that the condition for outputting prize ball information is satisfied.

  Next, if it is set, the payout control CPU 371 decrements the prize ball information output timer by 1 (step S7909), and checks whether the prize ball information output timer after the subtraction has timed out (step S7910). The prize ball information output timer is a timer for measuring the output duration time of prize ball information. If not timed out, the process proceeds to step S7914. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball information output number counter is 0 (step S7911). If the value of the prize ball information output number counter is 0, the process proceeds to step S7915. If the value of the winning ball information output number counter is not 0 (that is, if the number of winning ball information output conditions is still satisfied), the payout control CPU 371 subtracts 1 from the value of the winning ball information output number counter. (Step S7912). Next, the payout control CPU 371 sets a prize ball information output timer in order to start outputting the next prize ball information (step S7913). Then, the payout control CPU 371 performs control to output the prize ball information to the game control microcomputer 560 (step S7914). Specifically, the payout control CPU 371 performs a process of setting output data in a prize ball information output bit (bit 7, see FIG. 77) of the output port 1.

  Next, if the payout control CPU 371 is set, the prize ball signal 1 output timer is decremented by 1 (step S7915), and it is confirmed whether or not the prize ball signal 1 output timer after the subtraction has timed out (step S7916). ). The prize ball signal 1 output timer is a timer for measuring the output duration time of the prize ball signal 1. If not timed out, the process proceeds to step S7920. If time-out has occurred, the payout control CPU 371 checks whether or not the value of the prize ball signal 1 output number counter is 0 (step S7917). If the value of the winning ball signal 1 output number counter is 0, the process proceeds to step S7921. If the value of the prize ball signal 1 output number counter is not 0 (that is, if the number of established conditions for the prize ball signal 1 still remains), the payout control CPU 371 determines the value of the prize ball signal 1 output number counter. 1 is subtracted (step S7918). Next, the payout control CPU 371 sets a prize ball signal 1 output timer to start outputting the next prize ball signal 1 (step S7919). Then, the payout control CPU 371 performs control to output the prize ball signal 1 to the outside (step S7920). Specifically, the payout control CPU 371 performs processing for setting output data in a prize ball signal 1 output bit (bit 0; see FIG. 77) of the output port 0. In this embodiment, the winning ball signal 1 is not directly input to the terminal board 160 from the payout control board 31 and output to the outside, but is input to the terminal board 160 once through the main board 31. Is output externally.

  Next, the payout control CPU 371 performs processing for setting output data in the gaming machine error state signal output bit (bit 1, see FIG. 77) of the output port 0 (step S7921), and loads an error flag (step S7922). ). If either the ball breakage error designation bit or the full tank error designation bit is set in the error flag (Y in steps S7923 and S7924), the gaming machine error status signal output bit of the output port 0 remains set. The process ends. In this case, the gaming machine error status signal is output to the outside based on the fact that the gaming machine error status signal output bit of the output port 0 is set in step S7921. In this embodiment, the gaming machine error state signal is not directly input from the payout control board 31 to the terminal board 160 but externally output, but is input to the terminal board 160 once via the main board 31. And output externally. On the other hand, if neither the ball breakage error designation bit nor the full tank error designation bit is set in the error flag, the payout control CPU 371 clears the gaming machine error state signal output bit of the output port 0 (step S7925), and processing Exit.

  By executing the above processing, in this embodiment, the prize ball signal 1 is output to the outside every time one prize ball payout is detected on the payout control means side. Further, prize ball information is output to the game control means side every time ten payout balls are detected on the payout control means side. Further, when a ball break error or a full tank error is detected on the payout control means side, a gaming machine error state signal is output to the outside.

  Next, the operation of the effect control means will be described. FIG. 101 is a flowchart showing a main process executed by the effect control microcomputer 100 (specifically, effect control CPU 101a) as effect control means mounted on the effect control board 80. The effect control CPU 101a starts executing the main process when the power is turned on. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 4 ms) (step S781). . Thereafter, the effect control CPU 101a proceeds to a loop process for monitoring the timer interrupt flag (step S782). When a timer interrupt occurs, the effect control CPU 101a sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set in the main process, the effect control CPU 101a clears the flag (step S783) and executes the following effect control process.

  In the effect control process, the effect control CPU 101a first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S784).

  Next, the effect control CPU 101a performs effect control process processing (step S785). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the effect display device 9 is executed.

  Next, a random number update process for updating a count value of a counter for generating a random number such as a jackpot symbol determining random number is executed (step S786). Thereafter, the process proceeds to step S782.

  FIG. 102 is a flowchart illustrating a specific example of command analysis processing (step S784). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101a checks the content of the command stored in the command reception buffer.

  Note that FIG. 102 shows the processing in the case of receiving a command indicating an error relating to payout control among the effect control commands transmitted from the game control microcomputer 560. Various effect control commands such as a variation pattern command indicating a variation pattern and a display result specifying command indicating a display result indicating whether or not to win are transmitted from the game control microcomputer 560.

  In the command analysis process, the effect control CPU 101a first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101a reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that 2 bytes (1 command) are read at a time.

  If the received effect control command is a frame state display command (step S614), the effect control CPU 101a sets a prize ball error bit (bit 0; see FIG. 71) in the EXT data of the frame state display command. It is confirmed whether or not (step S615). If set, the effect control CPU 101a performs control to superimpose and display predetermined prize ball error notification information on the display screen of the effect display device 9 (step S616). For example, the effect control CPU 101 a performs control to display a character string such as “A prize ball error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the full error bit (bit 1; see FIG. 71) in the EXT data of the frame state display command is set (step S617). If set, the effect control CPU 101a performs control to superimpose and display predetermined full tank error notification information on the display screen of the effect display device 9 (step S618). For example, the effect control CPU 101 a performs control to display a character string such as “a full tank error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the ball break error bit (bit 2, see FIG. 71) in the EXT data of the frame state display command is set (step S619). If set, the effect control CPU 101a performs control to superimpose and display predetermined ball-out error notification information on the display screen of the effect display device 9 (step S620). For example, the effect control CPU 101 a performs control to display a character string such as “A ball break error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the payout number abnormality error bit (bit 3, see FIG. 71) in the EXT data of the frame state display command is set (step S621). If set, the effect control CPU 101a performs control to superimpose and display predetermined payout number abnormality error notification information on the display screen of the effect display device 9 (step S622). For example, the effect control CPU 101 a performs control to display a character string such as “A payout number error has occurred” on the display screen of the effect display device 9.

  Further, the effect control CPU 101a checks whether or not the door opening abnormality error bit (bit 7, see FIG. 71) in the EXT data of the frame state display command is set (step S623). If set, the production control CPU 101a outputs a sound signal (sound number data) for outputting a predetermined special sound for notifying that the open state of the glass door frame 2 is detected to the sound output board 70. (Step S624). In this case, the sound number data for special sounds input from the production control microcomputer 100 on the sound output board 70 is input to the sound synthesis IC 703 via the input driver 702. Then, the speech synthesis IC 703 generates a special sound (for example, a warning sound such as a beep sound) according to the sound number data and outputs it from the speaker 27 via the amplifier circuit 705.

  The special sound may be output continuously until, for example, the power supply to the gaming machine is turned off or until the glass door frame 2 is closed. The output may be continued until (for example, 10 seconds) elapses. When continuously outputting until the glass door frame 2 is closed, the game control microcomputer 560 detects that the glass door frame 2 has changed from the open state to the closed state. A command indicating this is transmitted to the production control microcomputer 100.

  If the received effect control command is a prize ball shortage error command (step S625), the effect control CPU 101a performs control to superimpose and display predetermined prize ball shortage error notification information on the display screen of the effect display device 9 (step S625). S626). For example, the effect control CPU 101 a performs control to display a character string such as “There was a shortage of prize balls error” on the display screen of the effect display device 9.

  If the received effect control command is a prize ball excess error command (step S627), the effect control CPU 101a performs control to superimpose and display predetermined prize ball excess error notification information on the display screen of the effect display device 9 (step S627). S628). For example, the effect control CPU 101a performs control to display a character string such as “An excessive prize ball error has occurred” on the display screen of the effect display device 9.

  In addition, each error display may not be simply displayed in a superimposed manner, but may be prioritized and notified of an error having a high priority by ranking from the viewpoint of fraud importance. For example, a payout number abnormality error may be preferentially notified with the highest priority, or a newly generated error may be preferentially notified when the error state changes.

  If the received effect control command is an initialization fraud notification command (step S629), the effect control CPU 101a performs control to superimpose and display predetermined initialization fraud notification information on the display screen of the effect display device 9 (step S630). ). For example, the effect control CPU 101a performs control to display a character string such as “the clear switch has been illegally pressed” on the display screen of the effect display device 9. Instead of displaying the predetermined initialization fraud information, for example, by outputting a predetermined warning sound or lighting or blinking the lamps 25, 28a, 28b, 28c in a predetermined pattern, You may make it alert | report the possibility that the clear switch was pressed illegally. Further, for example, a signal indicating the possibility that the clear switch has been illegally pressed may be output to an external device such as a hall computer via the terminal board 160.

  If the received effect control command is another command, the effect control CPU 101a sets a flag corresponding to the received effect control command (step S631). Then, control goes to a step S611. For example, when a variation pattern command or a display result designation command is received, the effect control CPU 101a also performs processing for storing the received variation pattern command or display result designation command in a predetermined storage area formed in the RAM. Do.

  FIG. 103 is a flowchart showing the effect control process (step S785) in the main process shown in FIG. In the effect control process, the effect control CPU 101a performs one of steps S800 to S806 according to the value of the effect control process flag. In each process, the following process is executed. In the effect control process, the display state of the effect display device 9 is controlled and variable display of the effect symbol is realized. However, control related to variable display of the effect symbol synchronized with the change of the first special symbol is also the second. Control related to the variable display of the effect symbol synchronized with the change of the special symbol is also executed in one effect control process. It should be noted that the variable display of the effect symbol synchronized with the variation of the first special symbol and the variable display of the effect symbol synchronized with the variation of the second special symbol may be executed by separate effect control process processing. Good. Further, in this case, it may be determined which special symbol variation display is being executed depending on which representation control process processing is performing the variation display of the representation symbol.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a variation pattern command has been received from the game control microcomputer 560. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If the change pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the effect symbol change start process (step S801).

  Production symbol variation start processing (step S801): Control is performed so that the variation of the production symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the effect symbol changing process (step S802).

  Production symbol variation processing (step S802): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the effect symbol variation stop process (step S803).

  Effect symbol variation stop processing (step S803): Control is performed to stop the variation of the effect symbol and derive and display the display result (stop symbol). Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S804): When the big hit is made, after the end of the variation time, the effect display device 9 is controlled to display a screen for notifying the occurrence of the big hit. Then, the value of the effect control process flag is updated to a value corresponding to the big hit game processing (step S805).

  Big hit game processing (step S805): Control during big hit game is performed. For example, when a special winning opening opening designation command or a special winning opening open designation command is received, display control of the number of rounds in the effect display device 9 is performed. Then, the value of the effect control process flag is updated to a value corresponding to the jackpot end effect process (step S806).

  Big hit end effect processing (step S806): In the effect display device 9, display control is performed to notify the player that the big hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800).

  Next, the operation timing of the random number circuit 509 will be described. FIG. 104 is a timing chart for explaining the operation of the random number circuit 509. In FIG. 104A, the control clock CCLK generated by the control clock generation circuit 111 mounted on the main board 31 is shown. FIG. 104B shows the random number clock RCLK generated by the random number clock generation circuit 112. Note that the various signals shown in FIG. 104 are negative logic signals that are turned off at a high level and turned on at a low level. As shown in FIGS. 104A and 104B, the oscillation frequency of the control clock CCLK and the oscillation frequency of the random number clock RCLK are different from each other. It does not become an integral multiple of the other oscillation frequency.

  As shown in FIG. 104 (B), the random number clock RCLK falls from the high level to the low level at timings T10, T11, T12,. The random number clock RCLK is supplied to the random number external clock terminal ERC of the game control microcomputer 560 and input to the clock terminal CK in the clock flip-flop 552 provided in the random number circuit 509 shown in FIG. The clock flip-flop 552 responds to the falling edge of the random number clock RCLK input to the clock terminal CK with the latch clock RC0 fed back from the negative phase output terminal (inverted output terminal) Q bar to the D input terminal. Then, it is taken in (latched) and outputted as a random number update clock RGK from the positive phase output terminal (non-inverted output terminal) Q. Thereby, as shown in FIG. 104C, the random number update clock RGK falls from the high level to the low level at the timings T10, T12, T14,..., And is ½ of the oscillation frequency of the random number clock RCLK. The signal has an oscillation frequency of. For example, if the oscillation frequency of the random number clock RCLK is 20 MHz, the oscillation frequency of the random number update clock RGK is 10 MHz. Since the oscillation frequency of the random number clock RCLK is neither an integer multiple nor a fraction of the oscillation frequency of the control clock CCLK, the oscillation frequency of the random number update clock RGK is the oscillation frequency of the control clock CCLK. Different frequency. The random number generation circuit 553 updates the numerical data in the count value permutation RCN in response to, for example, the falling edge of the random number update clock RGK. The random number sequence change circuit 555 changes the numerical data update order in the count value permutation RCN output from the random number generation circuit 553 based on the setting of the random number update rule by the random number sequence change setting circuit 556 as a random number sequence RSN. Output. Thus, the numerical data in the random number sequence RSN is updated in response to the falling edge of the random number update clock RGK, for example, as shown in FIG.

  As described above, the oscillation frequency of the random number clock RCLK generated by the random number clock generation circuit 112 and the oscillation frequency of the control clock CCLK generated by the control clock generation circuit 111 are different from each other. One oscillation frequency does not become an integral multiple of the other oscillation frequency. Therefore, the oscillation frequency of the random number update clock RGK and the latch clock RC0 generated by the clock flip-flop 552 of the random number circuit 509 is ½ of the oscillation frequency of the random number clock RCLK, but the oscillation of the control clock CCLK. The frequency and the oscillation frequency of the internal system clock SCLK that is ½ of the oscillation frequency of the control clock CCLK are different. Thus, the control clock CCLK, the internal system clock SCLK, and the random number update clock RGK are prevented from being synchronized. It becomes difficult to specify the update timing of numerical data in the random number sequence RSN to be performed. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the update operation of numerical data serving as a random number value in the random number circuit 509 from the operation timing of the CPU 56.

  The latch clock RC0 output from the clock flip-flop 552 is an inverted signal of the random number update clock RGK, the oscillation frequency thereof is the same as the oscillation frequency of the random number update clock RGK, and its phase is equal to the phase of the random number update clock RGK and π It differs by (= 180 °). The latch clock RC0 is branched into a latch clock RC1 and a latch clock RC2 at a branch point BR1. Therefore, for example, as shown in FIG. 104 (E), each of the latch clocks RC0, RC1, and RC2 is an oscillation signal whose signal state changes in a common cycle. The latch clock RC1 is input to the clock terminal CK of the latch flip-flop 557A. The latch clock RC2 is input to the clock terminal CK of the latch flip-flop 557B.

  Thus, the oscillation frequencies of the latch clocks RC1 and RC2 generated by branching the latch clock RC0 are different from the oscillation frequencies of the control clock CCLK and the internal system clock SCLK. Therefore, the control clock CCLK, the internal system clock SCLK, and the latch clocks RC1 and RC2 are prevented from being synchronized, and the random number circuit 509 takes in numerical data as a random value from the operation timing of the CPU 56. It becomes difficult to specify the timing. As a result, it is possible to reliably prevent aiming and the like based on the result of analyzing the operation of fetching numerical data as a random value in the random number circuit 509 from the operation timing of the CPU 56.

  The latch flip-flop 557A takes in (latches) the start winning signal SS transmitted from the start port switch 14a and supplied to the input port P0 in response to the falling edge of the latch clock RC1. The latch signal SL1 is output from the output terminal Q. Then, if the capturing method in the random number latch selector 558A is designated as signal input to the input port P0, the start winning latch signal SL1 is output as the random number latch signal LL1. Thus, for example, the start winning signal SS whose signal state changes between the off state (high level) and the on state (low level) at the timing shown in FIG. 104F is the timing T11 at which the latch clock RC1 falls. , T13,..., And then the latched flip-flop 557A takes the random number latch signal LL1 whose signal state changes between the off state and the on state at timings T11 and T13 as shown in FIG. , Output from the random number latch selector 558A. Here, the start winning signal SS transmitted from the start opening switch 14a changes from the off state to the on state when the start winning of the game ball at the start winning opening 14 is detected. The random number latch signal LL1 output from the latch flip-flop 557A via the random number latch selector 558A is supplied to the random number value register 559A serving as the random number value register R1D, and in the random number sequence RSN output from the random number sequence change circuit 555. Used to obtain numerical data. Thus, the latch flip-flop 557A and the random number latch selector 558A acquire numerical data as a random value using the latch clock RC1 based on the detection of the start winning of the game ball at the start winning opening 14. Random number latch signal LL1 is generated.

  The latch flip-flop 557B takes in (latches) the start winning signal SS transmitted from the start port switch 14a and supplied to the input port P1 in response to the falling edge of the latch clock RC2, and at the time of starting winning The latch signal SL2 is output from the output terminal Q. Then, if the capturing method in the random number latch selector 558B is designated as signal input to the input port P1, the start winning latch signal SL2 is output as the random number latch signal LL2. Thereby, for example, the start winning signal SS whose signal state changes between the off state (high level) and the on state (low level) at the timing shown in FIG. 104 (F) is the timing T11 at which the latch clock RC2 falls. , T13,..., And then the latched flip-flop 557B takes the random number latch signal LL2 whose signal state changes between the off state and the on state at timings T11 and T13 as shown in FIG. Are output from the random number latch selector 558B. Here, the start winning signal SS transmitted from the start opening switch 14a changes from the off state to the on state when the start winning of the game ball at the start winning opening 14 is detected. The random number latch signal LL2 output from the latch flip-flop 557B via the random number latch selector 558B is supplied to the random number value register 559B serving as the random number value register R2D, and the random number sequence RSN output from the random number sequence change circuit 555 Used to obtain numerical data. In this way, the latch flip-flop 557B and the random number latch selector 558B acquire numerical data as a random value using the latch clock RC2 based on the detection of the start winning of the game ball at the start winning opening 14. Random number latch signal LL2 is generated.

  In this way, the latch flip-flop 557A and the latch flip-flop 557B each have a common cycle by branching the latch clock RC0 generated by the common clock flip-flop 552 at the branch point BR1. Using the latch clocks RC1 and RC2 whose signal states change, a start winning latch signal SL1 and a start winning latch signal SL2 for obtaining numerical data as a random value are generated. Thereby, the circuit configuration in the random number circuit 509 can be simplified, and the manufacturing cost in the pachinko gaming machine 1 can be reduced.

  The random value register 559A serving as the random value register R1D receives the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 at the falling edge of the random number latch signal LL1 input from the random number latch selector 558A to the clock terminal. In response, the data is fetched (latched), and the numerical data serving as stored data is updated. The random value register 559B serving as the random value register R2D receives the numerical data in the random number sequence RSN output from the random number sequence change circuit 555 at the falling edge of the random number latch signal LL2 input from the random number latch selector 558B to the clock terminal. In response, the data is fetched (latched), and the numerical data serving as stored data is updated.

  For example, as shown in FIG. 104 (G), when a falling edge occurs in which the random number latch signal LL1 changes from the off state to the on state at timing T11, the random number sequence change circuit 555 outputs the timing T11. As shown in FIG. 104 (H), the numerical data in the random number sequence RSN that has been read is taken into the random value register R1D and acquired as numerical data that becomes a random value. Thereby, the random value register 559A serving as the random value register R1D can acquire and store numerical data used as a random number value based on the detection of the start winning of the game ball at the start winning opening 14.

  For example, as shown in FIG. 104 (I), the random number sequence changing circuit is also generated at the timing T11 when the falling edge of the random number latch signal LL2 is changed from the OFF state to the ON state at the timing T11. The numerical data in the random number sequence RSN output from 555 is taken into the random value register R2D as shown in FIG. 104 (J), and is acquired as numerical data that becomes a random value. Thus, the random value register 559B serving as the random value register R2D can acquire and store numerical data used as a random value based on the detection of the start winning of the game ball at the start winning opening 14.

  Thus, the random value register 559A responds to the falling edge of the start winning latch signal SL1 generated by the latch flip-flop 557A using the latch clock RC1 and the random number latch signal LL1 output from the random number latch selector 558A. The numerical data in the random value RSN is stored. The random value register 559B is responsive to the falling edge of the start winning latch signal SL2 generated by the latch flip-flop 557B using the latch clock RC2 and the random number latch signal LL2 output from the random number latch selector 558B. The numerical data in the random number sequence RSN is stored.

  As described above, in the random number circuit 509, the clock flip-flop 552, the random number generation circuit 553, the random number sequence change circuit 555, etc. acquire numerical data that becomes a random number value based on the start winning of the game ball at the start winning opening 14. A latch configured to acquire numerical data to be a random value based on the combination of the latch flip-flop 557A, the random number latch selector 558A, the random number value register 559A, and the starting winning of the game ball at the starting winning opening 14. The common flip-flop 557B, random number latch selector 558B, and random number value register 559B are combined. Thereby, the circuit configuration in the random number circuit 509 can be simplified, and the manufacturing cost of the pachinko gaming machine 1 can be reduced.

  In the random number latch flag register RDFM shown in FIG. 23 (A), the operation for reading and reading numerical data in the random value register 559A serving as the random value register R1D, and the numerical data in the random value register 559B serving as the random value register R2D. The corresponding bit value changes to “0” and “1” in response to the fetch operation and read operation. FIG. 105 is a timing chart for explaining changes in random number latch flag data RDFM0 and random number latch flag data RDFM1 stored in bit numbers [0] and [1] of random number latch flag register RDFM.

  As shown in FIG. 105A, at the timing T20 when the random number latch signal LL1 or the random number latch signal LL2 falls, numerical data is taken into the random value register R1D or the random value register R2D as shown in FIG. Corresponding to this, the bit values of the random number latch flag data RDFM0 and the random number latch flag data RDFM1 change from “0” to “1” as shown in FIG. For example, when numerical data is stored in the random value register R1D in response to the random number latch signal LL1 being turned on (low level) at the timing T20, the bit value of the random number latch flag data RDFM0 is “0”. By changing from “1” to “1”, the random number latch flag corresponding to the random number value register R1D is turned on. Further, when numerical data is stored in the random value register R2D in response to the random number latch signal LL2 being turned on (low level) at the timing T20, the bit value of the random number latch flag data RDFM1 is “0”. By changing from “1” to “1”, the random number latch flag corresponding to the random number value register R2D is turned on.

  When the random number latch flag is turned on in this manner, storage of new numerical data in the corresponding random number value register R1D or random number value register R2D is restricted. For example, when the bit value of the random number latch flag data RDFM0 changes from “0” to “1”, the random number latch flag corresponding to the random number value register R1D is turned on, and new numerical data is stored in the random number value register R1D. Is limited. When the bit value of the random number latch flag data RDFM1 changes from “0” to “1”, the random number latch flag corresponding to the random number value register R2D is turned on, and new numerical data is stored in the random number value register R2D. Is limited. Therefore, the random number latch signal LL1 and / or the random number latch for fetching numerical data corresponding to the input of the start winning signal SS is input to the random value register R1D and / or the random value register R2D in which the corresponding random number latch flag is on. Even when the signal LL2 is input, new numeric data included in the random number sequence RSN cannot be stored.

  Thus, after numerical data is temporarily stored in the random value register R1D or the random value register R2D, before the numerical data is read from the CPU 56 or the like, for example, the start winning signal SS is erroneously turned on due to noise or the like. Even in such a case, the numerical data already stored is updated, and it is possible to prevent the reading of an inaccurate random number value. Further, the bit value of the random value acquisition specification data RDLT0 or the random value acquisition specification data RDLT1 is intentionally set to “1” from the outside, or the start winning signal SS is intentionally turned on from the outside. For example, it is possible to prevent an illegal act such as modifying already stored numerical data. On the other hand, when the numerical data once stored in the random value register R1D or the random value register R2D is not read from the CPU 56 or the like for a long time, when the start winning signal SS is normally turned on thereafter, Accurate numerical data corresponding to the passage (entrance) of the game ball at the start winning opening 14 cannot be stored in the random value register R1D or the random value register R2D.

  Therefore, for example, the CPU 56 of the game control microcomputer 560 executes a predetermined random value register reading process as shown in FIG. 105 (D) when a predetermined random value reading condition is satisfied. Then, the random number value register R1D and the random number value register R2D are read to turn off the random number latch flag, thereby setting a state in which storage of new numerical data is permitted. As the random number value reading condition, the CPU 56 starts executing the game control in the pachinko gaming machine 1 and / or the reserved memory number of the special figure game when the game ball passes (enters) the start winning opening 14. Anything including that the predetermined upper limit value has been reached may be used. In the operation example shown in FIG. 105, in response to the completion of the random value register read processing shown in FIG. 105 (B) at timing T25, random number latch flag data RDFM0 and random number latch as shown in FIG. 105 (C). The bit value of the flag data RDFM1 is updated from “1” to “0”, and the corresponding random number latch flag is set to the off state.

  As an example, the CPU 56 executes a predetermined security check process and the like from the ROM 54 when the system reset of the game control microcomputer 560 is canceled based on the start of power supply in the pachinko gaming machine 1, and then the user program is read from the ROM 54. The control code indicating (game control game control program for game control) is read and the execution of the game control is started. At this time, the CPU 56 reads the numerical data stored in the random value register R1D and the random value register R2D by executing the process of step S5006 shown in FIG. 43 as the random value register read process, and sets the corresponding random number latch flag. Turn off. In the process of step S5006 shown in FIG. 43, the CPU 56 determines whether the random number latch flag is in the ON state based on the result of checking the bit values of the random number latch flag data RDFM1 and the random number latch flag data RDFM0. May be read out only. Alternatively, each random number latch flag may be turned off by reading numerical data from both the random value register R1D and the random value register R2D regardless of whether the random number latch flag is on.

  When the power of the pachinko gaming machine 1 is turned on, various power supply voltages gradually rise to specified values, such as the power supply voltage VSL and the power supply voltage VCC shown in FIGS. 8B and 8C, for example. While such a power supply voltage is rising, some of the various circuits, such as a built-in circuit of the game control microcomputer 560, operate normally, while other parts may not be able to operate normally. As an example, in a state where the power supply voltage is unstable, the start winning signal SS is erroneously turned on. For example, the random number circuit 509 captures and stores numerical data in the random value register R1D or the random value register R2D. There is a possibility that the storage of new numerical data may be restricted due to the corresponding random number latch flag being turned on. Further, after the execution of game control by the CPU 56 or the like is started and before the switch processing of step S21 shown in FIG. 45 is executed, the random number latch signal LL1 and the random number latch signal LL2 are stored at the random value register R1D and the random number latch signal LL2 at a predetermined timing. By inputting to the random value register R2D, there is a possibility that an illegal act of acquiring numerical data indicating a big hit determination random number (random R) with the special figure display result as “big hit” and controlling it to the big hit gaming state may be performed. is there. As described above, when the storage of new numerical data is restricted when the random number latch flag is turned on, an error due to noise or the like occurs after the start winning where the game ball passes (enters) the starting winning opening 14 is generated. Can be prevented from being stored in the random number value register R1D or the random number value register R2D, while the numerical value value is a random number value due to malfunction or fraud due to unstable power supply voltage before the start prize is generated. If the start prize is subsequently generated and stored in the register R1D or the random value register R2D, the numerical data already stored before the start prize is obtained as a random value. There is a possibility that it will be used to determine the special figure display result.

  Therefore, when the system reset in the game control microcomputer 560 is released and the game control is started, the random number latch flag is set to the off state to allow the storage of new numerical data. As a result, for example, the numerical data stored in the random value register R1D or the random value register R2D in error when the power supply voltage is unstable, such as when the power is turned on in the pachinko gaming machine 1, is acquired as a random value, and the game control It can be prevented from being used for various decisions. Further, after the execution of the game control is started, it is possible to prevent an illegal act of inputting the random number latch signal and controlling it to the big hit game state before the state of the start port switch 14a is checked.

  As another example, an on-state power-off signal is output from the power supply monitoring circuit 303 mounted on the power supply board 910 based on a decrease in the predetermined power supply voltage in the pachinko gaming machine 1, such as the power supply voltage VSL. The CPU 56 outputs an on-state power-off signal in step S450 of FIG. 46 (Y in step S450), and further, after the backup monitoring timer value reaches the backup determination value in step S453, the CPU 56 performs steps S454 to S481. By executing the above process to prepare for the unstable operation or operation stop of the pachinko gaming machine 1 due to the decrease in the power supply voltage, the process of step S482 is repeatedly executed until the game control microcomputer 560 is in the operation stop state. The input state of the power-off signal is repeatedly determined. Thereafter, when it is determined during the process of step S482 that the power-off signal is off and is not input, the CPU 56 executes the process of step S487 and then ends the power-off process and the game. By returning from the control timer interrupt process, the execution of the game control is started from the head of the control code indicating the user program (game control process program for game control) stored in the ROM 54. Here, after it is determined in step S482 that the power-off signal has been turned off and has not been input, before the power-off processing is terminated and the execution of game control is started from the beginning of the control code, By executing the processing from step S483 to step S486 as the random value register read processing, the numerical data stored in the random value register R1D or the random value register R2D is read, and the corresponding random number latch flag is set to the OFF state.

  FIG. 106 is a timing chart showing an operation example when the power supply voltage VSL decreases during execution of game control. First, based on the start of power supply to the pachinko gaming machine 1, for example, at a timing T30 before the timing T31 when the power supply voltage VSL shown in FIG. The power supply voltage VCC shown in (B) reaches a predetermined value VCC1. At this timing T30, the reset signal illustrated in FIG. 106C is changed from the on state to the off state. Subsequently, when the power supply voltage VSL reaches the predetermined value VSL1 at the timing T31, the power-off signal illustrated in FIG. Thereafter, for example, at timing T32, the bit value of the random number latch flag data RDFM0 shown in FIG. By changing from “1” to “1”, the random number latch flag corresponding to the random number register R1D is turned on.

  After the numerical data is stored in the random value register R1D at the timing T32 in this way, the power supply voltage VSL shown in FIG. 106A becomes the predetermined value VSL1 at the timing T33 before the numerical data is read by the CPU 56 or the like. Suppose that it is lower. At this time, based on the determination that the power-off signal shown in FIG. 106D is on (Y in step S450 in FIG. 46), is the power-off signal on in step S482? It is repeatedly determined whether or not. Thereafter, for example, at timing T34, when the power supply voltage VSL shown in FIG. 106A returns to the predetermined value VSL1, it is determined in step S482 shown in FIG. 46 that the power-off signal is in an off state and is not input. (N in step S482). Also, in step S483 shown in FIG. 46, based on the determination that the bit value of the random number latch flag data RDFM0 is “1” and the random number latch flag is on, the process of step S484 is executed. Then, the numerical data stored in the random value register R1D is read, the bit value of the random number latch flag data RDFM0 is updated from “1” to “0”, and the random number latch flag corresponding to the random number register R1D is turned off. Set to state. Thereafter, when the power-off process ends, for example, based on the contents specified in the power-off recovery vector table set in step S487 shown in FIG. 46, the user program stored in the ROM 54 (for game control) By starting the execution of the game control from the beginning of the control code indicating the (game control processing program), the main process as shown in FIG. 41 is executed from the beginning.

  In the random number circuit 509, in the case where numerical data that becomes a random number value is captured and stored in the random value register R1D or the random value register R2D in response to the rising edge of the start winning signal SS, for example, as shown in FIG. When the switch operation power supply voltage VDD drops below the predetermined switch voltage during a period in which the process of step S482 is repeatedly executed, and the normal voltage value is restored, a start winning signal is displayed during the restoration to the normal voltage value. A rising edge of SS occurs, and numerical data is captured and stored in all of the random value register R1D and the random value register R2D, and each random number latch flag may be turned on. If such an ON state of the random number latch flag is left unattended, when the game ball passes (enters) through the start winning opening 14 after the power supply voltage is restored and a start winning is generated, the random number latch flag is in the ON state. Numeric values that are captured at timings completely different from the timing of starting winnings, because data storage is limited, and special figure display results are determined based on numeric data captured during power supply voltage recovery, etc. There arises a problem that a decision using data is made. Therefore, the CPU 56 of the game control microcomputer 560 reads the random number value register R1D and the random number value register R2D in step S5006 shown in FIG. 43 and step S484 and / or step S486 shown in FIG. The above-described problem can be solved by starting (resuming) the execution of the game control after turning off.

  As another example of the random value reading condition, there is a case where the reserved memory number of the special-purpose game has reached a predetermined upper limit value when the game ball passes (enters) the start winning opening 14. Here, for example, after it is determined in step S311 shown in FIG. 72 that the start port switch 14a is in the ON state, the number of reserved memories is greater than or equal to a predetermined upper limit (eg, “4”) in step S321 shown in FIG. If it is determined that the hold data is stored in all entries (for example, entries corresponding to the hold numbers “1” to “4”) in the special figure hold memory, the hold in the special figure hold memory Since the data storage number has reached the upper limit storage number, new hold data cannot be stored in the special figure hold memory. In such a case, in general, the starting condition of the special game based on the passing of the game ball through (entering) the start winning opening 14 is not established, and only the winning ball is paid out.

  For this reason, it may be considered not to read out numerical data that is a random value generated by the random number circuit 509. However, in the random number circuit 509, in response to the start winning signal SS being turned on and input regardless of the number of reserved memories, numerical data that becomes a random value is stored in the random value register R1D or the random value register R2D. The data is fetched and stored, and the corresponding random number latch flag is turned on. Then, the next time the game ball passes (enters) through the start winning opening 14, even if the start winning signal SS is turned on and input, new numerical data is stored in the random value register R1D or the random value register R2D. Therefore, it is impossible to obtain an accurate random value corresponding to the occurrence of the start winning.

  On the other hand, when the CPU 56 of the game control microcomputer 560 determines in step S321 shown in FIG. 73 that the reserved storage number is equal to or larger than the predetermined upper limit (Y in step S321), the process of step S326 is performed. Is executed to read the numerical data stored in the random value register R1D or the random value register R2D, thereby turning off the corresponding random number latch flag, and the start port switch passing process is terminated.

  In the main board 31, the security check program 54A stored in the ROM 54 or the like is stored in the ROM 54 or the like when the initial power is supplied from the power board 910 (when power is turned on without a backup power supply) or when the system 56 is restarted after a system reset occurs. Is read and executed, the game control microcomputer 560 enters the security mode. At this time, as a process corresponding to the security check program 54A, for example, a security check process as shown in FIG. 40 is executed. Here, the security time when the game control microcomputer 560 is in the security mode is set in advance in the bit number [2-0] or bit number [4-3] of the security time setting KSES stored in the program management area of the ROM 54. Depending on the stored bit value, a time component different from the fixed time can be included.

  For example, if the bit value in the bit number [2-0] of the security time setting KSES is a value other than “000” (N in step S1002 shown in FIG. 40), the setting contents shown in FIG. Correspondingly, any one of a plurality of extension times that can be selected in advance in addition to the fixed time can be set as a time component included in the security time (step S1004). If the bit value in the bit number [4-3] of the security time setting KSES is a value other than “00” (N in step S1006), the short mode or the long mode as shown in FIG. 14C is supported. Then, a variable setting time that changes in a predetermined time range each time the initial setting process is executed based on system reset or power-on can be set as a time component included in the security time (step S1008).

  Until the security time set in this way has elapsed (N in step S1014), execution of the main process by the user program stored in the ROM 54 is not started. Then, the operation of generating numerical data to be a random number value by the random number circuit 509 may not be started during the period in which the game control microcomputer 560 is in the security mode. As a result, it becomes difficult to specify the operation start timing of the random number circuit 509 or the numerical data to be updated from the operation start timing due to power-on of the pachinko gaming machine 1 or system reset, and the analysis result of the game control processing program By connecting a so-called “hanging board” and inputting a fraud signal at a predetermined timing, it is possible to reliably prevent acts such as illegally generating a big hit gaming state.

  As an example, the bit value in the bit number [2-0] of the security time setting KSES is set to a different value for each model of the pachinko gaming machine 1. In this case, the extension time set in step S1004 shown in FIG. 40 can be made different for each model of the pachinko gaming machine 1, and the operation start timing of the random number circuit 509 is determined from the operation start timing of the pachinko gaming machine 1. It becomes difficult to specify. Further, by setting the bit value in the bit number [4-3] of the security time setting KSES to “01” or “10”, the variable setting time set in step S1008 is changed for each system reset. This makes it extremely difficult to specify the operation start timing of the random number circuit 509 from the operation start timing of the pachinko gaming machine 1.

  When it is determined in step S1014 shown in FIG. 40 that the security time has elapsed (Y in step S1014), the CPU 56 reads the user program stored in the ROM 54, and the main process shown in FIG. 41 is executed. The For example, the setting process in step S14a includes a random number circuit setting process as shown in FIG. Here, if the bit value at the bit number [0] of the second random number initial setting KRS2 as shown in FIG. 13B is set to “1”, the random number circuit 509 is subjected to the processing of step S5005 shown in FIG. The start value of the numerical data, which is a random value generated in this way, can be changed every time the system is reset. Thereby, even if the operation start timing of the random number circuit 509 can be specified, it becomes difficult to specify numerical data read from the random value register 559A and the random value register 559B included in the random number circuit 509. Aiming based on the analysis result of the control processing program, or connecting a so-called `` hanging board '' and inputting an illegal signal at a predetermined timing can reliably prevent acts such as illegally generating a big hit gaming state it can.

  The random number circuit 509 and the like are provided with a free-run counter 554A that updates a count value serving as initial value determination data separately from the operation of the CPU 56. When the bit value [0] of the second random number initial setting KRS2 is “1”, the free run counter 554A is set at the initial setting based on the setting by the start value initial setting circuit 554 of the random number circuit 509. The start value is randomly determined by using the count value as it is, or by using a value obtained by substituting the count value into a predetermined arithmetic function (for example, a hash function). As a result, it becomes difficult to specify the numerical data that will be the start value in the random number circuit 509 from the operation mode of the CPU 56, and aiming based on the analysis result of the game control processing program or connecting a so-called “hanging board” to a predetermined timing By inputting the fraud signal at, actions such as illegally generating a big hit gaming state can be reliably prevented.

  As described above, according to this embodiment, the game control microcomputer 560 determines whether or not an operation signal is input from the clear switch 921 when power supply is started, When it is determined that a signal is input, it is determined whether or not the mechanism plate is in an open state. The game control microcomputer 560 executes an initialization process for initializing the storage contents of the RAM 55 based on the input of the operation signal from the clear switch 921 and the determination that the game control microcomputer 560 is in the open state. On the other hand, the game control microcomputer 560 restricts the execution of the initialization process based on the determination that it is not in the open state even when the operation signal from the clear switch 921 is input. Therefore, illegal actions can be prevented by preventing the initialization process from being executed illegally.

  In addition, according to the present embodiment, a predetermined notification process (for example, the effect display device 9 of the effect display device 9) is detected based on the fact that the input of the operation signal from the clear switch 921 is detected but it is determined that the mechanism plate is not in the open state. Display the initialization fraud notification information on the display screen). Therefore, it is possible to notify that there is a possibility that fraud is being performed, and it is possible to strengthen measures for preventing fraud.

  Further, according to this embodiment, the game control microcomputer 560 shifts to the loop process based on the determination that the game control microcomputer 560 is not in the open state even if the operation signal from the game clear switch 921 is input, and the game Disables execution of control processing. Therefore, if it is detected that there is a possibility that an illegal act is performed, the continuation of the game can be disabled, and measures for preventing the illegal act can be strengthened.

  Further, according to this embodiment, when the payout control microcomputer 370 is set to a predetermined error state (for example, payout switch abnormality detection error 2, payout case error, main control communication error), It is determined whether or not an operation signal is input from the error release switch 375, and when it is determined that an operation signal is input, it is determined whether or not the mechanism plate is in an open state. Then, the payout control microcomputer 370 releases the predetermined error state based on the input of the operation signal from the error release switch 375 and the determination that it is in the open state. On the other hand, the payout control microcomputer 370 restricts the release of a predetermined error state based on the determination that the operation signal from the error release switch 375 is not open even when the operation signal is input. Therefore, also regarding the cancellation of the predetermined error state, it is possible to detect the possibility that fraud is being performed, and to strengthen countermeasures for preventing fraud.

  Further, according to this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 transmit and receive control commands by serial communication. Further, the game control microcomputer 560 sends a connection confirmation command for confirming the communication connection state with the payout control microcomputer 370 every time a predetermined period (1 second in this example) elapses. To 370. The payout control microcomputer 370 transmits a connection OK command to the game control microcomputer 560 based on the reception of the connection confirmation command. In this case, the payout control microcomputer 370 is connected in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error error). The command is transmitted to the game control microcomputer 560. With such a configuration, by using a serial communication method, it is possible to facilitate wiring between the game control microcomputer 560 and the payout control microcomputer 370. In addition, the control state signal (response signal to which the control state is added) is transmitted by placing the control state on the connection OK command that the payout control microcomputer 370 periodically outputs based on the reception of the connection confirmation command. Can do. Therefore, it is possible to prevent the control state signal from being missed without considering the output timing of the control state signal, and the communication between the game control microcomputer 560 and the payout control microcomputer 370 is reliably performed. be able to. In this embodiment, the cycle (interval) for transmitting the connection confirmation command is 1 second, but it may be 0.5 seconds or the like.

  Further, according to this embodiment, the game control microcomputer 560 resets a predetermined period (1 second in this example) to the prize ball process timer when the execution of the payout control is finished, and the prize ball process. Measurement control by the timer is started (see step S52505). If the number of prize balls is not stored (specifically, if no prize ball command output counter has a count value of 1 or more in step S52301), the game control microcomputer 560 resets the game. A new connection confirmation command is transmitted to the payout control microcomputer 370 based on the time-out of the prize ball process timer. For this reason, an interval period can be provided between the end of execution of payout control and the transmission of a new connection confirmation command, and processing at the end of execution of payout control is concentrated, and a new connection check command is overwritten. Can be prevented.

  Further, according to this embodiment, the game control microcomputer 560 transmits a winning ball number command to the payout control microcomputer 370 based on the detection of a winning regardless of the transmission timing of the connection confirmation command. To do. Further, the payout control microcomputer 370 transmits a prize ball number reception command based on the reception of the prize ball number command, and receives a prize ball preparation command during execution of the payout control. The signal is transmitted to the game control microcomputer 560 every signal output period (1 second in this example). In this case, the payout control microcomputer 370 receives the prize ball in such a manner that the game control microcomputer 560 can recognize the control state (in this example, a prize ball error, a full tank error, an out of ball error, and a payout number error error). The preparing command is transmitted to the game control microcomputer 560. Further, the game control microcomputer 560 stops the transmission of the connection confirmation command based on the reception of the prize ball number reception command. Therefore, it is possible to reduce the control burden of the game control microcomputer 560 by not performing connection control command transmission control unnecessarily during execution of payout control. Even when the payout control is being executed, the control state signal can be output by adding the control state to the award ball preparation command, so that the game control microcomputer 560 can recognize the control state. it can.

  Further, according to this embodiment, the game control microcomputer 560 receives the award ball end command and then stores the number of award balls (specifically, the prize ball command output counter in step S52301). If the count value is 1 or more), a new prize ball number command is immediately transmitted to the payout control microcomputer 370 regardless of the transmission of the connection confirmation command. Therefore, it is possible to speed up the execution process of the payout control.

  In addition, according to this embodiment, the game control microcomputer 60 determines whether a predetermined error (in this example, a prize ball error, a full tank error, a full ball error, etc.) based on the control state indicated by the received connection OK command. , And a payout quantity abnormality error). Then, the game control microcomputer 60 transmits a prize ball number command to the payout control microcomputer 370 on the condition that it is determined that a predetermined error has not occurred. Therefore, it is possible to prevent the inconvenience of sending a prize ball number command when the payout control cannot be normally performed due to an error state. In particular, in this embodiment, since the RAM provided in the payout control microcomputer 370 is not backed up by the backup power supply, if a prize ball number command is transmitted when there is an abnormality in the payout control, the power is reset. For example, the memorized number of prize balls may be lost, which may cause a great disadvantage to the player. Therefore, in this embodiment, when there is an abnormality in the payout control, the prize ball number command is transmitted while the memory of the prize ball number is retained on the game control microcomputer 560 side backed up by the backup power source. It is possible to prevent such a disadvantage from occurring by controlling to hold.

  Further, according to this embodiment, the game control microcomputer 560 increases the time interval for transmitting the connection confirmation command when the connection OK command cannot be received after transmitting the connection confirmation command. Whenever a specific period (10 seconds in this example) elapses, the control is switched to the connection confirmation command. Therefore, in a state where the communication state between the game control microcomputer 560 and the payout control microcomputer 370 is unstable, the connection confirmation command transmission process is performed by extending the interval period until the connection confirmation command is transmitted. Can be performed less frequently, and a wasteful processing load can be reduced.

  Further, according to this embodiment, the payout control microcomputer 370 causes the game to occur when a predetermined error (in this example, a prize ball error, a full tank error, a ball shortage error, and a payout number error) occurs. Information that allows the control microcomputer 560 to recognize a predetermined error is set by changing a specific bit of the connection OK command, and the connection OK command in which the setting has been made is transmitted to the game control microcomputer 560. The game control microcomputer 560 transmits a frame state display command in which information capable of recognizing a predetermined error set in the received connection OK command is set as it is to the effect control microcomputer 100. Then, based on the reception of the frame state display command, the production control microcomputer 100 controls the production device (the production display device 9 in this example) to notify that a predetermined error has occurred. Do. Therefore, it is possible to notify that a predetermined error has occurred using the effect device, and to reduce the processing load on the game control microcomputer 560.

  In addition, according to this embodiment, the payout control microcomputer 370 has a payout excess exceeding the number of unpaid game balls to be paid out and the number of unpaid games to be paid out. The number of shortage payouts that did not reach the ball is cumulatively counted using a payout number abnormality counter. When the value of the payout number abnormality counter becomes equal to or greater than a predetermined payout number error error determination value (2000 in this example), the payout control is stopped and the payout stop state is controlled. Therefore, instead of judging each payout control, the payout control is executed by comprehensively judging the payout control executed under an abnormal condition based on the value of the payout number abnormality counter counted up cumulatively. Can be stopped. Therefore, it is possible to more accurately prevent the act of illegally paying out the game ball.

  Further, according to this embodiment, the payout control microcomputer 370 counts up the value of the payout number abnormality counter when a payout shortage number equal to or greater than a predetermined reference number (2 in this example) occurs. Therefore, it is possible to prevent inconvenience that the execution of the payout control is stopped more than necessary. In other words, since there are not a few small numbers (1 in this example) of insufficient payouts in the operating state of the gaming machine, the number of insufficient payouts exceeding the predetermined reference number (2 in this example) has occurred. By counting up on the condition, it is possible to prevent the execution of the payout control from being stopped more than necessary.

  Further, according to this embodiment, the payout control microcomputer 370 executes re-payout control for driving and controlling the ball payout device 97 to pay out only one game ball when a payout shortage occurs. . If the payout of the game ball is not detected even after the re-payout control is executed, the value of the payout number abnormality counter is counted up. Therefore, even if the number of payout shortages is small, it is possible to appropriately stop the execution of payout control by reflecting it in the count value of the payout number abnormality counter, and to take illegal measures to prevent the act of illegally paying out game balls. Can be strengthened.

  Further, according to this embodiment, when the payout number abnormality error is detected and controlled to the payout stop state, the payout stop state is canceled on condition that the power supply of the gaming machine is reset. Therefore, in order to release the payout stop state, the game store clerk must confirm the abnormal state and then perform the release operation. Therefore, the payout stop state is canceled illegally and the game is continued in the abnormal state. This can be prevented.

  Further, according to this embodiment, the RAM 55 provided in the gaming control microcomputer 560 can retain the stored contents for a predetermined period by the backup power supply even when the power supply to the gaming machine is stopped. In addition, when the game control microcomputer 560 is controlled to be in the payout stop state, the game control microcomputer 560 prohibits the transmission of the winning ball number command even if a winning occurs. For this reason, the number of prize balls stored in the RAM 55 (specifically, the value of the prize ball command output counter) is cleared even though the payout is stopped due to an abnormality caused by the gaming machine side that is not caused by fraud. It is possible to prevent such a situation from occurring, and it is possible to prevent the player from being disadvantaged.

  Further, according to this embodiment, the game control microcomputer 560 adds the prize ball number to the prize ball number counter at the timing of sending the prize ball number command, and receives the prize ball information based on the received prize ball information. Subtract 10 from the value of the ball counter. Then, based on the fact that the value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (501 in this example), it is determined that there is a prize ball shortage error. Based on the fact that it is less than the determination value (0 in this example), it is determined that there is an excessive prize ball error. Therefore, the abnormal state can be detected by both the game control microcomputer 560 and the payout control microcomputer 370. Accordingly, it is possible to further strengthen the fraud countermeasure that prevents the act of illegally paying out the game ball.

  Further, according to this embodiment, the game control microcomputer 560 transmits a connection signal indicating a connection state of communication with the payout control microcomputer 370 to the payout control microcomputer 370 via the output port 57. Since the payout control microcomputer 370 can confirm the communication connection state at any timing, the payout of the prize ball is performed when the communication connection state is abnormal. This can be surely prevented.

  In the above embodiment, the game control microcomputer 560 normally transmits a connection confirmation command 1 second after the connection OK command is received, and when a communication error occurs (for example, connection When the OK command cannot be received), the connection confirmation command is transmitted 10 seconds after the connection confirmation command is transmitted, and the period of 1 second or 10 seconds is measured by a timer (a counter configured by software). However, the connection confirmation command may be transmitted by an internal interrupt that occurs when the counter updated as hardware by the internal clock reaches a predetermined value (1 second or 10 seconds). In that case, the counter may be cleared by reception of the connection OK command, or the counter may be cleared if an internal interrupt is generated with a predetermined value.

  Further, according to this embodiment, the random number circuit 590 includes the random number generation circuit 553 and the random number sequence change circuit 555 that update and output numerical data according to a predetermined procedure, and the output numerical data as a random value. The random number value register 559A (R1D) and the random number value register 559B (R2D) to be captured and stored and the random number latch signals LL1 and LL2 based on the start winning signal SS are output from the random number generation circuit 553 and the random number sequence change circuit 555. On the other hand, the stored numerical data is turned on when it is stored in the random value register 559A (R1D) or the random value register 559B (R2D), and storage of new numerical data is restricted, while the random value register 559A (R1D) The numerical data stored in the random value register 559B (R2D) is C at the read timing of the random value. Random latch flag RDFM0 which is turned off to allow the storage of new numerical data when read by U56, and a RDFM1. Further, the game control microcomputer 560 turns off the random number latch flags RDFM0 and RDFM1 when the game control by the CPU 56 is started. Therefore, according to such a configuration, numerical data stored in the random value register 559A (R1D) or the random value register 559B (R2D) is acquired as an accurate random value based on the input of the random number latch signals LL1 and LL2. can do. In addition, it is possible to prevent a situation in which numerical data stored in the random value register 559A (R1D) or the random value register 559B (R2D) is erroneously acquired when the power supplied to the gaming machine is unstable. .

  Further, according to this embodiment, when the system reset of the game control microcomputer 560 is released and the execution of the game control by the CPU 56 is started, the random number latch flags RDFM0 and RDFM1 are turned off. Therefore, for example, the numerical data stored in the random value register 559A (R1D) or the random value register 559B (R2D) is erroneously acquired as a random value when the power supply voltage is unstable, such as when the power is turned on. Can be prevented.

  Also, according to this embodiment, the game control microcomputer 560 repeatedly determines the input state of the detection signal until the operation stop state after the detection signal is output from the power supply monitoring circuit 920, and the detection signal When it is determined that is not input, execution of game control is started from the beginning of the game control processing program. In addition, the game control microcomputer 560 turns off the random number latch flags RDFM0 and RDFM1 after it is determined that the detection signal is not input and before the execution of the game control is started from the head of the game control processing program. Put it in a state. Therefore, for example, numerical data stored in the random value register 559A (R1D) or the random value register 559B (R2D) by mistake when the power supply voltage is unstable such as when the predetermined power supply voltage drops is obtained as a random value. Can be prevented.

  Further, according to this embodiment, the random number generation circuit 553 and the random number sequence change circuit 555 cyclically numerical data from a predetermined update initial value to a predetermined update final value within a predetermined range in which the numerical data can be updated. Update. Further, the game control microcomputer 560 can variably set a predetermined update initial value every time the game control microcomputer is reset. For this reason, it becomes difficult to specify numerical data that becomes a random value after the occurrence of a system reset, and it is possible to reliably prevent fraudulent acts such as aiming.

  In addition, according to this embodiment, after the power supply to the gaming machine is started, the free run counter 554A that counts the numerical value separately from the operation of the CPU 56 is provided. In addition, the game control microcomputer 560 determines a predetermined update initial value using the numerical value counted by the free-run counter 554A. Therefore, it becomes difficult to specify numerical data that is a random number value from the operation mode of the CPU 56, and it is possible to reliably prevent fraudulent acts such as aiming.

  In addition, according to this embodiment, game control microcomputer 560 includes internal resource access control circuit 501A for restricting external reading of nonvolatile memory (ROM 54) by other than CPU 56. Therefore, it becomes difficult to read out the control program stored in the non-volatile memory (ROM 54) from the outside of the game control microcomputer 560 and analyze it, and so on. Unauthorized acts caused by connecting the “hanging board” can be surely prevented.

  Further, according to this embodiment, the random number clock generation circuit 112 that generates a random number clock signal outside the game control microcomputer 560 and supplies the random number clock signal to the random number circuit, and the control clock supplied to the CPU 56 A control clock generation circuit 111 and a clock circuit 502 that generate signals are provided. The game control microcomputer 560 compares the input state of the random number clock signal supplied from the random number clock generation circuit 112 with the control clock signal generated by the control clock generation circuit 111 or the clock circuit 502. Thus, it is determined whether or not an abnormality has occurred in the input state of the random number clock signal. Therefore, it is possible to prevent the game control from being executed in a state where an abnormality has occurred in the operation of updating the numerical data that becomes the random value.

  Further, according to this embodiment, the game control microcomputer 560 executes a security check that checks whether or not the storage content of the nonvolatile memory (ROM 54) has been changed in a predetermined initial setting. The game control microcomputer 560 is configured to be able to variably set the security check execution time. Therefore, it becomes difficult to specify the execution start timing of the game control, and it is possible to reliably prevent a sniper based on an analysis result such as an initial setting operation or an illegal act by connecting a so-called “hanging board”. .

  In addition, according to this embodiment, the game control microcomputer 560, when the number of reserved storage in the special figure reservation memory reaches a predetermined upper limit number (for example, 4) at the read timing of the random number value, By reading the numerical data stored in the random value register 559A (R1D) and the random value register 559B (R2D), the random number latch flags RDFM0 and RDFM1 are turned off. Therefore, after the reserved storage number reaches the predetermined upper limit number, when the random number value is read out after the number becomes less than the upper limit number, it is accurate based on the input of the random number latch signals LL1 and LL2 based on the start winning signal SS Random numbers can be obtained.

  In the above embodiment, the case where the pachinko machine is applied as the gaming machine according to the present invention has been described. However, the parrot machine can also be applied as the gaming machine according to the present invention. In this case, when the configuration shown in the above embodiment is applied and power supply is started, it is determined whether or not an operation signal is input from the clear switch, and the operation signal is input. When it is determined, it may be determined whether or not the gaming machine is in an open state in which it can be contacted from the outside. An initialization signal is input based on the determination that the operation signal is input from the clear switch and the open state, and the operation signal is not open even if the operation signal is input from the clear switch. The execution of the initialization process may be limited.

  Hereinafter, embodiments of the slot machine will be described with reference to the drawings (FIGS. 107 and 108). As shown in FIG. 107, the slot machine 601 of the present embodiment (modified example) includes a housing (not shown) having an open front surface, a front door pivotally supported on a side end of the housing, It is composed of

  Inside the casing of the slot machine 601 of the present embodiment, reels 602L, 602C, and 602R (hereinafter also referred to as a left reel, a middle reel, and a right reel) in which a plurality of types of symbols are arranged on the outer periphery are arranged in parallel in the horizontal direction. As shown in FIG. 107, three consecutive symbols out of the symbols arranged on the reels 602L, 602C, and 602R are arranged so as to be seen from the see-through window 603 provided on the front door.

  For example, “red 7 (outline 7 in the figure)”, “BAR”, “replay”, “watermelon”, “cherry”, “bell” can be distinguished from each other on the outer periphery of the reels 602L, 602C, 602R. A plurality of types of symbols are drawn 21 in a predetermined order. The symbols drawn on the outer peripheries of the reels 602L, 602C, and 602R are displayed on the perspective window 603 in upper, middle, and lower three stages.

  The reels 602L, 602C, and 602R are provided in correspondence with each other and are rotated by reel motors 632L, 632C, and 632R (see FIG. 108), so that the symbols of the reels 602L, 602C, and 602R are continuously provided in the see-through window 603. In addition to being displayed while changing, by stopping the rotation of the reels 602L, 602C, and 602R, three continuous symbols are derived and displayed on the fluoroscopic window 603 as display results.

  Further, on the front door, a medal insertion unit 604 capable of inserting medals, a medal payout exit 609 from which medals are paid out, and credits (the number of medals stored as a player's own game value) are used for one medal. A single bet switch 605 that is operated when setting the bet number of the bet, and using a credit, a specified number of bet numbers determined according to the game state within the range (in this embodiment, in the normal game state, “ 3 ”, MAXBET switch 606 operated when setting“ 1 ”for the regular bonus), medals stored as credits and the medals used for setting the bet amount are settled (for setting the credit and bet number) A check switch 610 operated when the medal used is returned), a start switch 607 operated when starting the game, Le 602L, 602C, stop switch 608L is operated to stop each rotation of the 602R, 608C, 608R are provided.

  Also, on the front door, a credit indicator 611 that displays the number of medals stored as credits, a game that displays the number of medals acquired in a big bonus, which will be described later, and an error code indicating the contents when an error occurs, etc. An auxiliary indicator 612 and a payout indicator 613 for displaying the number of medals paid out due to the occurrence of a winning are provided.

  Also, on the front door, 1 BETLED 614 that notifies that the bet number is set by 1 is lit, 2 BETLED 615 that notifies that the bet number is set is 2 and lit that 3 bets are set 3BETLED 616 to be notified by, lighting request LED 617 to notify that the medal can be inserted by lighting, start valid LED 618 to notify that the game start operation by operating the start switch 607 is effective, weight (previous game) (Waiting to start reel rotation since a certain period of time has not elapsed since the start) LED 619 during waiting to notify that it is on, LED during replay 620 to notify that it is in a replay game to be described later Is provided.

  Further, inside the MAXBET switch 606, a BET switch valid LED 621 (see FIG. 108) is provided to notify that the bet number setting operation by the operation of the single BET switch 605 and the MAXBET switch 606 is valid. In the stop switches 608L, 608C, 608R, the left, middle, and right stop valid LEDs 622L, 622C, 622R that notify that the reel stop operation by the corresponding stop switches 608L, 608C, 608R is valid are turned on. (See FIG. 108).

  A liquid crystal display 651 capable of displaying an effect image or the like related to a game is provided at the upper center position inside the front door, and a display image displayed on the display screen through a liquid crystal display window 670 disposed in front of the liquid crystal display 651. Can be visually recognized. Further, on the left and right sides of the liquid crystal display 651, two movable accessories 675L and 675R that perform effects related to the game are respectively disposed, and are disposed in front of the left and right movable combinations 675L and 675R. As described above, the internal movable accessory 675L and 675R can be seen through from the production perspective windows 671L and 671R made of a transparent panel provided on the front door.

  Further, between the left and right movable combination objects 675L and 675R and the production perspective windows 671L and 671R, there is a concealment state in which the left and right movable combinations 675L and 675R are hidden from the production perspective windows 671L and 671R so that they cannot be seen through. , Endless shutter sheets constituting two shutter devices (not shown) that can be changed to a non-hidden state in which the left and right movable accessories 675L and 675R can be seen through the production perspective windows 671L and 671R are arranged. It is installed.

  Further, inside the front door, a reset switch 623 for detecting a reset operation for canceling an error state and a stop state excluding a RAM abnormality error by a predetermined key operation, changing a set value or checking a set value Set value display 624 for displaying the set value at that time, and the flow path of medals inserted from the medal insertion unit 604, the hopper tank (not shown) side provided inside the housing or the medal payout outlet 609 side A flow path switching solenoid 630 for selectively switching to any one of the above, a insertion medal sensor 631 for detecting a medal that has been inserted from the medal insertion unit 604 and flowed down to the hopper tank side is provided.

  Inside the casing, a reel unit (not shown) including reel sensors 633 capable of detecting the reel reference positions of the reels 602L, 602C, 602R, reel motors 632L, 632C, 632R, and reels 602L, 602C, 602R, respectively. , A hopper tank (not shown) for storing medals inserted from the medal insertion unit 604, a hopper motor 634 for paying out medals stored in the hopper tank from the medal payout outlet 609, and the hopper motor 634 being paid out. A payout sensor 635 for detecting a medal and a power supply box (not shown) are provided.

  On the front face of the power supply box, a stop switch 636 for selecting enable / disable of a stop function for controlling the stop state at the end of the big bonus (a state in which the progress of the game is restricted until a reset operation is performed), An automatic checkout switch 629 for selecting whether the automatic checkout function is valid / invalid for controlling automatic checkout processing (processing for adjusting (returning) medals stored as credits regardless of the player's operation) at the end of the big bonus, Setting key switch 637 for switching to the setting change mode at startup, functioning as a reset switch for canceling an error state or a stop state except for a RAM abnormality error in normal times, and winning probability of internal lottery in the setting change mode A reset / setting switch 638 that functions as a setting switch for changing the setting value of (delay rate) Power switch 639 is operated to ON / OFF the power is provided.

  When a game is played in the slot machine 601 of this embodiment, first, medals are inserted from the medal insertion unit 604, or credits are used to set the number of bets. In order to use the credit, the single BET switch 605 or the MAX BET switch 606 may be operated. When a predetermined number of bets determined according to the gaming state are set, the pay lines L1 to L5 (see FIG. 107) become valid, and the operation of the start switch 607 is valid, that is, the game can be started. It becomes a state. In the present embodiment, as the specified number of bets, three are determined in the normal gaming state, and one is determined in the regular bonus. If medals are inserted beyond the prescribed number corresponding to the gaming state, the amount is added to the credit.

  When the start switch (also referred to as a lever) 607 is operated while the game can be started, the reels 602L, 602C, and 602R rotate, and the symbols of the reels 602L, 602C, and 602R continuously change. When any one of the stop switches 608L, 608C, and 608R is operated in this state, the rotation of the corresponding reels 602L, 602C, and 602R is stopped, and the display result is derived and displayed on the fluoroscopic window 603.

  Then, when all the reels 602L, 602C and 602R are stopped, one game is completed, and a predetermined symbol combination (hereinafter also referred to as a role) is set on any of the activated pay lines L1 to L5. When the reels 602L, 602C, and 602R are stopped as a display result, a winning occurs, and a predetermined number of medals are awarded to the player and added to the credit. Further, when the credit reaches the upper limit (50 in this embodiment), medals are paid out directly from the medal payout exit 609 (see FIG. 107). If a combination of symbols with a medal payout is available on a plurality of activated pay lines, the total number of payouts determined for each combination of symbols on the activated pay line is totaled. The total number of medals is awarded to the player. However, an upper limit (15 in this embodiment) is set for the number of medals to be awarded in one game. When the total number of medals exceeds the upper limit, the upper limit number of medals is awarded. The Rukoto. In addition, when a combination of symbols accompanying the transition of the gaming state is stopped as a display result of each reel 602L, 602C, 602R on any of the activated pay lines L1 to L5, a game corresponding to the combination of symbols Transition to the state.

  FIG. 108 is a block diagram showing the configuration of the slot machine 601. As shown in FIG. 108, the slot machine 601 includes a game control board 640 (corresponding to the game control board (main board) 31 of FIG. 4), an effect control board 690 (corresponding to the effect control board 80 of FIG. 4), a power supply The board 600 is provided, the gaming state is controlled by the game control board 640, the presentation according to the gaming state is controlled by the presentation control board 690, and the power supply board 600 is used to drive electric power for the electrical components constituting the slot machine 601. Generated and supplied to each unit.

  The game control board 640 is connected to the one-sheet BET switch 605, the MAXBET switch 606, the start switch 607, the stop switches 608L, 608C, and 608R, the settlement switch 610, the reset switch 623, the insertion medal sensor 631, and the reel sensor 633. In addition, the above-described payout sensor 635, stop switch 636, automatic settlement switch 629, setting key switch 637, and reset / setting switch 638 are connected via the power supply board 600, and detection of these connected switches is detected. A signal is input.

  The game control board 640 includes the credit display 611, the game auxiliary display 612, the payout display 613, 1 to 3 BET LEDs 614 to 616, the insertion request LED 617, the start valid LED 618, the waiting LED 619, the replaying LED 620, and the BET. A switch valid LED 621, left, middle, and right stop valid LEDs 622L, 622C, and 622R, a set value display 624, a flow path switching solenoid 630, and reel motors 632L, 632C, and 632R are connected to each other, and are described above via the power supply board 600. The hopper motor 634 is connected, and these electric components are driven based on control of a main control unit 641 (corresponding to the game control microcomputer 560 of FIG. 4) described later mounted on the game control board 640. Like That.

  The game control board 640 includes a microcomputer having a CPU 641a, ROM 641b, RAM 641c, and I / O port 641d. A main control unit 641 for controlling the game, random numbers in a predetermined range (0 to 16383 in this embodiment) Random number generation circuit 642 for generating, sampling circuit 643 for obtaining random numbers from the random number generation circuit, detection signals input from switches such as sensors and switches connected directly to game control board 640 or via power supply board 600 Switch detection circuit 644, a motor drive circuit 645 that controls the drive of the reel motors 632L, 632C, and 632R, a solenoid drive circuit 646 that controls the drive of the flow path switching solenoid 630, various displays connected to the game control board 640, LED drive circuit for LED drive control 47. The power supply voltage supplied to the slot machine 601 is monitored, and when a voltage drop is detected, a power drop detection circuit 648 that outputs a voltage drop signal indicating that to the main control unit 641, A reset circuit 649 for providing a reset signal to the CPU 641a when an initialization command is not input from the CPU 641a, and other various devices and circuits are mounted.

  The CPU 641a transmits various commands to the effect control board 690 via the I / O port 641d. A command transmitted from the game control board 640 to the effect control board 690 is sent in only one direction, and no command is sent from the effect control board 690 to the game control board 640. A transmission line for commands transmitted from the game control board 640 to the effect control board 690 includes a strobe (INT) signal line, a data transmission line, and a ground line, and is connected via the effect relay board 680. The game control board 640 and the effect control board 690 are not directly connected.

  On the effect control board 690, a liquid crystal display 651 (see FIG. 107) disposed on the front door of the slot machine 601, an effect LED 652, speakers 653 and 654, a reel LED 655, a shutter motor 810, a shutter sensor 811, and a movable object Electrical components such as the LED 881, the movable object motor 805, and the movable object sensor 829 are connected, and these electrical components are driven based on control by a later-described sub-control unit 691 mounted on the effect control board 690. It is like that.

  The effect control board 690 is composed of a microcomputer having a CPU 691a, a ROM 691b, a RAM 691c, and an I / O port 691d in the same manner as the main control part 641, and includes a sub-control part 691 for effect control and an effect control board 690. A liquid crystal drive circuit 692 that controls the drive of the connected liquid crystal display 651, an effect effect LED 652, a reel LED 655, an LED drive circuit 693 that controls the drive of the movable object LED 881, and a sound that controls audio output from the speakers 653 and 654. Output circuit 694, detection signal input from switches such as a reset circuit 695 that provides a reset signal to the CPU 691a when the power is turned on or when an initialization command is not input from the CPU 691a, a shutter sensor 811, a movable object sensor 829, and switches Detect the switch The CPU 691a receives a command transmitted from the game control board 640, and is mounted with a motor driving circuit 697 for controlling the driving of the H detection circuit 696, the shutter motor 810, and the movable object motor 805. In addition to performing various controls for performing effects, each part of the control circuit mounted on the effect control board 690 is controlled directly or indirectly.

  Next, the internal lottery process executed by the main control unit 641 will be described. At the timing when the start switch 607 is turned on, the sampling circuit 643 acquires (extracts) a numerical value (random number) counted by the random number generation circuit 642. The sampling circuit 643 outputs the numerical value acquired as a random number to the CPU 641a in the main control unit 641.

  The CPU 641a in the main control unit 641 uses the numerical value acquired from the sampling circuit 643 and the determination value set for each combination (small combination, replay combination, special combination, etc.) in the internal lottery table stored in the ROM 641b. By comparing, it is determined whether or not a small role / replaying role / special role is won. Further, as a table for internal lottery, a plurality of tables are provided so that the medal payout rate changes according to the set value / game state (normal game state, regular bonus). For example, in the internal lottery table, a plurality of judgment values are set for each of a small combination (cherry, bell), a re-playing combination (replay), a special combination (regular bonus, big bonus), and a loss. Further, for example, when “1” to “6” are provided as setting values that can be set by the reset / setting switch 638, the determination value is assigned so that the medal payout rate changes as the setting value number increases. Table is used. In addition, when the gaming state is a normal gaming state, a table in which a judgment value is assigned to each of the roles and outliers so that any of the small roles, replaying roles, and special roles can be won is used. In the case of a regular bonus, a table in which judgment values are assigned to the small role and the offside so that only the small role can be won (a table in which no judgment value is assigned to the replaying role / special role) is used. . The setting of the determination value in the above table is an example, and the determination value is not limited to such setting. In this embodiment, the number of bets can be set by the player only “3” in the normal gaming state and “1” in the regular bonus, but either of the normal gaming state or the regular bonus can be set. Even in the gaming state, any one of “1” to “3” can be set by the player as the bet number. A plurality of internal lottery tables having different winning probabilities for replaying and special roles may be prepared, and internal lottery may be performed using tables corresponding to the number of bets.

  As described above, in the slot machine 601 of this embodiment, the medal payout rate changes according to the set value, and the winning probability of the internal lottery is determined according to the set value.

  In the slot machine 601 of the present embodiment, the prescribed number of bets that can be set is determined according to the gaming state as described above, and the prescribed number of bets determined according to the gaming state is set. It becomes possible to start the game on the condition. In this embodiment, there are a regular bonus and a normal gaming state as the gaming state. Among these, 1 is defined as the prescribed number of bets corresponding to the regular bonus, and the prescribed number of bets corresponding to the normal gaming state is as follows. 3 is defined. For this reason, when the gaming state is a regular bonus, the game can be started when the betting number is set to 1, and when the gaming state is the normal gaming state, the game is started when the betting number is set to 3. Can be started. In this embodiment, when a specified number of bets corresponding to the gaming state is set, all winning lines L1 to L5 are activated, and the specified number corresponding to the gaming state is If it is 1, all winning lines L1 to L5 are activated when 1 is set as the bet number, and if the specified number is 3 according to the gaming state, 3 is set as the bet number. All winning lines L1 to L5 are activated.

  In the slot machine 601 of this embodiment, when all the reels 602L, 602C, and 602R are stopped, the winning line that is activated (in the case of this embodiment, all the winning lines are always activated. The activated winning line is simply referred to as a winning line), and a winning combination is obtained when a combination of symbols called “comb” is arranged. The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that can start the next game without the need to set the number of bets. There are a game combination and a special combination with a transition of the game state. Below, a small role and a re-playing role are collectively called a general role. In order for winning of each combination determined according to the game state to occur, it is necessary to win an internal lottery and the winning flag of the combination must be set in the RAM 641c.

  Of the winning flags for each of these combinations, the winning flag for the small role and the re-playing role is valid only in the game in which the flag is set, and is invalid in the next game. It is valid until the combination of combinations permitted by the flag is complete, and is invalid in a game having the combination of combinations permitted. In other words, once the special combination winning flag is won, even if the combination of the combination permitted by the flag cannot be made, the winning flag is not invalidated and is carried over to the next game. It becomes. As described above, in the slot machine 601 according to the present invention, when it is determined by the prize predetermining means that the generation of the specific prize is permitted and the specific prize display result is not derived to the prize variable display section, There is a carry-over means for carrying over the decision to allow the generation of a prize from the next game. In such a configuration, even when the specific winning display result is not derived to the winning variable display section, the decision to allow the occurrence of the specific winning is carried over from the next game onward, A loss to the player can be prevented.

  As a combination in the slot machine 601, a big bonus and a regular bonus are defined as a special combination, cherry and bell are defined as a small combination, and replay is defined as a re-playing combination. In addition, as a combination of combinations in the slot machine 601, big bonus + cherry and regular bonus + cherry are determined. That is, the total of the combination of the combination and combination is 7.

  In the slot machine 601 of the present embodiment, the combination of combinations and combinations of combinations that are subject to lottery differ depending on whether the gaming state is a normal gaming state or a regular bonus. Furthermore, when the gaming state is the normal gaming state, it depends on whether any special role is being carried over (whether any special role has already been set in the winning flag of the special role). The combination of combinations and combinations that are subject to lottery are also different. In this embodiment, a state number corresponding to the gaming state is assigned, and when performing an internal lottery, a state number corresponding to the current gaming state is set, and a role to be a lottery object is determined according to this state number. It becomes possible to specify. Specifically, when no special combination is carried over in the normal gaming state, “0” is set as the state number, and when any special combination is carried over in the normal gaming state, “1” is set as the state number, and “2” is set as the state number in the case of a regular bonus.

  When the gaming state is a normal gaming state and no special role is carried over, that is, when the state number is set to “0”, a big bonus, a regular bonus, a big bonus + cherry, a regular bonus + Cherry, replay, cherry, bell, that is, all combinations and combinations of combinations are subject to internal lottery. In addition, when the game state is the normal game state and any special combination is carried over, that is, when the state number is set to “1”, a combination of replay, cherry, bell combination and combination Is subject to internal lottery. Further, when the game state is a regular bonus, that is, “2” is set as the state number, the combination of cherry and bell and combinations of combinations are targeted for internal lottery.

  Cherry is awarded when the “Cherry” symbol is derived on one of the winning lines for the left reel in any gaming state, and two medals are paid out in the normal gaming state. 15 medals are paid out. If the “Cherry” symbol stops at the upper or lower level of the left reel, the combination of cherries will be aligned on the two winning lines L2 and L4 or the winning lines L3 and L5. Since you won the cherry on the winning line, 4 medals will be paid out in the normal gaming state, but in the regular bonus, even if you win the cherry on the 2 winning lines, one game Since the upper limit of the number of medals to be paid out at 15 is set to 15, only 15 medals are paid out. A bell is awarded when a combination of “Bell-Bell-Bell” is placed on any of the winning lines in any gaming state, and in the normal gaming state, 8 medals are paid out. 15 medals are paid out.

  Replay is awarded when a combination of “replay-replay-replay” is arranged on any of the winning lines in the normal gaming state. When a replay is won, the medals will not be paid out, but the next game can be started without setting the number of bets again, so the number of bets no longer required to be set in the next game (the regular bonus will not be replayed and will always be 3) This is substantially the same as when three corresponding medals are paid out.

  The regular bonus is awarded when a combination of “red 7-red 7-BAR” is arranged on any of the winning lines in the normal gaming state. When the regular bonus is won, the gaming state shifts from the normal gaming state to the regular bonus. The regular bonus ends when 12 games are consumed, or when 8 games are won (any kind of combination is possible), whichever comes first. While the game state is the regular bonus, the regular bonus medium flag is set in the RAM 641c.

  The big bonus is awarded when a combination of “red 7-red 7-red 7” is aligned on any of the winning lines in the normal gaming state. When the big bonus is won, the gaming state shifts to the big bonus. When transitioning to the big bonus, the transition to the regular bonus is performed at the same time as the transition to the big bonus. Controlled by regular bonus. That is, during the big bonus, the regular bonus is always controlled. The big bonus ends when the total number of medals paid out to the player in the big bonus exceeds 465. At this time, the regular bonus is ended regardless of whether the regular bonus end condition is satisfied. While the gaming state is the big bonus, the big bonus medium flag is set in the RAM 641c.

  The regular bonus and the big bonus described above may be collectively referred to simply as “bonus”.

  In addition, in the reels 601L, 601C, and 601R in FIG. 107, only the white symbol 7 is drawn, but the illustration is omitted, and the reels 601L, 601C, and 601R are actually also surrounded by dotted lines. The design is drawn.

  In the slot machine 601 of the present embodiment, there is a possibility that a small role, a re-playing role or a special role (bonus) is won in the internal lottery (a small role, a re-playing role or a special role is won by winning the internal lottery). Suggestive effects suggesting that there is a possibility that the winning flag is set in the RAM 641c) on the stage members (liquid display 651, movable right and left movable parts 675L, 675R, etc. of the liquid crystal display 651). To be executed. In particular, based on the fact that it is determined that the special combination is allowed to be generated by the internal lottery process (a state in which the internal lottery is won and the special combination winning flag is set in the RAM 641c), the CPU 691a displays the liquid crystal display. The suggestion effect is executed so that a specific display result (for example, “7, 7 and 7” are aligned) is obtained as a combination of the left, middle, and right symbols Z1 to Z3 displayed on the display screen of the device 651. .

  Note that the gaming state advantageous to the player is not limited to the above big bonus and regular bonus, but for example, a notification target winning that occurs on condition that reel deriving conditions (for example, stop order or stop timing) are satisfied. When a stop switch 606L, 606C, or 606R is operated by limiting a game state (so-called assist time (AT)) in which an operation procedure that satisfies a derivation condition is notified or at least one of the reels is retracted. Control the displayed symbols to be easy to stop, and the challenge time (CT) that allows the player to derive a combination of winning symbols by pushing forward, specific winnings (for example, replay winnings and singles) Gaming state (so-called replay time (RT) Middle state), and further, a game state (for example, ART that combines assist time and replay time) may be mounted, and the suggestion producing means establishes a transition condition for shifting to these game states. The suggestion effect may be performed so that a specific display result is obtained based on what is being performed.

  Further, the type of specific display result may be different depending on the type of gaming state where the transition condition is satisfied. (For example, “7 ・ 7 ・ 7” or “3 ・ 3 ・ 3” is based on the fact that the big bonus was won as a special role in the internal lottery, and the regular bonus was won as a special role in the internal lottery. “3.3.3” is prepared, and “1.1.1” is prepared based on the fact that the transition condition for shifting to the replay time (RT) is satisfied.)

  In addition, in embodiment shown above, the characteristic structure of the gaming machine as shown to the following (1)-(33) is also shown.

(1) A gaming machine can use a game medium (for example, a game ball) to allow a player to play a predetermined game, and a predetermined payout condition is satisfied (for example, a game ball wins a winning opening) A gaming machine that pays out game media based on a game control microcomputer that controls the progress of the game (for example, a game control microcomputer 560), and a payout means that pays out game media (for example, , A ball payout device 97) and a payout control microcomputer (for example, a payout control microcomputer 370) for controlling the payout means. The game control microcomputer and the payout control microcomputer are connected by serial communication. For example, the game control microcomputer 560 and the payout control microcomputer 370 are connected to each other. Each serial communication circuit 511, 380 is built in and the payout control command shown in FIG. 41 is transmitted / received by serial communication), and the game control microcomputer determines whether or not a predetermined period (for example, 1 second) has elapsed. A connection confirmation signal (for example, a connection confirmation command) for confirming a communication connection state between the predetermined period determination means (for example, the part for executing step S52313 in the game control microcomputer 560) and the payout control microcomputer. The connection confirmation signal output means for outputting to the payout control microcomputer every time it is determined by the predetermined time period determination means that the predetermined time period has elapsed (for example, after the game control microcomputer 560 determines Y in step S52313, step S5211). And the predetermined payout conditions Payout number data (for example, prize balls) that can specify the number of prize game media (for example, the number of prize balls) as prizes to be paid out based on the establishment (for example, that the game balls have won a prize opening) The number of prize game media to be paid out is specified based on the number-of-payout storage means (for example, a prize ball command output counter) that stores the command output counter) and the number-of-payout data stored in the number-of-payout storage means. A payout number signal output means for outputting a possible payout number signal (for example, a prize ball number command) to the payout control microcomputer (for example, a part for executing step S52305 in the game control microcomputer 560), and a payout number signal output. The output of the connection confirmation signal by the connection confirmation signal output means is stopped based on the output of the number-of-payout signal by the means. Stop means (for example, in the game control microcomputer 560, after the prize ball number command is transmitted in step S52305 of the prize ball transmission process 2, the prize ball is received without moving to the prize ball transmission process 1 for transmitting the connection confirmation command. A part for stopping the transmission of the connection confirmation command by shifting to the confirmation process (see step S52306). For example, the game control microcomputer 560 performs a process of transmitting a connection confirmation command only in the prize ball transmission process 1 shown in FIG. 61 (see step S5211), and moves to after the prize ball number command is transmitted, as shown in FIG. In the ball receipt confirmation process, a process for transmitting a connection confirmation command is not performed. The payout control microcomputer outputs a response signal (for example, a connection OK command) to the game control microcomputer based on the input of the connection confirmation signal output from the connection confirmation signal output means. The number of unpaid premium game media specified by the payout number signal output by the signal output means (for example, the part for executing steps S7415 and S74208 in the payout control microcomputer 370) and the payout number signal output means is paid out. Game medium payout control means for executing payout control for driving and paying out the means (for example, the payout motor 289 is activated by executing the processing in step S75113 in the payout control microcomputer 370, and the payout motor control in step S756) Processing part), and a response signal output The means outputs a response signal to the game control microcomputer in such a manner that the game control microcomputer can recognize the control state (for example, the payout control microcomputer 370 executes the processes of steps S7414 and S74207, As shown in FIG. 45, a prize ball error, a full tank error, a ball shortage error, a payout number error error are set in the lower 4 bits of the connection OK command and transmitted), and the game control microcomputer further executes the payout control. When the process is finished, the number-of-payout data determination means for determining whether or not the number-of-payout data is stored in the number-of-payout storage means (for example, it is determined as Y in step S52503 in the game control microcomputer 560 and step S52504 is executed). Step S52 when the process proceeds to the prize ball transmission process 2 The payout number signal output means stores the payout number data in the payout number storage means when the payout number data determination means determines that the payout number data is stored in the payout number storage means. Based on the stored payout number data, a new payout number signal is output to the payout control microcomputer (for example, the game control microcomputer 560 executes step S52305 based on the determination of Y in step S52301). A new prize ball number command), and the connection confirmation signal output means determines the predetermined period when the payout number data determination means determines that no payout number data is stored in the payout number storage means. Based on the determination that the predetermined period has passed, a new connection confirmation signal is output to the dispensing control microcomputer. (For example, the game control microcomputer 560 determines N in step S52301, then becomes Y in step S52313, shifts to prize ball transmission processing 1, and executes step S5211 to transmit a new connection confirmation command. You may put it configured. According to such a configuration, it is possible to facilitate the wiring of the game control microcomputer and the payout control microcomputer by using the serial communication method. In addition, a control state signal (a response signal to which a control state is added) can be output by adding a control state to a response signal periodically output by the payout control microcomputer based on the input of the connection confirmation signal. Therefore, it is possible to prevent the control state signal from being missed without considering the output timing of the control state signal, and to reliably perform communication between the game control microcomputer and the payout control microcomputer. it can.

(2) The predetermined period determining means determines whether or not the predetermined period has elapsed using a measurement timer (for example, a prize ball process timer) for measuring the predetermined period (for example, the game control microcomputer 560 is Then, after setting the connection confirmation time 1 (1 second) to the prize ball process timer in step S5226, the processing of step S52313 is executed.) When the game control microcomputer finishes executing the payout control, the measurement timer Measurement timer start means for resetting a predetermined period to start measurement control by the measurement timer (for example, the connection confirmation time 1 (1 second) is set in the award ball process timer in step S52505 in the game control microcomputer 560) Thereafter, the process proceeds to the prize ball transmission process 2 and the measurement of step S52313 is started). The signal output means is based on the fact that the measurement timer reset by the measurement timer start means has timed out when it is determined by the payout number data determination means that the payout number data is not stored in the payout number storage means. A new connection confirmation signal is output to the payout control microcomputer (for example, when the game control microcomputer 560 becomes Y in step S52313, the process shifts to prize ball transmission processing 1 and executes step S5211). It may be configured. According to such a configuration, an interval period can be provided between the end of execution of payout control and the output of a new connection confirmation signal, and processing at the end of execution of payout control is concentrated and new It is possible to prevent the connection confirmation signal from being lost.

(3) The payout number signal output means outputs a payout number signal to the payout control microcomputer based on the fact that a predetermined payout condition is satisfied regardless of the output timing of the connection confirmation signal by the connection confirmation signal output means. (For example, the game control microcomputer 560 executes step S52305 when Y in step S52301 regardless of the transmission timing of the connection confirmation command), and the game medium payout control means outputs the payout number signal output means. The payout control is started based on the input of the payout number signal (for example, the payout control microcomputer 370 determines the number of prize balls designated by the prize ball number command in steps S74214 and S74319 as the number of unpaid balls. Set to the counter, and the value of the unpaid-out number counter is 0 in step S75109. The payout motor 289 is activated based on the fact that the payout motor 289 is activated), and the payout control microcomputer inputs the payout number signal output from the payout number signal output means. A reception signal output means for outputting a reception signal (for example, a prize ball number reception command) indicating that a number signal has been input to the game control microcomputer (for example, a part for executing steps S74215 and S74320 in the payout control microcomputer 370) ) And a payout signal (for example, a prize ball preparation command) indicating that the payout control is being executed during execution of the payout control for each predetermined payout signal output period (for example, 1 second). Payout signal output means for outputting to the microcomputer for use (for example, a microcomputer for payout control) A portion for executing steps S74222, S74313, and S74413 in 370) and, when the execution of the payout control is finished, a payout end signal (for example, a prize ball end command) indicating that the payout control is finished. A payout end signal output means (for example, a part for executing step S74417 in the payout control microcomputer 370), and the payout signal output means is capable of recognizing the control state by the game control microcomputer. The payout-in-progress signal is output to the game control microcomputer (for example, the payout control microcomputer 370 executes the processes of steps S74221, S74312, and S74412, and, as shown in FIG. 4 bit prize ball error and full tank The stop means outputs the connection confirmation signal from the connection confirmation signal output means based on the reception signal output from the reception signal output means. (For example, the game control microcomputer 560 executes step S52405 without moving to the prize ball transmission process 1 for transmitting the connection confirmation command based on the determination of Y in step S52403, and ends the prize ball. The measurement timer starting means resets a predetermined period in the measurement timer and starts measurement control by the measurement timer based on the output of the payout end signal by the payout end signal output means. (For example, the game control microcomputer 560 determines that Y is determined in step S52503. After setting the connection confirmation time 1 (1 second) prize balls process timer at step S52505, starts measuring step S52313 goes to prize balls transmission process 2) it may be configured so. According to such a configuration, it is possible to reduce the control burden of the game control microcomputer by not performing the output control of the connection confirmation signal during the payout control. Even when the payout control is being executed, the control state signal can be output by adding the control state to the paying-in signal, so that the control state can be recognized on the game control microcomputer side.

(4) The game control microcomputer uses error determination means (for example, game control) to determine whether or not a predetermined error has occurred based on the control state indicated by the response signal output by the response signal output means. The payout number signal output means uses the payout number signal for payout control on condition that the error determination means determines that a predetermined error has not occurred. The game control microcomputer 560 may be configured to output to the microcomputer (for example, when the game control microcomputer 560 determines Y in step S52302, it executes step S52305 and transmits a prize ball number command). According to such a configuration, it is possible to prevent the inconvenience of outputting a payout number signal when the payout control cannot be normally performed due to an error state.

(5) The payout number signal output means inputs the payout end signal output by the payout end signal output means, and then determines that the payout number data is stored in the payout number storage means by the payout number data determination means. Sometimes, regardless of the determination by the error determination means, a new payout number signal is output to the payout control microcomputer (for example, the game control microcomputer 560 determines Y in step S52503 and award ball transmission process 2). After shifting to, based on the determination of Y in step S52301, the process of step S52305 may be executed to transmit a winning ball number command). According to such a configuration, it is possible to speed up the execution process of the payout control.

(6) The game control microcomputer is a specific period determination means (for example, a game control microcomputer) that determines whether or not a specific period (for example, connection confirmation time 2 (10 seconds)) longer than a predetermined period has elapsed. 560, step S5213 is executed based on the connection confirmation time 2 (10 seconds) set in the prize ball process timer) and whether or not a response signal is input after outputting the connection confirmation signal. Including a response signal determination means for determining (for example, a part of step S5223 in the game control microcomputer 560), and the connection confirmation signal output means determines that the response signal is not input by the response signal determination means. , Each time the connection confirmation signal is determined by the specific period determination means that the specific period has passed, Switching to control to be output to the microcomputer (for example, if the game control microcomputer 560 does not determine Y in step S5223, it proceeds to the award ball transmission process 1 based on the determination of Y in step S5227). (S5211 may be executed). According to such a configuration, when the communication state between the game control microcomputer and the payout control microcomputer is unstable, the connection check is performed by extending the interval period until the connection check signal is output. It is possible to reduce the frequency of wasteful execution of signal output processing and reduce the wasteful processing load.

(7) The gaming machine includes an effect control microcomputer (for example, the effect control microcomputer 100) for controlling a predetermined effect device (for example, the effect display device 9), and the response signal output means has a predetermined error. When this occurs, information that allows the game control microcomputer to recognize the predetermined error is set by changing a specific bit of the response signal (for example, the payout control microcomputer 370 is configured as shown in FIG. 45). In addition, by setting bit 0 to bit 3 of the connection OK command, a prize ball error, a full tank error, a ball shortage error, and a payout number error error are set), and the response signal thus set is sent to the game control micro (For example, the payout control microcomputer 370 outputs the information to steps S7414 and S7. 207 is executed to execute steps S7515 and S74208), the game control microcomputer can recognize the predetermined error set in the response signal when the response signal output by the response signal output means is input. Informing error signal output means for outputting to the effect control microcomputer a notification error signal (for example, a frame state display command) in which various information is set as it is (for example, a part for executing step S398 in the game control microcomputer 560). The effect control microcomputer controls the effect device to notify that a predetermined error has occurred based on the input of the notification error signal (for example, the effect control microcomputer 100). When it is determined as Y in step S614 Step S616, S618, S620, it may be configured so as to include a portion) to perform S622. According to such a configuration, it is possible to notify that a predetermined error has occurred using the rendering device, and to reduce the processing burden on the game control microcomputer.

(8) The gaming machine allows a player to play a predetermined game using a game medium (for example, a game ball), and that a predetermined payout condition is satisfied (for example, a game ball wins a winning opening) A gaming machine that pays out game media based on a game control microcomputer that controls the progress of the game (for example, a game control microcomputer 560), and a payout means that pays out game media (for example, , A ball payout device 97) and a payout control microcomputer (for example, payout control microcomputer 370) for controlling the payout means, and the game control microcomputer is satisfied that a payout condition for the game is satisfied (eg, The number of prize game media (for example, the number of prize balls) can be specified as a prize to be paid Payout number storage means (for example, a prize ball command output counter) for storing a payout number data (for example, a count value of a prize ball command output counter) and a payout number data stored in the payout number storage means. A payout number signal output means (for example, step S52305 in the game control microcomputer 560 is executed) that outputs a payout number signal (for example, a prize ball number command) that can specify the number of prize game media to be output to the payout control microcomputer. The payout control microcomputer at least controls the payout means to control the payout means for the number of unpaid prize game media specified by the payout number signal output by the payout number signal output means. Game medium payout control means for executing payout control (for example, a payout control microcomputer 370) In step S75113, the payout motor 289 is started and the payout motor control process in step S756 is executed), and at least the payout excess and the payout number exceeding the number specified by the payout number signal. Cumulative update means (for example, step S7503 in the payout control microcomputer 370) that cumulatively updates data (for example, the count value of the payout number abnormality counter) indicating the number of shortage payouts that is less than the number specified by the signal. When the data updated by the cumulative update means and the data updated by the cumulative update means become a specific value (for example, a predetermined payout number abnormality error determination value (for example, 2000)), payout by the game medium payout control means Dispensing stop means for controlling the execution to the payout stop state by stopping execution of the control (for example, , After setting the payout number abnormality error designation bit in steps S7505, S75322, and S7726 in the payout control microcomputer 370, the control is made so that the payout operation is not performed by determining N in step S75101). It may be configured. According to such a configuration, instead of judging each payout control, the payout control is executed by comprehensively judging the payout control executed under abnormal conditions based on the cumulatively updated data. Can be stopped. Therefore, it is possible to more accurately prevent the act of illegally paying out game media.

(9) The cumulative update means updates the data when an excessive number of payouts or an insufficient payout number equal to or greater than a predetermined reference number (for example, 2) occurs (for example, the payout control microcomputer 370 determines Y in step S75319). Step S75320 may be executed when the determination is made). According to such a configuration, it is possible to prevent inconvenience that the execution of the payout control is stopped more than necessary.

(10) The payout control microcomputer performs re-payout control means (for example, payout control) for performing re-payout control for driving out the payout means and paying out only one game medium when an insufficient payout number occurs. The cumulative updating means updates the data when no payout of the game medium is detected even if the re-payout control by the re-payout control means is executed, including a portion of steps S75314 to S75333 in the microcomputer 370. (For example, the part which performs step S75325, S75335 in the payout control microcomputer 370) may be configured. According to such a configuration, even when the number of payout shortages is small, the execution of payout control can be stopped appropriately by reflecting it in the data, and more fraud countermeasures can be implemented to prevent the act of illegally paying out game media. Can be strengthened.

(11) When the power supply to the gaming machine is started, the gaming machine cancels the payout stop state (for example, the payout control microcomputer 370 uses the payout control microcomputer 370 in steps S7701 and S7707 in FIG. 82). As shown, the part that prevents the payout number abnormality error from being canceled unless the power supply reset of the gaming machine is performed by not performing reset processing on the payout number abnormality error designation bit in the error flag) It may be configured to include. According to such a configuration, in order to release the payout stop state, the game store clerk must confirm the abnormal state and then perform the release operation. Therefore, the payout stop state is canceled illegally and remains in the abnormal state. It is possible to prevent the game from being continued.

(12) The gaming machine is provided with a backup power supply (for example, a backup power supply created on a power supply board) that can supply power to the gaming control microcomputer only for a predetermined period even when power supply to the gaming machine is stopped. The number storage means can retain the stored contents by a backup power source for a predetermined period even when the power supply to the gaming machine is stopped (for example, the RAM 55 provided in the game control microcomputer 560 is partially or entirely a power supply board). When the game control microcomputer is controlled in the payout stop state, the payout number signal output means outputs the payout number signal even if the payout condition for the game is satisfied. Payout number signal prohibiting means (for example, a game control microcomputer 56) May be configured so as to include a portion) that controls not to execute the processing in step S52305 when it is determined that N in step S52302 in. According to such a configuration, it is possible to prevent a situation in which the number-of-payout data is cleared even though the payout is stopped due to an abnormality caused by the gaming machine side that does not depend on fraud. It is possible to prevent a disadvantage from occurring.

(13) The gaming machine includes an effect control microcomputer (for example, the effect control microcomputer 100) that controls a predetermined effect device (for example, the effect display device 9), and the payout control microcomputer is a payout stop means. When the payout stop state is controlled by, an error signal indicating that a predetermined error has occurred (for example, a connection OK command in which error information is set or a winning ball preparation command) is output to the game control microcomputer. Error signal output means (for example, in the payout control microcomputer 370, as shown in FIG. 45, by setting bits 0 to 3 of a connection OK command or a winning ball preparation command, a winning ball error, a full tank error, A ball breakage error and a payout quantity abnormality error are set, and steps S7415 and S7 are performed. 208, S74222, S74313, SS74413), and the game control microcomputer is used to notify that a predetermined error has occurred when an error signal is output by the error signal output means. Including a notification error signal output means for outputting an error signal (for example, a frame state display command) to the effect control microcomputer (for example, a part for executing step S398 in the game control microcomputer 560); Is based on the fact that the error signal for notification is input and controls the effect device to notify that a predetermined error has occurred (for example, it is determined as Y in step S614 in the effect control microcomputer 100). Sometimes steps S616, S 18, S620, may be configured so as to include a portion) to perform S622. According to such a structure, it can alert | report that the predetermined | prescribed error generate | occur | produced using a production | presentation apparatus, and can recognize that abnormality had generate | occur | produced with respect to the game store clerk.

(14) The gaming machine allows a player to play a predetermined game using a game medium (for example, a game ball), and a predetermined payout condition is satisfied (for example, a ball rental request has been made) ), A payout means (for example, a ball payout device 97) for paying out the game medium, and a control microcomputer for controlling the payout means (for example, a payout control microcomputer) 370), and the control microcomputer executes a payout control for executing payout control for driving and paying out payout means for at least unpaid out game media based on establishment of a payout condition based on the loan request. Means (for example, the processing of step S75113 in the payout control microcomputer 370 is executed, the payout motor 289 is activated, and the step Data indicating the payout motor control processing in step S756), at least an excessive payout amount exceeding the requested loan amount and an insufficient payout amount less than the requested loan amount (for example, the number of payouts) Cumulative update means for cumulatively updating (count value of the abnormality counter) (for example, a part for executing steps S7503, S75320, S75325, and S75335 in the payout control microcomputer 370) and data updated by the cumulative update means are specified. When a value (for example, a predetermined payout number abnormality error determination value (for example, 2000)) is reached, a payout stop unit (for example, for payout control) that stops execution of the payout control by the game medium payout control unit and controls the payout stop state. In steps S7505, S75322, and S7726 in the microcomputer 370 After setting the number abnormal error specified bit output, it is determined that N and portions) for controlling so as not to perform the dispensing operation in step S75101, may be configured to include. According to such a configuration, instead of judging each payout control, the payout control is executed by comprehensively judging the payout control executed under abnormal conditions based on the cumulatively updated data. Can be stopped. Therefore, it is possible to more accurately prevent the act of illegally paying out game media.

(15) The gaming machine allows a player to play a predetermined game using a game medium (for example, a game ball), and that a predetermined payout condition is satisfied (for example, a game ball wins a winning opening) A game machine which pays out game media based on a ball lending request), a payout means (for example, a ball payout device 97) for paying out game media, and a control for controlling the payout means A control microcomputer (for example, a payout control microcomputer 370), and the control microcomputer executes payout control for driving out payout means for paying out unpaid game media based on the establishment of payout conditions. Game medium payout control means (for example, the process of step S75113 in the payout control microcomputer 370 is executed to start the payout motor 289, and The portion where the payout motor control process of step S756 is executed), the payout excess exceeding the number of unpaid game media to be paid out, and the number of payout shortages that did not satisfy the number of unpaid game media to be paid out And cumulative updating means for cumulatively updating data (for example, the count value of the payout number abnormality counter) (for example, a part for executing steps S7503, S75320, S75325, and S75335 in the payout control microcomputer 370), and cumulative When the data updated by the updating means reaches a specific value (for example, a predetermined payout number abnormality error determination value (for example, 2000)), the execution of the payout control by the game medium payout control means is stopped to control the payout stop state. Dispensing stop means (for example, steps S7505 and S7 in the dispensing control microcomputer 370) 322, after setting the payout number abnormal error bits specified in S7726, it is determined that N and portions) for controlling so as not to perform the dispensing operation in step S75101, may be configured to include. According to such a configuration, instead of judging each payout control, the payout control is executed by comprehensively judging the payout control executed under abnormal conditions based on the cumulatively updated data. Can be stopped. Therefore, it is possible to more accurately prevent the act of illegally paying out game media.

(16) The gaming machine can play a predetermined game using a game medium (for example, a game ball) and a predetermined payout condition is satisfied (for example, a game ball wins a winning opening) A gaming machine that pays out game media based on a game control microcomputer that controls the progress of the game (for example, a game control microcomputer 560), and a payout means that pays out game media (for example, , A ball payout device 97), a payout control microcomputer for controlling the payout means (for example, payout control microcomputer 370), and fulfillment of payout conditions by the game (for example, the game ball has won a winning opening) A payout detection that detects payout of a prize game medium as a base prize (for example, prize ball payout) and outputs a detection signal to a microcomputer for payout control Means (for example, the number-of-payout counting switch 301), and the game control microcomputer should pay out based on the fact that a payout condition for the game has been established (for example, a game ball has won a winning opening). A payout number storage means (for example, a prize ball command output counter) for storing payout number data (for example, a count value of a prize ball command output counter) capable of specifying the number of prize game media (for example, the number of prize balls), and a payout Based on the number-of-payout data stored in the number storage means, a number-of-payout signal that outputs a number-of-payout signal (for example, a prize ball number command) that can specify the number of prize game media to be paid out is output to the payout control microcomputer. Means (for example, a part for executing step S52305 in the game control microcomputer 560) and a payout number signal are output. Update means for updating the first data (for example, the count value of the prize ball number counter) indicating the number of prize game media to be paid out (for example, a part for executing step S52308 in the game control microcomputer 560). And the payout control microcomputer receives the detection signal from the payout detection means for a predetermined number of times (for example, a prize ball information output determination value (10 times)) to the game control microcomputer. Counting signal output means (for example, a part executing step S7914 in the payout control microcomputer 370) for outputting a game medium count signal (for example, prize ball information) indicating detection of payout of prize game media, and at least payout Number of unpaid premiums specified by the number-of-payout signal output by the number signal output means Game medium payout control means for executing payout control for driving the payout means to pay out game media (for example, the process of step S75113 in the payout control microcomputer 370 is executed to start the payout motor 289, and step S756). The payout motor control process is executed), and at least a second payout number exceeding the number specified by the payout number signal and a second payout shortage not exceeding the number specified by the payout number signal. Cumulative update means for cumulatively updating data (for example, the count value of the payout number abnormality counter) (for example, a portion for executing steps S7503, S75320, S75325, and S75335 in the payout control microcomputer 370) and cumulative update means The updated second data is a specific value (for example, a predetermined payout number abnormality) When the error determination value (for example, 2000) is reached, the payout stop means (for example, steps S7505 and S75322 in the payout control microcomputer 370) stops execution of the payout control by the game medium payout control means and controls the payout stop state. The game control microcomputer further includes a counting signal output means, and sets the payout number abnormality error designation bit in S7726, and then determines that N is determined in step S75101 so as not to perform the payout operation. Based on the output of the game medium count signal by the reverse update means for updating the first data in the reverse direction (for example, the part for executing step S5311 in the game control microcomputer 560), and the first data is predetermined. Threshold value (for example, prize ball shortage determination value (501)). An abnormal state determination means (for example, a part that executes steps S52309 and S5312 in the game control microcomputer 560) that determines that the abnormal state is based on the fact that the award ball excess determination value (0) is reached. It may be configured as follows. According to such a configuration, instead of determining each payout control, payout control is performed by comprehensively determining payout control executed under abnormal conditions based on the cumulatively updated second data. Execution can be stopped. Therefore, it is possible to more accurately prevent the act of illegally paying out game media. Further, since the game control microcomputer side can also determine the abnormal state based on the first data, both the game control microcomputer and the payout control microcomputer can detect the abnormal state. Therefore, it is possible to further strengthen the fraud countermeasure that prevents the act of illegally paying out the game medium.

(17) The gaming machine allows a player to play a predetermined game using a game medium (for example, a game ball), and that a predetermined payout condition is satisfied (for example, a game ball wins a winning opening) A gaming machine that pays out game media based on a ball lending request), a game control microcomputer that controls the progress of the game (for example, a game control microcomputer 560), and a game A payout means (for example, a ball payout device 97) for paying out a medium, a payout control microcomputer (for example, a payout control microcomputer 370) for controlling the payout means, and a game payout condition is satisfied (eg, a game ball) (For example, prize ball payout) and fulfillment of a payout condition by a loan request (for example, a prize ball) A payout detecting means (for example, a payout number count switch 301) which detects a payout of a rental game medium based on a ball lending request (for example, a ball lending payout) and outputs a detection signal to a payout control microcomputer. And the game control microcomputer is configured to count the number of prize game media to be paid out (for example, a prize ball) based on the fact that a game payout condition has been established (for example, a game ball has won a prize opening). The number of payouts that can be specified (for example, the count value of the prize ball command output counter) (for example, the prize ball command output counter) and the number of payouts stored in the number of payouts storage Based on this, a payout number signal (for example, a prize ball number command) that can specify the number of prize game media to be paid out is a microcomputer for payout control. A payout number signal output means for outputting to the computer (for example, a part for executing step S52305 in the game control microcomputer 560) and a first number indicating the number of prize game media to be paid out at the timing when the payout number signal is output. Update means for updating data (for example, the count value of the prize ball number counter) (for example, a part for executing step S52308 in the game control microcomputer 560), the payout control microcomputer from the payout detection means Payout determination means for determining whether the input detection signal is a payout of a prize game medium or a rental game medium (for example, a part for executing steps S7902 and S7903 in the payout control microcomputer 370), and a payout determination The detection signal is paid by the means A game medium count signal (detection of game medium payout to the game control microcomputer based on the determination of a predetermined number of times (e.g., award ball information output determination value (10 times)). For example, count signal output means for outputting prize ball information (for example, a part for executing step S7914 in the payout control microcomputer 370) and the number specified by the payout number signal output by the payout number signal output means. Game medium payout control means (for example, payout control) for executing payout control for driving out payout means for paying out a predetermined number of loaned game media based on fulfillment of payout conditions based on a loan request or unpaid premium game media The processing of step S75113 in the microcomputer 370 is executed, the payout motor 289 is activated, and the step 756 payout motor control process is executed), the number specified by the payout number signal or the number of payouts exceeding the predetermined number, and the number specified by the payout number signal or the number of payout shortages not satisfying the predetermined number Second update data (for example, a count value of a payout number abnormality counter) that cumulatively updates (for example, a portion that executes steps S7503, S75320, S75325, and S75335 in the payout control microcomputer 370); When the second data updated by the cumulative update means reaches a specific value (for example, a predetermined payout number abnormality error determination value (for example, 2000)), the execution of the payout control by the game medium payout control means is stopped to stop payout. Dispensing stop means for controlling the state (for example, step S75 in the dispensing control microcomputer 370) The game control microcomputer further includes: a portion for controlling to not perform a payout operation by determining N in step S75101 after the payout number abnormality error designation bit is set in 5, S75322, S7726. On the basis of the output of the game medium count signal by the count signal output means, reverse update means for updating the first data in the reverse direction (for example, a part for executing step S5311 in the game control microcomputer 560), One data is a predetermined threshold (for example, a prize ball shortage determination value (501)). An abnormal state determination means (for example, a part that executes steps S52309 and S5312 in the game control microcomputer 560) that determines that the abnormal state is based on the fact that the award ball excess determination value (0) is reached. It may be configured as follows. According to such a configuration, instead of determining each payout control, payout control is performed by comprehensively determining payout control executed under abnormal conditions based on the cumulatively updated second data. Execution can be stopped. Therefore, it is possible to more accurately prevent the act of illegally paying out game media. Further, since the game control microcomputer side can also determine the abnormal state based on the first data, both the game control microcomputer and the payout control microcomputer can detect the abnormal state. Accordingly, it is possible to further strengthen the fraud countermeasure that prevents the act of illegally paying out the game medium.

(18) The gaming machine can play a predetermined game using a game medium (for example, a game ball), and a predetermined payout condition is satisfied (for example, a game ball wins a winning opening) A gaming machine that pays out game media based on a game control microcomputer that controls the progress of the game (for example, a game control microcomputer 560), and a payout means that pays out game media (for example, , A ball payout device 97) and a payout control microcomputer (for example, a payout control microcomputer 370) for controlling the payout means. The game control microcomputer and the payout control microcomputer are connected by serial communication. Input / output signals (for example, the game control microcomputer 560 and the payout control microcomputer 370 Each serial communication circuit 511, 380 is built in and the payout control command shown in FIG. 41 is transmitted / received by serial communication), and the game control microcomputer determines whether or not a predetermined period (for example, 1 second) has elapsed. A connection confirmation signal (for example, a connection confirmation command) for confirming a communication connection state between the predetermined period determination means for determining (for example, the portion of step S52313 in the game control microcomputer 560 that executes step S52313) and the payout control microcomputer. Is output to the payout control microcomputer every time it is determined by the predetermined period determination means that the predetermined period has elapsed (for example, after the game control microcomputer 560 determines Y in step S52313, the step Part to execute S5211) and pay by game Based on the fact that the condition is satisfied (for example, that a game ball has won a prize opening), the number of payout data (for example, the number of prize balls) as the prize to be paid out (for example, the number of prize balls) (for example, The number of prize game media to be paid out based on the number-of-payout storage means (for example, the prize-ball command output counter) for storing the prize ball command output counter) and the number-of-payout data stored in the number-of-payout storage means Payout number signal output means for outputting a payout number signal (for example, a prize ball number command) that can be specified to the payout control microcomputer (for example, a part for executing step S52305 in the game control microcomputer 560). The payout control microcomputer responds based on the input of the connection confirmation signal output from the connection confirmation signal output means. Response signal output means for outputting a signal (for example, connection OK command) to the game control microcomputer (for example, a part for executing steps S7415 and S74208 in the payout control microcomputer 370) and at least a payout number signal output means Game medium payout control means (for example, step in the payout control microcomputer 370) that executes payout control for driving the payout means to pay out the number of unpaid premium game media specified by the output payout number signal. The process of S75113 is executed to start the payout motor 289, and the payout motor control process of step S756 is executed), and at least the payout excess and the payout number signal exceeding the number specified by the payout number signal Data indicating the number of underpayments that did not reach the specified number (for example, Cumulative update means for cumulatively updating (count value of the payout number abnormality counter) (for example, a part for executing steps S7503, S75320, S75325, and S75335 in the payout control microcomputer 370) and data updated by the cumulative update means Becomes a specific value (for example, a predetermined payout number abnormality error determination value (for example, 2000)), a payout stop unit (for example, a payout) that stops execution of the payout control by the game medium payout control unit and controls the payout stop state. The control microcomputer 370 sets a payout number abnormality error designation bit in steps S7505, S75322, and S7726, and then determines that N is determined in step S75101 so as not to perform a payout operation). The output means is a game control microphone. A response signal is output to the game control microcomputer in such a manner that the computer can recognize the control state (for example, the payout control microcomputer 370 executes the processes of steps S7414 and S74207 to connect as shown in FIG. (The award ball error, full tank error, out of ball error, and payout number error error may be set and transmitted in the lower 4 bits of the OK command). According to such a configuration, it is possible to facilitate the wiring of the game control microcomputer and the payout control microcomputer by using the serial communication method. In addition, a control state signal (a response signal to which a control state is added) can be output by adding a control state to a response signal periodically output by the payout control microcomputer based on the input of the connection confirmation signal. Therefore, it is possible to prevent the control state signal from being missed without considering the output timing of the control state signal, and to reliably perform communication between the game control microcomputer and the payout control microcomputer. it can. Furthermore, instead of determining each payout control, the payout control executed under an abnormal condition can be comprehensively determined based on the cumulatively updated data, and the payout control can be stopped. . Therefore, it is possible to more accurately prevent the act of illegally paying out game media.

(19) The game control microcomputer stops the output of the connection confirmation signal by the connection confirmation signal output means based on the output of the payout number signal by the payout number signal output means (for example, for game control When the execution of the payout control is terminated, the payout amount data is stored in the payout amount storage means when the microcomputer 560 finishes executing the payout control. The number-of-payout data determination means for determining whether or not is stored (for example, when it is determined as Y in step S52503 in the game control microcomputer 560 and step S52504 is executed to move to the prize ball transmission process 2) The payout number signal output means includes a payout number data determination means. When it is determined that the payout number data is stored in the payout number storage means, a new payout number signal is sent to the payout control microcomputer based on the payout number data stored in the payout number storage means. (For example, the game control microcomputer 560 executes step S52305 based on the determination of Y in step S52301 and transmits a new prize ball number command), and the connection confirmation signal output means outputs the number of payouts. When it is determined by the data determining means that the payout number data is not stored in the payout number storage means, a new connection confirmation signal is issued based on the predetermined period determining means determining that the predetermined period has elapsed. The information is output to the control microcomputer (for example, the game control microcomputer 560 outputs step S52301). It moves to prize balls transmission process 1 becomes Y in step S52313 after determining that N, then executes step S5211 and transmits the new connection confirmation command) may also be configured. According to such a configuration, it is possible to prevent the processing at the end of the execution of the payout control from being concentrated and the occurrence of a new connection confirmation signal to be missed, thereby speeding up the execution processing of the payout control. be able to.

(20) The gaming machine detects a payout of a prize game medium as a prize (for example, a prize ball payout) based on the establishment of a payout condition by a game (for example, a game ball has won a prize opening) and is used for payout control The microcomputer includes a payout detection means (for example, a payout number count switch 301) for outputting a detection signal to the microcomputer, and the game control microcomputer indicates the number of prize game media to be paid out at the timing when the payout number signal is output. Including update means (for example, a part for executing step S52308 in the game control microcomputer 560) for updating the medium number data (for example, the count value of the prize ball number counter), the payout control microcomputer from the payout detection means The detection signal is input a predetermined number of times (for example, prize ball information output determination value (10 times)). Then, a counting signal output means (for example, step S7914 in the payout control microcomputer 370) that outputs a game medium count signal (for example, prize ball information) indicating detection of payout of the prize game medium to the game control microcomputer. The game control microcomputer further includes reverse update means for updating the medium number data in the reverse direction based on the output of the game medium count signal by the count signal output means. For example, the part for executing step S5311 in the game control microcomputer 560 and the medium number data have reached a predetermined threshold value (for example, a shortage determination value (501) for a shortage of winning balls). Based on the abnormal state determination means for determining the abnormal state (for example, a game control microcomputer A portion) for performing the steps S52309, S5312 in Yuta 560, may be configured to include. According to such a configuration, since the abnormal state can be determined on the game control microcomputer side based on the medium number data, the abnormal state can be detected by both the game control microcomputer and the payout control microcomputer. it can. Accordingly, it is possible to further strengthen the fraud countermeasure that prevents the act of illegally paying out the game medium.

(21) The gaming machine allows a player to play a predetermined game using a game medium (for example, a game ball), and a predetermined payout condition is satisfied (for example, a ball rental request has been made) ) Based on the game control microcomputer for controlling the progress of the game (for example, the game control microcomputer 560) and the payout means for paying out the game medium (for example, a ball). A payout device 97) and a payout control microcomputer (for example, a payout control microcomputer 370) for controlling the payout means, and the game control microcomputer and the payout control microcomputer send a signal by serial communication. For example, the game control microcomputer 560 and the payout control microcomputer 370 are respectively Serial communication circuits 511 and 380 are incorporated, and the payout control command shown in FIG. 41 is transmitted and received by serial communication). The game control microcomputer determines whether or not a predetermined period (for example, 1 second) has elapsed. A connection confirmation signal (for example, a connection confirmation command) for confirming the communication connection state between the period determining means (for example, the part for executing step S52313 in the game control microcomputer 560) and the payout control microcomputer is predetermined. Connection confirmation signal output means that outputs to the payout control microcomputer every time the period determination means determines that the predetermined period has elapsed (for example, the game control microcomputer 560 executes step S5211 after determining Y in step S52313) Part) and for payout control The microcomputer uses response signal output means (for example, for payout control) that outputs a response signal (for example, connection OK command) to the game control microcomputer based on the input of the connection confirmation signal output by the connection confirmation signal output means. A part for executing steps S7415 and S74208 in the microcomputer 370) and a game medium for executing payout control for driving and paying out a predetermined number of rental game media based on establishment of a payout condition based on a loan request by driving the payout means The payout control means (for example, the part where the payout motor 289 is started by executing the process of step S75113 in the payout control microcomputer 370 and the payout motor control process of step S756 is executed) and at least a predetermined number Overdue and the predetermined number is not met Cumulative update means (for example, steps S7503, S75320, S75325, and S75335 in the payout control microcomputer 370 are executed to cumulatively update data indicating the number of payout shortages (for example, the count value of the payout number abnormality counter). Portion) and the data updated by the cumulative update means become a specific value (for example, a predetermined payout number abnormality error determination value (for example, 2000)), the execution of the payout control by the game medium payout control means is stopped and paid out. The payout stopping means for controlling the stop state (for example, after setting the payout number error error designation bit in steps S7505, S75322, and S7726 in the payout control microcomputer 370, it is determined as N in step S75101 and the payout operation is not performed. Control part), and The answer signal output means outputs a response signal to the game control microcomputer in a manner in which the game control microcomputer can recognize the control state, and is controlled to the payout stop state when controlled to the payout stop state. A response signal is output to the game control microcomputer so that it can be recognized (for example, the payout control microcomputer 370 executes the processing of steps S7414 and S74207 to display the subordinate of the connection OK command as shown in FIG. 4) Set the award ball error, full tank error, out-of-ball error, and payout error error to 4 bits, and the game control microcomputer will further send a response signal that can recognize that the payout stop state has been controlled. Based on the input, payout is performed to notify that the payout is stopped. It is configured to include stop notification control means (for example, a part that causes the control microcomputer to perform error notification by executing step S398 in the game control microcomputer 560 and transmitting a frame state display command). May be. According to such a configuration, it is possible to facilitate the wiring of the game control microcomputer and the payout control microcomputer by using the serial communication method. In addition, a control state signal (a response signal to which a control state is added) can be output by adding a control state to a response signal periodically output by the payout control microcomputer based on the input of the connection confirmation signal. Therefore, it is possible to prevent the control state signal from being missed without considering the output timing of the control state signal, and to reliably perform communication between the game control microcomputer and the payout control microcomputer. it can. Further, instead of determining each payout control, it is possible to stop the payout control by comprehensively determining the payout control executed under an abnormal condition based on the cumulatively updated data. . Therefore, it is possible to more accurately prevent the act of illegally paying out game media. Furthermore, it is possible to notify that the payout has been stopped, and to allow the game store clerk to recognize that an abnormality has occurred.

(22) The game control microcomputer, based on the fact that the game payout condition is satisfied, payout number data (for example, the number of prize balls) as the prize to be paid out (for example, the number of prize balls) (for example, The number of prize game media to be paid out based on the number-of-payout storage means (for example, the prize-ball command output counter) for storing the prize ball command output counter) and the number-of-payout data stored in the number-of-payout storage means The number-of-payout signal (for example, a part for executing step S52305 in the game control microcomputer 560) for outputting a number-of-payout signal (for example, a prize ball number command) to the payout control microcomputer, and the number of payouts Based on the output of the payout number signal by the signal output means, the connection confirmation signal output means confirms the connection. Stop means for stopping signal output (for example, a portion that shifts to a prize ball end confirmation process without shifting to a prize ball transmission process 1 for transmitting a connection confirmation command in the game control microcomputer 560) and execution of payout control When the game is finished, the number-of-payout data determination means for determining whether or not the number-of-payout data is stored in the number-of-payout storage means (for example, it is determined as Y in step S52503 in the game control microcomputer 560, and step S52504 is executed). The payout number signal output means stores the payout number data in the payout number storage means by the payout number data determination means. Is determined based on the payout amount data stored in the payout amount storage means. Is output to the payout control microcomputer (for example, the game control microcomputer 560 executes step S52305 based on the determination of Y in step S52301 and transmits a new prize ball number command) to confirm the connection. The signal output means is based on the fact that the predetermined period determining means determines that the predetermined period has elapsed when the payout number data determining means determines that the payout number storage means does not store the payout number data. A new connection confirmation signal is output to the payout control microcomputer (for example, the game control microcomputer 560 determines “N” in step S52301, then becomes “Y” in step S52313, and proceeds to the award ball transmission process 1.) (S5211 is executed and a new connection confirmation command is transmitted) It may be configured. According to such a configuration, it is possible to prevent the processing at the end of the execution of the payout control from being concentrated and the occurrence of a new connection confirmation signal to be missed, thereby speeding up the execution processing of the payout control. be able to.

(23) The gaming machine pays out a prize game medium as a prize (for example, pays out a prize ball) based on the establishment of a game payout condition (for example, a game ball has won a prize opening) and a payout condition for a lending request A payout detection means (for example, a payout) that detects a payout of a rental game medium (for example, a ballrent payout) based on the establishment of (for example, a ball lending request) and outputs a detection signal to the payout control microcomputer The game control microcomputer is provided with a number count switch 301), and at the timing when a payout number signal is output, medium number data (for example, a count value of a prize ball number counter) indicating the number of premium game media to be paid out is provided. An update means for updating (for example, a part for executing step S52308 in the game control microcomputer 560) and paying out The control microcomputer determines whether the detection signal input from the payout detection means is a payout game medium or a rented game medium. The payout determination means (for example, steps S7902, S7903 in the payout control microcomputer 370). And a game control micro based on that the detection signal is determined a predetermined number of times (for example, a prize ball information output determination value (10 times)) by the payout determination means. Counting signal output means (for example, a part for executing step S7914 in the payout control microcomputer 370) for outputting a game medium count signal (for example, prize ball information) indicating detection of game medium payout to the computer; In addition, the game control microcomputer further includes a counting signal. Based on the output of the game medium count signal by the output means, reverse update means for updating the medium number data in the reverse direction (for example, the part for executing step S5311 in the game control microcomputer 560), and the medium number data Is an abnormal state determination means (for example, a game control micro) that determines an abnormal state based on a predetermined threshold value (for example, a shortage determination value (501) for a prize ball, a determination value (0) for a prize ball excess)). And a portion for executing steps S52309 and S5312 in the computer 560). According to such a configuration, since the abnormal state can be determined on the game control microcomputer side based on the medium number data, the abnormal state can be detected by both the game control microcomputer and the payout control microcomputer. it can. Accordingly, it is possible to further strengthen the fraud countermeasure that prevents the act of illegally paying out the game medium.

(24) The gaming machine can play a predetermined game using a game medium (for example, a game ball), and a predetermined payout condition is satisfied (for example, a game ball wins a winning opening) A gaming machine that pays out game media based on a ball lending request), a game control microcomputer that controls the progress of the game (for example, a game control microcomputer 560), and a game A payout means (for example, a ball payout device 97) for paying out a medium and a payout control microcomputer (for example, a payout control microcomputer 370) for controlling the payout means are provided, and the game control microcomputer and the payout control are provided. The microcomputer for input / output of signals by serial communication (for example, a game control microcomputer 560 and a payout control microphone) The computer 370 includes serial communication circuits 511 and 380, respectively, and sends and receives the payout control command shown in FIG. 41 by serial communication.) Whether the game control microcomputer has passed a predetermined period (for example, 1 second) A connection confirmation signal (for example, connection) for confirming a communication connection state between the predetermined period determination means for determining whether or not (for example, the portion of step S52313 in the game control microcomputer 560 that executes step S52313) and the payout control microcomputer The connection confirmation signal output means (for example, the game control microcomputer 560 determines Y in step S52313) to output a confirmation command) to the payout control microcomputer every time the predetermined period determination means determines that the predetermined period has elapsed. Step S5211 is executed after The number of prize game media as prizes to be paid out (for example, the number of prize balls) based on the fact that the game payout condition has been established (for example, a game ball has won a prize opening) Based on payout number storage means (for example, a prize ball command output counter) for storing possible payout number data (for example, a count value of a prize ball command output counter) and payout number data stored in the payout number storage means, A payout number signal output means (for example, step S52305 in the game control microcomputer 560) that outputs a payout number signal (for example, a prize ball number command) that can specify the number of prize game media to be paid out to the payout control microcomputer. The payout control microcomputer inputs the connection confirmation signal output from the connection confirmation signal output means. A response signal output means for outputting a response signal (for example, connection OK command) to the game control microcomputer based on the input (for example, a portion for executing steps S7415 and S74208 in the payout control microcomputer 370); Game for executing payout control for driving out payout means to drive out a predetermined number of rental game media based on the number specified by the payout number signal output by the number signal output means or establishment of the payout condition by the loan request The medium payout control means (for example, the portion where the payout motor 289 is started by executing the process of step S75113 in the payout control microcomputer 370 and the payout motor control process of step S756 is executed) and the payout number signal are specified. Or the number of payouts exceeding the specified number and the payout number signal Cumulative update means (for example, step S7503 in the payout control microcomputer 370) that cumulatively updates data indicating the predetermined number or the number of shortage payouts that did not satisfy the predetermined number (for example, the count value of the payout number abnormality counter). , S75320, S75325, S75335) and the data updated by the cumulative update means become a specific value (for example, a predetermined payout number abnormality error determination value (for example, 2000)), the game medium payout control means Discharge stop means for stopping the execution of the payout control to control the payout stop state (for example, after setting the payout quantity abnormality error designation bit at steps S7505, S75322, and S7726 in the payout control microcomputer 370, N is set at step S75101. Judgment and do not perform payout operation The response signal output means outputs a response signal to the game control microcomputer in a manner that allows the game control microcomputer to recognize the control state (for example, a payout control microcomputer). 370 executes the processes of steps S7414 and S74207, and transmits a prize ball error, a full tank error, a ball shortage error, and a payout number error error in the lower 4 bits of the connection OK command as shown in FIG. 45) It may be configured as follows. According to such a configuration, it is possible to facilitate the wiring of the game control microcomputer and the payout control microcomputer by using the serial communication method. In addition, a control state signal (a response signal to which a control state is added) can be output by adding a control state to a response signal periodically output by the payout control microcomputer based on the input of the connection confirmation signal. Therefore, it is possible to prevent the control state signal from being missed without considering the output timing of the control state signal, and to reliably perform communication between the game control microcomputer and the payout control microcomputer. it can. Furthermore, instead of determining each payout control, the payout control executed under an abnormal condition can be comprehensively determined based on the cumulatively updated data, and the payout control can be stopped. . Therefore, it is possible to more accurately prevent the act of illegally paying out game media.

(25) The game control microcomputer has a built-in control CPU (for example, CPU 56) that executes game control in the game machine based on the stored contents of the nonvolatile memory (for example, ROM 54) after executing predetermined initial settings. And a random number circuit (for example, a random number circuit 509) that is built in or externally attached to a game control microcomputer (for example, the game control microcomputer 560) and generates numerical data that becomes a random number value. Numerical value updating means (for example, random number generation circuit 553 or random number sequence changing circuit 555) that updates and outputs data according to a predetermined procedure, and randomness that takes numerical data output from numerical value updating means as a random value and stores it Numerical value storage means (for example, random value register 559A (R1D) or random value register 559B) R2D)) and a predetermined signal (for example, random number latch signals LL1 and LL2 based on the start winning signal SS), the numerical data output from the numerical value updating means is stored in the random value storage means. In the meantime, the storage of new numerical data is restricted and the numerical data stored in the random number storage means is turned off when the random number value is read out by the control CPU at the read timing of the random value, and the new numerical value is stored. And a predetermined flag that permits data storage (for example, random number latch flags RDFM0 and RDFM1), and the game control microcomputer turns off the predetermined flag when game control by the control CPU is started. Game control start processing means (for example, executing step S5006 in the game control microcomputer 560) Number latch flag RDFM0, RDFM1 clears the portion. Steps in the game control microcomputer 560 S484, perform the S486 and random number latch flag RDFM0, RDFM1 clearing portion.) May be configured to include. According to such a configuration, the numerical data stored in the random value storage unit based on the input of the predetermined signal can be acquired as an accurate random value. In addition, it is possible to prevent a situation in which numerical data stored in the random value storage means is erroneously acquired in a state where the power supplied to the gaming machine is unstable.

(26) The game control start time processing means is a system reset time processing for turning off a predetermined flag when the system reset of the game control microcomputer is released and the execution of the game control by the control CPU is started. Means (for example, a part for executing step S5006 in the game control microcomputer 560 to clear the random number latch flags RDFM0 and RDFM1) may be included. According to such a configuration, for example, it is possible to prevent the numerical data stored in the random number storage means from being erroneously acquired as a random value when the power supply voltage is unstable when the power is turned on. .

(27) The gaming machine monitors a predetermined power supply voltage generated based on power supply to the gaming machine and outputs a detection signal (for example, a power-off signal) based on the decrease in the predetermined power supply voltage. A detection judgment provided with monitoring means (for example, a power supply monitoring circuit 920), wherein the game control microcomputer repeatedly determines the input state of the detection signal until the operation stop state after the detection signal is output from the power supply monitoring means. When the determination that the detection signal is not input by the means (for example, the part for executing step S482 in the game control microcomputer 560) and the detection determination means, the game control processing program starts from the beginning. The power failure recovery control means for starting execution (for example, in the game control microcomputer 560, step S487 is executed). The game control start time processing means after the determination that the detection signal is not input by the detection determination means, and when the power interruption is restored. Before the control means starts executing the game control from the beginning of the game control processing program, the power failure recovery processing means for turning off a predetermined flag (for example, steps S484 and S486 in the game control microcomputer 560 are executed). It may be configured to include a portion that executes and clears the random number latch flags RDFM0 and RDFM1). According to such a configuration, for example, it is possible to prevent the numerical data stored in the random value storage means from being erroneously acquired as a random value when the power supply voltage is unstable, for example, when the predetermined power supply voltage is lowered. be able to.

(28) The numerical value updating means cyclically updates the numerical data from a predetermined update initial value to a predetermined update final value within a predetermined range in which the numerical data can be updated (for example, the random number generation circuit 553 or the random number sequence change) The part for generating the random number sequence RSN as shown in FIG. 32 or FIG. 33 in the circuit 555), the game control microcomputer variably sets a predetermined update initial value every time the game control microcomputer is system reset. Possible random number initial value setting means (for example, a part for executing step S5005 in the game control microcomputer 560) may be included. According to such a configuration, it becomes difficult to specify numerical data that becomes a random number value after the occurrence of a system reset, and it is possible to reliably prevent an illegal act due to a shooting or the like.

(29) The gaming machine includes a counting unit (for example, a free-run counter 554A) that counts a numerical value separately from the operation of the control CPU after power supply to the gaming machine is started, and a random number initial value setting unit Uses the numerical value counted by the counting means to determine a predetermined update initial value (for example, the start value setting circuit 554 sets the start value based on the processing of step S5005 by the game control microcomputer 560). (Part)). According to such a configuration, it becomes difficult to specify numerical data that is a random number value from the operation mode of the control CPU, and it is possible to reliably prevent fraudulent acts such as aiming.

(30) The nonvolatile memory is built in the game control microcomputer, and the game control microcomputer restricts external reading of the nonvolatile memory other than by the control CPU (for example, the internal resource access control circuit 501A). ) May be included. According to such a configuration, it becomes difficult to read out and analyze the control program stored in the non-volatile memory from the outside of the game control microcomputer, and aiming based on the analysis result of the control program, etc. It is possible to surely prevent an illegal act by connecting a so-called “hanging board”.

(31) The gaming machine generates a random number clock signal outside the gaming control microcomputer and supplies the random number clock signal to the random number circuit (for example, the random number clock generation circuit 112), and a control CPU And a control clock generation circuit (for example, the control clock generation circuit 111 or the clock circuit 502) that generates a control clock signal supplied to the game control microcomputer. The microcomputer for microcomputer changes the input state of the random number clock signal supplied from the random number clock generation circuit to the input state of the random number clock signal by comparing the input state of the random number clock signal with the control clock signal generated by the control clock generation circuit. Random number clock abnormality determination means for determining whether or not an abnormality has occurred (for example, frequency monitoring circuit 551, It may be configured so as to include a portion) for performing the steps S562~S566 in the gaming control microcomputer 560 and. According to such a configuration, it is possible to prevent the game control from being executed in a state where an abnormality has occurred in the operation of updating the numerical data that is the random value.

(32) The game control microcomputer performs security check to check whether or not the stored contents of the nonvolatile memory have been changed in a predetermined initial setting (for example, step S1009 in the game control microcomputer 560). To S1014) and security time setting means that can variably set the execution time of the security check by the security check means (for example, based on the bit number [2-0] of the security time setting KSES) The part which performs step S1001-S1004 in computer 560. Based on bit number [4-3] of security time setting KSES, step S1005 in microcomputer 560 for game control 1008 and the portions for performing), it may be configured to include. According to such a configuration, it becomes difficult to specify the execution start timing of the game control, and it is possible to reliably perform a sniper based on an analysis result such as an initial setting operation or an illegal act by connecting a so-called “hanging board”. Can be prevented.

(33) The game control microcomputer reads the numerical data stored in the random value storage means when the number of the reserved memories in the reserved storage means reaches a predetermined upper limit number at the read timing of the random number values. May be configured to include upper limit storage reading means for turning off the predetermined flag (for example, a portion for executing step S326 in the game control microcomputer 560 to clear the random number latch flags RDFM0 and RDFM1). . According to such a configuration, an accurate random number value based on an input of a predetermined signal when the number of reserved memories reaches a predetermined upper limit number and becomes a random number read timing after the number becomes less than the upper limit number. Can be obtained.

  The present invention can be suitably applied to gaming machines such as pachinko gaming machines and slot machines.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 9 Production display device 14 Start winning opening 14a Start opening switch 15 Variable winning ball apparatus 31 Game control board (main board)
37 Dispensing control board 56 CPU
80 Production control board 100 Production control microcomputer 101a Production control CPU
101b Serial communication circuit (production control side)
155A Door opening sensor 155B Mechanism plate opening sensor 160 Terminal board 370 Discharge control microcomputer 371 Discharge control CPU
380 Serial communication circuit (withdrawal control side)
501 External bus interface 501A Internal resource access control circuit 502 Clock circuit 503 Specific information storage circuit 504 Reset / interrupt controller 508 CTC
509 Random number circuit 510 PIP
511 Serial communication circuit (game control side)
512 Address decode circuit 551 Frequency monitoring circuit 552 Clock flip-flop 553 Random number generation circuit 554 Start value setting circuit 554A Free run counter 555 Random number sequence change circuit 556 Random number sequence change setting circuit 557A, 557B Latch flip-flops 558A, 558B Random number latch selector 559A, 559B Random value register 560 Microcomputer for game control

Claims (1)

A gaming machine capable of playing a game,
Game control means for controlling the progress of the game;
Electrical component control means for controlling electrical components provided in the gaming machine;
It is possible to operate by opening the open / close door provided in the gaming machine, and includes an initialization operation means that outputs an operation signal according to the operation,
The game control means includes
Operation signal determination means for determining whether or not the operation signal is input from the initialization operation means when power to the gaming machine is turned on;
An open state determining means for determining whether or not the open state when the power to the gaming machine is turned on;
Initialization processing execution means for executing an initialization process based on the determination that the operation signal is input by the operation signal determination means and the determination of the open state by the open state determination means When,
An initialization command output means for outputting an initialization command for initializing the electrical component control means when the initialization process is executed;
An initialization limiting unit that limits execution of the initialization process by the initialization process execution unit based on the determination that the release state determination unit is not in the open state ;
Upon detection of a predetermined abnormality, seen including a deactivation means for deactivation of the progression of the game,
The disabling by the disabling means is to turn on the power to the gaming machine again, the operation signal determining means determines that the operation signal is input, and the open state determining means is in the open state. A gaming machine that is released when the initialization process is executed by the initialization process execution means based on the determination that there is a game machine.

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