JP6004614B2 - Manufacturing method for chemically sensitive field effect transistors - Google Patents

Description

  The present invention relates to a method of manufacturing a field effect transistor, which is a chemically sensitive field effect transistor especially for gas sensors, and to a field effect transistor of this kind and its use.

  Sensor elements for chemical gas sensors are based on field effect transistors and wide bandgap semiconductor materials and are currently built exclusively using standard materials in semiconductor technology. However, chemical gas sensors require a so-called “open” gate comprising a very thin fragile gate insulating layer and a sensing layer disposed on the gate insulating layer.

  Gate insulation layers are usually manufactured to avoid metal contamination (failure points) in the gate insulation layer, which can degrade electrical properties and impair stability, and for example, to avoid temperature loads from other components. Performed at the start of the process (front end). In known manufacturing methods for conventional transistors, the gate insulating layer is covered with a gate electrode layer made of a conductive material which remains there immediately after the gate insulating layer is produced.

  However, during many additional processes, such as lithographic, coating, etching and sputtering, the material of the gate insulating layer is exposed to the physical and chemical effects associated therewith, and as a result, the gate electrode layer is chemically treated. Measures to manufacture a chemically sensitive field effect transistor with a sensing layer are not suitable or must severely limit subsequent processing steps.

  Thus, for example, within the framework of a known manufacturing method, a layer made of the same material, such as a gate insulating layer or a gate electrode layer, cannot be constructed and structured in subsequent processing steps. This is because if these layers are open, the gate insulating layer or the gate electrode layer is also invaded and removed.

  For this reason, for example, in known manufacturing methods, the gate insulating layer is formed for the first time after the attachment and structuring of the oxidation field.

  Similarly, in the known production method, the structuring of the metal layer that is subsequently constructed is usually performed only by the wet chemical lift-off method. This is because dry etching may also invade the gate insulating layer.

  The object of the present invention is to increase the possibility of changes in the number of processing techniques and materials that can be used and the order of the processing techniques.

The subject of the present invention is a method of manufacturing a field effect transistor, in particular a chemically sensitive field effect transistor for a gas sensor,
a) preparing a substrate layer of semiconductor material, in particular a wafer;
b) forming / attaching a gate insulating layer on the substrate layer;
c) forming / attaching at least one gate insulating protective layer on the gate insulating layer;
d) completely or partially removing the gate insulating protective layer;
And e) forming / attaching a gate electrode layer (sensing layer) on the gate insulating layer or on the remaining portion of the gate insulating protective layer;
It is a manufacturing method containing.

  The method of the present invention has the advantage that the gate insulating layer is protected from environmental influences by the gate insulating protective layer. For example, method step c) can advantageously be further processed between method step c) and method step d), in particular it can be further processed, for example performing an advantageous method step such as backsputtering. can do. This was not possible within the framework of known methods with “open” gate insulation layers. Advantageously, the number of processing techniques and materials and deformable means that can be used in a sequence of processing techniques can be significantly increased. Furthermore, the gate insulating protective layer can be used as a transport protective portion and as a contamination protective portion at the time of individualization, and can be removed, for example, immediately before forming the gate electrode layer (detecting layer). In particular, the gate insulating protective layer can be part of the gate insulating layer. This is done by leaving part of the gate insulating protective layer or the gate insulating protective layer on the gate insulating layer or on another region of the field effect transistor. Furthermore, the gate insulating protective layer advantageously allows the position and edge shape of the layer formed between method steps c) and d) to be adjusted. In particular, the integrity of the gate insulating layer can be checked by means of a conductive gate insulating protective layer.

  Preferably, at least a plurality of the gate insulating protective layers are resistant to the method steps performed between method steps c) and d), so that they are performed between method steps c) and d). During the method steps, the gate insulating layer is protected against environmental influences. In particular, the gate insulating protective layer can preferably be selectively removed from the gate insulating layer.

Prior to method step c), the method is preferably inter alia by gas plasma treatment, for example by stripping and / or soil removal, or by backsputtering and / or by wet or dry chemical etching, and / or for example an oxygen-containing atmosphere Method step c0) of cleaning the gate insulating layer by heat treatment in or by a combination thereof. In this way, advantageously, organic components can be removed and the functionality of the field effect transistor can be improved. The gas plasma treatment can be performed in pure gas or in a mixed gas of, for example, argon, oxygen and / or nitrogen. Backsputtering can be performed using, for example, argon, nitrogen and / or oxygen. Wet chemical etching can be performed, for example, in a buffer solution containing HF. Dry etching can be performed, for example, in an atmosphere containing CF ₄ or SF ₆ . For example, during cleaning, the layer thickness is removed in the range of ≧ 2 nm to ≦ 30 nm.

  Preferably method step c) is carried out (directly) following method step b) or c0).

  The gate insulating protective layer can be formed or attached particularly flat or completely flat in method step c).

  In a method embodiment, in step c), two or more gate insulating protective layers of different materials are formed or attached in sequence.

  In the case of a plurality of gate insulating protective layers, the materials of the individual gate insulating protective layers and their order are preferably matched between the subsequent method steps, in particular method steps c) and d). Here, the individual materials can be chosen to have a high (physical and / or chemical) resistance or inertness, in particular for the individual method steps between subsequent method steps c) and d). it can. This allows the entire gate insulation protection layer system to have a smaller overall thickness than individual gate insulation protection layers having the same resistance or inertness.

  Within the framework of a further embodiment of the method, method step c) comprises a material resistant to physical cutting or dry etching, in particular back sputtering, ion beam etching (IBE) or reactive ion beam etching (RIBE), Gate insulation protection made of a material that can be dissolved or stripped by wet chemical etching, for example metal aluminum and / or nickel, before forming or attaching a gate insulation protection layer made of silicon carbide, silicon nitride, titanium nitride, silicon carbonitride, etc. A layer is formed or attached. In this way, the outer gate insulating protective layer can protect the gate insulating layer during physical cutting or dry etching, and the underlying gate insulating protective layer that can be dissolved or peeled off by wet chemical etching. It can be peeled by dissolving or peeling.

  As a material for the gate insulating protective layer, amorphous silicon or polycrystalline silicon is particularly suitable. This is because silicon is in any case a component of the substrate and is usually also an insulating layer. Other materials are possible as an alternative or in addition to this. For example, metallic aluminum and / or nickel as a metal that can be easily removed later, or silicon nitride, or an organic material layer or layer with an organic material, or other insulating material that can be selectively removed compared to silicon dioxide Suitable.

Thus, within the framework of further embodiments, method step c) forms or attaches one or more gate insulating protective layers, which gate insulating protective layers are
Oxides, nitrides, and silicates of silicon, aluminum, zirconium, hafnium, and mixtures thereof, such as silicon dioxide, silicon nitride, aluminum oxide, zirconium oxide, zirconium silicate, hafnium oxide, hafnium silicate A material selected from the group consisting of salts, and mixtures thereof, and / or a mixture of silicon (Si), boron (B), carbon (C) and nitrogen (N), and / or silicon (Si), A mixture of aluminum (Al), oxide (O) and nitride (N), also referred to as SiAlON, and / or aluminum and / or nickel, and / or silicon, such as amorphous silicon or polycrystalline silicon, In particular polycrystalline silicon and / or titanium and / or tantalum And / or niobium, and / or silicon carbonitride, and / or silicon carbide, such as amorphous silicon carbide or polycrystalline silicon carbide, especially low conductivity silicon carbide, and / or silicon nitride and / or titanium nitride And / or tantalum nitride, and / or silicon oxide and / or titanium oxide, and / or organic materials, or can be made from them.

  If one or more conductive gate insulating protective layers are formed or attached in method step c), these are preferably removed completely completely in method step d).

  The gate insulating protective layer formed or attached in method step c) has an overall thickness d, for example in the range 10 ≧ nm to ≦ 10 μm, in particular in the range 50 ≧ nm to ≦ 1000 nm, for example in the range ≧ 50 nm to ≦ 500 nm. be able to.

  The gate insulating protective layer is applied in method step c), for example physical vapor deposition (PVD), eg sputtering, or reactive sputtering, or chemical vapor deposition (CVD), eg low pressure chemical vapor deposition (LPCVD). , Low pressure chemical vapor deposition), or plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD), or a combination of these methods.

For example, in method step c)
First, oxides, nitrides, and silicates of silicon, aluminum, zirconium, hafnium, and mixtures thereof, such as silicon dioxide, silicon nitride, aluminum oxide, zirconium oxide, zirconium silicate, hafnium oxide, hafnium At least one gate insulating protective layer comprising a dielectric material selected from the group consisting of silicates and mixtures thereof; and then silicon (Si), boron (B), carbon (C) and nitrogen (N And / or a mixture of silicon (Si), aluminum (Al), oxygen (O) and nitrogen (N), also referred to as SiAlON, and / or silicon, aluminum, zirconium, hafnium and mixtures thereof, For example, silicon oxide, silicon nitride, aluminum oxide, acid Zirconium silicate, zirconium oxide, hafnium silicate, hafnium and dielectric materials and / or made of self-passivating material at least one of the gate insulating protective layer is a material selected from the group consisting of,
At least comprising, or consisting of, in particular, silicon carbide, such as amorphous silicon carbide or polycrystalline silicon carbide, in particular silicon carbide with low conductivity, and / or carbonitrided silicon nitride and / or silicon nitride and / or titanium nitride One gate insulating protective layer is formed or attached.

At this time, in method step c),
First, the gate insulating protective layer is formed, for example by physical vapor deposition, for example by sputtering or reactive sputtering, or by chemical vapor deposition, for example by plasma chemical vapor deposition or atom layer deposition, for example (total) layer thickness dD ≧ 3 nm Formed or attached to ≦ 300 nm from
The next formed or attached gate insulation protective layer, for example by (respectively) physical vapor deposition, for example by sputtering or reactive sputtering, or by chemical vapor deposition, for example by plasma chemical vapor deposition or atom layer deposition, for example (Overall) forming or attaching the layer thickness dD from ≧ 100 nm to ≦ 300 nm,
A subsequently formed or attached gate insulating protective layer, for example by physical vapor deposition, for example by sputtering or chemical vapor deposition, for example by low pressure chemical vapor deposition or plasma chemical vapor deposition, for example (total) layer thickness dD Is formed or attached so that ≧ 100 nm to ≦ 300 nm.

  Within the framework of further embodiments of the method, method step c) first comprises oxides, nitrides and silicates of silicon, aluminum, zirconium, hafnium and mixtures thereof, such as silicon dioxide, silicon nitride. Forming or attaching a gate insulating protective layer comprising a gate insulating protective layer material selected from the group consisting of aluminum oxide, zirconium oxide, zirconium silicate, hafnium oxide, hafnium silicate, and mixtures thereof. In method step e), the gate insulating protective layer is advantageously left partially or completely on the gate insulating layer and used as a reinforced gate insulating layer.

  Preferably in method step c) at least one gate insulating protective layer is formed or attached from an inorganic material. In particular, all gate insulating protective layers formed or attached in method step c) consist of inorganic materials.

  Within the frame of another embodiment of the method, in method step c), at least one gate insulating protective layer made of a conductive material is formed or attached. This means that, in method step d0), a gate insulating protective layer, in particular made of a conductive material, is electrically connected to the inspection / probe needle, and capacitive voltage measurement (CV measurement) or current intensity voltage measurement (IV). By performing (measurement), there is an advantage that the integrity of the gate insulating layer can be inspected.

As already explained, the method between method steps c) and d) may comprise at least one method step d0): further process of method step c), in particular further processing, wherein the gate insulating layer is In method step d0), it remains covered by at least part of the gate insulating protective layer. The gate insulation layer by a method step d0), by leaving covered by at least a portion of the gate insulating protective layer, preferably influences or damage method step d0) is avoided, or sufficiently thick insulating layer And / or areas that do not have important electrical functions.

Within the framework of further embodiments of the method, the method between method step c) and method step d) is:
Structuring by partially removing the gate insulating protective layer, in particular lateral structuring;
One or more other layers that are metal / conductive layers, electrically insulating layers, and / or passivating layers, for the formation of electrical contacts, conductive paths, insulating layers, and / or protective layers Forming / applying;
One or more layers formed or attached, eg gate insulating protective layers, metal / conductive layers, electrically insulating layers, and / or passivating layers, electrical contacts, conductive paths, insulating layers, and / or Or structuring by partial removal to form a protective layer;
・ Electrically connecting the conductive gate insulating protective layer to the inspection needle / probe needle and performing capacitive voltage measurement (CV measurement) or current intensity voltage measurement (IV measurement) Checking integrity;
-Individualizing the resulting construct by cutting out;
-Conveying the resulting structure;
One or more method steps d0) selected from the group consisting of: and combinations thereof, wherein the gate insulating layer remains covered by at least part of the gate insulating protective layer.

  Within the framework of method step d0), a number of different techniques can be applied, such as coating techniques, etching techniques, transport techniques, lithographic techniques and separation techniques.

  The structuring can be carried out in method step d0), in particular by wet chemical etching or dry etching or physical cutting methods such as back sputtering, ion beam etching IBE or reactive ion beam etching RIBE. The gate insulating protective layer and / or other layers formed or attached here can be structured in two or more method steps d0), in particular each partially removed.

  Here the cutting is preferably monitored by spectroscopic measurements (optical emission) or spectrometric measurements (via a spectrometer). The specific cutting component defect detected in advance here can be used as a stop signal for the cutting method in combination with a predetermined time signal from the start of cutting. If the exposed layer has a sufficient layer thickness, the appearance of the cutting component of this layer can be used as a stop signal for the cutting method. In this way, when stopping the cutting method, the exposed layer material, for example the gate insulating layer, is present without leaving any layer to be cut.

  After the method step d0) of structuring the gate insulating protective layer, one or more further layers are applied, for example by physical vapor deposition (PVD), for example sputtering, or reactive sputtering, or chemical vapor deposition ( CVD, chemical vapor deposition), for example, low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD), or these It can be formed or attached by a combination of methods. These layers can optionally be attached to reinforce the gate insulating protective layer.

  For example, one or more metal layers can be attached for the formation of conductor tracks and / or electrical contacts. For example, one or more layers, in particular conductor tracks, can be formed from metals or metal mixtures, in particular from two or three metal mixtures, these mixtures comprising platinum, rhodium, ruthenium, tantalum, palladium, iridium, And at least one metal selected from the group consisting of and mixtures thereof, optionally additionally selected from the group consisting of chromium, cobalt, copper, titanium, gold, silicon, silver, tungsten, zirconium, and mixtures thereof At least one metal may be included. In particular, the metal layer with the function of the conductor track is from the group consisting of up to 30% by weight of platinum and platinum, rhodium, ruthenium, tantalum, titanium, palladium, iridium, and mixtures thereof, based on the total weight of the metal mixture. It can be formed from a metal mixture containing one or more selected metals. The metal layer, in particular the conductor track, can be formed or attached with a layer thickness dL in the range from 10 nm to 10 μm, for example in the range from 50 nm to 500 nm.

  Within the framework of another embodiment of the method, the gate insulating protective layer is structured in method step d0) to be used as a marking for a subsequently formed or attached layer, for example a metal layer. This type of marking advantageously allows the edges of subsequently attached layers to be modified and adapted for later use. Here the gate insulation protective layer can be used as a marking, possibly multiple times, and only after the final marking is removed so that only the gate insulation protective layer remains protected during the rest of the process. Can do. Here, when there are a plurality of gate insulating protective layers, individual gate insulating protective layers can be left under the layer to be marked as expected.

  The removal of the gate insulating protective layer in method step d) can comprise two or more partial removal method steps.

  Within the framework of another embodiment of the method, the removal of the gate insulating protective layer in method step d) is performed by dry etching or wet chemical etching. In particular, the removal of the gate insulating protective layer in method step d) is carried out by wet chemical etching. This is because wet chemical etching has high selectivity for the gate insulating layer.

  Within the frame of another embodiment of the method, method step e) is carried out (directly) following method step d).

  In method step e), a gate electrode layer is formed or attached on at least part of the gate insulating layer and / or at least part of the remaining part of the gate insulating protective layer. Further, a gate electrode layer can be formed or attached over at least a portion of the field insulating layer and / or at least a portion of the conductor track. Preferably, the gate electrode layer is made from a conductive material. In particular, the gate electrode layer can be made from a metal, a metal mixture, an alloy, or a ceramic metal mixture, such as a platinum-rhodium mixture.

  The attachment of the gate electrode layer (sensing layer) in method step e) can be performed by a wet coating method. Since there are defined surface properties after removal of the gate insulating protective layer, in the case of wet coating, the defined wetting properties can be obtained without additional cleaning steps.

  In particular, the substrate layer can be made of a semiconductor material having a wide band gap (wide band gap semiconductor), for example, silicon carbide. In the present invention, “a semiconductor material having a wide band gap” is a semiconductor material having a band gap larger than 1 eV, for example, 2 eV or more.

  Furthermore, the method can include a method step b0) of attaching a field insulating layer (field oxide, FOX) to the substrate layer. Here, method step b0) can be carried out before method step b), at method step d0) after method step b) or simultaneously with method step b).

  For example, the field insulating layer can first be attached in method step b0), optionally structured, and then the gate insulating layer can be attached in method step b). Here, the gate insulating layer can be attached or grown in a vacant region between the field insulating layer regions, for example. This order is advantageous when the field insulating layer and the gate insulating layer are made from the same material. Alternatively, the gate insulating layer can first be attached in method step b), optionally structured, and then the field insulating layer can be attached in method step b0). Here, the gate insulating layer can be attached or grown so as to cover the surface. This order is advantageous when the field insulating layer and the gate insulating layer are made of different materials. When the gate insulating layer is attached in front of the field insulating layer, the gate insulating protective layer can be used as a mask for the field insulating layer. In method step c), a gate insulating protective layer can be applied partially or completely on the field oxide layer.

  The gate insulating layer can be formed particularly flat or completely flat in method step b). The gate insulating layer can in particular be an oxide layer. For example, the gate insulating layer can be made from silicon dioxide. The attachment of the gate insulating layer in method step b) can be performed, for example, by thermal oxidation of the semiconductor material. Here, the gate insulating layer can be made of the same material as the field insulating layer or a different material. For example, the field insulating layer and the gate insulating layer can be made of silicon dioxide. This can be done by thermally oxidizing a silicon-containing wafer, such as a silicon carbide wafer, after high temperature oxide (HTO) has been deposited as a field oxide. Here, however, the field insulating layer and / or the gate insulating layer can also be attached using tetraethylorthosilicate (TEOS). Instead, the field insulating layer and / or the gate insulating layer can also be made from hafnium silicate.

  A further subject of the present invention is a chemically sensitive field effect transistor for gas sensors made by the method of the present invention.

  A further subject of the present invention is a chemically sensitive field effect transistor for gas sensors made by the method of the present invention, which field effect transistor comprises at least one substrate layer, a gate insulating layer, a field insulating layer (field oxide). FOX), a conductor path, and a gate electrode layer (sensing layer), and the gate electrode layer is disposed on at least a part of the gate insulating layer. Here, according to the invention, a gate electrode layer is additionally arranged on at least part of the field insulating layer and / or on at least part of the conductor track. This type of field effect transistor can advantageously be produced for the first time by the method of the invention. For further advantages and additional features, please refer to the advantages and features described in connection with the method of the present invention.

  Here, the gate insulating layer and / or the gate insulating layer can be disposed on the substrate layer. The field insulating layer and the gate insulating layer are in contact with each other and / or overlap each other. For example, at least a portion of the field insulating layer can be disposed on at least a portion of the gate insulating layer, or at least a portion of the gate insulating layer can be disposed on at least a portion of the field insulating layer. Alternatively, the gate insulating layer can be attached to an empty area between the field insulating layers. The conductor track can be disposed on the field insulating layer.

  In particular, the substrate layer can be made of a semiconductor material having a wide band gap (wide band gap semiconductor), for example, silicon carbide (SiC). The substrate layer may be this type of wafer.

  The field insulating layer and the gate insulating layer can be made of the same material or different materials. For example, the field insulating layer and the gate insulating layer are independent of each other, and oxides, nitrides, and silicates of silicon, aluminum, zirconium, hafnium, and mixtures thereof, such as silicon dioxide, silicon nitride, aluminum oxide. , Zirconium oxide, zirconium silicate, hafnium oxide, hafnium silicate, and mixtures thereof can be made from a dielectric material. Optionally both the field insulating layer and the gate insulating layer can be made from an oxide, in particular silicon dioxide.

  The gate insulating layer is composed of oxides, nitrides, and silicates of silicon, aluminum, zirconium, hafnium, and mixtures thereof, such as silicon dioxide, silicon nitride, aluminum oxide, zirconium oxide, zirconium silicate, hafnium oxide. Can have two or more layers of different materials selected from the group consisting of: hafnium silicate, and mixtures thereof.

  For example, the conductor track can be formed from a metal or a metal mixture, especially a two or three metal mixture, these mixtures from the group consisting of platinum, rhodium, ruthenium, tantalum, palladium, iridium, and mixtures thereof. At least one selected metal and optionally at least one metal selected from the group consisting of chromium, cobalt, copper, titanium, gold, silicon, silver, tungsten, zirconium, and mixtures thereof. In particular, the conductor track is one or more selected from the group consisting of up to 30% by weight platinum based on the total weight of the metal mixture and platinum, rhodium, ruthenium, tantalum, titanium, palladium, iridium, and mixtures thereof. It can be made from a metal mixture containing the metals. For example, the conductor path has a layer thickness dL in the range of 10 nm or more and 10 μm or less, for example, 50 nm or more and 500 nm or less.

  Preferably, the gate electrode layer is made from a conductive material. In particular, the gate electrode layer can be made from a metal, a metal mixture, an alloy, or a ceramic metal mixture, such as a platinum-rhodium mixture.

  Furthermore, the field effect transistor can comprise a protective layer system consisting of one protective layer or two or more, in particular three or more protective layers. For example, a field effect transistor can include a base layer, a cover layer, and optionally at least one intermediate layer disposed between the base layer and the cover layer. This can be arranged, for example, on at least part of the substrate layer and / or the field insulating layer and / or the gate insulating layer and / or the conductor track. In particular, the protective layer or the protective layer system can be in contact with the gate electrode layer.

  A “layer system” can be understood as a system of three or more sequentially arranged layers of different materials for the purpose of the present invention. Here, the “base layer” is a layer system layer in contact with the covered layer, and the “cover layer” is a layer on the opposite side of the covered layer or the outermost / top layer of the layer system. is there.

For example, field effect transistors
Oxides, nitrides, and silicates of silicon, aluminum, zirconium, hafnium, and mixtures thereof, such as silicon dioxide, silicon nitride, aluminum oxide, zirconium oxide, zirconium silicate, hafnium oxide, hafnium silicate A base layer made of a dielectric material selected from the group consisting of salts, and mixtures thereof, and / or especially silicon carbide, such as amorphous silicon carbide or polycrystalline silicon carbide, especially low conductivity silicon carbide and / or carburizing A cover layer comprising a chemical resistant material comprising or consisting of silicon nitride, and / or a mixture of silicon (Si), boron (B), carbon (C) and nitrogen (N), and / or SiAlON Called silicon (Si), aluminum (Al A mixture of oxygen (O) and nitrogen (N) and / or silicon, aluminum, zirconium, hafnium and mixtures thereof such as silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, zirconium silicate, hafnium oxide, silica An intermediate layer comprising a dielectric material and / or a self-passivating material that is a material selected from the group consisting of hafnium acid salt and combinations thereof, or a protective layer system comprising an intermediate layer comprised thereof can be included.

  Here, the layer thickness d1B of the base layer is 3 nm or more and 300 nm or less, and / or the layer thickness d1D of the cover layer is 100 nm or more and 300 nm or less, and / or the layer thickness d1Z of the intermediate layer (whole) is 100 nm. As mentioned above, it is 300 nm or less. Overall, the total layer thickness d1 of this layer system can be in the range 10 ≧ nm to ≦ 10 μm, in particular in the range 50 ≧ nm to ≦ 1000 nm, for example in the range ≧ 50 nm to ≦ 500 nm. This kind of protective layer system can be arranged on at least part of the field insulating layer and / or the gate insulating layer and / or the conductor track.

  Alternatively or additionally, the field effect transistor comprises a protective layer comprising a base layer made of a material containing or consisting of a diffusion-blocked material, in particular titanium nitride and / or tantalum nitride (conductor track), and / or Or an intermediate layer comprising or consisting of titanium, silicon, tantalum and / or niobium, in particular titanium and / or silicon, made from a material forming an oxidation protection layer, and / or titanium oxide, silicon oxide, tantalum oxide and It may have a cover layer made of an oxide material comprising or consisting of niobium oxide, in particular titanium oxide and / or silicon oxide. Here, the base layer can have a layer thickness d2B in the range of 5 nm or more and 50 nm or less, and / or the cover layer can have a total layer thickness d2ZD of 5 nm or more and 50 nm or less. As a whole, the total layer thickness d2 of this layer system is in the range of 10 nm or more and 200 μm or less, for example 10 nm or more and 100 nm or less. This kind of protective layer system can be arranged, inter alia, on at least part of the conductor track.

  Furthermore, the subject of the invention is a field effect transistor and / or exhaust gas produced according to the invention, in particular nitrogen oxides, according to the invention for detecting and / or analyzing, for example, in the context of on-board diagnostics (OBD). The present invention relates to a method of using the manufactured field effect transistor.

  Further advantages and advantageous configurations of the subject of the invention are illustrated by the drawings and are described in the following specification. The drawings herein are for illustrative purposes only and do not limit the invention in any way.

FIG. 3 is a schematic cross-sectional view, not to scale, illustrating an embodiment of the method and field effect transistor of the present invention. FIG. 4 is a schematic cross-sectional view, not to scale, illustrating another embodiment of the method and field effect transistor of the present invention. FIG. 4 is a schematic cross-sectional view, not to scale, illustrating another embodiment of the method and field effect transistor of the present invention.

  FIG. 1a shows a method step a) in the frame of this embodiment of the method in which a substrate layer 1 is made from a semiconductor material, and a field insulating layer 4 is first formed in this substrate layer in method step b0) and structured. Subsequently, the state in which the gate insulating layer 2 is formed in the empty region between the two field insulating layer regions 4 in the method step b) is shown.

  FIG. 1b shows how the gate insulating protective layer 3 is formed on and adjacent to the gate insulating layer 2 in method step c).

  FIG. 1c shows how the metal layer 5 is formed on the field insulating layer region 4 in method step d0) following method step c). The metal layer 5 is adjacent to the gate insulating protective layer 3 and is used as a conductor path.

  FIG. 1d shows how the gate insulating protective layer 3 is completely removed after method step d0) of method step d).

  FIG. 1 e shows that the gate electrode layer 6 is formed on the gate insulating layer 2 directly following method step d). The gate electrode layer 6 is additionally disposed on a part of the field insulating layer 4 and a part of the conductor path 5 adjacent to the gate insulating layer 2. Furthermore, it can be seen from FIG. 1 e that the protective layer 7 is formed on a part of the conductor path 5 adjacent to the gate electrode layer 6.

  FIG. 2 shows that, within the frame of this embodiment of the method, a substrate layer 1 made of semiconductor material is also prepared in method step a) and field insulation is performed on this substrate layer in method steps b0) and b). A state in which the layer 4 and the gate insulating layer 2 are formed is shown. Unlike the embodiment shown in FIGS. 1a to 1d, in this embodiment method step c), three gate insulating protective layers 3 ′, 3 ″, 3 ″ ′ of different materials are connected to the gate insulating layer 2 and to this. Formed on the adjacent field insulating layer region 4, only the two gate insulating protective layers 3 ", 3" 'are completely removed in method step d). In the subsequent method step e), a gate electrode layer (not shown) is formed on the remaining gate insulating protective layer 3 ', and the remaining gate insulating protective layer 3' functions as a reinforced gate insulating layer.

  FIG. 3a shows that within this embodiment of the method, a substrate layer 1 made of a semiconductor material is also prepared in method step a), and field insulation is performed on this substrate layer in method steps b0) and b). The layer 4 and the gate insulating layer 2 are formed, and a state in which the gate insulating protective layer 3 is further attached to the entire surface in the method step c) is shown. Unlike the embodiment shown in FIGS. 1a to 1d and FIG. 2, in the first method step d0) of this embodiment, the gate insulating protective layer 3 is partially removed.

  FIG. 3b shows how the gate insulating protective layer 3 is used as a mask in a second method step d0) in which the first metal layer 8 is applied over the entire surface to form a contact surface. FIG. 3b further shows that following the third method step d0), the gate insulating protective layer 3 and the first metal layer 8 are partially removed. Furthermore, FIG. 3 b shows that the attached first metal layer 8 now reinforces the remaining area of the gate insulating protective layer 3.

  FIG. 3c shows the second method step d0) for forming the conductor track with the second metal layer 5 attached to the entire surface. Similarly, the second metal layer 5 reinforces the remaining region of the gate insulating protective layer 3. Here, the partially removed gate insulating protective layer 3 is newly used as masking.

FIG. 3d shows how the gate insulating protective layer 3, the metal layer 8 and the metal layer 5 are partially removed in a fifth method step d0). Figure 3d cutting against the gate insulating protective layer 3, showing a state in which is limited to the area of the field insulating layer 4 having a sufficient thickness. In a subsequent method step d) (not shown), the gate insulation protective layer 3 can be removed together with the metal layers 8, 5 disposed thereon, for example by a lift-off method. In this lift-off method, the gate insulating protective layer 3 is dissolved or peeled off, for example, by wet chemical.

Claims (8)

A method of manufacturing a chemically sensitive field effect transistor for a gas sensor, comprising:
a) preparing a substrate layer (1) made of a semiconductor material;
b) forming a gate insulating layer (2) and a field insulating layer (4) on the substrate layer (1);
c) forming a first gate insulating protective layer (3, 3 ') on the gate insulating layer (2) from a material that can be dissolved or peeled off by wet chemical etching; step d) a second gate insulating protective layer from materials which are resistant against processing carried out between the (3 ", 3"') the first gate insulating protective layer (3, 3' on the) Forming into steps;
d0) forming a conductor track (5) on the field insulating layer (4);
d) completely or partially removing the second gate insulating protective layer (3 ″, 3 ″ ′) by dissolving or peeling off the first gate insulating protective layer (3, 3 ′). When,
e) A gate electrode layer (6) is disposed on at least a part of the gate insulating layer (2) and the first and second gate insulating protective layers (3, 3 ', 3 ", 3"') Forming on the remaining part of the manufacturing method. The method according to claim 1, characterized in that the second gate insulating protective layer (3 ", 3"') is made of a material that is resistant to physical cutting or dry etching. . The first gate insulating protective layer (3, 3 ′)
· A aluminum, includes a gate insulating protective layer made of wood charge selected from the group consisting of nickel and its these,
The second gate insulating protective layer (3 ", 3"') is
· Carbonization silicon and the gate insulating protective layer containing at least one carbonitride, silicon and silicon nitride and titanium nitride
Including,
The method according to claim 1 or 2, characterized in that   4. The method according to claim 1, wherein, in the method step c), the first gate insulating protective layer (3 ') is formed from a gate insulating protective material. In the method step c), the method according to any one of claims 1 to 4 before Symbol second gate insulating protective layer (3 '') is formed of a conductive material, characterized in that . Said method step d0) comprises one or more method steps selected from the group:
Structuring at least one of the first and second gate insulating protective layers (3, 3 ′, 3 ″, 3 ″ ′);
Forming one or more further layers (4, 5, 6, 7, 8) to form electrical contacts, conductor tracks, insulating layers and / or protective layers;
-One or more formed layers (2, 3, 3 ', 3 ", 3"', 4, 5, 6, 7, 8), electrical contacts, conductor tracks, insulating layers and / or protective layers Structuring to form,
Checking the integrity of the gate insulating layer (2) by means of electrical contacts of the second gate insulating protective layer (3 ″ ′) having conductivity;
Individualizing the resulting constructs (1, 2, 3, 3 ′, 3 ″, 3 ″ ′, 4, 5, 6, 7, 8);
-Conveying the resulting construct (1, 2, 3, 3 ', 3 ", 3"', 4, 5, 6, 7, 8);
Combining these steps, wherein the gate insulating layer (2) is covered by at least a part of the first and second gate insulating protective layers (3, 3 ′, 3 ″, 3 ″ ′) Step to leave,
The method according to claim 1, comprising:   The first gate insulating protective layer (3) is structured in the method step d0) to be used as a mask for the later formed layers (4, 5, 6, 7, 8); The method according to claim 6.   The gate electrode layer (6) is further formed on at least a part of the field insulating layer (4) and / or on at least a part of the conductor track (5). The method according to any one of the preceding items.

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