JP5993665B2 - Serial data receiving circuit and receiving method, audio signal processing circuit, electronic device, and audio system - Google Patents

Description

  The present invention relates to a receiving circuit that receives serial data.

In order to transmit information between integrated circuits, a 2-wire or 3-wire serial interface is used. The I ² C (Inter Integrated Circuit) bus standard is proposed as a 2-wire serial interface, and the I ² S (Inter Integrated circuit Sound) bus standard for transmitting digital audio signals is proposed and used as a 3-wire serial interface. It has become.

FIG. 1 is a diagram illustrating an I ² S signal format. The serial data DATA includes 64 bits for each sampling period Ts. Of the 64 bits, 32 bits are assigned to the L channel and 32 bits are assigned to the R channel. The data for each L channel and R channel is called one word.
The bit clock BCK has a positive edge for each bit of the serial data DATA. That is, the frequency of the bit clock BCK is 64 times the sampling frequency fs (= 1 / Ts).

In the I ² S transmission, in addition to these, a word clock LRCK having a positive edge and a negative edge is input for each word (32 bits). When the word clock LRCK is at a low level, L channel data is transmitted, and when the word clock LRCK is at a high level, R channel data is transmitted.

In I ² S communication, a maximum of 24 bits are assigned to audio data out of 32 bits per word. This bit length K is variable according to the sound quality. In the case of left-justified, the upper K bits of the 32 bits are data indicating audio signals (referred to as audio data), and in the case of right-justified, the lower K bits are audio data. The L channel audio data is referred to as Lch data, and the R channel audio data is referred to as Rch data.

The above is the outline of the format of the I ² S communication.

FIG. 2 is a block diagram showing a configuration of a receiving circuit 100r having an I ² S communication interface studied by the present inventors. It should be noted that the configuration and operation of the receiving circuit 100r in FIG. The receiving circuit 100r includes a serial interface circuit 10, a multiplying circuit 30, and an input stage 50 of a DSP (Digital Signal Processor).

  The serial interface circuit 10 receives the word clock LRCK, the bit clock BCK, and the data DATA, performs parallel-serial conversion, and outputs the L channel data D_Lch and the R channel data D_Rch to the input stage 50 of the subsequent DSP.

  The multiplier circuit 30 includes, for example, a PLL circuit, and generates a system clock PLLCK that is 1024 times the sampling frequency fs by multiplying the bit clock BCK by 16. The DSP that is the data receiving destination processes the audio data D_Lch and D_Rch in synchronization with the system clock PLLCK.

  The serial interface circuit 10 includes a serial / parallel converter 11, a first counter 12, and a counter clear circuit 16.

  The serial / parallel converter 11 extracts L channel data D_Lch and R channel data D_Rch included in the serial data DATA in synchronization with the bit clock BCK and the word clock LRCK.

The serial / parallel converter 11 includes a shift register 14, an Lch buffer BUF_L, an Rch buffer BUF_R, and a timing control unit 15.
The serial data DATA includes 32-bit L channel data and 32-bit R channel data, of which the effective audio data has a maximum length of 24 bits. Therefore, the shift register 14 is composed of 24 bits and shifts the serial data DATA bit by bit in synchronization with the bit clock BCK. The shift register 14 outputs 24-bit parallel data Dp.

The timing controller 15 asserts the first timing signal after counting 24 bit clocks BCK from the negative edge of the word clock LRCK. When the first timing signal is asserted, the Lch buffer BUF_L latches the parallel data Dp stored in the shift register 14 as L channel data D_Lch.
The timing controller 15 asserts the second timing signal when (32 + 24) bit clocks BCK are counted from the negative edge of the word clock LRCK or 24 bit clocks BCK are counted from the positive edge of the word clock LRCK. . When the second timing signal is asserted, the Rch buffer BUF_R latches the parallel data Dp stored in the shift register 14 as R channel data D_Rch.

  When the clear command is issued, the first counter 12 is cleared to zero at the timing of the negative edge of the next word clock LRCK. Thereafter, the first counter 12 performs a count operation in synchronization with the bit clock BCK, and returns to 0 every time the count value CNT1 reaches a predetermined value (for example, 1023), and repeats the operation of counting up again.

  The counter clear circuit 16 receives the count value CNT1 of the first counter 12, and asserts the counter clear signal CNT_CLR every time the count value CNT1 reaches a predetermined value (for example, 800).

  The DSP input stage 50 includes an Lch latch 52, an Rch latch 54, a second counter (DSP sequence counter) 56, and a strobe signal generator 58.

  The second counter 56 is cleared to zero each time the count clear signal CNT_CLR is asserted, and repeats the operation of counting up. The strobe signal generator 58 asserts the first strobe signal STRB1 every time the count value CNT2 of the second counter 56 reaches a first predetermined value (for example, 0), in other words, every time the count clear signal CNT_CLR is asserted, The second strobe signal STRB2 is asserted every time the count value CNT2 becomes a second predetermined value (for example, 512).

  The Lch latch 52 latches the L channel data D_Lch stored in the Lch buffer BUF_L in synchronization with the first strobe signal STRB1. Similarly, the Rch latch 54 latches the R channel data D_Rch stored in the Rch buffer BUF_R in synchronization with the second strobe signal STRB2.

JP 2000-078027 A JP-A-6-224873

The inventor has studied the circuit operation of the receiving circuit 100r in FIG. 2 and has recognized the following problems. FIGS. 3A and 3B are waveform diagrams showing the operation of the receiving circuit 100r in FIG.
FIG. 3A shows an operation when the frequency of the system clock PLLCK is maintained at 1024 × fs. In this case, the counter clear signal CNT_CLR is to be asserted in the vicinity of the center of the L-channel data _{L n,} stably data is captured.

In an actual circuit, the frequency of the system clock PLLCK fluctuates due to the influence of noise or the like and deviates from 1024 × fs. In this case, the clearing timing of the first counter 12 deviates from the negative edge of the word clock LRCK. As a result, the Lch latch 52 of the input stage 50, or _{L n} is _taken, or _{L n + 1} is taken, the operation becomes unstable.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and one of exemplary purposes of an embodiment thereof is to provide a receiving circuit capable of stably receiving serial data regardless of fluctuations in the frequency of the system clock. is there.

In one aspect of the present invention, serial data including valid bits to be received as K bits (K is a natural number) is transmitted in units of M bits (M is a natural number), and an edge is provided for each bit of the serial data. The present invention relates to a receiving circuit that receives a bit clock having a bit clock and a word clock having an edge every M bits.
The receiving circuit multiplies the bit clock by N (N is a natural number), generates a system clock, receives a serial data, shifts every bit clock edge, and stores in the shift register. A first buffer that captures the data to be stored at a predetermined phase, a second buffer that captures the same data as the data stored in the first buffer at a phase delayed from the first buffer, and a system clock, The first counter that repeats the operation of resetting the count value to the initial value in synchronization with the data fetch timing of the first buffer, and the system clock is counted, and the count value is set to the initial value every time the count value reaches the set value. A second counter that repeats the resetting operation, and the count value of the second counter is a first predetermined value And a strobe signal generation unit that generates a first strobe signal that is asserted each time the signal reaches the threshold value, and selectively latches one of the data stored in each of the first buffer and the second buffer in synchronization with the first strobe signal. And a latch circuit.

  According to this aspect, the parallel data generated by the shift register is held in the first and second buffers over different periods, and the data stored in one buffer is selected according to the frequency fluctuation of the system clock. Thus, correct data can be taken into the latch circuit, and serial data can be stably received.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  The receiving circuit according to the present invention can stably receive serial data.

It is a diagram illustrating a signal format of the I 2 ^S. Is a block diagram showing the configuration of a receiving circuit comprising I ^{2 S} communication interface studied by the present inventor. FIGS. 3A and 3B are waveform diagrams showing the operation of the receiving circuit of FIG. It is a block diagram which shows the structure of the receiving circuit which concerns on embodiment. It is a figure which shows the state transition of a sequencer. FIGS. 6A and 6B are waveform diagrams showing the operation of the receiving circuit of FIG. It is a block diagram which shows the structure of the audio system using the audio signal processing circuit provided with a receiving circuit. 8A to 8C are external views of electronic devices or audio component devices.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

FIG. 4 is a block diagram illustrating a configuration of the receiving circuit 100 according to the embodiment. The receiving circuit 100 is a source-synchronous three-wire serial interface circuit, and receives a bit clock BCK, a word clock LRCK, and serial data DATA from a transmitting circuit (not shown). The bit clock BCK has an edge for each bit of the serial data DATA. In the following, a system that receives digital audio data compliant with the I ² S bus standard will be described as an example.

  The audio signal is sampled at the sampling frequency fs. The serial data DATA includes 64 bits for each sampling period Ts (= 1 / fs). Of the 64 bits, 32 bits are assigned to the L channel and 32 bits are assigned to the R channel. The 32 bits for each L channel and R channel are referred to as one word. That is, the serial data DATA is transmitted in units of 2 words and M (= 64 bits).

  The bit clock BCK has a positive edge for each bit of the serial data DATA. That is, the frequency of the bit clock BCK is 64 times the sampling frequency fs (= 1 / Ts).

In the I ² S transmission, in addition to these, a word clock LRCK having a positive edge and a negative edge at the boundary of one word (32 bits) is transmitted. When the word clock LRCK is at a low level, L channel data is transmitted, and when the word clock LRCK is at a high level, R channel data is transmitted.

In I ² S communication, a maximum of K (= 24) bits are assigned to audio data out of one word and 32 bits. In I ² S communication, K bits (= 24) out of 32 bits per word are valid bits to be received, and in the case of left-justified, the upper 24 bits of 32 bits are used for audio signals. Assigned to the audio data shown. The L channel audio data (24 bits) is referred to as Lch data D_Lch, and the R channel audio data is referred to as Rch data D_Rch.

  The receiving circuit 100 includes a serial interface circuit 10, a multiplier circuit 30, and an input stage 50, and is integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate. By integrating the circuit as one IC, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

  The serial interface circuit 10 receives the word clock LRCK, the bit clock BCK, and the data DATA, performs parallel-serial conversion, and outputs parallel data to the DSP 110.

  The multiplication circuit 30 multiplies the bit clock BCK by N (N is an integer of 2 or more, and N = 16 in the present embodiment), thereby multiplying the sampling frequency fs by M × N (= 1024). A clock PLLCK is generated. For example, the multiplier circuit 30 is configured by a PLL circuit.

  A DSP (Digital Signal Processor) 50 which is a data receiving destination processes the audio data D_Lch and D_Rch in synchronization with the system clock PLLCK.

  The serial interface circuit 10 includes a first counter (internal counter) 12, a shift register 14, a timing control unit 15, a first buffer BUF1, a second buffer BUF2, a third buffer BUF3, a fourth buffer BUF4, and a selection circuit 20. .

  The serial data DATA includes 32-bit L channel data and 32-bit R channel data, of which the effective audio data has a maximum length of 24 bits. Therefore, the shift register 14 is composed of 24 bits and shifts the serial data DATA bit by bit in synchronization with the bit clock BCK. The shift register 206 outputs 24-bit parallel data Dp.

  The first buffer BUF1 takes in the L channel data stored in the shift register 14 at a predetermined phase. The second buffer BUF2 takes in the same data as the L channel data stored in the first buffer BUF1 with a phase delayed from the first buffer BUF1. Preferably, the second buffer BUF2 captures data with a phase delayed by 180 degrees with respect to the first buffer BUF1.

  The third buffer BUF3 takes in the R channel data stored in the shift register 14 at a predetermined phase. The fourth buffer BUF4 takes in the same data as the R channel data stored in the third buffer BUF3 with a phase delayed from the third buffer BUF3. Preferably, the fourth buffer BUF4 captures data with a phase delayed by 180 degrees with respect to the third buffer BUF3.

  The timing control unit 15 controls the capture timing of the first buffer BUF1 to the fourth buffer BUF4. The timing controller 15 receives the word clock LRCK and the bit clock BCK. When the L channel data and the R channel data are left-justified, the timing controller 15 counts 24 bit clocks BCK from the negative edge of the word clock LRCK and takes the output Dp of the shift register 14 into the first buffer BUF1. Instruct.

  Subsequently, the timing control unit 15 instructs the first buffer BUF1 to capture data, counts a predetermined number of bit clocks BCK, and then instructs the second buffer BUF2 to capture the same data as the first buffer BUF1. When the phase difference between the first buffer BUF1 and the second buffer BUF2 is 180 degrees, the second buffer BUF2 captures data 32 clocks after the data capture of the first buffer BUF1.

  The timing controller 15 counts 24 bit clocks BCK from the positive edge of the word clock LRCK, or counts (32 + 24) bit clocks BCK from the negative edge of the word clock LRCK, and stores it in the third buffer BUF3. Instruct to capture the output Dp of the shift register 14.

  Subsequently, the timing controller 15 instructs the third buffer BUF3 to take in data, counts a predetermined number of bit clocks BCK, and then instructs the fourth buffer BUF4 to take in the same data as the third buffer BUF3. When the phase difference between the third buffer BUF3 and the fourth buffer BUF4 is 180 degrees, the fourth buffer BUF4 captures data 32 clocks after the data capture of the third buffer BUF3.

  The first counter 12 counts the system clock PLLCK and repeats the operation of resetting the count value to an initial value (for example, zero) in synchronization with the data fetch timing of the first buffer BUF1.

  The selection circuit 20 will be described later.

  The input stage 50 includes a latch circuit 51, a second counter 56, and a strobe signal generator 58.

  The second counter 56 counts the system clock PLLCK and repeats the operation of resetting the count value to an initial value (for example, 0) every time the count value CNT2 reaches a set value (for example, 1023). That is, the second counter 56 repeats free run.

  The strobe signal generator 58 generates a first strobe signal STRB1 that is asserted every time the count value CNT2 of the second counter 56 reaches the first predetermined value V1. The strobe signal generator 58 generates a second strobe signal STRB2 that is asserted every time the count value CNT2 of the second counter 56 reaches the second predetermined value V2. For example, the difference between the first predetermined value V 1 and the second predetermined value V 2 is ½ of the count cycle 1024 of the second counter 56. In this embodiment, V1 = 1023 and V2 = 511.

  Latch circuit 51 includes an Lch latch 52 and an Rch latch 54. The Lch latch 52 selectively latches one of the data stored in the first buffer BUF1 and the second buffer BUF2 in synchronization with the first strobe signal STBR1. The Rch latch 54 selectively latches one of the data stored in the third buffer BUF3 and the fourth buffer BUF4 in synchronization with the second strobe signal STBR2.

  Here, the count value CNT1 of the first counter 12 at a certain determination timing changes according to the frequency (cycle) of the system clock PLLCK. That is, if the frequency of the system clock PLLCK is higher than the reference value 1024 × fs, the count value CNT1 at the determination timing increases for each sampling period. On the contrary, if the frequency of the system clock PLLCK is lower than the reference value 1024 × fs, the count value CNT1 at the determination timing becomes smaller for each sampling period.

  Therefore, the selection circuit 20 selects one of the data stored in each of the first buffer BUF1 and the second buffer BUF2 based on the count value CNT1 of the first counter 12 at a predetermined determination timing, and outputs it to the latch circuit 51. . Similarly, the selection circuit 20 selects one of the data stored in each of the third buffer BUF3 and the fourth buffer BUF4 based on the count value CNT1 of the first counter 12 at a predetermined determination timing, and sends it to the latch circuit 51. Output. That is, the selection circuit 20 selects data according to the frequency of the system clock PLLCK.

  For example, the determination timing corresponds to the timing at which the Lch latch 52 of the latch circuit 51 takes in data, that is, the strobe signal STBR1. In the modification, the determination timing may be in accordance with the timing at which the Rch latch 54 of the latch circuit 51 captures data, that is, the strobe signal STBR2.

  The selection circuit 20 may switch the data to be supplied to the input stage 50 based on the value x of the upper P bits (P is a natural number) of the count value CNT1 of the first counter 12. When the first counter 12 is a 10-bit counter, P = 3 may be set. In this case, the upper 3 bits of the count value CNT1 indicate that the count value CNT1 is any of 0 to 127, 128 to 255, 256 to 383, 384 to 511, 512 to 639, 640 to 767, 768 to 895, and 896 to 1023. It is included in the range.

  The selection circuit 20 includes a first selector 22, a second selector 24, and a sequencer 26. The first selector 22 selects one of the data L1 and L2 of each of the first buffer BUF1 and the second buffer BUF2 and outputs it to the Lch latch 52. The second selector 24 selects one of the data R1 and R2 of each of the third buffer BUF3 and the fourth buffer BUF4 and outputs it to the Rch latch 54. The sequencer 26 switches the states of the first selector 22 and the second selector 24 based on the count value CNT1.

  The sequencer 26 is a two-state state machine, and transits between the first state φ1 and the second state φ2. In the first state φ1, the first selector 22 selects the first buffer BUF1, and the second selector 24 selects the third buffer BUF3. In the second state φ2, the first selector 22 selects the second buffer BUF2, and the second selector 24 selects the fourth buffer BUF4.

FIG. 5 is a diagram showing state transition of the sequencer 26.
In the state transition of the sequencer 26, a dead zone and a hysteresis are set for the count value CNT1 of the first counter 12. Specifically, in the first state φ1, when the value 3 of the upper 3 bits of the count value CNT1 takes 0 or 7 at the determination timing, the state transitions to the second state φ2 (S100). In the second state φ2, when the value 3 of the upper 3 bits of the count value CNT1 takes 3 or 4 at the determination timing, the state transitions to the first state φ1 (S102).

The above is the configuration of the receiving circuit 100. Next, the operation will be described.
6A and 6B are waveform diagrams showing the operation of the receiving circuit 100 of FIG. As described above, the second counter (DSP sequence counter) 56 is free-running and is asynchronous with the word clock LRCK.

  6A and 6B, the count value of the second counter 56 is different. Each time the count value CNT2 of the second counter 56 becomes V1 = 1023, the strobe signal STRB1 is asserted. In FIG. 6A, the count value CNT1 of the first counter 12 is 7 at the timing of the strobe signal STRB1. Therefore, the selection circuit 20 selects the data L2 and R2 of the second buffer BUF2 and the fourth buffer BUF4 and outputs them to the latch circuit 51.

  In FIG. 6B, the count value CNT1 of the first counter 12 is 3 at the timing of the strobe signal STRB1. Therefore, the selection circuit 20 selects the data L1 and R1 of the first buffer BUF1 and the third buffer BUF3 and outputs them to the latch circuit 51.

  The above is the operation of the receiving circuit 100. According to this receiving circuit 100, parallel data of the L channel (R channel) generated by the shift register 14 is held in the two buffers BUF1 and BUF2 (BUF3 and BUF4) over different periods. Even when the frequency of the system clock PLLCK changes, by selecting one of the data stored in the two buffers, correct data can be taken into the latch circuit, and serial data can be received stably. it can.

  Further, the frequency of the system clock PLLCK is monitored by referring to the count value CNT1 of the first counter 12, and an appropriate one of the data stored in the two buffers is selected according to the frequency of the system clock PLLCK. can do.

  In addition, by providing hysteresis and a dead band in the state transition of the selection circuit 20, it is possible to suppress the state from frequently changing and the system from becoming unstable.

Next, the use of the receiving circuit 100 will be described.
FIG. 7 is a block diagram illustrating a configuration of an audio system 500 using the audio signal processing circuit 200 including the receiving circuit 100.

  The audio system 500 includes a sound source 2, an audio signal processing circuit 200, amplifiers 8L and 8R, and speakers 9L and 9R.

  The audio signal processing circuit 200 is connected to the sound source 2 such as a CD player via a 3-wire serial interface and receives a digital audio signal. The audio signal processing circuit 200 includes a plurality of processing units 203 and a D / A converter 204 in addition to the receiving circuit 100 described above. The input stage 50 and the plurality of processing units 203 are collectively referred to as a DSP 202.

  The input stage 50 receives the digital audio signal from the sound source 2 and generates L channel data D_Lch and R channel data D_Rch. The data D_Lch and D_Rch output from the input stage 50 are input to the subsequent processing unit 203. The processing unit 203 is a digital volume circuit, a multiband equalizer, a loudness circuit, a crossover filter, a bass boost circuit, and the like, and performs predetermined signal processing on the data D_Lch and D_Rch.

  The signal processing of the processing unit 203 is synchronized with the count value CNT2 of the second counter 56 of the input stage 50. That is, when the count value CNT2 is in the first range, the first processing unit 203 performs signal processing, and when the count value CNT2 is in the second range, the second processing unit 203 performs signal processing.

  The D / A converters 204L and 204R convert the audio data D_Lch and D_Rch that have passed through the processing unit 203 from digital to analog, and generate analog audio signals S_Lch and S_Rch, respectively.

  The amplifiers 8L and 8R amplify the analog audio signals S_Lch and S_Rch and output them to the speakers 9L and 9R.

  The audio signal processing circuit 200 of FIG. 7 can also be used for an in-vehicle audio device and a home audio component device. Alternatively, the audio signal processing circuit 200 can be mounted on an electronic device such as a television, a desktop PC, a notebook PC, a tablet PC, a mobile phone terminal, a digital camera, or a portable audio player.

  8A to 8C are external views of electronic devices or audio component devices. FIG. 8A illustrates a display device 600 that is an example of an electronic device. The display device 600 includes a housing 602 and a speaker 9. The audio signal processing circuit 200 is built in the casing and drives the speaker 9.

  FIG. 7B shows an audio component 700. The audio component 700 includes a housing 702 and a speaker 9. The audio signal processing circuit 200 is built in the housing 702 and drives the speaker 9.

  FIG. 7C illustrates a small information terminal 800 which is an example of an electronic device. The small information terminal 800 is a mobile phone, PHS (Personal Handy-phone System), PDA (Personal Digital Assistant), tablet PC (Personal Computer), audio player, or the like. The small information terminal 800 includes a housing 802, a speaker 9, and a display 804. The audio signal processing circuit 200 is built in the housing 802 and drives the speaker 9.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

In the embodiment, the serial data of the I ² S bus standard has been described as an example. However, the present invention is not limited thereto, and may be used for transmission of serial data compliant with other standards such as the I ² C bus standard. it can. In this case, the values of the natural numbers M and K that are parameters may be changed as appropriate. Further, there may be a plurality of lines for transmitting serial data. The serial data is not limited to audio data and may be arbitrary data.

  In the embodiment, the case where the buffer is selected based on the count value of the first counter at the determination timing has been described, but the present invention is not limited thereto. For example, a frequency counter may be separately provided, the frequency of the system clock PLLCK may be counted, and the buffer may be selected based on the value.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

BCK ... bit clock, DATA ... serial data, LRCK ... word clock, PLLCK ... system clock, 100 ... receiving circuit, 10 ... serial interface circuit, 12 ... first counter, 14 ... shift register, 16 ... counter clear circuit, 30 ... Multiplier circuit 50 ... Input stage 52 ... Lch latch 54 ... Rch latch 56 ... Second counter 58 ... Strobe signal generation unit 70 ... Period setting unit 200 ... Audio signal processing circuit 202 ... DSP 203 ... Processing unit, 204 ... D / A converter, 500 ... audio system, 2 ... sound source, 8 ... amplifier, 9 ... speaker.

Claims (21)

Serial data including effective bits to be received in M bits (M is a natural number), K bits (K is a natural number), a bit clock having an edge for each bit of the serial data, and A receiving circuit for receiving a word clock having an edge every M bits,
A multiplier for generating a system clock by multiplying the bit clock by N (N is a natural number);
A K-bit shift register that receives the serial data and shifts every edge of the bit clock;
A first buffer for capturing data stored in the shift register at a predetermined phase;
A second buffer for capturing the same data as the data stored in the first buffer with a phase delayed from the first buffer;
A first counter that counts the system clock and repeats an operation of resetting the count value to an initial value in synchronization with the data fetch timing of the first buffer;
A second counter that repeats an operation of counting the system clock and resetting the count value to an initial value every time the count value reaches a set value;
A strobe signal generator that generates a first strobe signal that is asserted every time the count value of the second counter reaches a first predetermined value;
A latch circuit that selectively latches one of the data stored in each of the first buffer and the second buffer in synchronization with the first strobe signal;
A receiving circuit comprising:   A selection circuit for selecting one of data stored in each of the first buffer and the second buffer based on a count value of the first counter at a predetermined determination timing and outputting the selected data to the latch circuit; The receiving circuit according to claim 1, wherein:   The receiving circuit according to claim 2, wherein the predetermined determination timing corresponds to a timing at which the latch circuit captures data.   The data stored in each of the first buffer and the second buffer is selected based on the value of the upper P bits (P is a natural number) of the count value of the first counter. The receiving circuit according to any one of 1 to 3.   3. The receiving circuit according to claim 2, wherein the selection of data by the selection circuit is such that hysteresis is set for a count value of the first counter.   6. The receiving circuit according to claim 1, wherein the second buffer takes in data with a phase delayed by 180 degrees with respect to the first buffer.   7. The receiving circuit according to claim 1, wherein the serial data includes L channel data and R channel data each having K bits. A third buffer for capturing R channel data stored in the shift register at a predetermined phase;
A fourth buffer for capturing the same data as the L channel data stored in the third buffer with a phase delayed from the third buffer;
Further comprising
The first buffer captures L channel data stored in the shift register at a predetermined phase,
The second buffer captures the same data as the L channel data stored in the first buffer with a phase delayed from the first buffer,
The strobe signal generation unit generates a second strobe signal that is asserted every time the count value of the second counter reaches a second predetermined value;
8. The latch circuit according to claim 7, wherein the L channel data is latched in synchronization with the first strobe signal, and the R channel data is latched in synchronization with the second strobe signal. Receiver circuit. The second buffer captures L channel data with a phase delayed by 180 degrees with respect to the first buffer,
9. The receiving circuit according to claim 8, wherein the fourth buffer captures R channel data with a phase delayed by 180 degrees with respect to the third buffer.   The receiving circuit according to claim 1, wherein the serial data includes audio data.   11. The receiving circuit according to claim 1, wherein the receiving circuit is integrated on a single semiconductor substrate. A receiving circuit according to any one of claims 1 to 11,
A processing unit for signal processing the data received by the receiving circuit;
An audio signal processing circuit comprising:   An electronic apparatus comprising the audio signal processing circuit according to claim 12.   An audio system comprising the audio signal processing circuit according to claim 12. Serial data including effective bits to be received in M bits (M is a natural number), K bits (K is a natural number), a bit clock having an edge for each bit of the serial data, A word clock having an edge every M bits, comprising:
Generating a system clock by multiplying the bit clock by N (N is a natural number);
Shifting the serial data for each edge of the bit clock by a K-bit shift register;
Capturing the data stored in the shift register into the first buffer at a predetermined phase;
Capturing the same data as the data stored in the first buffer into the second buffer with a phase delayed from the first buffer;
Repeating the operation of counting the system clock by a first counter and resetting the count value to an initial value in synchronization with the data fetch timing of the first buffer;
Repeating the operation of counting the system clock by a second counter and resetting the count value to an initial value every time the count value reaches a set value;
Generating a first strobe signal that is asserted every time the count value of the second counter reaches a first predetermined value;
Selectively latching one of data stored in each of the first buffer and the second buffer in synchronization with the first strobe signal;
A method comprising the steps of:   The method according to claim 15, wherein one of data stored in each of the first buffer and the second buffer is selected based on a count value of the first counter at a predetermined determination timing.   The method according to claim 16, wherein the predetermined determination timing is in accordance with a timing at which the first buffer fetches data.   16. One of the data stored in each of the first buffer and the second buffer is selected based on the value of the upper P bits (P is a natural number) of the count value of the first counter. 18. The method according to any one of 17 to 17.   The method according to claim 16, wherein the data is selected by setting a hysteresis with respect to a count value of the first counter.   The method according to any one of claims 15 to 19, wherein the second buffer captures data with a phase delayed by 180 degrees with respect to the first buffer.   21. The method according to claim 15, wherein the serial data includes L channel data and R channel data each having K bits.

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